drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
 163                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 164         } else {
 165                 DRM_INFO("Forcing AGP to PCI mode\n");
 166                 rdev->flags |= RADEON_IS_PCI;
 167                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 168                 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 169                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 170         }
 171         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 172 }
 173
 174 /*
 175  * ASIC
 176  */
 177
 178 static struct radeon_asic_ring r100_gfx_ring = {
 179         .ib_execute = &r100_ring_ib_execute,
 180         .emit_fence = &r100_fence_ring_emit,
 181         .emit_semaphore = &r100_semaphore_ring_emit,
 182         .cs_parse = &r100_cs_parse,
 183         .ring_start = &r100_ring_start,
 184         .ring_test = &r100_ring_test,
 185         .ib_test = &r100_ib_test,
 186         .is_lockup = &r100_gpu_is_lockup,
 187         .get_rptr = &r100_gfx_get_rptr,
 188         .get_wptr = &r100_gfx_get_wptr,
 189         .set_wptr = &r100_gfx_set_wptr,
 190 };
 191
 192 static struct radeon_asic r100_asic = {
 193         .init = &r100_init,
 194         .fini = &r100_fini,
 195         .suspend = &r100_suspend,
 196         .resume = &r100_resume,
 197         .vga_set_state = &r100_vga_set_state,
 198         .asic_reset = &r100_asic_reset,
 199         .mmio_hdp_flush = NULL,
 200         .gui_idle = &r100_gui_idle,
 201         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 202         .gart = {
 203                 .tlb_flush = &r100_pci_gart_tlb_flush,
 204                 .get_page_entry = &r100_pci_gart_get_page_entry,
 205                 .set_page = &r100_pci_gart_set_page,
 206         },
 207         .ring = {
 208                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 209         },
 210         .irq = {
 211                 .set = &r100_irq_set,
 212                 .process = &r100_irq_process,
 213         },
 214         .display = {
 215                 .bandwidth_update = &r100_bandwidth_update,
 216                 .get_vblank_counter = &r100_get_vblank_counter,
 217                 .wait_for_vblank = &r100_wait_for_vblank,
 218                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 219                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 220         },
 221         .copy = {
 222                 .blit = &r100_copy_blit,
 223                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 224                 .dma = NULL,
 225                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 226                 .copy = &r100_copy_blit,
 227                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 228         },
 229         .surface = {
 230                 .set_reg = r100_set_surface_reg,
 231                 .clear_reg = r100_clear_surface_reg,
 232         },
 233         .hpd = {
 234                 .init = &r100_hpd_init,
 235                 .fini = &r100_hpd_fini,
 236                 .sense = &r100_hpd_sense,
 237                 .set_polarity = &r100_hpd_set_polarity,
 238         },
 239         .pm = {
 240                 .misc = &r100_pm_misc,
 241                 .prepare = &r100_pm_prepare,
 242                 .finish = &r100_pm_finish,
 243                 .init_profile = &r100_pm_init_profile,
 244                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 245                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 246                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 247                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 248                 .set_memory_clock = NULL,
 249                 .get_pcie_lanes = NULL,
 250                 .set_pcie_lanes = NULL,
 251                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 252         },
 253         .pflip = {
 254                 .page_flip = &r100_page_flip,
 255                 .page_flip_pending = &r100_page_flip_pending,
 256         },
 257 };
 258
 259 static struct radeon_asic r200_asic = {
 260         .init = &r100_init,
 261         .fini = &r100_fini,
 262         .suspend = &r100_suspend,
 263         .resume = &r100_resume,
 264         .vga_set_state = &r100_vga_set_state,
 265         .asic_reset = &r100_asic_reset,
 266         .mmio_hdp_flush = NULL,
 267         .gui_idle = &r100_gui_idle,
 268         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 269         .gart = {
 270                 .tlb_flush = &r100_pci_gart_tlb_flush,
 271                 .get_page_entry = &r100_pci_gart_get_page_entry,
 272                 .set_page = &r100_pci_gart_set_page,
 273         },
 274         .ring = {
 275                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 276         },
 277         .irq = {
 278                 .set = &r100_irq_set,
 279                 .process = &r100_irq_process,
 280         },
 281         .display = {
 282                 .bandwidth_update = &r100_bandwidth_update,
 283                 .get_vblank_counter = &r100_get_vblank_counter,
 284                 .wait_for_vblank = &r100_wait_for_vblank,
 285                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 286                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 287         },
 288         .copy = {
 289                 .blit = &r100_copy_blit,
 290                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 291                 .dma = &r200_copy_dma,
 292                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 293                 .copy = &r100_copy_blit,
 294                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 295         },
 296         .surface = {
 297                 .set_reg = r100_set_surface_reg,
 298                 .clear_reg = r100_clear_surface_reg,
 299         },
 300         .hpd = {
 301                 .init = &r100_hpd_init,
 302                 .fini = &r100_hpd_fini,
 303                 .sense = &r100_hpd_sense,
 304                 .set_polarity = &r100_hpd_set_polarity,
 305         },
 306         .pm = {
 307                 .misc = &r100_pm_misc,
 308                 .prepare = &r100_pm_prepare,
 309                 .finish = &r100_pm_finish,
 310                 .init_profile = &r100_pm_init_profile,
 311                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 312                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 313                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 314                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 315                 .set_memory_clock = NULL,
 316                 .get_pcie_lanes = NULL,
 317                 .set_pcie_lanes = NULL,
 318                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 319         },
 320         .pflip = {
 321                 .page_flip = &r100_page_flip,
 322                 .page_flip_pending = &r100_page_flip_pending,
 323         },
 324 };
 325
 326 static struct radeon_asic_ring r300_gfx_ring = {
 327         .ib_execute = &r100_ring_ib_execute,
 328         .emit_fence = &r300_fence_ring_emit,
 329         .emit_semaphore = &r100_semaphore_ring_emit,
 330         .cs_parse = &r300_cs_parse,
 331         .ring_start = &r300_ring_start,
 332         .ring_test = &r100_ring_test,
 333         .ib_test = &r100_ib_test,
 334         .is_lockup = &r100_gpu_is_lockup,
 335         .get_rptr = &r100_gfx_get_rptr,
 336         .get_wptr = &r100_gfx_get_wptr,
 337         .set_wptr = &r100_gfx_set_wptr,
 338 };
 339
 340 static struct radeon_asic_ring rv515_gfx_ring = {
 341         .ib_execute = &r100_ring_ib_execute,
 342         .emit_fence = &r300_fence_ring_emit,
 343         .emit_semaphore = &r100_semaphore_ring_emit,
 344         .cs_parse = &r300_cs_parse,
 345         .ring_start = &rv515_ring_start,
 346         .ring_test = &r100_ring_test,
 347         .ib_test = &r100_ib_test,
 348         .is_lockup = &r100_gpu_is_lockup,
 349         .get_rptr = &r100_gfx_get_rptr,
 350         .get_wptr = &r100_gfx_get_wptr,
 351         .set_wptr = &r100_gfx_set_wptr,
 352 };
 353
 354 static struct radeon_asic r300_asic = {
 355         .init = &r300_init,
 356         .fini = &r300_fini,
 357         .suspend = &r300_suspend,
 358         .resume = &r300_resume,
 359         .vga_set_state = &r100_vga_set_state,
 360         .asic_reset = &r300_asic_reset,
 361         .mmio_hdp_flush = NULL,
 362         .gui_idle = &r100_gui_idle,
 363         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 364         .gart = {
 365                 .tlb_flush = &r100_pci_gart_tlb_flush,
 366                 .get_page_entry = &r100_pci_gart_get_page_entry,
 367                 .set_page = &r100_pci_gart_set_page,
 368         },
 369         .ring = {
 370                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 371         },
 372         .irq = {
 373                 .set = &r100_irq_set,
 374                 .process = &r100_irq_process,
 375         },
 376         .display = {
 377                 .bandwidth_update = &r100_bandwidth_update,
 378                 .get_vblank_counter = &r100_get_vblank_counter,
 379                 .wait_for_vblank = &r100_wait_for_vblank,
 380                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 381                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 382         },
 383         .copy = {
 384                 .blit = &r100_copy_blit,
 385                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 386                 .dma = &r200_copy_dma,
 387                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 388                 .copy = &r100_copy_blit,
 389                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 390         },
 391         .surface = {
 392                 .set_reg = r100_set_surface_reg,
 393                 .clear_reg = r100_clear_surface_reg,
 394         },
 395         .hpd = {
 396                 .init = &r100_hpd_init,
 397                 .fini = &r100_hpd_fini,
 398                 .sense = &r100_hpd_sense,
 399                 .set_polarity = &r100_hpd_set_polarity,
 400         },
 401         .pm = {
 402                 .misc = &r100_pm_misc,
 403                 .prepare = &r100_pm_prepare,
 404                 .finish = &r100_pm_finish,
 405                 .init_profile = &r100_pm_init_profile,
 406                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 407                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 408                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 409                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 410                 .set_memory_clock = NULL,
 411                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 412                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 413                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 414         },
 415         .pflip = {
 416                 .page_flip = &r100_page_flip,
 417                 .page_flip_pending = &r100_page_flip_pending,
 418         },
 419 };
 420
 421 static struct radeon_asic r300_asic_pcie = {
 422         .init = &r300_init,
 423         .fini = &r300_fini,
 424         .suspend = &r300_suspend,
 425         .resume = &r300_resume,
 426         .vga_set_state = &r100_vga_set_state,
 427         .asic_reset = &r300_asic_reset,
 428         .mmio_hdp_flush = NULL,
 429         .gui_idle = &r100_gui_idle,
 430         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 431         .gart = {
 432                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 433                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 434                 .set_page = &rv370_pcie_gart_set_page,
 435         },
 436         .ring = {
 437                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 438         },
 439         .irq = {
 440                 .set = &r100_irq_set,
 441                 .process = &r100_irq_process,
 442         },
 443         .display = {
 444                 .bandwidth_update = &r100_bandwidth_update,
 445                 .get_vblank_counter = &r100_get_vblank_counter,
 446                 .wait_for_vblank = &r100_wait_for_vblank,
 447                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 448                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 449         },
 450         .copy = {
 451                 .blit = &r100_copy_blit,
 452                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 453                 .dma = &r200_copy_dma,
 454                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 455                 .copy = &r100_copy_blit,
 456                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 457         },
 458         .surface = {
 459                 .set_reg = r100_set_surface_reg,
 460                 .clear_reg = r100_clear_surface_reg,
 461         },
 462         .hpd = {
 463                 .init = &r100_hpd_init,
 464                 .fini = &r100_hpd_fini,
 465                 .sense = &r100_hpd_sense,
 466                 .set_polarity = &r100_hpd_set_polarity,
 467         },
 468         .pm = {
 469                 .misc = &r100_pm_misc,
 470                 .prepare = &r100_pm_prepare,
 471                 .finish = &r100_pm_finish,
 472                 .init_profile = &r100_pm_init_profile,
 473                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 474                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 475                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 476                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 477                 .set_memory_clock = NULL,
 478                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 479                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 480                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 481         },
 482         .pflip = {
 483                 .page_flip = &r100_page_flip,
 484                 .page_flip_pending = &r100_page_flip_pending,
 485         },
 486 };
 487
 488 static struct radeon_asic r420_asic = {
 489         .init = &r420_init,
 490         .fini = &r420_fini,
 491         .suspend = &r420_suspend,
 492         .resume = &r420_resume,
 493         .vga_set_state = &r100_vga_set_state,
 494         .asic_reset = &r300_asic_reset,
 495         .mmio_hdp_flush = NULL,
 496         .gui_idle = &r100_gui_idle,
 497         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 498         .gart = {
 499                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 500                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 501                 .set_page = &rv370_pcie_gart_set_page,
 502         },
 503         .ring = {
 504                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 505         },
 506         .irq = {
 507                 .set = &r100_irq_set,
 508                 .process = &r100_irq_process,
 509         },
 510         .display = {
 511                 .bandwidth_update = &r100_bandwidth_update,
 512                 .get_vblank_counter = &r100_get_vblank_counter,
 513                 .wait_for_vblank = &r100_wait_for_vblank,
 514                 .set_backlight_level = &atombios_set_backlight_level,
 515                 .get_backlight_level = &atombios_get_backlight_level,
 516         },
 517         .copy = {
 518                 .blit = &r100_copy_blit,
 519                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 520                 .dma = &r200_copy_dma,
 521                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 522                 .copy = &r100_copy_blit,
 523                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 524         },
 525         .surface = {
 526                 .set_reg = r100_set_surface_reg,
 527                 .clear_reg = r100_clear_surface_reg,
 528         },
 529         .hpd = {
 530                 .init = &r100_hpd_init,
 531                 .fini = &r100_hpd_fini,
 532                 .sense = &r100_hpd_sense,
 533                 .set_polarity = &r100_hpd_set_polarity,
 534         },
 535         .pm = {
 536                 .misc = &r100_pm_misc,
 537                 .prepare = &r100_pm_prepare,
 538                 .finish = &r100_pm_finish,
 539                 .init_profile = &r420_pm_init_profile,
 540                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 541                 .get_engine_clock = &radeon_atom_get_engine_clock,
 542                 .set_engine_clock = &radeon_atom_set_engine_clock,
 543                 .get_memory_clock = &radeon_atom_get_memory_clock,
 544                 .set_memory_clock = &radeon_atom_set_memory_clock,
 545                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 546                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 547                 .set_clock_gating = &radeon_atom_set_clock_gating,
 548         },
 549         .pflip = {
 550                 .page_flip = &r100_page_flip,
 551                 .page_flip_pending = &r100_page_flip_pending,
 552         },
 553 };
 554
 555 static struct radeon_asic rs400_asic = {
 556         .init = &rs400_init,
 557         .fini = &rs400_fini,
 558         .suspend = &rs400_suspend,
 559         .resume = &rs400_resume,
 560         .vga_set_state = &r100_vga_set_state,
 561         .asic_reset = &r300_asic_reset,
 562         .mmio_hdp_flush = NULL,
 563         .gui_idle = &r100_gui_idle,
 564         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 565         .gart = {
 566                 .tlb_flush = &rs400_gart_tlb_flush,
 567                 .get_page_entry = &rs400_gart_get_page_entry,
 568                 .set_page = &rs400_gart_set_page,
 569         },
 570         .ring = {
 571                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 572         },
 573         .irq = {
 574                 .set = &r100_irq_set,
 575                 .process = &r100_irq_process,
 576         },
 577         .display = {
 578                 .bandwidth_update = &r100_bandwidth_update,
 579                 .get_vblank_counter = &r100_get_vblank_counter,
 580                 .wait_for_vblank = &r100_wait_for_vblank,
 581                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 582                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 583         },
 584         .copy = {
 585                 .blit = &r100_copy_blit,
 586                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 587                 .dma = &r200_copy_dma,
 588                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 589                 .copy = &r100_copy_blit,
 590                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 591         },
 592         .surface = {
 593                 .set_reg = r100_set_surface_reg,
 594                 .clear_reg = r100_clear_surface_reg,
 595         },
 596         .hpd = {
 597                 .init = &r100_hpd_init,
 598                 .fini = &r100_hpd_fini,
 599                 .sense = &r100_hpd_sense,
 600                 .set_polarity = &r100_hpd_set_polarity,
 601         },
 602         .pm = {
 603                 .misc = &r100_pm_misc,
 604                 .prepare = &r100_pm_prepare,
 605                 .finish = &r100_pm_finish,
 606                 .init_profile = &r100_pm_init_profile,
 607                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 608                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 609                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 610                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 611                 .set_memory_clock = NULL,
 612                 .get_pcie_lanes = NULL,
 613                 .set_pcie_lanes = NULL,
 614                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 615         },
 616         .pflip = {
 617                 .page_flip = &r100_page_flip,
 618                 .page_flip_pending = &r100_page_flip_pending,
 619         },
 620 };
 621
 622 static struct radeon_asic rs600_asic = {
 623         .init = &rs600_init,
 624         .fini = &rs600_fini,
 625         .suspend = &rs600_suspend,
 626         .resume = &rs600_resume,
 627         .vga_set_state = &r100_vga_set_state,
 628         .asic_reset = &rs600_asic_reset,
 629         .mmio_hdp_flush = NULL,
 630         .gui_idle = &r100_gui_idle,
 631         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 632         .gart = {
 633                 .tlb_flush = &rs600_gart_tlb_flush,
 634                 .get_page_entry = &rs600_gart_get_page_entry,
 635                 .set_page = &rs600_gart_set_page,
 636         },
 637         .ring = {
 638                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 639         },
 640         .irq = {
 641                 .set = &rs600_irq_set,
 642                 .process = &rs600_irq_process,
 643         },
 644         .display = {
 645                 .bandwidth_update = &rs600_bandwidth_update,
 646                 .get_vblank_counter = &rs600_get_vblank_counter,
 647                 .wait_for_vblank = &avivo_wait_for_vblank,
 648                 .set_backlight_level = &atombios_set_backlight_level,
 649                 .get_backlight_level = &atombios_get_backlight_level,
 650                 .hdmi_enable = &r600_hdmi_enable,
 651                 .hdmi_setmode = &r600_hdmi_setmode,
 652         },
 653         .copy = {
 654                 .blit = &r100_copy_blit,
 655                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 656                 .dma = &r200_copy_dma,
 657                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 658                 .copy = &r100_copy_blit,
 659                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 660         },
 661         .surface = {
 662                 .set_reg = r100_set_surface_reg,
 663                 .clear_reg = r100_clear_surface_reg,
 664         },
 665         .hpd = {
 666                 .init = &rs600_hpd_init,
 667                 .fini = &rs600_hpd_fini,
 668                 .sense = &rs600_hpd_sense,
 669                 .set_polarity = &rs600_hpd_set_polarity,
 670         },
 671         .pm = {
 672                 .misc = &rs600_pm_misc,
 673                 .prepare = &rs600_pm_prepare,
 674                 .finish = &rs600_pm_finish,
 675                 .init_profile = &r420_pm_init_profile,
 676                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 677                 .get_engine_clock = &radeon_atom_get_engine_clock,
 678                 .set_engine_clock = &radeon_atom_set_engine_clock,
 679                 .get_memory_clock = &radeon_atom_get_memory_clock,
 680                 .set_memory_clock = &radeon_atom_set_memory_clock,
 681                 .get_pcie_lanes = NULL,
 682                 .set_pcie_lanes = NULL,
 683                 .set_clock_gating = &radeon_atom_set_clock_gating,
 684         },
 685         .pflip = {
 686                 .page_flip = &rs600_page_flip,
 687                 .page_flip_pending = &rs600_page_flip_pending,
 688         },
 689 };
 690
 691 static struct radeon_asic rs690_asic = {
 692         .init = &rs690_init,
 693         .fini = &rs690_fini,
 694         .suspend = &rs690_suspend,
 695         .resume = &rs690_resume,
 696         .vga_set_state = &r100_vga_set_state,
 697         .asic_reset = &rs600_asic_reset,
 698         .mmio_hdp_flush = NULL,
 699         .gui_idle = &r100_gui_idle,
 700         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 701         .gart = {
 702                 .tlb_flush = &rs400_gart_tlb_flush,
 703                 .get_page_entry = &rs400_gart_get_page_entry,
 704                 .set_page = &rs400_gart_set_page,
 705         },
 706         .ring = {
 707                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 708         },
 709         .irq = {
 710                 .set = &rs600_irq_set,
 711                 .process = &rs600_irq_process,
 712         },
 713         .display = {
 714                 .get_vblank_counter = &rs600_get_vblank_counter,
 715                 .bandwidth_update = &rs690_bandwidth_update,
 716                 .wait_for_vblank = &avivo_wait_for_vblank,
 717                 .set_backlight_level = &atombios_set_backlight_level,
 718                 .get_backlight_level = &atombios_get_backlight_level,
 719                 .hdmi_enable = &r600_hdmi_enable,
 720                 .hdmi_setmode = &r600_hdmi_setmode,
 721         },
 722         .copy = {
 723                 .blit = &r100_copy_blit,
 724                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 725                 .dma = &r200_copy_dma,
 726                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 727                 .copy = &r200_copy_dma,
 728                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 729         },
 730         .surface = {
 731                 .set_reg = r100_set_surface_reg,
 732                 .clear_reg = r100_clear_surface_reg,
 733         },
 734         .hpd = {
 735                 .init = &rs600_hpd_init,
 736                 .fini = &rs600_hpd_fini,
 737                 .sense = &rs600_hpd_sense,
 738                 .set_polarity = &rs600_hpd_set_polarity,
 739         },
 740         .pm = {
 741                 .misc = &rs600_pm_misc,
 742                 .prepare = &rs600_pm_prepare,
 743                 .finish = &rs600_pm_finish,
 744                 .init_profile = &r420_pm_init_profile,
 745                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 746                 .get_engine_clock = &radeon_atom_get_engine_clock,
 747                 .set_engine_clock = &radeon_atom_set_engine_clock,
 748                 .get_memory_clock = &radeon_atom_get_memory_clock,
 749                 .set_memory_clock = &radeon_atom_set_memory_clock,
 750                 .get_pcie_lanes = NULL,
 751                 .set_pcie_lanes = NULL,
 752                 .set_clock_gating = &radeon_atom_set_clock_gating,
 753         },
 754         .pflip = {
 755                 .page_flip = &rs600_page_flip,
 756                 .page_flip_pending = &rs600_page_flip_pending,
 757         },
 758 };
 759
 760 static struct radeon_asic rv515_asic = {
 761         .init = &rv515_init,
 762         .fini = &rv515_fini,
 763         .suspend = &rv515_suspend,
 764         .resume = &rv515_resume,
 765         .vga_set_state = &r100_vga_set_state,
 766         .asic_reset = &rs600_asic_reset,
 767         .mmio_hdp_flush = NULL,
 768         .gui_idle = &r100_gui_idle,
 769         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 770         .gart = {
 771                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 772                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 773                 .set_page = &rv370_pcie_gart_set_page,
 774         },
 775         .ring = {
 776                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 777         },
 778         .irq = {
 779                 .set = &rs600_irq_set,
 780                 .process = &rs600_irq_process,
 781         },
 782         .display = {
 783                 .get_vblank_counter = &rs600_get_vblank_counter,
 784                 .bandwidth_update = &rv515_bandwidth_update,
 785                 .wait_for_vblank = &avivo_wait_for_vblank,
 786                 .set_backlight_level = &atombios_set_backlight_level,
 787                 .get_backlight_level = &atombios_get_backlight_level,
 788         },
 789         .copy = {
 790                 .blit = &r100_copy_blit,
 791                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 792                 .dma = &r200_copy_dma,
 793                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 794                 .copy = &r100_copy_blit,
 795                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 796         },
 797         .surface = {
 798                 .set_reg = r100_set_surface_reg,
 799                 .clear_reg = r100_clear_surface_reg,
 800         },
 801         .hpd = {
 802                 .init = &rs600_hpd_init,
 803                 .fini = &rs600_hpd_fini,
 804                 .sense = &rs600_hpd_sense,
 805                 .set_polarity = &rs600_hpd_set_polarity,
 806         },
 807         .pm = {
 808                 .misc = &rs600_pm_misc,
 809                 .prepare = &rs600_pm_prepare,
 810                 .finish = &rs600_pm_finish,
 811                 .init_profile = &r420_pm_init_profile,
 812                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 813                 .get_engine_clock = &radeon_atom_get_engine_clock,
 814                 .set_engine_clock = &radeon_atom_set_engine_clock,
 815                 .get_memory_clock = &radeon_atom_get_memory_clock,
 816                 .set_memory_clock = &radeon_atom_set_memory_clock,
 817                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 818                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 819                 .set_clock_gating = &radeon_atom_set_clock_gating,
 820         },
 821         .pflip = {
 822                 .page_flip = &rs600_page_flip,
 823                 .page_flip_pending = &rs600_page_flip_pending,
 824         },
 825 };
 826
 827 static struct radeon_asic r520_asic = {
 828         .init = &r520_init,
 829         .fini = &rv515_fini,
 830         .suspend = &rv515_suspend,
 831         .resume = &r520_resume,
 832         .vga_set_state = &r100_vga_set_state,
 833         .asic_reset = &rs600_asic_reset,
 834         .mmio_hdp_flush = NULL,
 835         .gui_idle = &r100_gui_idle,
 836         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 837         .gart = {
 838                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 839                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 840                 .set_page = &rv370_pcie_gart_set_page,
 841         },
 842         .ring = {
 843                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 844         },
 845         .irq = {
 846                 .set = &rs600_irq_set,
 847                 .process = &rs600_irq_process,
 848         },
 849         .display = {
 850                 .bandwidth_update = &rv515_bandwidth_update,
 851                 .get_vblank_counter = &rs600_get_vblank_counter,
 852                 .wait_for_vblank = &avivo_wait_for_vblank,
 853                 .set_backlight_level = &atombios_set_backlight_level,
 854                 .get_backlight_level = &atombios_get_backlight_level,
 855         },
 856         .copy = {
 857                 .blit = &r100_copy_blit,
 858                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 859                 .dma = &r200_copy_dma,
 860                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 861                 .copy = &r100_copy_blit,
 862                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 863         },
 864         .surface = {
 865                 .set_reg = r100_set_surface_reg,
 866                 .clear_reg = r100_clear_surface_reg,
 867         },
 868         .hpd = {
 869                 .init = &rs600_hpd_init,
 870                 .fini = &rs600_hpd_fini,
 871                 .sense = &rs600_hpd_sense,
 872                 .set_polarity = &rs600_hpd_set_polarity,
 873         },
 874         .pm = {
 875                 .misc = &rs600_pm_misc,
 876                 .prepare = &rs600_pm_prepare,
 877                 .finish = &rs600_pm_finish,
 878                 .init_profile = &r420_pm_init_profile,
 879                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 880                 .get_engine_clock = &radeon_atom_get_engine_clock,
 881                 .set_engine_clock = &radeon_atom_set_engine_clock,
 882                 .get_memory_clock = &radeon_atom_get_memory_clock,
 883                 .set_memory_clock = &radeon_atom_set_memory_clock,
 884                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 885                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 886                 .set_clock_gating = &radeon_atom_set_clock_gating,
 887         },
 888         .pflip = {
 889                 .page_flip = &rs600_page_flip,
 890                 .page_flip_pending = &rs600_page_flip_pending,
 891         },
 892 };
 893
 894 static struct radeon_asic_ring r600_gfx_ring = {
 895         .ib_execute = &r600_ring_ib_execute,
 896         .emit_fence = &r600_fence_ring_emit,
 897         .emit_semaphore = &r600_semaphore_ring_emit,
 898         .cs_parse = &r600_cs_parse,
 899         .ring_test = &r600_ring_test,
 900         .ib_test = &r600_ib_test,
 901         .is_lockup = &r600_gfx_is_lockup,
 902         .get_rptr = &r600_gfx_get_rptr,
 903         .get_wptr = &r600_gfx_get_wptr,
 904         .set_wptr = &r600_gfx_set_wptr,
 905 };
 906
 907 static struct radeon_asic_ring r600_dma_ring = {
 908         .ib_execute = &r600_dma_ring_ib_execute,
 909         .emit_fence = &r600_dma_fence_ring_emit,
 910         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 911         .cs_parse = &r600_dma_cs_parse,
 912         .ring_test = &r600_dma_ring_test,
 913         .ib_test = &r600_dma_ib_test,
 914         .is_lockup = &r600_dma_is_lockup,
 915         .get_rptr = &r600_dma_get_rptr,
 916         .get_wptr = &r600_dma_get_wptr,
 917         .set_wptr = &r600_dma_set_wptr,
 918 };
 919
 920 static struct radeon_asic r600_asic = {
 921         .init = &r600_init,
 922         .fini = &r600_fini,
 923         .suspend = &r600_suspend,
 924         .resume = &r600_resume,
 925         .vga_set_state = &r600_vga_set_state,
 926         .asic_reset = &r600_asic_reset,
 927         .mmio_hdp_flush = r600_mmio_hdp_flush,
 928         .gui_idle = &r600_gui_idle,
 929         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 930         .get_xclk = &r600_get_xclk,
 931         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 932         .gart = {
 933                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 934                 .get_page_entry = &rs600_gart_get_page_entry,
 935                 .set_page = &rs600_gart_set_page,
 936         },
 937         .ring = {
 938                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 939                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 940         },
 941         .irq = {
 942                 .set = &r600_irq_set,
 943                 .process = &r600_irq_process,
 944         },
 945         .display = {
 946                 .bandwidth_update = &rv515_bandwidth_update,
 947                 .get_vblank_counter = &rs600_get_vblank_counter,
 948                 .wait_for_vblank = &avivo_wait_for_vblank,
 949                 .set_backlight_level = &atombios_set_backlight_level,
 950                 .get_backlight_level = &atombios_get_backlight_level,
 951                 .hdmi_enable = &r600_hdmi_enable,
 952                 .hdmi_setmode = &r600_hdmi_setmode,
 953         },
 954         .copy = {
 955                 .blit = &r600_copy_cpdma,
 956                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 957                 .dma = &r600_copy_dma,
 958                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 959                 .copy = &r600_copy_cpdma,
 960                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 961         },
 962         .surface = {
 963                 .set_reg = r600_set_surface_reg,
 964                 .clear_reg = r600_clear_surface_reg,
 965         },
 966         .hpd = {
 967                 .init = &r600_hpd_init,
 968                 .fini = &r600_hpd_fini,
 969                 .sense = &r600_hpd_sense,
 970                 .set_polarity = &r600_hpd_set_polarity,
 971         },
 972         .pm = {
 973                 .misc = &r600_pm_misc,
 974                 .prepare = &rs600_pm_prepare,
 975                 .finish = &rs600_pm_finish,
 976                 .init_profile = &r600_pm_init_profile,
 977                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 978                 .get_engine_clock = &radeon_atom_get_engine_clock,
 979                 .set_engine_clock = &radeon_atom_set_engine_clock,
 980                 .get_memory_clock = &radeon_atom_get_memory_clock,
 981                 .set_memory_clock = &radeon_atom_set_memory_clock,
 982                 .get_pcie_lanes = &r600_get_pcie_lanes,
 983                 .set_pcie_lanes = &r600_set_pcie_lanes,
 984                 .set_clock_gating = NULL,
 985                 .get_temperature = &rv6xx_get_temp,
 986         },
 987         .pflip = {
 988                 .page_flip = &rs600_page_flip,
 989                 .page_flip_pending = &rs600_page_flip_pending,
 990         },
 991 };
 992
 993 static struct radeon_asic_ring rv6xx_uvd_ring = {
 994         .ib_execute = &uvd_v1_0_ib_execute,
 995         .emit_fence = &uvd_v1_0_fence_emit,
 996         .emit_semaphore = &uvd_v1_0_semaphore_emit,
 997         .cs_parse = &radeon_uvd_cs_parse,
 998         .ring_test = &uvd_v1_0_ring_test,
 999         .ib_test = &uvd_v1_0_ib_test,
1000         .is_lockup = &radeon_ring_test_lockup,
1001         .get_rptr = &uvd_v1_0_get_rptr,
1002         .get_wptr = &uvd_v1_0_get_wptr,
1003         .set_wptr = &uvd_v1_0_set_wptr,
1004 };
1005
1006 static struct radeon_asic rv6xx_asic = {
1007         .init = &r600_init,
1008         .fini = &r600_fini,
1009         .suspend = &r600_suspend,
1010         .resume = &r600_resume,
1011         .vga_set_state = &r600_vga_set_state,
1012         .asic_reset = &r600_asic_reset,
1013         .mmio_hdp_flush = r600_mmio_hdp_flush,
1014         .gui_idle = &r600_gui_idle,
1015         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1016         .get_xclk = &r600_get_xclk,
1017         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1018         .gart = {
1019                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1020                 .get_page_entry = &rs600_gart_get_page_entry,
1021                 .set_page = &rs600_gart_set_page,
1022         },
1023         .ring = {
1024                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1025                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1026                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1027         },
1028         .irq = {
1029                 .set = &r600_irq_set,
1030                 .process = &r600_irq_process,
1031         },
1032         .display = {
1033                 .bandwidth_update = &rv515_bandwidth_update,
1034                 .get_vblank_counter = &rs600_get_vblank_counter,
1035                 .wait_for_vblank = &avivo_wait_for_vblank,
1036                 .set_backlight_level = &atombios_set_backlight_level,
1037                 .get_backlight_level = &atombios_get_backlight_level,
1038                 .hdmi_enable = &r600_hdmi_enable,
1039                 .hdmi_setmode = &r600_hdmi_setmode,
1040         },
1041         .copy = {
1042                 .blit = &r600_copy_cpdma,
1043                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1044                 .dma = &r600_copy_dma,
1045                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1046                 .copy = &r600_copy_cpdma,
1047                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1048         },
1049         .surface = {
1050                 .set_reg = r600_set_surface_reg,
1051                 .clear_reg = r600_clear_surface_reg,
1052         },
1053         .hpd = {
1054                 .init = &r600_hpd_init,
1055                 .fini = &r600_hpd_fini,
1056                 .sense = &r600_hpd_sense,
1057                 .set_polarity = &r600_hpd_set_polarity,
1058         },
1059         .pm = {
1060                 .misc = &r600_pm_misc,
1061                 .prepare = &rs600_pm_prepare,
1062                 .finish = &rs600_pm_finish,
1063                 .init_profile = &r600_pm_init_profile,
1064                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1065                 .get_engine_clock = &radeon_atom_get_engine_clock,
1066                 .set_engine_clock = &radeon_atom_set_engine_clock,
1067                 .get_memory_clock = &radeon_atom_get_memory_clock,
1068                 .set_memory_clock = &radeon_atom_set_memory_clock,
1069                 .get_pcie_lanes = &r600_get_pcie_lanes,
1070                 .set_pcie_lanes = &r600_set_pcie_lanes,
1071                 .set_clock_gating = NULL,
1072                 .get_temperature = &rv6xx_get_temp,
1073                 .set_uvd_clocks = &r600_set_uvd_clocks,
1074         },
1075         .dpm = {
1076                 .init = &rv6xx_dpm_init,
1077                 .setup_asic = &rv6xx_setup_asic,
1078                 .enable = &rv6xx_dpm_enable,
1079                 .late_enable = &r600_dpm_late_enable,
1080                 .disable = &rv6xx_dpm_disable,
1081                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1082                 .set_power_state = &rv6xx_dpm_set_power_state,
1083                 .post_set_power_state = &r600_dpm_post_set_power_state,
1084                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1085                 .fini = &rv6xx_dpm_fini,
1086                 .get_sclk = &rv6xx_dpm_get_sclk,
1087                 .get_mclk = &rv6xx_dpm_get_mclk,
1088                 .print_power_state = &rv6xx_dpm_print_power_state,
1089                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1090                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1091         },
1092         .pflip = {
1093                 .page_flip = &rs600_page_flip,
1094                 .page_flip_pending = &rs600_page_flip_pending,
1095         },
1096 };
1097
1098 static struct radeon_asic rs780_asic = {
1099         .init = &r600_init,
1100         .fini = &r600_fini,
1101         .suspend = &r600_suspend,
1102         .resume = &r600_resume,
1103         .vga_set_state = &r600_vga_set_state,
1104         .asic_reset = &r600_asic_reset,
1105         .mmio_hdp_flush = r600_mmio_hdp_flush,
1106         .gui_idle = &r600_gui_idle,
1107         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1108         .get_xclk = &r600_get_xclk,
1109         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1110         .gart = {
1111                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1112                 .get_page_entry = &rs600_gart_get_page_entry,
1113                 .set_page = &rs600_gart_set_page,
1114         },
1115         .ring = {
1116                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1117                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1118                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1119         },
1120         .irq = {
1121                 .set = &r600_irq_set,
1122                 .process = &r600_irq_process,
1123         },
1124         .display = {
1125                 .bandwidth_update = &rs690_bandwidth_update,
1126                 .get_vblank_counter = &rs600_get_vblank_counter,
1127                 .wait_for_vblank = &avivo_wait_for_vblank,
1128                 .set_backlight_level = &atombios_set_backlight_level,
1129                 .get_backlight_level = &atombios_get_backlight_level,
1130                 .hdmi_enable = &r600_hdmi_enable,
1131                 .hdmi_setmode = &r600_hdmi_setmode,
1132         },
1133         .copy = {
1134                 .blit = &r600_copy_cpdma,
1135                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1136                 .dma = &r600_copy_dma,
1137                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1138                 .copy = &r600_copy_cpdma,
1139                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1140         },
1141         .surface = {
1142                 .set_reg = r600_set_surface_reg,
1143                 .clear_reg = r600_clear_surface_reg,
1144         },
1145         .hpd = {
1146                 .init = &r600_hpd_init,
1147                 .fini = &r600_hpd_fini,
1148                 .sense = &r600_hpd_sense,
1149                 .set_polarity = &r600_hpd_set_polarity,
1150         },
1151         .pm = {
1152                 .misc = &r600_pm_misc,
1153                 .prepare = &rs600_pm_prepare,
1154                 .finish = &rs600_pm_finish,
1155                 .init_profile = &rs780_pm_init_profile,
1156                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1157                 .get_engine_clock = &radeon_atom_get_engine_clock,
1158                 .set_engine_clock = &radeon_atom_set_engine_clock,
1159                 .get_memory_clock = NULL,
1160                 .set_memory_clock = NULL,
1161                 .get_pcie_lanes = NULL,
1162                 .set_pcie_lanes = NULL,
1163                 .set_clock_gating = NULL,
1164                 .get_temperature = &rv6xx_get_temp,
1165                 .set_uvd_clocks = &r600_set_uvd_clocks,
1166         },
1167         .dpm = {
1168                 .init = &rs780_dpm_init,
1169                 .setup_asic = &rs780_dpm_setup_asic,
1170                 .enable = &rs780_dpm_enable,
1171                 .late_enable = &r600_dpm_late_enable,
1172                 .disable = &rs780_dpm_disable,
1173                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1174                 .set_power_state = &rs780_dpm_set_power_state,
1175                 .post_set_power_state = &r600_dpm_post_set_power_state,
1176                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1177                 .fini = &rs780_dpm_fini,
1178                 .get_sclk = &rs780_dpm_get_sclk,
1179                 .get_mclk = &rs780_dpm_get_mclk,
1180                 .print_power_state = &rs780_dpm_print_power_state,
1181                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1182                 .force_performance_level = &rs780_dpm_force_performance_level,
1183         },
1184         .pflip = {
1185                 .page_flip = &rs600_page_flip,
1186                 .page_flip_pending = &rs600_page_flip_pending,
1187         },
1188 };
1189
1190 static struct radeon_asic_ring rv770_uvd_ring = {
1191         .ib_execute = &uvd_v1_0_ib_execute,
1192         .emit_fence = &uvd_v2_2_fence_emit,
1193         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1194         .cs_parse = &radeon_uvd_cs_parse,
1195         .ring_test = &uvd_v1_0_ring_test,
1196         .ib_test = &uvd_v1_0_ib_test,
1197         .is_lockup = &radeon_ring_test_lockup,
1198         .get_rptr = &uvd_v1_0_get_rptr,
1199         .get_wptr = &uvd_v1_0_get_wptr,
1200         .set_wptr = &uvd_v1_0_set_wptr,
1201 };
1202
1203 static struct radeon_asic rv770_asic = {
1204         .init = &rv770_init,
1205         .fini = &rv770_fini,
1206         .suspend = &rv770_suspend,
1207         .resume = &rv770_resume,
1208         .asic_reset = &r600_asic_reset,
1209         .vga_set_state = &r600_vga_set_state,
1210         .mmio_hdp_flush = r600_mmio_hdp_flush,
1211         .gui_idle = &r600_gui_idle,
1212         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1213         .get_xclk = &rv770_get_xclk,
1214         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1215         .gart = {
1216                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1217                 .get_page_entry = &rs600_gart_get_page_entry,
1218                 .set_page = &rs600_gart_set_page,
1219         },
1220         .ring = {
1221                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1222                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1223                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1224         },
1225         .irq = {
1226                 .set = &r600_irq_set,
1227                 .process = &r600_irq_process,
1228         },
1229         .display = {
1230                 .bandwidth_update = &rv515_bandwidth_update,
1231                 .get_vblank_counter = &rs600_get_vblank_counter,
1232                 .wait_for_vblank = &avivo_wait_for_vblank,
1233                 .set_backlight_level = &atombios_set_backlight_level,
1234                 .get_backlight_level = &atombios_get_backlight_level,
1235                 .hdmi_enable = &r600_hdmi_enable,
1236                 .hdmi_setmode = &dce3_1_hdmi_setmode,
1237         },
1238         .copy = {
1239                 .blit = &r600_copy_cpdma,
1240                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1241                 .dma = &rv770_copy_dma,
1242                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1243                 .copy = &rv770_copy_dma,
1244                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1245         },
1246         .surface = {
1247                 .set_reg = r600_set_surface_reg,
1248                 .clear_reg = r600_clear_surface_reg,
1249         },
1250         .hpd = {
1251                 .init = &r600_hpd_init,
1252                 .fini = &r600_hpd_fini,
1253                 .sense = &r600_hpd_sense,
1254                 .set_polarity = &r600_hpd_set_polarity,
1255         },
1256         .pm = {
1257                 .misc = &rv770_pm_misc,
1258                 .prepare = &rs600_pm_prepare,
1259                 .finish = &rs600_pm_finish,
1260                 .init_profile = &r600_pm_init_profile,
1261                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1262                 .get_engine_clock = &radeon_atom_get_engine_clock,
1263                 .set_engine_clock = &radeon_atom_set_engine_clock,
1264                 .get_memory_clock = &radeon_atom_get_memory_clock,
1265                 .set_memory_clock = &radeon_atom_set_memory_clock,
1266                 .get_pcie_lanes = &r600_get_pcie_lanes,
1267                 .set_pcie_lanes = &r600_set_pcie_lanes,
1268                 .set_clock_gating = &radeon_atom_set_clock_gating,
1269                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1270                 .get_temperature = &rv770_get_temp,
1271         },
1272         .dpm = {
1273                 .init = &rv770_dpm_init,
1274                 .setup_asic = &rv770_dpm_setup_asic,
1275                 .enable = &rv770_dpm_enable,
1276                 .late_enable = &rv770_dpm_late_enable,
1277                 .disable = &rv770_dpm_disable,
1278                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1279                 .set_power_state = &rv770_dpm_set_power_state,
1280                 .post_set_power_state = &r600_dpm_post_set_power_state,
1281                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1282                 .fini = &rv770_dpm_fini,
1283                 .get_sclk = &rv770_dpm_get_sclk,
1284                 .get_mclk = &rv770_dpm_get_mclk,
1285                 .print_power_state = &rv770_dpm_print_power_state,
1286                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1287                 .force_performance_level = &rv770_dpm_force_performance_level,
1288                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1289         },
1290         .pflip = {
1291                 .page_flip = &rv770_page_flip,
1292                 .page_flip_pending = &rv770_page_flip_pending,
1293         },
1294 };
1295
1296 static struct radeon_asic_ring evergreen_gfx_ring = {
1297         .ib_execute = &evergreen_ring_ib_execute,
1298         .emit_fence = &r600_fence_ring_emit,
1299         .emit_semaphore = &r600_semaphore_ring_emit,
1300         .cs_parse = &evergreen_cs_parse,
1301         .ring_test = &r600_ring_test,
1302         .ib_test = &r600_ib_test,
1303         .is_lockup = &evergreen_gfx_is_lockup,
1304         .get_rptr = &r600_gfx_get_rptr,
1305         .get_wptr = &r600_gfx_get_wptr,
1306         .set_wptr = &r600_gfx_set_wptr,
1307 };
1308
1309 static struct radeon_asic_ring evergreen_dma_ring = {
1310         .ib_execute = &evergreen_dma_ring_ib_execute,
1311         .emit_fence = &evergreen_dma_fence_ring_emit,
1312         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1313         .cs_parse = &evergreen_dma_cs_parse,
1314         .ring_test = &r600_dma_ring_test,
1315         .ib_test = &r600_dma_ib_test,
1316         .is_lockup = &evergreen_dma_is_lockup,
1317         .get_rptr = &r600_dma_get_rptr,
1318         .get_wptr = &r600_dma_get_wptr,
1319         .set_wptr = &r600_dma_set_wptr,
1320 };
1321
1322 static struct radeon_asic evergreen_asic = {
1323         .init = &evergreen_init,
1324         .fini = &evergreen_fini,
1325         .suspend = &evergreen_suspend,
1326         .resume = &evergreen_resume,
1327         .asic_reset = &evergreen_asic_reset,
1328         .vga_set_state = &r600_vga_set_state,
1329         .mmio_hdp_flush = r600_mmio_hdp_flush,
1330         .gui_idle = &r600_gui_idle,
1331         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1332         .get_xclk = &rv770_get_xclk,
1333         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1334         .gart = {
1335                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1336                 .get_page_entry = &rs600_gart_get_page_entry,
1337                 .set_page = &rs600_gart_set_page,
1338         },
1339         .ring = {
1340                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1341                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1342                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1343         },
1344         .irq = {
1345                 .set = &evergreen_irq_set,
1346                 .process = &evergreen_irq_process,
1347         },
1348         .display = {
1349                 .bandwidth_update = &evergreen_bandwidth_update,
1350                 .get_vblank_counter = &evergreen_get_vblank_counter,
1351                 .wait_for_vblank = &dce4_wait_for_vblank,
1352                 .set_backlight_level = &atombios_set_backlight_level,
1353                 .get_backlight_level = &atombios_get_backlight_level,
1354                 .hdmi_enable = &evergreen_hdmi_enable,
1355                 .hdmi_setmode = &evergreen_hdmi_setmode,
1356         },
1357         .copy = {
1358                 .blit = &r600_copy_cpdma,
1359                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1360                 .dma = &evergreen_copy_dma,
1361                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1362                 .copy = &evergreen_copy_dma,
1363                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1364         },
1365         .surface = {
1366                 .set_reg = r600_set_surface_reg,
1367                 .clear_reg = r600_clear_surface_reg,
1368         },
1369         .hpd = {
1370                 .init = &evergreen_hpd_init,
1371                 .fini = &evergreen_hpd_fini,
1372                 .sense = &evergreen_hpd_sense,
1373                 .set_polarity = &evergreen_hpd_set_polarity,
1374         },
1375         .pm = {
1376                 .misc = &evergreen_pm_misc,
1377                 .prepare = &evergreen_pm_prepare,
1378                 .finish = &evergreen_pm_finish,
1379                 .init_profile = &r600_pm_init_profile,
1380                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1381                 .get_engine_clock = &radeon_atom_get_engine_clock,
1382                 .set_engine_clock = &radeon_atom_set_engine_clock,
1383                 .get_memory_clock = &radeon_atom_get_memory_clock,
1384                 .set_memory_clock = &radeon_atom_set_memory_clock,
1385                 .get_pcie_lanes = &r600_get_pcie_lanes,
1386                 .set_pcie_lanes = &r600_set_pcie_lanes,
1387                 .set_clock_gating = NULL,
1388                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1389                 .get_temperature = &evergreen_get_temp,
1390         },
1391         .dpm = {
1392                 .init = &cypress_dpm_init,
1393                 .setup_asic = &cypress_dpm_setup_asic,
1394                 .enable = &cypress_dpm_enable,
1395                 .late_enable = &rv770_dpm_late_enable,
1396                 .disable = &cypress_dpm_disable,
1397                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1398                 .set_power_state = &cypress_dpm_set_power_state,
1399                 .post_set_power_state = &r600_dpm_post_set_power_state,
1400                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1401                 .fini = &cypress_dpm_fini,
1402                 .get_sclk = &rv770_dpm_get_sclk,
1403                 .get_mclk = &rv770_dpm_get_mclk,
1404                 .print_power_state = &rv770_dpm_print_power_state,
1405                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1406                 .force_performance_level = &rv770_dpm_force_performance_level,
1407                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1408         },
1409         .pflip = {
1410                 .page_flip = &evergreen_page_flip,
1411                 .page_flip_pending = &evergreen_page_flip_pending,
1412         },
1413 };
1414
1415 static struct radeon_asic sumo_asic = {
1416         .init = &evergreen_init,
1417         .fini = &evergreen_fini,
1418         .suspend = &evergreen_suspend,
1419         .resume = &evergreen_resume,
1420         .asic_reset = &evergreen_asic_reset,
1421         .vga_set_state = &r600_vga_set_state,
1422         .mmio_hdp_flush = r600_mmio_hdp_flush,
1423         .gui_idle = &r600_gui_idle,
1424         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1425         .get_xclk = &r600_get_xclk,
1426         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1427         .gart = {
1428                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1429                 .get_page_entry = &rs600_gart_get_page_entry,
1430                 .set_page = &rs600_gart_set_page,
1431         },
1432         .ring = {
1433                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1434                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1435                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1436         },
1437         .irq = {
1438                 .set = &evergreen_irq_set,
1439                 .process = &evergreen_irq_process,
1440         },
1441         .display = {
1442                 .bandwidth_update = &evergreen_bandwidth_update,
1443                 .get_vblank_counter = &evergreen_get_vblank_counter,
1444                 .wait_for_vblank = &dce4_wait_for_vblank,
1445                 .set_backlight_level = &atombios_set_backlight_level,
1446                 .get_backlight_level = &atombios_get_backlight_level,
1447                 .hdmi_enable = &evergreen_hdmi_enable,
1448                 .hdmi_setmode = &evergreen_hdmi_setmode,
1449         },
1450         .copy = {
1451                 .blit = &r600_copy_cpdma,
1452                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1453                 .dma = &evergreen_copy_dma,
1454                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1455                 .copy = &evergreen_copy_dma,
1456                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1457         },
1458         .surface = {
1459                 .set_reg = r600_set_surface_reg,
1460                 .clear_reg = r600_clear_surface_reg,
1461         },
1462         .hpd = {
1463                 .init = &evergreen_hpd_init,
1464                 .fini = &evergreen_hpd_fini,
1465                 .sense = &evergreen_hpd_sense,
1466                 .set_polarity = &evergreen_hpd_set_polarity,
1467         },
1468         .pm = {
1469                 .misc = &evergreen_pm_misc,
1470                 .prepare = &evergreen_pm_prepare,
1471                 .finish = &evergreen_pm_finish,
1472                 .init_profile = &sumo_pm_init_profile,
1473                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1474                 .get_engine_clock = &radeon_atom_get_engine_clock,
1475                 .set_engine_clock = &radeon_atom_set_engine_clock,
1476                 .get_memory_clock = NULL,
1477                 .set_memory_clock = NULL,
1478                 .get_pcie_lanes = NULL,
1479                 .set_pcie_lanes = NULL,
1480                 .set_clock_gating = NULL,
1481                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1482                 .get_temperature = &sumo_get_temp,
1483         },
1484         .dpm = {
1485                 .init = &sumo_dpm_init,
1486                 .setup_asic = &sumo_dpm_setup_asic,
1487                 .enable = &sumo_dpm_enable,
1488                 .late_enable = &sumo_dpm_late_enable,
1489                 .disable = &sumo_dpm_disable,
1490                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1491                 .set_power_state = &sumo_dpm_set_power_state,
1492                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1493                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1494                 .fini = &sumo_dpm_fini,
1495                 .get_sclk = &sumo_dpm_get_sclk,
1496                 .get_mclk = &sumo_dpm_get_mclk,
1497                 .print_power_state = &sumo_dpm_print_power_state,
1498                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1499                 .force_performance_level = &sumo_dpm_force_performance_level,
1500         },
1501         .pflip = {
1502                 .page_flip = &evergreen_page_flip,
1503                 .page_flip_pending = &evergreen_page_flip_pending,
1504         },
1505 };
1506
1507 static struct radeon_asic btc_asic = {
1508         .init = &evergreen_init,
1509         .fini = &evergreen_fini,
1510         .suspend = &evergreen_suspend,
1511         .resume = &evergreen_resume,
1512         .asic_reset = &evergreen_asic_reset,
1513         .vga_set_state = &r600_vga_set_state,
1514         .mmio_hdp_flush = r600_mmio_hdp_flush,
1515         .gui_idle = &r600_gui_idle,
1516         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1517         .get_xclk = &rv770_get_xclk,
1518         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1519         .gart = {
1520                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1521                 .get_page_entry = &rs600_gart_get_page_entry,
1522                 .set_page = &rs600_gart_set_page,
1523         },
1524         .ring = {
1525                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1526                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1527                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1528         },
1529         .irq = {
1530                 .set = &evergreen_irq_set,
1531                 .process = &evergreen_irq_process,
1532         },
1533         .display = {
1534                 .bandwidth_update = &evergreen_bandwidth_update,
1535                 .get_vblank_counter = &evergreen_get_vblank_counter,
1536                 .wait_for_vblank = &dce4_wait_for_vblank,
1537                 .set_backlight_level = &atombios_set_backlight_level,
1538                 .get_backlight_level = &atombios_get_backlight_level,
1539                 .hdmi_enable = &evergreen_hdmi_enable,
1540                 .hdmi_setmode = &evergreen_hdmi_setmode,
1541         },
1542         .copy = {
1543                 .blit = &r600_copy_cpdma,
1544                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1545                 .dma = &evergreen_copy_dma,
1546                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1547                 .copy = &evergreen_copy_dma,
1548                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1549         },
1550         .surface = {
1551                 .set_reg = r600_set_surface_reg,
1552                 .clear_reg = r600_clear_surface_reg,
1553         },
1554         .hpd = {
1555                 .init = &evergreen_hpd_init,
1556                 .fini = &evergreen_hpd_fini,
1557                 .sense = &evergreen_hpd_sense,
1558                 .set_polarity = &evergreen_hpd_set_polarity,
1559         },
1560         .pm = {
1561                 .misc = &evergreen_pm_misc,
1562                 .prepare = &evergreen_pm_prepare,
1563                 .finish = &evergreen_pm_finish,
1564                 .init_profile = &btc_pm_init_profile,
1565                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1566                 .get_engine_clock = &radeon_atom_get_engine_clock,
1567                 .set_engine_clock = &radeon_atom_set_engine_clock,
1568                 .get_memory_clock = &radeon_atom_get_memory_clock,
1569                 .set_memory_clock = &radeon_atom_set_memory_clock,
1570                 .get_pcie_lanes = &r600_get_pcie_lanes,
1571                 .set_pcie_lanes = &r600_set_pcie_lanes,
1572                 .set_clock_gating = NULL,
1573                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1574                 .get_temperature = &evergreen_get_temp,
1575         },
1576         .dpm = {
1577                 .init = &btc_dpm_init,
1578                 .setup_asic = &btc_dpm_setup_asic,
1579                 .enable = &btc_dpm_enable,
1580                 .late_enable = &rv770_dpm_late_enable,
1581                 .disable = &btc_dpm_disable,
1582                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1583                 .set_power_state = &btc_dpm_set_power_state,
1584                 .post_set_power_state = &btc_dpm_post_set_power_state,
1585                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1586                 .fini = &btc_dpm_fini,
1587                 .get_sclk = &btc_dpm_get_sclk,
1588                 .get_mclk = &btc_dpm_get_mclk,
1589                 .print_power_state = &rv770_dpm_print_power_state,
1590                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1591                 .force_performance_level = &rv770_dpm_force_performance_level,
1592                 .vblank_too_short = &btc_dpm_vblank_too_short,
1593         },
1594         .pflip = {
1595                 .page_flip = &evergreen_page_flip,
1596                 .page_flip_pending = &evergreen_page_flip_pending,
1597         },
1598 };
1599
1600 static struct radeon_asic_ring cayman_gfx_ring = {
1601         .ib_execute = &cayman_ring_ib_execute,
1602         .ib_parse = &evergreen_ib_parse,
1603         .emit_fence = &cayman_fence_ring_emit,
1604         .emit_semaphore = &r600_semaphore_ring_emit,
1605         .cs_parse = &evergreen_cs_parse,
1606         .ring_test = &r600_ring_test,
1607         .ib_test = &r600_ib_test,
1608         .is_lockup = &cayman_gfx_is_lockup,
1609         .vm_flush = &cayman_vm_flush,
1610         .get_rptr = &cayman_gfx_get_rptr,
1611         .get_wptr = &cayman_gfx_get_wptr,
1612         .set_wptr = &cayman_gfx_set_wptr,
1613 };
1614
1615 static struct radeon_asic_ring cayman_dma_ring = {
1616         .ib_execute = &cayman_dma_ring_ib_execute,
1617         .ib_parse = &evergreen_dma_ib_parse,
1618         .emit_fence = &evergreen_dma_fence_ring_emit,
1619         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1620         .cs_parse = &evergreen_dma_cs_parse,
1621         .ring_test = &r600_dma_ring_test,
1622         .ib_test = &r600_dma_ib_test,
1623         .is_lockup = &cayman_dma_is_lockup,
1624         .vm_flush = &cayman_dma_vm_flush,
1625         .get_rptr = &cayman_dma_get_rptr,
1626         .get_wptr = &cayman_dma_get_wptr,
1627         .set_wptr = &cayman_dma_set_wptr
1628 };
1629
1630 static struct radeon_asic_ring cayman_uvd_ring = {
1631         .ib_execute = &uvd_v1_0_ib_execute,
1632         .emit_fence = &uvd_v2_2_fence_emit,
1633         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1634         .cs_parse = &radeon_uvd_cs_parse,
1635         .ring_test = &uvd_v1_0_ring_test,
1636         .ib_test = &uvd_v1_0_ib_test,
1637         .is_lockup = &radeon_ring_test_lockup,
1638         .get_rptr = &uvd_v1_0_get_rptr,
1639         .get_wptr = &uvd_v1_0_get_wptr,
1640         .set_wptr = &uvd_v1_0_set_wptr,
1641 };
1642
1643 static struct radeon_asic cayman_asic = {
1644         .init = &cayman_init,
1645         .fini = &cayman_fini,
1646         .suspend = &cayman_suspend,
1647         .resume = &cayman_resume,
1648         .asic_reset = &cayman_asic_reset,
1649         .vga_set_state = &r600_vga_set_state,
1650         .mmio_hdp_flush = r600_mmio_hdp_flush,
1651         .gui_idle = &r600_gui_idle,
1652         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1653         .get_xclk = &rv770_get_xclk,
1654         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1655         .gart = {
1656                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1657                 .get_page_entry = &rs600_gart_get_page_entry,
1658                 .set_page = &rs600_gart_set_page,
1659         },
1660         .vm = {
1661                 .init = &cayman_vm_init,
1662                 .fini = &cayman_vm_fini,
1663                 .copy_pages = &cayman_dma_vm_copy_pages,
1664                 .write_pages = &cayman_dma_vm_write_pages,
1665                 .set_pages = &cayman_dma_vm_set_pages,
1666                 .pad_ib = &cayman_dma_vm_pad_ib,
1667         },
1668         .ring = {
1669                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1670                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1671                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1672                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1673                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1674                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1675         },
1676         .irq = {
1677                 .set = &evergreen_irq_set,
1678                 .process = &evergreen_irq_process,
1679         },
1680         .display = {
1681                 .bandwidth_update = &evergreen_bandwidth_update,
1682                 .get_vblank_counter = &evergreen_get_vblank_counter,
1683                 .wait_for_vblank = &dce4_wait_for_vblank,
1684                 .set_backlight_level = &atombios_set_backlight_level,
1685                 .get_backlight_level = &atombios_get_backlight_level,
1686                 .hdmi_enable = &evergreen_hdmi_enable,
1687                 .hdmi_setmode = &evergreen_hdmi_setmode,
1688         },
1689         .copy = {
1690                 .blit = &r600_copy_cpdma,
1691                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1692                 .dma = &evergreen_copy_dma,
1693                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1694                 .copy = &evergreen_copy_dma,
1695                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1696         },
1697         .surface = {
1698                 .set_reg = r600_set_surface_reg,
1699                 .clear_reg = r600_clear_surface_reg,
1700         },
1701         .hpd = {
1702                 .init = &evergreen_hpd_init,
1703                 .fini = &evergreen_hpd_fini,
1704                 .sense = &evergreen_hpd_sense,
1705                 .set_polarity = &evergreen_hpd_set_polarity,
1706         },
1707         .pm = {
1708                 .misc = &evergreen_pm_misc,
1709                 .prepare = &evergreen_pm_prepare,
1710                 .finish = &evergreen_pm_finish,
1711                 .init_profile = &btc_pm_init_profile,
1712                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1713                 .get_engine_clock = &radeon_atom_get_engine_clock,
1714                 .set_engine_clock = &radeon_atom_set_engine_clock,
1715                 .get_memory_clock = &radeon_atom_get_memory_clock,
1716                 .set_memory_clock = &radeon_atom_set_memory_clock,
1717                 .get_pcie_lanes = &r600_get_pcie_lanes,
1718                 .set_pcie_lanes = &r600_set_pcie_lanes,
1719                 .set_clock_gating = NULL,
1720                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1721                 .get_temperature = &evergreen_get_temp,
1722         },
1723         .dpm = {
1724                 .init = &ni_dpm_init,
1725                 .setup_asic = &ni_dpm_setup_asic,
1726                 .enable = &ni_dpm_enable,
1727                 .late_enable = &rv770_dpm_late_enable,
1728                 .disable = &ni_dpm_disable,
1729                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1730                 .set_power_state = &ni_dpm_set_power_state,
1731                 .post_set_power_state = &ni_dpm_post_set_power_state,
1732                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1733                 .fini = &ni_dpm_fini,
1734                 .get_sclk = &ni_dpm_get_sclk,
1735                 .get_mclk = &ni_dpm_get_mclk,
1736                 .print_power_state = &ni_dpm_print_power_state,
1737                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1738                 .force_performance_level = &ni_dpm_force_performance_level,
1739                 .vblank_too_short = &ni_dpm_vblank_too_short,
1740         },
1741         .pflip = {
1742                 .page_flip = &evergreen_page_flip,
1743                 .page_flip_pending = &evergreen_page_flip_pending,
1744         },
1745 };
1746
1747 static struct radeon_asic trinity_asic = {
1748         .init = &cayman_init,
1749         .fini = &cayman_fini,
1750         .suspend = &cayman_suspend,
1751         .resume = &cayman_resume,
1752         .asic_reset = &cayman_asic_reset,
1753         .vga_set_state = &r600_vga_set_state,
1754         .mmio_hdp_flush = r600_mmio_hdp_flush,
1755         .gui_idle = &r600_gui_idle,
1756         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1757         .get_xclk = &r600_get_xclk,
1758         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1759         .gart = {
1760                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1761                 .get_page_entry = &rs600_gart_get_page_entry,
1762                 .set_page = &rs600_gart_set_page,
1763         },
1764         .vm = {
1765                 .init = &cayman_vm_init,
1766                 .fini = &cayman_vm_fini,
1767                 .copy_pages = &cayman_dma_vm_copy_pages,
1768                 .write_pages = &cayman_dma_vm_write_pages,
1769                 .set_pages = &cayman_dma_vm_set_pages,
1770                 .pad_ib = &cayman_dma_vm_pad_ib,
1771         },
1772         .ring = {
1773                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1774                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1775                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1776                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1777                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1778                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1779         },
1780         .irq = {
1781                 .set = &evergreen_irq_set,
1782                 .process = &evergreen_irq_process,
1783         },
1784         .display = {
1785                 .bandwidth_update = &dce6_bandwidth_update,
1786                 .get_vblank_counter = &evergreen_get_vblank_counter,
1787                 .wait_for_vblank = &dce4_wait_for_vblank,
1788                 .set_backlight_level = &atombios_set_backlight_level,
1789                 .get_backlight_level = &atombios_get_backlight_level,
1790                 .hdmi_enable = &evergreen_hdmi_enable,
1791                 .hdmi_setmode = &evergreen_hdmi_setmode,
1792         },
1793         .copy = {
1794                 .blit = &r600_copy_cpdma,
1795                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1796                 .dma = &evergreen_copy_dma,
1797                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1798                 .copy = &evergreen_copy_dma,
1799                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1800         },
1801         .surface = {
1802                 .set_reg = r600_set_surface_reg,
1803                 .clear_reg = r600_clear_surface_reg,
1804         },
1805         .hpd = {
1806                 .init = &evergreen_hpd_init,
1807                 .fini = &evergreen_hpd_fini,
1808                 .sense = &evergreen_hpd_sense,
1809                 .set_polarity = &evergreen_hpd_set_polarity,
1810         },
1811         .pm = {
1812                 .misc = &evergreen_pm_misc,
1813                 .prepare = &evergreen_pm_prepare,
1814                 .finish = &evergreen_pm_finish,
1815                 .init_profile = &sumo_pm_init_profile,
1816                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1817                 .get_engine_clock = &radeon_atom_get_engine_clock,
1818                 .set_engine_clock = &radeon_atom_set_engine_clock,
1819                 .get_memory_clock = NULL,
1820                 .set_memory_clock = NULL,
1821                 .get_pcie_lanes = NULL,
1822                 .set_pcie_lanes = NULL,
1823                 .set_clock_gating = NULL,
1824                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1825                 .get_temperature = &tn_get_temp,
1826         },
1827         .dpm = {
1828                 .init = &trinity_dpm_init,
1829                 .setup_asic = &trinity_dpm_setup_asic,
1830                 .enable = &trinity_dpm_enable,
1831                 .late_enable = &trinity_dpm_late_enable,
1832                 .disable = &trinity_dpm_disable,
1833                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1834                 .set_power_state = &trinity_dpm_set_power_state,
1835                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1836                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1837                 .fini = &trinity_dpm_fini,
1838                 .get_sclk = &trinity_dpm_get_sclk,
1839                 .get_mclk = &trinity_dpm_get_mclk,
1840                 .print_power_state = &trinity_dpm_print_power_state,
1841                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1842                 .force_performance_level = &trinity_dpm_force_performance_level,
1843                 .enable_bapm = &trinity_dpm_enable_bapm,
1844         },
1845         .pflip = {
1846                 .page_flip = &evergreen_page_flip,
1847                 .page_flip_pending = &evergreen_page_flip_pending,
1848         },
1849 };
1850
1851 static struct radeon_asic_ring si_gfx_ring = {
1852         .ib_execute = &si_ring_ib_execute,
1853         .ib_parse = &si_ib_parse,
1854         .emit_fence = &si_fence_ring_emit,
1855         .emit_semaphore = &r600_semaphore_ring_emit,
1856         .cs_parse = NULL,
1857         .ring_test = &r600_ring_test,
1858         .ib_test = &r600_ib_test,
1859         .is_lockup = &si_gfx_is_lockup,
1860         .vm_flush = &si_vm_flush,
1861         .get_rptr = &cayman_gfx_get_rptr,
1862         .get_wptr = &cayman_gfx_get_wptr,
1863         .set_wptr = &cayman_gfx_set_wptr,
1864 };
1865
1866 static struct radeon_asic_ring si_dma_ring = {
1867         .ib_execute = &cayman_dma_ring_ib_execute,
1868         .ib_parse = &evergreen_dma_ib_parse,
1869         .emit_fence = &evergreen_dma_fence_ring_emit,
1870         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1871         .cs_parse = NULL,
1872         .ring_test = &r600_dma_ring_test,
1873         .ib_test = &r600_dma_ib_test,
1874         .is_lockup = &si_dma_is_lockup,
1875         .vm_flush = &si_dma_vm_flush,
1876         .get_rptr = &cayman_dma_get_rptr,
1877         .get_wptr = &cayman_dma_get_wptr,
1878         .set_wptr = &cayman_dma_set_wptr,
1879 };
1880
1881 static struct radeon_asic si_asic = {
1882         .init = &si_init,
1883         .fini = &si_fini,
1884         .suspend = &si_suspend,
1885         .resume = &si_resume,
1886         .asic_reset = &si_asic_reset,
1887         .vga_set_state = &r600_vga_set_state,
1888         .mmio_hdp_flush = r600_mmio_hdp_flush,
1889         .gui_idle = &r600_gui_idle,
1890         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1891         .get_xclk = &si_get_xclk,
1892         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1893         .gart = {
1894                 .tlb_flush = &si_pcie_gart_tlb_flush,
1895                 .get_page_entry = &rs600_gart_get_page_entry,
1896                 .set_page = &rs600_gart_set_page,
1897         },
1898         .vm = {
1899                 .init = &si_vm_init,
1900                 .fini = &si_vm_fini,
1901                 .copy_pages = &si_dma_vm_copy_pages,
1902                 .write_pages = &si_dma_vm_write_pages,
1903                 .set_pages = &si_dma_vm_set_pages,
1904                 .pad_ib = &cayman_dma_vm_pad_ib,
1905         },
1906         .ring = {
1907                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1908                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1909                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1910                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1911                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1912                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1913         },
1914         .irq = {
1915                 .set = &si_irq_set,
1916                 .process = &si_irq_process,
1917         },
1918         .display = {
1919                 .bandwidth_update = &dce6_bandwidth_update,
1920                 .get_vblank_counter = &evergreen_get_vblank_counter,
1921                 .wait_for_vblank = &dce4_wait_for_vblank,
1922                 .set_backlight_level = &atombios_set_backlight_level,
1923                 .get_backlight_level = &atombios_get_backlight_level,
1924                 .hdmi_enable = &evergreen_hdmi_enable,
1925                 .hdmi_setmode = &evergreen_hdmi_setmode,
1926         },
1927         .copy = {
1928                 .blit = &r600_copy_cpdma,
1929                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1930                 .dma = &si_copy_dma,
1931                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1932                 .copy = &si_copy_dma,
1933                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1934         },
1935         .surface = {
1936                 .set_reg = r600_set_surface_reg,
1937                 .clear_reg = r600_clear_surface_reg,
1938         },
1939         .hpd = {
1940                 .init = &evergreen_hpd_init,
1941                 .fini = &evergreen_hpd_fini,
1942                 .sense = &evergreen_hpd_sense,
1943                 .set_polarity = &evergreen_hpd_set_polarity,
1944         },
1945         .pm = {
1946                 .misc = &evergreen_pm_misc,
1947                 .prepare = &evergreen_pm_prepare,
1948                 .finish = &evergreen_pm_finish,
1949                 .init_profile = &sumo_pm_init_profile,
1950                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1951                 .get_engine_clock = &radeon_atom_get_engine_clock,
1952                 .set_engine_clock = &radeon_atom_set_engine_clock,
1953                 .get_memory_clock = &radeon_atom_get_memory_clock,
1954                 .set_memory_clock = &radeon_atom_set_memory_clock,
1955                 .get_pcie_lanes = &r600_get_pcie_lanes,
1956                 .set_pcie_lanes = &r600_set_pcie_lanes,
1957                 .set_clock_gating = NULL,
1958                 .set_uvd_clocks = &si_set_uvd_clocks,
1959                 .get_temperature = &si_get_temp,
1960         },
1961         .dpm = {
1962                 .init = &si_dpm_init,
1963                 .setup_asic = &si_dpm_setup_asic,
1964                 .enable = &si_dpm_enable,
1965                 .late_enable = &si_dpm_late_enable,
1966                 .disable = &si_dpm_disable,
1967                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1968                 .set_power_state = &si_dpm_set_power_state,
1969                 .post_set_power_state = &si_dpm_post_set_power_state,
1970                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1971                 .fini = &si_dpm_fini,
1972                 .get_sclk = &ni_dpm_get_sclk,
1973                 .get_mclk = &ni_dpm_get_mclk,
1974                 .print_power_state = &ni_dpm_print_power_state,
1975                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1976                 .force_performance_level = &si_dpm_force_performance_level,
1977                 .vblank_too_short = &ni_dpm_vblank_too_short,
1978         },
1979         .pflip = {
1980                 .page_flip = &evergreen_page_flip,
1981                 .page_flip_pending = &evergreen_page_flip_pending,
1982         },
1983 };
1984
1985 static struct radeon_asic_ring ci_gfx_ring = {
1986         .ib_execute = &cik_ring_ib_execute,
1987         .ib_parse = &cik_ib_parse,
1988         .emit_fence = &cik_fence_gfx_ring_emit,
1989         .emit_semaphore = &cik_semaphore_ring_emit,
1990         .cs_parse = NULL,
1991         .ring_test = &cik_ring_test,
1992         .ib_test = &cik_ib_test,
1993         .is_lockup = &cik_gfx_is_lockup,
1994         .vm_flush = &cik_vm_flush,
1995         .get_rptr = &cik_gfx_get_rptr,
1996         .get_wptr = &cik_gfx_get_wptr,
1997         .set_wptr = &cik_gfx_set_wptr,
1998 };
1999
2000 static struct radeon_asic_ring ci_cp_ring = {
2001         .ib_execute = &cik_ring_ib_execute,
2002         .ib_parse = &cik_ib_parse,
2003         .emit_fence = &cik_fence_compute_ring_emit,
2004         .emit_semaphore = &cik_semaphore_ring_emit,
2005         .cs_parse = NULL,
2006         .ring_test = &cik_ring_test,
2007         .ib_test = &cik_ib_test,
2008         .is_lockup = &cik_gfx_is_lockup,
2009         .vm_flush = &cik_vm_flush,
2010         .get_rptr = &cik_compute_get_rptr,
2011         .get_wptr = &cik_compute_get_wptr,
2012         .set_wptr = &cik_compute_set_wptr,
2013 };
2014
2015 static struct radeon_asic_ring ci_dma_ring = {
2016         .ib_execute = &cik_sdma_ring_ib_execute,
2017         .ib_parse = &cik_ib_parse,
2018         .emit_fence = &cik_sdma_fence_ring_emit,
2019         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2020         .cs_parse = NULL,
2021         .ring_test = &cik_sdma_ring_test,
2022         .ib_test = &cik_sdma_ib_test,
2023         .is_lockup = &cik_sdma_is_lockup,
2024         .vm_flush = &cik_dma_vm_flush,
2025         .get_rptr = &cik_sdma_get_rptr,
2026         .get_wptr = &cik_sdma_get_wptr,
2027         .set_wptr = &cik_sdma_set_wptr,
2028 };
2029
2030 static struct radeon_asic_ring ci_vce_ring = {
2031         .ib_execute = &radeon_vce_ib_execute,
2032         .emit_fence = &radeon_vce_fence_emit,
2033         .emit_semaphore = &radeon_vce_semaphore_emit,
2034         .cs_parse = &radeon_vce_cs_parse,
2035         .ring_test = &radeon_vce_ring_test,
2036         .ib_test = &radeon_vce_ib_test,
2037         .is_lockup = &radeon_ring_test_lockup,
2038         .get_rptr = &vce_v1_0_get_rptr,
2039         .get_wptr = &vce_v1_0_get_wptr,
2040         .set_wptr = &vce_v1_0_set_wptr,
2041 };
2042
2043 static struct radeon_asic ci_asic = {
2044         .init = &cik_init,
2045         .fini = &cik_fini,
2046         .suspend = &cik_suspend,
2047         .resume = &cik_resume,
2048         .asic_reset = &cik_asic_reset,
2049         .vga_set_state = &r600_vga_set_state,
2050         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2051         .gui_idle = &r600_gui_idle,
2052         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2053         .get_xclk = &cik_get_xclk,
2054         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2055         .gart = {
2056                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2057                 .get_page_entry = &rs600_gart_get_page_entry,
2058                 .set_page = &rs600_gart_set_page,
2059         },
2060         .vm = {
2061                 .init = &cik_vm_init,
2062                 .fini = &cik_vm_fini,
2063                 .copy_pages = &cik_sdma_vm_copy_pages,
2064                 .write_pages = &cik_sdma_vm_write_pages,
2065                 .set_pages = &cik_sdma_vm_set_pages,
2066                 .pad_ib = &cik_sdma_vm_pad_ib,
2067         },
2068         .ring = {
2069                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2070                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2071                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2072                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2073                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2074                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2075                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2076                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2077         },
2078         .irq = {
2079                 .set = &cik_irq_set,
2080                 .process = &cik_irq_process,
2081         },
2082         .display = {
2083                 .bandwidth_update = &dce8_bandwidth_update,
2084                 .get_vblank_counter = &evergreen_get_vblank_counter,
2085                 .wait_for_vblank = &dce4_wait_for_vblank,
2086                 .set_backlight_level = &atombios_set_backlight_level,
2087                 .get_backlight_level = &atombios_get_backlight_level,
2088                 .hdmi_enable = &evergreen_hdmi_enable,
2089                 .hdmi_setmode = &evergreen_hdmi_setmode,
2090         },
2091         .copy = {
2092                 .blit = &cik_copy_cpdma,
2093                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2094                 .dma = &cik_copy_dma,
2095                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2096                 .copy = &cik_copy_dma,
2097                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2098         },
2099         .surface = {
2100                 .set_reg = r600_set_surface_reg,
2101                 .clear_reg = r600_clear_surface_reg,
2102         },
2103         .hpd = {
2104                 .init = &evergreen_hpd_init,
2105                 .fini = &evergreen_hpd_fini,
2106                 .sense = &evergreen_hpd_sense,
2107                 .set_polarity = &evergreen_hpd_set_polarity,
2108         },
2109         .pm = {
2110                 .misc = &evergreen_pm_misc,
2111                 .prepare = &evergreen_pm_prepare,
2112                 .finish = &evergreen_pm_finish,
2113                 .init_profile = &sumo_pm_init_profile,
2114                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2115                 .get_engine_clock = &radeon_atom_get_engine_clock,
2116                 .set_engine_clock = &radeon_atom_set_engine_clock,
2117                 .get_memory_clock = &radeon_atom_get_memory_clock,
2118                 .set_memory_clock = &radeon_atom_set_memory_clock,
2119                 .get_pcie_lanes = NULL,
2120                 .set_pcie_lanes = NULL,
2121                 .set_clock_gating = NULL,
2122                 .set_uvd_clocks = &cik_set_uvd_clocks,
2123                 .set_vce_clocks = &cik_set_vce_clocks,
2124                 .get_temperature = &ci_get_temp,
2125         },
2126         .dpm = {
2127                 .init = &ci_dpm_init,
2128                 .setup_asic = &ci_dpm_setup_asic,
2129                 .enable = &ci_dpm_enable,
2130                 .late_enable = &ci_dpm_late_enable,
2131                 .disable = &ci_dpm_disable,
2132                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2133                 .set_power_state = &ci_dpm_set_power_state,
2134                 .post_set_power_state = &ci_dpm_post_set_power_state,
2135                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2136                 .fini = &ci_dpm_fini,
2137                 .get_sclk = &ci_dpm_get_sclk,
2138                 .get_mclk = &ci_dpm_get_mclk,
2139                 .print_power_state = &ci_dpm_print_power_state,
2140                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2141                 .force_performance_level = &ci_dpm_force_performance_level,
2142                 .vblank_too_short = &ci_dpm_vblank_too_short,
2143                 .powergate_uvd = &ci_dpm_powergate_uvd,
2144         },
2145         .pflip = {
2146                 .page_flip = &evergreen_page_flip,
2147                 .page_flip_pending = &evergreen_page_flip_pending,
2148         },
2149 };
2150
2151 static struct radeon_asic kv_asic = {
2152         .init = &cik_init,
2153         .fini = &cik_fini,
2154         .suspend = &cik_suspend,
2155         .resume = &cik_resume,
2156         .asic_reset = &cik_asic_reset,
2157         .vga_set_state = &r600_vga_set_state,
2158         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2159         .gui_idle = &r600_gui_idle,
2160         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2161         .get_xclk = &cik_get_xclk,
2162         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2163         .gart = {
2164                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2165                 .get_page_entry = &rs600_gart_get_page_entry,
2166                 .set_page = &rs600_gart_set_page,
2167         },
2168         .vm = {
2169                 .init = &cik_vm_init,
2170                 .fini = &cik_vm_fini,
2171                 .copy_pages = &cik_sdma_vm_copy_pages,
2172                 .write_pages = &cik_sdma_vm_write_pages,
2173                 .set_pages = &cik_sdma_vm_set_pages,
2174                 .pad_ib = &cik_sdma_vm_pad_ib,
2175         },
2176         .ring = {
2177                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2178                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2179                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2180                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2181                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2182                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2183                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2184                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2185         },
2186         .irq = {
2187                 .set = &cik_irq_set,
2188                 .process = &cik_irq_process,
2189         },
2190         .display = {
2191                 .bandwidth_update = &dce8_bandwidth_update,
2192                 .get_vblank_counter = &evergreen_get_vblank_counter,
2193                 .wait_for_vblank = &dce4_wait_for_vblank,
2194                 .set_backlight_level = &atombios_set_backlight_level,
2195                 .get_backlight_level = &atombios_get_backlight_level,
2196                 .hdmi_enable = &evergreen_hdmi_enable,
2197                 .hdmi_setmode = &evergreen_hdmi_setmode,
2198         },
2199         .copy = {
2200                 .blit = &cik_copy_cpdma,
2201                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2202                 .dma = &cik_copy_dma,
2203                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2204                 .copy = &cik_copy_dma,
2205                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2206         },
2207         .surface = {
2208                 .set_reg = r600_set_surface_reg,
2209                 .clear_reg = r600_clear_surface_reg,
2210         },
2211         .hpd = {
2212                 .init = &evergreen_hpd_init,
2213                 .fini = &evergreen_hpd_fini,
2214                 .sense = &evergreen_hpd_sense,
2215                 .set_polarity = &evergreen_hpd_set_polarity,
2216         },
2217         .pm = {
2218                 .misc = &evergreen_pm_misc,
2219                 .prepare = &evergreen_pm_prepare,
2220                 .finish = &evergreen_pm_finish,
2221                 .init_profile = &sumo_pm_init_profile,
2222                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2223                 .get_engine_clock = &radeon_atom_get_engine_clock,
2224                 .set_engine_clock = &radeon_atom_set_engine_clock,
2225                 .get_memory_clock = &radeon_atom_get_memory_clock,
2226                 .set_memory_clock = &radeon_atom_set_memory_clock,
2227                 .get_pcie_lanes = NULL,
2228                 .set_pcie_lanes = NULL,
2229                 .set_clock_gating = NULL,
2230                 .set_uvd_clocks = &cik_set_uvd_clocks,
2231                 .set_vce_clocks = &cik_set_vce_clocks,
2232                 .get_temperature = &kv_get_temp,
2233         },
2234         .dpm = {
2235                 .init = &kv_dpm_init,
2236                 .setup_asic = &kv_dpm_setup_asic,
2237                 .enable = &kv_dpm_enable,
2238                 .late_enable = &kv_dpm_late_enable,
2239                 .disable = &kv_dpm_disable,
2240                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2241                 .set_power_state = &kv_dpm_set_power_state,
2242                 .post_set_power_state = &kv_dpm_post_set_power_state,
2243                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2244                 .fini = &kv_dpm_fini,
2245                 .get_sclk = &kv_dpm_get_sclk,
2246                 .get_mclk = &kv_dpm_get_mclk,
2247                 .print_power_state = &kv_dpm_print_power_state,
2248                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2249                 .force_performance_level = &kv_dpm_force_performance_level,
2250                 .powergate_uvd = &kv_dpm_powergate_uvd,
2251                 .enable_bapm = &kv_dpm_enable_bapm,
2252         },
2253         .pflip = {
2254                 .page_flip = &evergreen_page_flip,
2255                 .page_flip_pending = &evergreen_page_flip_pending,
2256         },
2257 };
2258
2259 /**
2260  * radeon_asic_init - register asic specific callbacks
2261  *
2262  * @rdev: radeon device pointer
2263  *
2264  * Registers the appropriate asic specific callbacks for each
2265  * chip family.  Also sets other asics specific info like the number
2266  * of crtcs and the register aperture accessors (all asics).
2267  * Returns 0 for success.
2268  */
2269 int radeon_asic_init(struct radeon_device *rdev)
2270 {
2271         radeon_register_accessor_init(rdev);
2272
2273         /* set the number of crtcs */
2274         if (rdev->flags & RADEON_SINGLE_CRTC)
2275                 rdev->num_crtc = 1;
2276         else
2277                 rdev->num_crtc = 2;
2278
2279         rdev->has_uvd = false;
2280
2281         switch (rdev->family) {
2282         case CHIP_R100:
2283         case CHIP_RV100:
2284         case CHIP_RS100:
2285         case CHIP_RV200:
2286         case CHIP_RS200:
2287                 rdev->asic = &r100_asic;
2288                 break;
2289         case CHIP_R200:
2290         case CHIP_RV250:
2291         case CHIP_RS300:
2292         case CHIP_RV280:
2293                 rdev->asic = &r200_asic;
2294                 break;
2295         case CHIP_R300:
2296         case CHIP_R350:
2297         case CHIP_RV350:
2298         case CHIP_RV380:
2299                 if (rdev->flags & RADEON_IS_PCIE)
2300                         rdev->asic = &r300_asic_pcie;
2301                 else
2302                         rdev->asic = &r300_asic;
2303                 break;
2304         case CHIP_R420:
2305         case CHIP_R423:
2306         case CHIP_RV410:
2307                 rdev->asic = &r420_asic;
2308                 /* handle macs */
2309                 if (rdev->bios == NULL) {
2310                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2311                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2312                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2313                         rdev->asic->pm.set_memory_clock = NULL;
2314                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2315                 }
2316                 break;
2317         case CHIP_RS400:
2318         case CHIP_RS480:
2319                 rdev->asic = &rs400_asic;
2320                 break;
2321         case CHIP_RS600:
2322                 rdev->asic = &rs600_asic;
2323                 break;
2324         case CHIP_RS690:
2325         case CHIP_RS740:
2326                 rdev->asic = &rs690_asic;
2327                 break;
2328         case CHIP_RV515:
2329                 rdev->asic = &rv515_asic;
2330                 break;
2331         case CHIP_R520:
2332         case CHIP_RV530:
2333         case CHIP_RV560:
2334         case CHIP_RV570:
2335         case CHIP_R580:
2336                 rdev->asic = &r520_asic;
2337                 break;
2338         case CHIP_R600:
2339                 rdev->asic = &r600_asic;
2340                 break;
2341         case CHIP_RV610:
2342         case CHIP_RV630:
2343         case CHIP_RV620:
2344         case CHIP_RV635:
2345         case CHIP_RV670:
2346                 rdev->asic = &rv6xx_asic;
2347                 rdev->has_uvd = true;
2348                 break;
2349         case CHIP_RS780:
2350         case CHIP_RS880:
2351                 rdev->asic = &rs780_asic;
2352                 /* 760G/780V/880V don't have UVD */
2353                 if ((rdev->pdev->device == 0x9616)||
2354                     (rdev->pdev->device == 0x9611)||
2355                     (rdev->pdev->device == 0x9613)||
2356                     (rdev->pdev->device == 0x9711)||
2357                     (rdev->pdev->device == 0x9713))
2358                         rdev->has_uvd = false;
2359                 else
2360                         rdev->has_uvd = true;
2361                 break;
2362         case CHIP_RV770:
2363         case CHIP_RV730:
2364         case CHIP_RV710:
2365         case CHIP_RV740:
2366                 rdev->asic = &rv770_asic;
2367                 rdev->has_uvd = true;
2368                 break;
2369         case CHIP_CEDAR:
2370         case CHIP_REDWOOD:
2371         case CHIP_JUNIPER:
2372         case CHIP_CYPRESS:
2373         case CHIP_HEMLOCK:
2374                 /* set num crtcs */
2375                 if (rdev->family == CHIP_CEDAR)
2376                         rdev->num_crtc = 4;
2377                 else
2378                         rdev->num_crtc = 6;
2379                 rdev->asic = &evergreen_asic;
2380                 rdev->has_uvd = true;
2381                 break;
2382         case CHIP_PALM:
2383         case CHIP_SUMO:
2384         case CHIP_SUMO2:
2385                 rdev->asic = &sumo_asic;
2386                 rdev->has_uvd = true;
2387                 break;
2388         case CHIP_BARTS:
2389         case CHIP_TURKS:
2390         case CHIP_CAICOS:
2391                 /* set num crtcs */
2392                 if (rdev->family == CHIP_CAICOS)
2393                         rdev->num_crtc = 4;
2394                 else
2395                         rdev->num_crtc = 6;
2396                 rdev->asic = &btc_asic;
2397                 rdev->has_uvd = true;
2398                 break;
2399         case CHIP_CAYMAN:
2400                 rdev->asic = &cayman_asic;
2401                 /* set num crtcs */
2402                 rdev->num_crtc = 6;
2403                 rdev->has_uvd = true;
2404                 break;
2405         case CHIP_ARUBA:
2406                 rdev->asic = &trinity_asic;
2407                 /* set num crtcs */
2408                 rdev->num_crtc = 4;
2409                 rdev->has_uvd = true;
2410                 break;
2411         case CHIP_TAHITI:
2412         case CHIP_PITCAIRN:
2413         case CHIP_VERDE:
2414         case CHIP_OLAND:
2415         case CHIP_HAINAN:
2416                 rdev->asic = &si_asic;
2417                 /* set num crtcs */
2418                 if (rdev->family == CHIP_HAINAN)
2419                         rdev->num_crtc = 0;
2420                 else if (rdev->family == CHIP_OLAND)
2421                         rdev->num_crtc = 2;
2422                 else
2423                         rdev->num_crtc = 6;
2424                 if (rdev->family == CHIP_HAINAN)
2425                         rdev->has_uvd = false;
2426                 else
2427                         rdev->has_uvd = true;
2428                 switch (rdev->family) {
2429                 case CHIP_TAHITI:
2430                         rdev->cg_flags =
2431                                 RADEON_CG_SUPPORT_GFX_MGCG |
2432                                 RADEON_CG_SUPPORT_GFX_MGLS |
2433                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2434                                 RADEON_CG_SUPPORT_GFX_CGLS |
2435                                 RADEON_CG_SUPPORT_GFX_CGTS |
2436                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2437                                 RADEON_CG_SUPPORT_MC_MGCG |
2438                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2439                                 RADEON_CG_SUPPORT_BIF_LS |
2440                                 RADEON_CG_SUPPORT_VCE_MGCG |
2441                                 RADEON_CG_SUPPORT_UVD_MGCG |
2442                                 RADEON_CG_SUPPORT_HDP_LS |
2443                                 RADEON_CG_SUPPORT_HDP_MGCG;
2444                         rdev->pg_flags = 0;
2445                         break;
2446                 case CHIP_PITCAIRN:
2447                         rdev->cg_flags =
2448                                 RADEON_CG_SUPPORT_GFX_MGCG |
2449                                 RADEON_CG_SUPPORT_GFX_MGLS |
2450                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2451                                 RADEON_CG_SUPPORT_GFX_CGLS |
2452                                 RADEON_CG_SUPPORT_GFX_CGTS |
2453                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2454                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2455                                 RADEON_CG_SUPPORT_MC_LS |
2456                                 RADEON_CG_SUPPORT_MC_MGCG |
2457                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2458                                 RADEON_CG_SUPPORT_BIF_LS |
2459                                 RADEON_CG_SUPPORT_VCE_MGCG |
2460                                 RADEON_CG_SUPPORT_UVD_MGCG |
2461                                 RADEON_CG_SUPPORT_HDP_LS |
2462                                 RADEON_CG_SUPPORT_HDP_MGCG;
2463                         rdev->pg_flags = 0;
2464                         break;
2465                 case CHIP_VERDE:
2466                         rdev->cg_flags =
2467                                 RADEON_CG_SUPPORT_GFX_MGCG |
2468                                 RADEON_CG_SUPPORT_GFX_MGLS |
2469                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2470                                 RADEON_CG_SUPPORT_GFX_CGLS |
2471                                 RADEON_CG_SUPPORT_GFX_CGTS |
2472                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2473                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2474                                 RADEON_CG_SUPPORT_MC_LS |
2475                                 RADEON_CG_SUPPORT_MC_MGCG |
2476                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2477                                 RADEON_CG_SUPPORT_BIF_LS |
2478                                 RADEON_CG_SUPPORT_VCE_MGCG |
2479                                 RADEON_CG_SUPPORT_UVD_MGCG |
2480                                 RADEON_CG_SUPPORT_HDP_LS |
2481                                 RADEON_CG_SUPPORT_HDP_MGCG;
2482                         rdev->pg_flags = 0 |
2483                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2484                                 RADEON_PG_SUPPORT_SDMA;
2485                         break;
2486                 case CHIP_OLAND:
2487                         rdev->cg_flags =
2488                                 RADEON_CG_SUPPORT_GFX_MGCG |
2489                                 RADEON_CG_SUPPORT_GFX_MGLS |
2490                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2491                                 RADEON_CG_SUPPORT_GFX_CGLS |
2492                                 RADEON_CG_SUPPORT_GFX_CGTS |
2493                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2494                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2495                                 RADEON_CG_SUPPORT_MC_LS |
2496                                 RADEON_CG_SUPPORT_MC_MGCG |
2497                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2498                                 RADEON_CG_SUPPORT_BIF_LS |
2499                                 RADEON_CG_SUPPORT_UVD_MGCG |
2500                                 RADEON_CG_SUPPORT_HDP_LS |
2501                                 RADEON_CG_SUPPORT_HDP_MGCG;
2502                         rdev->pg_flags = 0;
2503                         break;
2504                 case CHIP_HAINAN:
2505                         rdev->cg_flags =
2506                                 RADEON_CG_SUPPORT_GFX_MGCG |
2507                                 RADEON_CG_SUPPORT_GFX_MGLS |
2508                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2509                                 RADEON_CG_SUPPORT_GFX_CGLS |
2510                                 RADEON_CG_SUPPORT_GFX_CGTS |
2511                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2512                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2513                                 RADEON_CG_SUPPORT_MC_LS |
2514                                 RADEON_CG_SUPPORT_MC_MGCG |
2515                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2516                                 RADEON_CG_SUPPORT_BIF_LS |
2517                                 RADEON_CG_SUPPORT_HDP_LS |
2518                                 RADEON_CG_SUPPORT_HDP_MGCG;
2519                         rdev->pg_flags = 0;
2520                         break;
2521                 default:
2522                         rdev->cg_flags = 0;
2523                         rdev->pg_flags = 0;
2524                         break;
2525                 }
2526                 break;
2527         case CHIP_BONAIRE:
2528         case CHIP_HAWAII:
2529                 rdev->asic = &ci_asic;
2530                 rdev->num_crtc = 6;
2531                 rdev->has_uvd = true;
2532                 if (rdev->family == CHIP_BONAIRE) {
2533                         rdev->cg_flags =
2534                                 RADEON_CG_SUPPORT_GFX_MGCG |
2535                                 RADEON_CG_SUPPORT_GFX_MGLS |
2536                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2537                                 RADEON_CG_SUPPORT_GFX_CGLS |
2538                                 RADEON_CG_SUPPORT_GFX_CGTS |
2539                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2540                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2541                                 RADEON_CG_SUPPORT_MC_LS |
2542                                 RADEON_CG_SUPPORT_MC_MGCG |
2543                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2544                                 RADEON_CG_SUPPORT_SDMA_LS |
2545                                 RADEON_CG_SUPPORT_BIF_LS |
2546                                 RADEON_CG_SUPPORT_VCE_MGCG |
2547                                 RADEON_CG_SUPPORT_UVD_MGCG |
2548                                 RADEON_CG_SUPPORT_HDP_LS |
2549                                 RADEON_CG_SUPPORT_HDP_MGCG;
2550                         rdev->pg_flags = 0;
2551                 } else {
2552                         rdev->cg_flags =
2553                                 RADEON_CG_SUPPORT_GFX_MGCG |
2554                                 RADEON_CG_SUPPORT_GFX_MGLS |
2555                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2556                                 RADEON_CG_SUPPORT_GFX_CGLS |
2557                                 RADEON_CG_SUPPORT_GFX_CGTS |
2558                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2559                                 RADEON_CG_SUPPORT_MC_LS |
2560                                 RADEON_CG_SUPPORT_MC_MGCG |
2561                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2562                                 RADEON_CG_SUPPORT_SDMA_LS |
2563                                 RADEON_CG_SUPPORT_BIF_LS |
2564                                 RADEON_CG_SUPPORT_VCE_MGCG |
2565                                 RADEON_CG_SUPPORT_UVD_MGCG |
2566                                 RADEON_CG_SUPPORT_HDP_LS |
2567                                 RADEON_CG_SUPPORT_HDP_MGCG;
2568                         rdev->pg_flags = 0;
2569                 }
2570                 break;
2571         case CHIP_KAVERI:
2572         case CHIP_KABINI:
2573         case CHIP_MULLINS:
2574                 rdev->asic = &kv_asic;
2575                 /* set num crtcs */
2576                 if (rdev->family == CHIP_KAVERI) {
2577                         rdev->num_crtc = 4;
2578                         rdev->cg_flags =
2579                                 RADEON_CG_SUPPORT_GFX_MGCG |
2580                                 RADEON_CG_SUPPORT_GFX_MGLS |
2581                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2582                                 RADEON_CG_SUPPORT_GFX_CGLS |
2583                                 RADEON_CG_SUPPORT_GFX_CGTS |
2584                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2585                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2586                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2587                                 RADEON_CG_SUPPORT_SDMA_LS |
2588                                 RADEON_CG_SUPPORT_BIF_LS |
2589                                 RADEON_CG_SUPPORT_VCE_MGCG |
2590                                 RADEON_CG_SUPPORT_UVD_MGCG |
2591                                 RADEON_CG_SUPPORT_HDP_LS |
2592                                 RADEON_CG_SUPPORT_HDP_MGCG;
2593                         rdev->pg_flags = 0;
2594                                 /*RADEON_PG_SUPPORT_GFX_PG |
2595                                 RADEON_PG_SUPPORT_GFX_SMG |
2596                                 RADEON_PG_SUPPORT_GFX_DMG |
2597                                 RADEON_PG_SUPPORT_UVD |
2598                                 RADEON_PG_SUPPORT_VCE |
2599                                 RADEON_PG_SUPPORT_CP |
2600                                 RADEON_PG_SUPPORT_GDS |
2601                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2602                                 RADEON_PG_SUPPORT_ACP |
2603                                 RADEON_PG_SUPPORT_SAMU;*/
2604                 } else {
2605                         rdev->num_crtc = 2;
2606                         rdev->cg_flags =
2607                                 RADEON_CG_SUPPORT_GFX_MGCG |
2608                                 RADEON_CG_SUPPORT_GFX_MGLS |
2609                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2610                                 RADEON_CG_SUPPORT_GFX_CGLS |
2611                                 RADEON_CG_SUPPORT_GFX_CGTS |
2612                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2613                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2614                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2615                                 RADEON_CG_SUPPORT_SDMA_LS |
2616                                 RADEON_CG_SUPPORT_BIF_LS |
2617                                 RADEON_CG_SUPPORT_VCE_MGCG |
2618                                 RADEON_CG_SUPPORT_UVD_MGCG |
2619                                 RADEON_CG_SUPPORT_HDP_LS |
2620                                 RADEON_CG_SUPPORT_HDP_MGCG;
2621                         rdev->pg_flags = 0;
2622                                 /*RADEON_PG_SUPPORT_GFX_PG |
2623                                 RADEON_PG_SUPPORT_GFX_SMG |
2624                                 RADEON_PG_SUPPORT_UVD |
2625                                 RADEON_PG_SUPPORT_VCE |
2626                                 RADEON_PG_SUPPORT_CP |
2627                                 RADEON_PG_SUPPORT_GDS |
2628                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2629                                 RADEON_PG_SUPPORT_SAMU;*/
2630                 }
2631                 rdev->has_uvd = true;
2632                 break;
2633         default:
2634                 /* FIXME: not supported yet */
2635                 return -EINVAL;
2636         }
2637
2638         if (rdev->flags & RADEON_IS_IGP) {
2639                 rdev->asic->pm.get_memory_clock = NULL;
2640                 rdev->asic->pm.set_memory_clock = NULL;
2641         }
2642
2643         return 0;
2644 }
2645