drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/engctx.h>
  27 #include <core/ramht.h>
  28 #include <core/class.h>
  29
  30 #include <subdev/timer.h>
  31 #include <subdev/bar.h>
  32
  33 #include <engine/dmaobj.h>
  34 #include <engine/fifo.h>
  35
  36 #include "nv50.h"
  37
  38 /*******************************************************************************
  39  * FIFO channel objects
  40  ******************************************************************************/
  41
  42 static void
  43 nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
  44 {
  45         struct nouveau_bar *bar = nouveau_bar(priv);
  46         struct nouveau_gpuobj *cur;
  47         int i, p;
  48
  49         cur = priv->playlist[priv->cur_playlist];
  50         priv->cur_playlist = !priv->cur_playlist;
  51
  52         for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
  53                 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
  54                         nv_wo32(cur, p++ * 4, i);
  55         }
  56
  57         bar->flush(bar);
  58
  59         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
  60         nv_wr32(priv, 0x0032ec, p);
  61         nv_wr32(priv, 0x002500, 0x00000101);
  62 }
  63
  64 void
  65 nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
  66 {
  67         mutex_lock(&nv_subdev(priv)->mutex);
  68         nv50_fifo_playlist_update_locked(priv);
  69         mutex_unlock(&nv_subdev(priv)->mutex);
  70 }
  71
  72 static int
  73 nv50_fifo_context_attach(struct nouveau_object *parent,
  74                          struct nouveau_object *object)
  75 {
  76         struct nouveau_bar *bar = nouveau_bar(parent);
  77         struct nv50_fifo_base *base = (void *)parent->parent;
  78         struct nouveau_gpuobj *ectx = (void *)object;
  79         u64 limit = ectx->addr + ectx->size - 1;
  80         u64 start = ectx->addr;
  81         u32 addr;
  82
  83         switch (nv_engidx(object->engine)) {
  84         case NVDEV_ENGINE_SW   : return 0;
  85         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
  86         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  87         default:
  88                 return -EINVAL;
  89         }
  90
  91         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  92         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  93         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  94         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  95         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  96                                         upper_32_bits(start));
  97         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  98         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  99         bar->flush(bar);
 100         return 0;
 101 }
 102
 103 static int
 104 nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 105                          struct nouveau_object *object)
 106 {
 107         struct nouveau_bar *bar = nouveau_bar(parent);
 108         struct nv50_fifo_priv *priv = (void *)parent->engine;
 109         struct nv50_fifo_base *base = (void *)parent->parent;
 110         struct nv50_fifo_chan *chan = (void *)parent;
 111         u32 addr, me;
 112         int ret = 0;
 113
 114         switch (nv_engidx(object->engine)) {
 115         case NVDEV_ENGINE_SW   : return 0;
 116         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
 117         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
 118         default:
 119                 return -EINVAL;
 120         }
 121
 122         /* HW bug workaround:
 123          *
 124          * PFIFO will hang forever if the connected engines don't report
 125          * that they've processed the context switch request.
 126          *
 127          * In order for the kickoff to work, we need to ensure all the
 128          * connected engines are in a state where they can answer.
 129          *
 130          * Newer chipsets don't seem to suffer from this issue, and well,
 131          * there's also a "ignore these engines" bitmask reg we can use
 132          * if we hit the issue there..
 133          */
 134         me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
 135
 136         /* do the kickoff... */
 137         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 138         if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
 139                 nv_error(priv, "channel %d [%s] unload timeout\n",
 140                          chan->base.chid, nouveau_client_name(chan));
 141                 if (suspend)
 142                         ret = -EBUSY;
 143         }
 144         nv_wr32(priv, 0x00b860, me);
 145
 146         if (ret == 0) {
 147                 nv_wo32(base->eng, addr + 0x00, 0x00000000);
 148                 nv_wo32(base->eng, addr + 0x04, 0x00000000);
 149                 nv_wo32(base->eng, addr + 0x08, 0x00000000);
 150                 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 151                 nv_wo32(base->eng, addr + 0x10, 0x00000000);
 152                 nv_wo32(base->eng, addr + 0x14, 0x00000000);
 153                 bar->flush(bar);
 154         }
 155
 156         return ret;
 157 }
 158
 159 static int
 160 nv50_fifo_object_attach(struct nouveau_object *parent,
 161                         struct nouveau_object *object, u32 handle)
 162 {
 163         struct nv50_fifo_chan *chan = (void *)parent;
 164         u32 context;
 165
 166         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 167                 context = nv_gpuobj(object)->node->offset >> 4;
 168         else
 169                 context = 0x00000004; /* just non-zero */
 170
 171         switch (nv_engidx(object->engine)) {
 172         case NVDEV_ENGINE_DMAOBJ:
 173         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 174         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 175         case NVDEV_ENGINE_MPEG  : context |= 0x00200000; break;
 176         default:
 177                 return -EINVAL;
 178         }
 179
 180         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 181 }
 182
 183 void
 184 nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
 185 {
 186         struct nv50_fifo_chan *chan = (void *)parent;
 187         nouveau_ramht_remove(chan->ramht, cookie);
 188 }
 189
 190 static int
 191 nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
 192                         struct nouveau_object *engine,
 193                         struct nouveau_oclass *oclass, void *data, u32 size,
 194                         struct nouveau_object **pobject)
 195 {
 196         struct nouveau_bar *bar = nouveau_bar(parent);
 197         struct nv50_fifo_base *base = (void *)parent;
 198         struct nv50_fifo_chan *chan;
 199         struct nv03_channel_dma_class *args = data;
 200         int ret;
 201
 202         if (size < sizeof(*args))
 203                 return -EINVAL;
 204
 205         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 206                                           0x2000, args->pushbuf,
 207                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 208                                           (1ULL << NVDEV_ENGINE_SW) |
 209                                           (1ULL << NVDEV_ENGINE_GR) |
 210                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 211         *pobject = nv_object(chan);
 212         if (ret)
 213                 return ret;
 214
 215         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 216         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 217         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 218         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 219
 220         ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 221                                 &chan->ramht);
 222         if (ret)
 223                 return ret;
 224
 225         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
 226         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
 227         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
 228         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
 229         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 230         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 231         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 232         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 233         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 234         nv_wo32(base->ramfc, 0x78, 0x00000000);
 235         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 236         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 237                                    (4 << 24) /* SEARCH_FULL */ |
 238                                    (chan->ramht->base.node->offset >> 4));
 239         bar->flush(bar);
 240         return 0;
 241 }
 242
 243 static int
 244 nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
 245                         struct nouveau_object *engine,
 246                         struct nouveau_oclass *oclass, void *data, u32 size,
 247                         struct nouveau_object **pobject)
 248 {
 249         struct nv50_channel_ind_class *args = data;
 250         struct nouveau_bar *bar = nouveau_bar(parent);
 251         struct nv50_fifo_base *base = (void *)parent;
 252         struct nv50_fifo_chan *chan;
 253         u64 ioffset, ilength;
 254         int ret;
 255
 256         if (size < sizeof(*args))
 257                 return -EINVAL;
 258
 259         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 260                                           0x2000, args->pushbuf,
 261                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 262                                           (1ULL << NVDEV_ENGINE_SW) |
 263                                           (1ULL << NVDEV_ENGINE_GR) |
 264                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 265         *pobject = nv_object(chan);
 266         if (ret)
 267                 return ret;
 268
 269         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 270         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 271         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 272         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 273
 274         ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 275                                &chan->ramht);
 276         if (ret)
 277                 return ret;
 278
 279         ioffset = args->ioffset;
 280         ilength = order_base_2(args->ilength / 8);
 281
 282         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 283         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 284         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 285         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 286         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 287         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 288         nv_wo32(base->ramfc, 0x78, 0x00000000);
 289         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 290         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 291                                    (4 << 24) /* SEARCH_FULL */ |
 292                                    (chan->ramht->base.node->offset >> 4));
 293         bar->flush(bar);
 294         return 0;
 295 }
 296
 297 void
 298 nv50_fifo_chan_dtor(struct nouveau_object *object)
 299 {
 300         struct nv50_fifo_chan *chan = (void *)object;
 301         nouveau_ramht_ref(NULL, &chan->ramht);
 302         nouveau_fifo_channel_destroy(&chan->base);
 303 }
 304
 305 static int
 306 nv50_fifo_chan_init(struct nouveau_object *object)
 307 {
 308         struct nv50_fifo_priv *priv = (void *)object->engine;
 309         struct nv50_fifo_base *base = (void *)object->parent;
 310         struct nv50_fifo_chan *chan = (void *)object;
 311         struct nouveau_gpuobj *ramfc = base->ramfc;
 312         u32 chid = chan->base.chid;
 313         int ret;
 314
 315         ret = nouveau_fifo_channel_init(&chan->base);
 316         if (ret)
 317                 return ret;
 318
 319         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
 320         nv50_fifo_playlist_update(priv);
 321         return 0;
 322 }
 323
 324 int
 325 nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 326 {
 327         struct nv50_fifo_priv *priv = (void *)object->engine;
 328         struct nv50_fifo_chan *chan = (void *)object;
 329         u32 chid = chan->base.chid;
 330
 331         /* remove channel from playlist, fifo will unload context */
 332         nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
 333         nv50_fifo_playlist_update(priv);
 334         nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
 335
 336         return nouveau_fifo_channel_fini(&chan->base, suspend);
 337 }
 338
 339 static struct nouveau_ofuncs
 340 nv50_fifo_ofuncs_dma = {
 341         .ctor = nv50_fifo_chan_ctor_dma,
 342         .dtor = nv50_fifo_chan_dtor,
 343         .init = nv50_fifo_chan_init,
 344         .fini = nv50_fifo_chan_fini,
 345         .rd32 = _nouveau_fifo_channel_rd32,
 346         .wr32 = _nouveau_fifo_channel_wr32,
 347 };
 348
 349 static struct nouveau_ofuncs
 350 nv50_fifo_ofuncs_ind = {
 351         .ctor = nv50_fifo_chan_ctor_ind,
 352         .dtor = nv50_fifo_chan_dtor,
 353         .init = nv50_fifo_chan_init,
 354         .fini = nv50_fifo_chan_fini,
 355         .rd32 = _nouveau_fifo_channel_rd32,
 356         .wr32 = _nouveau_fifo_channel_wr32,
 357 };
 358
 359 static struct nouveau_oclass
 360 nv50_fifo_sclass[] = {
 361         { NV50_CHANNEL_DMA_CLASS, &nv50_fifo_ofuncs_dma },
 362         { NV50_CHANNEL_IND_CLASS, &nv50_fifo_ofuncs_ind },
 363         {}
 364 };
 365
 366 /*******************************************************************************
 367  * FIFO context - basically just the instmem reserved for the channel
 368  ******************************************************************************/
 369
 370 static int
 371 nv50_fifo_context_ctor(struct nouveau_object *parent,
 372                        struct nouveau_object *engine,
 373                        struct nouveau_oclass *oclass, void *data, u32 size,
 374                        struct nouveau_object **pobject)
 375 {
 376         struct nv50_fifo_base *base;
 377         int ret;
 378
 379         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 380                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 381         *pobject = nv_object(base);
 382         if (ret)
 383                 return ret;
 384
 385         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
 386                                  0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 387         if (ret)
 388                 return ret;
 389
 390         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
 391                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 392         if (ret)
 393                 return ret;
 394
 395         ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
 396                                 &base->pgd);
 397         if (ret)
 398                 return ret;
 399
 400         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 401         if (ret)
 402                 return ret;
 403
 404         return 0;
 405 }
 406
 407 void
 408 nv50_fifo_context_dtor(struct nouveau_object *object)
 409 {
 410         struct nv50_fifo_base *base = (void *)object;
 411         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 412         nouveau_gpuobj_ref(NULL, &base->pgd);
 413         nouveau_gpuobj_ref(NULL, &base->eng);
 414         nouveau_gpuobj_ref(NULL, &base->ramfc);
 415         nouveau_gpuobj_ref(NULL, &base->cache);
 416         nouveau_fifo_context_destroy(&base->base);
 417 }
 418
 419 static struct nouveau_oclass
 420 nv50_fifo_cclass = {
 421         .handle = NV_ENGCTX(FIFO, 0x50),
 422         .ofuncs = &(struct nouveau_ofuncs) {
 423                 .ctor = nv50_fifo_context_ctor,
 424                 .dtor = nv50_fifo_context_dtor,
 425                 .init = _nouveau_fifo_context_init,
 426                 .fini = _nouveau_fifo_context_fini,
 427                 .rd32 = _nouveau_fifo_context_rd32,
 428                 .wr32 = _nouveau_fifo_context_wr32,
 429         },
 430 };
 431
 432 /*******************************************************************************
 433  * PFIFO engine
 434  ******************************************************************************/
 435
 436 static int
 437 nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 438                struct nouveau_oclass *oclass, void *data, u32 size,
 439                struct nouveau_object **pobject)
 440 {
 441         struct nv50_fifo_priv *priv;
 442         int ret;
 443
 444         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 445         *pobject = nv_object(priv);
 446         if (ret)
 447                 return ret;
 448
 449         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
 450                                 &priv->playlist[0]);
 451         if (ret)
 452                 return ret;
 453
 454         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
 455                                 &priv->playlist[1]);
 456         if (ret)
 457                 return ret;
 458
 459         nv_subdev(priv)->unit = 0x00000100;
 460         nv_subdev(priv)->intr = nv04_fifo_intr;
 461         nv_engine(priv)->cclass = &nv50_fifo_cclass;
 462         nv_engine(priv)->sclass = nv50_fifo_sclass;
 463         return 0;
 464 }
 465
 466 void
 467 nv50_fifo_dtor(struct nouveau_object *object)
 468 {
 469         struct nv50_fifo_priv *priv = (void *)object;
 470
 471         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 472         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 473
 474         nouveau_fifo_destroy(&priv->base);
 475 }
 476
 477 int
 478 nv50_fifo_init(struct nouveau_object *object)
 479 {
 480         struct nv50_fifo_priv *priv = (void *)object;
 481         int ret, i;
 482
 483         ret = nouveau_fifo_init(&priv->base);
 484         if (ret)
 485                 return ret;
 486
 487         nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
 488         nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
 489         nv_wr32(priv, 0x00250c, 0x6f3cfc34);
 490         nv_wr32(priv, 0x002044, 0x01003fff);
 491
 492         nv_wr32(priv, 0x002100, 0xffffffff);
 493         nv_wr32(priv, 0x002140, 0xbfffffff);
 494
 495         for (i = 0; i < 128; i++)
 496                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
 497         nv50_fifo_playlist_update_locked(priv);
 498
 499         nv_wr32(priv, 0x003200, 0x00000001);
 500         nv_wr32(priv, 0x003250, 0x00000001);
 501         nv_wr32(priv, 0x002500, 0x00000001);
 502         return 0;
 503 }
 504
 505 struct nouveau_oclass *
 506 nv50_fifo_oclass = &(struct nouveau_oclass) {
 507         .handle = NV_ENGINE(FIFO, 0x50),
 508         .ofuncs = &(struct nouveau_ofuncs) {
 509                 .ctor = nv50_fifo_ctor,
 510                 .dtor = nv50_fifo_dtor,
 511                 .init = nv50_fifo_init,
 512                 .fini = _nouveau_fifo_fini,
 513         },
 514 };