drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  41 {
  42         /* paranoia */
  43         if (!mode->crtc_htotal)
  44                 return 1;
  45
  46         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  47 }
  48
  49 static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  50 {
  51         struct drm_device *dev = crtc->base.dev;
  52         const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
  53         enum pipe pipe = crtc->pipe;
  54         long timeout = msecs_to_jiffies_timeout(1);
  55         int scanline, min, max, vblank_start;
  56         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  57         DEFINE_WAIT(wait);
  58
  59         WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
  60
  61         vblank_start = mode->crtc_vblank_start;
  62         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  63                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  64
  65         /* FIXME needs to be calibrated sensibly */
  66         min = vblank_start - usecs_to_scanlines(mode, 100);
  67         max = vblank_start - 1;
  68
  69         if (min <= 0 || max <= 0)
  70                 return false;
  71
  72         if (WARN_ON(drm_vblank_get(dev, pipe)))
  73                 return false;
  74
  75         local_irq_disable();
  76
  77         trace_i915_pipe_update_start(crtc, min, max);
  78
  79         for (;;) {
  80                 /*
  81                  * prepare_to_wait() has a memory barrier, which guarantees
  82                  * other CPUs can see the task state update by the time we
  83                  * read the scanline.
  84                  */
  85                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  86
  87                 scanline = intel_get_crtc_scanline(crtc);
  88                 if (scanline < min || scanline > max)
  89                         break;
  90
  91                 if (timeout <= 0) {
  92                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  93                                   pipe_name(crtc->pipe));
  94                         break;
  95                 }
  96
  97                 local_irq_enable();
  98
  99                 timeout = schedule_timeout(timeout);
 100
 101                 local_irq_disable();
 102         }
 103
 104         finish_wait(wq, &wait);
 105
 106         drm_vblank_put(dev, pipe);
 107
 108         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 109
 110         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 111
 112         return true;
 113 }
 114
 115 static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 116 {
 117         struct drm_device *dev = crtc->base.dev;
 118         enum pipe pipe = crtc->pipe;
 119         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 120
 121         trace_i915_pipe_update_end(crtc, end_vbl_count);
 122
 123         local_irq_enable();
 124
 125         if (start_vbl_count != end_vbl_count)
 126                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 127                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 128 }
 129
 130 static void intel_update_primary_plane(struct intel_crtc *crtc)
 131 {
 132         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 133         int reg = DSPCNTR(crtc->plane);
 134
 135         if (crtc->primary_enabled)
 136                 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 137         else
 138                 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 139 }
 140
 141 static void
 142 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 143                  struct drm_framebuffer *fb,
 144                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 145                  unsigned int crtc_w, unsigned int crtc_h,
 146                  uint32_t x, uint32_t y,
 147                  uint32_t src_w, uint32_t src_h)
 148 {
 149         struct drm_device *dev = drm_plane->dev;
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 152         const int pipe = intel_plane->pipe;
 153         const int plane = intel_plane->plane + 1;
 154         u32 plane_ctl, stride;
 155         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 156
 157         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 158
 159         /* Mask out pixel format bits in case we change it */
 160         plane_ctl &= ~PLANE_CTL_FORMAT_MASK;
 161         plane_ctl &= ~PLANE_CTL_ORDER_RGBX;
 162         plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK;
 163         plane_ctl &= ~PLANE_CTL_TILED_MASK;
 164         plane_ctl &= ~PLANE_CTL_ALPHA_MASK;
 165         plane_ctl &= ~PLANE_CTL_ROTATE_MASK;
 166
 167         /* Trickle feed has to be enabled */
 168         plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE;
 169
 170         switch (fb->pixel_format) {
 171         case DRM_FORMAT_RGB565:
 172                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
 173                 break;
 174         case DRM_FORMAT_XBGR8888:
 175                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
 176                 break;
 177         case DRM_FORMAT_XRGB8888:
 178                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
 179                 break;
 180         /*
 181          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
 182          * to be already pre-multiplied. We need to add a knob (or a different
 183          * DRM_FORMAT) for user-space to configure that.
 184          */
 185         case DRM_FORMAT_ABGR8888:
 186                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
 187                              PLANE_CTL_ORDER_RGBX |
 188                              PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 189                 break;
 190         case DRM_FORMAT_ARGB8888:
 191                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
 192                              PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 193                 break;
 194         case DRM_FORMAT_YUYV:
 195                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
 196                 break;
 197         case DRM_FORMAT_YVYU:
 198                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
 199                 break;
 200         case DRM_FORMAT_UYVY:
 201                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
 202                 break;
 203         case DRM_FORMAT_VYUY:
 204                 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 205                 break;
 206         default:
 207                 BUG();
 208         }
 209
 210         switch (obj->tiling_mode) {
 211         case I915_TILING_NONE:
 212                 stride = fb->pitches[0] >> 6;
 213                 break;
 214         case I915_TILING_X:
 215                 plane_ctl |= PLANE_CTL_TILED_X;
 216                 stride = fb->pitches[0] >> 9;
 217                 break;
 218         default:
 219                 BUG();
 220         }
 221         if (intel_plane->rotation == BIT(DRM_ROTATE_180))
 222                 plane_ctl |= PLANE_CTL_ROTATE_180;
 223
 224         plane_ctl |= PLANE_CTL_ENABLE;
 225         plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 226
 227         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 228                                        pixel_size, true,
 229                                        src_w != crtc_w || src_h != crtc_h);
 230
 231         /* Sizes are 0 based */
 232         src_w--;
 233         src_h--;
 234         crtc_w--;
 235         crtc_h--;
 236
 237         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
 238         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 239         I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 240         I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 241         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 242         I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));
 243         POSTING_READ(PLANE_SURF(pipe, plane));
 244 }
 245
 246 static void
 247 skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
 248 {
 249         struct drm_device *dev = drm_plane->dev;
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 252         const int pipe = intel_plane->pipe;
 253         const int plane = intel_plane->plane + 1;
 254
 255         I915_WRITE(PLANE_CTL(pipe, plane),
 256                    I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
 257
 258         /* Activate double buffered register update */
 259         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 260         POSTING_READ(PLANE_CTL(pipe, plane));
 261
 262         intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false);
 263 }
 264
 265 static int
 266 skl_update_colorkey(struct drm_plane *drm_plane,
 267                     struct drm_intel_sprite_colorkey *key)
 268 {
 269         struct drm_device *dev = drm_plane->dev;
 270         struct drm_i915_private *dev_priv = dev->dev_private;
 271         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 272         const int pipe = intel_plane->pipe;
 273         const int plane = intel_plane->plane;
 274         u32 plane_ctl;
 275
 276         I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 277         I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 278         I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 279
 280         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 281         plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK;
 282         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 283                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 284         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 285                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 286         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 287
 288         POSTING_READ(PLANE_CTL(pipe, plane));
 289
 290         return 0;
 291 }
 292
 293 static void
 294 skl_get_colorkey(struct drm_plane *drm_plane,
 295                  struct drm_intel_sprite_colorkey *key)
 296 {
 297         struct drm_device *dev = drm_plane->dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 300         const int pipe = intel_plane->pipe;
 301         const int plane = intel_plane->plane;
 302         u32 plane_ctl;
 303
 304         key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane));
 305         key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane));
 306         key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane));
 307
 308         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
 309
 310         switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) {
 311         case PLANE_CTL_KEY_ENABLE_DESTINATION:
 312                 key->flags = I915_SET_COLORKEY_DESTINATION;
 313                 break;
 314         case PLANE_CTL_KEY_ENABLE_SOURCE:
 315                 key->flags = I915_SET_COLORKEY_SOURCE;
 316                 break;
 317         default:
 318                 key->flags = I915_SET_COLORKEY_NONE;
 319         }
 320 }
 321
 322 static void
 323 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 324                  struct drm_framebuffer *fb,
 325                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 326                  unsigned int crtc_w, unsigned int crtc_h,
 327                  uint32_t x, uint32_t y,
 328                  uint32_t src_w, uint32_t src_h)
 329 {
 330         struct drm_device *dev = dplane->dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332         struct intel_plane *intel_plane = to_intel_plane(dplane);
 333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 334         int pipe = intel_plane->pipe;
 335         int plane = intel_plane->plane;
 336         u32 sprctl;
 337         unsigned long sprsurf_offset, linear_offset;
 338         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 339         u32 start_vbl_count;
 340         bool atomic_update;
 341
 342         sprctl = I915_READ(SPCNTR(pipe, plane));
 343
 344         /* Mask out pixel format bits in case we change it */
 345         sprctl &= ~SP_PIXFORMAT_MASK;
 346         sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
 347         sprctl &= ~SP_TILED;
 348         sprctl &= ~SP_ROTATE_180;
 349
 350         switch (fb->pixel_format) {
 351         case DRM_FORMAT_YUYV:
 352                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 353                 break;
 354         case DRM_FORMAT_YVYU:
 355                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 356                 break;
 357         case DRM_FORMAT_UYVY:
 358                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 359                 break;
 360         case DRM_FORMAT_VYUY:
 361                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 362                 break;
 363         case DRM_FORMAT_RGB565:
 364                 sprctl |= SP_FORMAT_BGR565;
 365                 break;
 366         case DRM_FORMAT_XRGB8888:
 367                 sprctl |= SP_FORMAT_BGRX8888;
 368                 break;
 369         case DRM_FORMAT_ARGB8888:
 370                 sprctl |= SP_FORMAT_BGRA8888;
 371                 break;
 372         case DRM_FORMAT_XBGR2101010:
 373                 sprctl |= SP_FORMAT_RGBX1010102;
 374                 break;
 375         case DRM_FORMAT_ABGR2101010:
 376                 sprctl |= SP_FORMAT_RGBA1010102;
 377                 break;
 378         case DRM_FORMAT_XBGR8888:
 379                 sprctl |= SP_FORMAT_RGBX8888;
 380                 break;
 381         case DRM_FORMAT_ABGR8888:
 382                 sprctl |= SP_FORMAT_RGBA8888;
 383                 break;
 384         default:
 385                 /*
 386                  * If we get here one of the upper layers failed to filter
 387                  * out the unsupported plane formats
 388                  */
 389                 BUG();
 390                 break;
 391         }
 392
 393         /*
 394          * Enable gamma to match primary/cursor plane behaviour.
 395          * FIXME should be user controllable via propertiesa.
 396          */
 397         sprctl |= SP_GAMMA_ENABLE;
 398
 399         if (obj->tiling_mode != I915_TILING_NONE)
 400                 sprctl |= SP_TILED;
 401
 402         sprctl |= SP_ENABLE;
 403
 404         intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
 405                                        pixel_size, true,
 406                                        src_w != crtc_w || src_h != crtc_h);
 407
 408         /* Sizes are 0 based */
 409         src_w--;
 410         src_h--;
 411         crtc_w--;
 412         crtc_h--;
 413
 414         linear_offset = y * fb->pitches[0] + x * pixel_size;
 415         sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
 416                                                         obj->tiling_mode,
 417                                                         pixel_size,
 418                                                         fb->pitches[0]);
 419         linear_offset -= sprsurf_offset;
 420
 421         if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
 422                 sprctl |= SP_ROTATE_180;
 423
 424                 x += src_w;
 425                 y += src_h;
 426                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 427         }
 428
 429         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 430
 431         intel_update_primary_plane(intel_crtc);
 432
 433         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 434         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 435
 436         if (obj->tiling_mode != I915_TILING_NONE)
 437                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 438         else
 439                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 440
 441         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 442         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 443         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 444                    sprsurf_offset);
 445
 446         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 447
 448         if (atomic_update)
 449                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 450 }
 451
 452 static void
 453 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 454 {
 455         struct drm_device *dev = dplane->dev;
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         struct intel_plane *intel_plane = to_intel_plane(dplane);
 458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 459         int pipe = intel_plane->pipe;
 460         int plane = intel_plane->plane;
 461         u32 start_vbl_count;
 462         bool atomic_update;
 463
 464         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 465
 466         intel_update_primary_plane(intel_crtc);
 467
 468         I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
 469                    ~SP_ENABLE);
 470         /* Activate double buffered register update */
 471         I915_WRITE(SPSURF(pipe, plane), 0);
 472
 473         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 474
 475         if (atomic_update)
 476                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 477
 478         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 479 }
 480
 481 static int
 482 vlv_update_colorkey(struct drm_plane *dplane,
 483                     struct drm_intel_sprite_colorkey *key)
 484 {
 485         struct drm_device *dev = dplane->dev;
 486         struct drm_i915_private *dev_priv = dev->dev_private;
 487         struct intel_plane *intel_plane = to_intel_plane(dplane);
 488         int pipe = intel_plane->pipe;
 489         int plane = intel_plane->plane;
 490         u32 sprctl;
 491
 492         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 493                 return -EINVAL;
 494
 495         I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 496         I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 497         I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 498
 499         sprctl = I915_READ(SPCNTR(pipe, plane));
 500         sprctl &= ~SP_SOURCE_KEY;
 501         if (key->flags & I915_SET_COLORKEY_SOURCE)
 502                 sprctl |= SP_SOURCE_KEY;
 503         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 504
 505         POSTING_READ(SPKEYMSK(pipe, plane));
 506
 507         return 0;
 508 }
 509
 510 static void
 511 vlv_get_colorkey(struct drm_plane *dplane,
 512                  struct drm_intel_sprite_colorkey *key)
 513 {
 514         struct drm_device *dev = dplane->dev;
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516         struct intel_plane *intel_plane = to_intel_plane(dplane);
 517         int pipe = intel_plane->pipe;
 518         int plane = intel_plane->plane;
 519         u32 sprctl;
 520
 521         key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
 522         key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
 523         key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
 524
 525         sprctl = I915_READ(SPCNTR(pipe, plane));
 526         if (sprctl & SP_SOURCE_KEY)
 527                 key->flags = I915_SET_COLORKEY_SOURCE;
 528         else
 529                 key->flags = I915_SET_COLORKEY_NONE;
 530 }
 531
 532 static void
 533 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 534                  struct drm_framebuffer *fb,
 535                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 536                  unsigned int crtc_w, unsigned int crtc_h,
 537                  uint32_t x, uint32_t y,
 538                  uint32_t src_w, uint32_t src_h)
 539 {
 540         struct drm_device *dev = plane->dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         struct intel_plane *intel_plane = to_intel_plane(plane);
 543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 544         int pipe = intel_plane->pipe;
 545         u32 sprctl, sprscale = 0;
 546         unsigned long sprsurf_offset, linear_offset;
 547         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 548         u32 start_vbl_count;
 549         bool atomic_update;
 550
 551         sprctl = I915_READ(SPRCTL(pipe));
 552
 553         /* Mask out pixel format bits in case we change it */
 554         sprctl &= ~SPRITE_PIXFORMAT_MASK;
 555         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
 556         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
 557         sprctl &= ~SPRITE_TILED;
 558         sprctl &= ~SPRITE_ROTATE_180;
 559
 560         switch (fb->pixel_format) {
 561         case DRM_FORMAT_XBGR8888:
 562                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 563                 break;
 564         case DRM_FORMAT_XRGB8888:
 565                 sprctl |= SPRITE_FORMAT_RGBX888;
 566                 break;
 567         case DRM_FORMAT_YUYV:
 568                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 569                 break;
 570         case DRM_FORMAT_YVYU:
 571                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 572                 break;
 573         case DRM_FORMAT_UYVY:
 574                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 575                 break;
 576         case DRM_FORMAT_VYUY:
 577                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 578                 break;
 579         default:
 580                 BUG();
 581         }
 582
 583         /*
 584          * Enable gamma to match primary/cursor plane behaviour.
 585          * FIXME should be user controllable via propertiesa.
 586          */
 587         sprctl |= SPRITE_GAMMA_ENABLE;
 588
 589         if (obj->tiling_mode != I915_TILING_NONE)
 590                 sprctl |= SPRITE_TILED;
 591
 592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 593                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 594         else
 595                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 596
 597         sprctl |= SPRITE_ENABLE;
 598
 599         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 600                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 601
 602         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 603                                        true,
 604                                        src_w != crtc_w || src_h != crtc_h);
 605
 606         /* Sizes are 0 based */
 607         src_w--;
 608         src_h--;
 609         crtc_w--;
 610         crtc_h--;
 611
 612         if (crtc_w != src_w || crtc_h != src_h)
 613                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 614
 615         linear_offset = y * fb->pitches[0] + x * pixel_size;
 616         sprsurf_offset =
 617                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 618                                                pixel_size, fb->pitches[0]);
 619         linear_offset -= sprsurf_offset;
 620
 621         if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
 622                 sprctl |= SPRITE_ROTATE_180;
 623
 624                 /* HSW and BDW does this automagically in hardware */
 625                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 626                         x += src_w;
 627                         y += src_h;
 628                         linear_offset += src_h * fb->pitches[0] +
 629                                 src_w * pixel_size;
 630                 }
 631         }
 632
 633         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 634
 635         intel_update_primary_plane(intel_crtc);
 636
 637         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 638         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 639
 640         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 641          * register */
 642         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 643                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 644         else if (obj->tiling_mode != I915_TILING_NONE)
 645                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 646         else
 647                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 648
 649         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 650         if (intel_plane->can_scale)
 651                 I915_WRITE(SPRSCALE(pipe), sprscale);
 652         I915_WRITE(SPRCTL(pipe), sprctl);
 653         I915_WRITE(SPRSURF(pipe),
 654                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 655
 656         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 657
 658         if (atomic_update)
 659                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 660 }
 661
 662 static void
 663 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 664 {
 665         struct drm_device *dev = plane->dev;
 666         struct drm_i915_private *dev_priv = dev->dev_private;
 667         struct intel_plane *intel_plane = to_intel_plane(plane);
 668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 669         int pipe = intel_plane->pipe;
 670         u32 start_vbl_count;
 671         bool atomic_update;
 672
 673         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 674
 675         intel_update_primary_plane(intel_crtc);
 676
 677         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 678         /* Can't leave the scaler enabled... */
 679         if (intel_plane->can_scale)
 680                 I915_WRITE(SPRSCALE(pipe), 0);
 681         /* Activate double buffered register update */
 682         I915_WRITE(SPRSURF(pipe), 0);
 683
 684         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 685
 686         if (atomic_update)
 687                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 688
 689         /*
 690          * Avoid underruns when disabling the sprite.
 691          * FIXME remove once watermark updates are done properly.
 692          */
 693         intel_wait_for_vblank(dev, pipe);
 694
 695         intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
 696 }
 697
 698 static int
 699 ivb_update_colorkey(struct drm_plane *plane,
 700                     struct drm_intel_sprite_colorkey *key)
 701 {
 702         struct drm_device *dev = plane->dev;
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         struct intel_plane *intel_plane;
 705         u32 sprctl;
 706         int ret = 0;
 707
 708         intel_plane = to_intel_plane(plane);
 709
 710         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 711         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 712         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 713
 714         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 715         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 716         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 717                 sprctl |= SPRITE_DEST_KEY;
 718         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 719                 sprctl |= SPRITE_SOURCE_KEY;
 720         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 721
 722         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 723
 724         return ret;
 725 }
 726
 727 static void
 728 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 729 {
 730         struct drm_device *dev = plane->dev;
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732         struct intel_plane *intel_plane;
 733         u32 sprctl;
 734
 735         intel_plane = to_intel_plane(plane);
 736
 737         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 738         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 739         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 740         key->flags = 0;
 741
 742         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 743
 744         if (sprctl & SPRITE_DEST_KEY)
 745                 key->flags = I915_SET_COLORKEY_DESTINATION;
 746         else if (sprctl & SPRITE_SOURCE_KEY)
 747                 key->flags = I915_SET_COLORKEY_SOURCE;
 748         else
 749                 key->flags = I915_SET_COLORKEY_NONE;
 750 }
 751
 752 static void
 753 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 754                  struct drm_framebuffer *fb,
 755                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 756                  unsigned int crtc_w, unsigned int crtc_h,
 757                  uint32_t x, uint32_t y,
 758                  uint32_t src_w, uint32_t src_h)
 759 {
 760         struct drm_device *dev = plane->dev;
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         struct intel_plane *intel_plane = to_intel_plane(plane);
 763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 764         int pipe = intel_plane->pipe;
 765         unsigned long dvssurf_offset, linear_offset;
 766         u32 dvscntr, dvsscale;
 767         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 768         u32 start_vbl_count;
 769         bool atomic_update;
 770
 771         dvscntr = I915_READ(DVSCNTR(pipe));
 772
 773         /* Mask out pixel format bits in case we change it */
 774         dvscntr &= ~DVS_PIXFORMAT_MASK;
 775         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 776         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 777         dvscntr &= ~DVS_TILED;
 778         dvscntr &= ~DVS_ROTATE_180;
 779
 780         switch (fb->pixel_format) {
 781         case DRM_FORMAT_XBGR8888:
 782                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 783                 break;
 784         case DRM_FORMAT_XRGB8888:
 785                 dvscntr |= DVS_FORMAT_RGBX888;
 786                 break;
 787         case DRM_FORMAT_YUYV:
 788                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 789                 break;
 790         case DRM_FORMAT_YVYU:
 791                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 792                 break;
 793         case DRM_FORMAT_UYVY:
 794                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 795                 break;
 796         case DRM_FORMAT_VYUY:
 797                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 798                 break;
 799         default:
 800                 BUG();
 801         }
 802
 803         /*
 804          * Enable gamma to match primary/cursor plane behaviour.
 805          * FIXME should be user controllable via propertiesa.
 806          */
 807         dvscntr |= DVS_GAMMA_ENABLE;
 808
 809         if (obj->tiling_mode != I915_TILING_NONE)
 810                 dvscntr |= DVS_TILED;
 811
 812         if (IS_GEN6(dev))
 813                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 814         dvscntr |= DVS_ENABLE;
 815
 816         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 817                                        pixel_size, true,
 818                                        src_w != crtc_w || src_h != crtc_h);
 819
 820         /* Sizes are 0 based */
 821         src_w--;
 822         src_h--;
 823         crtc_w--;
 824         crtc_h--;
 825
 826         dvsscale = 0;
 827         if (crtc_w != src_w || crtc_h != src_h)
 828                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 829
 830         linear_offset = y * fb->pitches[0] + x * pixel_size;
 831         dvssurf_offset =
 832                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 833                                                pixel_size, fb->pitches[0]);
 834         linear_offset -= dvssurf_offset;
 835
 836         if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
 837                 dvscntr |= DVS_ROTATE_180;
 838
 839                 x += src_w;
 840                 y += src_h;
 841                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 842         }
 843
 844         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 845
 846         intel_update_primary_plane(intel_crtc);
 847
 848         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 849         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 850
 851         if (obj->tiling_mode != I915_TILING_NONE)
 852                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 853         else
 854                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 855
 856         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 857         I915_WRITE(DVSSCALE(pipe), dvsscale);
 858         I915_WRITE(DVSCNTR(pipe), dvscntr);
 859         I915_WRITE(DVSSURF(pipe),
 860                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 861
 862         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 863
 864         if (atomic_update)
 865                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 866 }
 867
 868 static void
 869 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 870 {
 871         struct drm_device *dev = plane->dev;
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873         struct intel_plane *intel_plane = to_intel_plane(plane);
 874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 875         int pipe = intel_plane->pipe;
 876         u32 start_vbl_count;
 877         bool atomic_update;
 878
 879         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
 880
 881         intel_update_primary_plane(intel_crtc);
 882
 883         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 884         /* Disable the scaler */
 885         I915_WRITE(DVSSCALE(pipe), 0);
 886         /* Flush double buffered register updates */
 887         I915_WRITE(DVSSURF(pipe), 0);
 888
 889         intel_flush_primary_plane(dev_priv, intel_crtc->plane);
 890
 891         if (atomic_update)
 892                 intel_pipe_update_end(intel_crtc, start_vbl_count);
 893
 894         /*
 895          * Avoid underruns when disabling the sprite.
 896          * FIXME remove once watermark updates are done properly.
 897          */
 898         intel_wait_for_vblank(dev, pipe);
 899
 900         intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
 901 }
 902
 903 static void
 904 intel_post_enable_primary(struct drm_crtc *crtc)
 905 {
 906         struct drm_device *dev = crtc->dev;
 907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 908
 909         /*
 910          * BDW signals flip done immediately if the plane
 911          * is disabled, even if the plane enable is already
 912          * armed to occur at the next vblank :(
 913          */
 914         if (IS_BROADWELL(dev))
 915                 intel_wait_for_vblank(dev, intel_crtc->pipe);
 916
 917         /*
 918          * FIXME IPS should be fine as long as one plane is
 919          * enabled, but in practice it seems to have problems
 920          * when going from primary only to sprite only and vice
 921          * versa.
 922          */
 923         hsw_enable_ips(intel_crtc);
 924
 925         mutex_lock(&dev->struct_mutex);
 926         intel_update_fbc(dev);
 927         mutex_unlock(&dev->struct_mutex);
 928 }
 929
 930 static void
 931 intel_pre_disable_primary(struct drm_crtc *crtc)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 936
 937         mutex_lock(&dev->struct_mutex);
 938         if (dev_priv->fbc.plane == intel_crtc->plane)
 939                 intel_disable_fbc(dev);
 940         mutex_unlock(&dev->struct_mutex);
 941
 942         /*
 943          * FIXME IPS should be fine as long as one plane is
 944          * enabled, but in practice it seems to have problems
 945          * when going from primary only to sprite only and vice
 946          * versa.
 947          */
 948         hsw_disable_ips(intel_crtc);
 949 }
 950
 951 static int
 952 ilk_update_colorkey(struct drm_plane *plane,
 953                     struct drm_intel_sprite_colorkey *key)
 954 {
 955         struct drm_device *dev = plane->dev;
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         struct intel_plane *intel_plane;
 958         u32 dvscntr;
 959         int ret = 0;
 960
 961         intel_plane = to_intel_plane(plane);
 962
 963         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 964         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 965         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 966
 967         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 968         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 969         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 970                 dvscntr |= DVS_DEST_KEY;
 971         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 972                 dvscntr |= DVS_SOURCE_KEY;
 973         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 974
 975         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 976
 977         return ret;
 978 }
 979
 980 static void
 981 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 982 {
 983         struct drm_device *dev = plane->dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         struct intel_plane *intel_plane;
 986         u32 dvscntr;
 987
 988         intel_plane = to_intel_plane(plane);
 989
 990         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 991         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 992         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 993         key->flags = 0;
 994
 995         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 996
 997         if (dvscntr & DVS_DEST_KEY)
 998                 key->flags = I915_SET_COLORKEY_DESTINATION;
 999         else if (dvscntr & DVS_SOURCE_KEY)
1000                 key->flags = I915_SET_COLORKEY_SOURCE;
1001         else
1002                 key->flags = I915_SET_COLORKEY_NONE;
1003 }
1004
1005 static bool
1006 format_is_yuv(uint32_t format)
1007 {
1008         switch (format) {
1009         case DRM_FORMAT_YUYV:
1010         case DRM_FORMAT_UYVY:
1011         case DRM_FORMAT_VYUY:
1012         case DRM_FORMAT_YVYU:
1013                 return true;
1014         default:
1015                 return false;
1016         }
1017 }
1018
1019 static bool colorkey_enabled(struct intel_plane *intel_plane)
1020 {
1021         struct drm_intel_sprite_colorkey key;
1022
1023         intel_plane->get_colorkey(&intel_plane->base, &key);
1024
1025         return key.flags != I915_SET_COLORKEY_NONE;
1026 }
1027
1028 static int
1029 intel_check_sprite_plane(struct drm_plane *plane,
1030                          struct intel_plane_state *state)
1031 {
1032         struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
1033         struct intel_plane *intel_plane = to_intel_plane(plane);
1034         struct drm_framebuffer *fb = state->fb;
1035         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1036         struct drm_i915_gem_object *obj = intel_fb->obj;
1037         int crtc_x, crtc_y;
1038         unsigned int crtc_w, crtc_h;
1039         uint32_t src_x, src_y, src_w, src_h;
1040         struct drm_rect *src = &state->src;
1041         struct drm_rect *dst = &state->dst;
1042         struct drm_rect *orig_src = &state->orig_src;
1043         const struct drm_rect *clip = &state->clip;
1044         int hscale, vscale;
1045         int max_scale, min_scale;
1046         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
1047
1048         /* Don't modify another pipe's plane */
1049         if (intel_plane->pipe != intel_crtc->pipe) {
1050                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
1051                 return -EINVAL;
1052         }
1053
1054         /* FIXME check all gen limits */
1055         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
1056                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
1057                 return -EINVAL;
1058         }
1059
1060         /* Sprite planes can be linear or x-tiled surfaces */
1061         switch (obj->tiling_mode) {
1062                 case I915_TILING_NONE:
1063                 case I915_TILING_X:
1064                         break;
1065                 default:
1066                         DRM_DEBUG_KMS("Unsupported tiling mode\n");
1067                         return -EINVAL;
1068         }
1069
1070         /*
1071          * FIXME the following code does a bunch of fuzzy adjustments to the
1072          * coordinates and sizes. We probably need some way to decide whether
1073          * more strict checking should be done instead.
1074          */
1075         max_scale = intel_plane->max_downscale << 16;
1076         min_scale = intel_plane->can_scale ? 1 : (1 << 16);
1077
1078         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
1079                         intel_plane->rotation);
1080
1081         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
1082         BUG_ON(hscale < 0);
1083
1084         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
1085         BUG_ON(vscale < 0);
1086
1087         state->visible =  drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
1088
1089         crtc_x = dst->x1;
1090         crtc_y = dst->y1;
1091         crtc_w = drm_rect_width(dst);
1092         crtc_h = drm_rect_height(dst);
1093
1094         if (state->visible) {
1095                 /* check again in case clipping clamped the results */
1096                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
1097                 if (hscale < 0) {
1098                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
1099                         drm_rect_debug_print(src, true);
1100                         drm_rect_debug_print(dst, false);
1101
1102                         return hscale;
1103                 }
1104
1105                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
1106                 if (vscale < 0) {
1107                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
1108                         drm_rect_debug_print(src, true);
1109                         drm_rect_debug_print(dst, false);
1110
1111                         return vscale;
1112                 }
1113
1114                 /* Make the source viewport size an exact multiple of the scaling factors. */
1115                 drm_rect_adjust_size(src,
1116                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
1117                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
1118
1119                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1120                                     intel_plane->rotation);
1121
1122                 /* sanity check to make sure the src viewport wasn't enlarged */
1123                 WARN_ON(src->x1 < (int) orig_src->x1 ||
1124                         src->y1 < (int) orig_src->y1 ||
1125                         src->x2 > (int) orig_src->x2 ||
1126                         src->y2 > (int) orig_src->y2);
1127
1128                 /*
1129                  * Hardware doesn't handle subpixel coordinates.
1130                  * Adjust to (macro)pixel boundary, but be careful not to
1131                  * increase the source viewport size, because that could
1132                  * push the downscaling factor out of bounds.
1133                  */
1134                 src_x = src->x1 >> 16;
1135                 src_w = drm_rect_width(src) >> 16;
1136                 src_y = src->y1 >> 16;
1137                 src_h = drm_rect_height(src) >> 16;
1138
1139                 if (format_is_yuv(fb->pixel_format)) {
1140                         src_x &= ~1;
1141                         src_w &= ~1;
1142
1143                         /*
1144                          * Must keep src and dst the
1145                          * same if we can't scale.
1146                          */
1147                         if (!intel_plane->can_scale)
1148                                 crtc_w &= ~1;
1149
1150                         if (crtc_w == 0)
1151                                 state->visible = false;
1152                 }
1153         }
1154
1155         /* Check size restrictions when scaling */
1156         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
1157                 unsigned int width_bytes;
1158
1159                 WARN_ON(!intel_plane->can_scale);
1160
1161                 /* FIXME interlacing min height is 6 */
1162
1163                 if (crtc_w < 3 || crtc_h < 3)
1164                         state->visible = false;
1165
1166                 if (src_w < 3 || src_h < 3)
1167                         state->visible = false;
1168
1169                 width_bytes = ((src_x * pixel_size) & 63) +
1170                                         src_w * pixel_size;
1171
1172                 if (src_w > 2048 || src_h > 2048 ||
1173                     width_bytes > 4096 || fb->pitches[0] > 4096) {
1174                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1175                         return -EINVAL;
1176                 }
1177         }
1178
1179         if (state->visible) {
1180                 src->x1 = src_x;
1181                 src->x2 = src_x + src_w;
1182                 src->y1 = src_y;
1183                 src->y2 = src_y + src_h;
1184         }
1185
1186         dst->x1 = crtc_x;
1187         dst->x2 = crtc_x + crtc_w;
1188         dst->y1 = crtc_y;
1189         dst->y2 = crtc_y + crtc_h;
1190
1191         return 0;
1192 }
1193
1194 static int
1195 intel_commit_sprite_plane(struct drm_plane *plane,
1196                           struct intel_plane_state *state)
1197 {
1198         struct drm_device *dev = plane->dev;
1199         struct drm_crtc *crtc = state->crtc;
1200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1201         struct intel_plane *intel_plane = to_intel_plane(plane);
1202         enum pipe pipe = intel_crtc->pipe;
1203         struct drm_framebuffer *fb = state->fb;
1204         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1205         struct drm_i915_gem_object *obj = intel_fb->obj;
1206         struct drm_i915_gem_object *old_obj = intel_plane->obj;
1207         int crtc_x, crtc_y;
1208         unsigned int crtc_w, crtc_h;
1209         uint32_t src_x, src_y, src_w, src_h;
1210         struct drm_rect *dst = &state->dst;
1211         const struct drm_rect *clip = &state->clip;
1212         bool primary_enabled;
1213         int ret;
1214
1215         /*
1216          * If the sprite is completely covering the primary plane,
1217          * we can disable the primary and save power.
1218          */
1219         primary_enabled = !drm_rect_equals(dst, clip) || colorkey_enabled(intel_plane);
1220         WARN_ON(!primary_enabled && !state->visible && intel_crtc->active);
1221
1222
1223         if (old_obj != obj) {
1224                 mutex_lock(&dev->struct_mutex);
1225
1226                 /* Note that this will apply the VT-d workaround for scanouts,
1227                  * which is more restrictive than required for sprites. (The
1228                  * primary plane requires 256KiB alignment with 64 PTE padding,
1229                  * the sprite planes only require 128KiB alignment and 32 PTE
1230                  * padding.
1231                  */
1232                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
1233                 if (ret == 0)
1234                         i915_gem_track_fb(old_obj, obj,
1235                                           INTEL_FRONTBUFFER_SPRITE(pipe));
1236                 mutex_unlock(&dev->struct_mutex);
1237                 if (ret)
1238                         return ret;
1239         }
1240
1241         intel_plane->crtc_x = state->orig_dst.x1;
1242         intel_plane->crtc_y = state->orig_dst.y1;
1243         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
1244         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
1245         intel_plane->src_x = state->orig_src.x1;
1246         intel_plane->src_y = state->orig_src.y1;
1247         intel_plane->src_w = drm_rect_width(&state->orig_src);
1248         intel_plane->src_h = drm_rect_height(&state->orig_src);
1249         intel_plane->obj = obj;
1250
1251         if (intel_crtc->active) {
1252                 bool primary_was_enabled = intel_crtc->primary_enabled;
1253
1254                 intel_crtc->primary_enabled = primary_enabled;
1255
1256                 if (primary_was_enabled != primary_enabled)
1257                         intel_crtc_wait_for_pending_flips(crtc);
1258
1259                 if (primary_was_enabled && !primary_enabled)
1260                         intel_pre_disable_primary(crtc);
1261
1262                 if (state->visible) {
1263                         crtc_x = state->dst.x1;
1264                         crtc_y = state->dst.y1;
1265                         crtc_w = drm_rect_width(&state->dst);
1266                         crtc_h = drm_rect_height(&state->dst);
1267                         src_x = state->src.x1;
1268                         src_y = state->src.y1;
1269                         src_w = drm_rect_width(&state->src);
1270                         src_h = drm_rect_height(&state->src);
1271                         intel_plane->update_plane(plane, crtc, fb, obj,
1272                                                   crtc_x, crtc_y, crtc_w, crtc_h,
1273                                                   src_x, src_y, src_w, src_h);
1274                 } else {
1275                         intel_plane->disable_plane(plane, crtc);
1276                 }
1277
1278
1279                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe));
1280
1281                 if (!primary_was_enabled && primary_enabled)
1282                         intel_post_enable_primary(crtc);
1283         }
1284
1285         /* Unpin old obj after new one is active to avoid ugliness */
1286         if (old_obj && old_obj != obj) {
1287
1288                 /*
1289                  * It's fairly common to simply update the position of
1290                  * an existing object.  In that case, we don't need to
1291                  * wait for vblank to avoid ugliness, we only need to
1292                  * do the pin & ref bookkeeping.
1293                  */
1294                 if (intel_crtc->active)
1295                         intel_wait_for_vblank(dev, intel_crtc->pipe);
1296
1297                 mutex_lock(&dev->struct_mutex);
1298                 intel_unpin_fb_obj(old_obj);
1299                 mutex_unlock(&dev->struct_mutex);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int
1306 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1307                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
1308                    unsigned int crtc_w, unsigned int crtc_h,
1309                    uint32_t src_x, uint32_t src_y,
1310                    uint32_t src_w, uint32_t src_h)
1311 {
1312         struct intel_plane_state state;
1313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314         int ret;
1315
1316         state.crtc = crtc;
1317         state.fb = fb;
1318
1319         /* sample coordinates in 16.16 fixed point */
1320         state.src.x1 = src_x;
1321         state.src.x2 = src_x + src_w;
1322         state.src.y1 = src_y;
1323         state.src.y2 = src_y + src_h;
1324
1325         /* integer pixels */
1326         state.dst.x1 = crtc_x;
1327         state.dst.x2 = crtc_x + crtc_w;
1328         state.dst.y1 = crtc_y;
1329         state.dst.y2 = crtc_y + crtc_h;
1330
1331         state.clip.x1 = 0;
1332         state.clip.y1 = 0;
1333         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
1334         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
1335         state.orig_src = state.src;
1336         state.orig_dst = state.dst;
1337
1338         ret = intel_check_sprite_plane(plane, &state);
1339         if (ret)
1340                 return ret;
1341
1342         return intel_commit_sprite_plane(plane, &state);
1343 }
1344
1345 static int
1346 intel_disable_plane(struct drm_plane *plane)
1347 {
1348         struct drm_device *dev = plane->dev;
1349         struct intel_plane *intel_plane = to_intel_plane(plane);
1350         struct intel_crtc *intel_crtc;
1351         enum pipe pipe;
1352
1353         if (!plane->fb)
1354                 return 0;
1355
1356         if (WARN_ON(!plane->crtc))
1357                 return -EINVAL;
1358
1359         intel_crtc = to_intel_crtc(plane->crtc);
1360         pipe = intel_crtc->pipe;
1361
1362         if (intel_crtc->active) {
1363                 bool primary_was_enabled = intel_crtc->primary_enabled;
1364
1365                 intel_crtc->primary_enabled = true;
1366
1367                 intel_plane->disable_plane(plane, plane->crtc);
1368
1369                 if (!primary_was_enabled && intel_crtc->primary_enabled)
1370                         intel_post_enable_primary(plane->crtc);
1371         }
1372
1373         if (intel_plane->obj) {
1374                 if (intel_crtc->active)
1375                         intel_wait_for_vblank(dev, intel_plane->pipe);
1376
1377                 mutex_lock(&dev->struct_mutex);
1378                 intel_unpin_fb_obj(intel_plane->obj);
1379                 i915_gem_track_fb(intel_plane->obj, NULL,
1380                                   INTEL_FRONTBUFFER_SPRITE(pipe));
1381                 mutex_unlock(&dev->struct_mutex);
1382
1383                 intel_plane->obj = NULL;
1384         }
1385
1386         return 0;
1387 }
1388
1389 static void intel_destroy_plane(struct drm_plane *plane)
1390 {
1391         struct intel_plane *intel_plane = to_intel_plane(plane);
1392         intel_disable_plane(plane);
1393         drm_plane_cleanup(plane);
1394         kfree(intel_plane);
1395 }
1396
1397 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1398                               struct drm_file *file_priv)
1399 {
1400         struct drm_intel_sprite_colorkey *set = data;
1401         struct drm_plane *plane;
1402         struct intel_plane *intel_plane;
1403         int ret = 0;
1404
1405         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1406                 return -ENODEV;
1407
1408         /* Make sure we don't try to enable both src & dest simultaneously */
1409         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1410                 return -EINVAL;
1411
1412         drm_modeset_lock_all(dev);
1413
1414         plane = drm_plane_find(dev, set->plane_id);
1415         if (!plane) {
1416                 ret = -ENOENT;
1417                 goto out_unlock;
1418         }
1419
1420         intel_plane = to_intel_plane(plane);
1421         ret = intel_plane->update_colorkey(plane, set);
1422
1423 out_unlock:
1424         drm_modeset_unlock_all(dev);
1425         return ret;
1426 }
1427
1428 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1429                               struct drm_file *file_priv)
1430 {
1431         struct drm_intel_sprite_colorkey *get = data;
1432         struct drm_plane *plane;
1433         struct intel_plane *intel_plane;
1434         int ret = 0;
1435
1436         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1437                 return -ENODEV;
1438
1439         drm_modeset_lock_all(dev);
1440
1441         plane = drm_plane_find(dev, get->plane_id);
1442         if (!plane) {
1443                 ret = -ENOENT;
1444                 goto out_unlock;
1445         }
1446
1447         intel_plane = to_intel_plane(plane);
1448         intel_plane->get_colorkey(plane, get);
1449
1450 out_unlock:
1451         drm_modeset_unlock_all(dev);
1452         return ret;
1453 }
1454
1455 int intel_plane_set_property(struct drm_plane *plane,
1456                              struct drm_property *prop,
1457                              uint64_t val)
1458 {
1459         struct drm_device *dev = plane->dev;
1460         struct intel_plane *intel_plane = to_intel_plane(plane);
1461         uint64_t old_val;
1462         int ret = -ENOENT;
1463
1464         if (prop == dev->mode_config.rotation_property) {
1465                 /* exactly one rotation angle please */
1466                 if (hweight32(val & 0xf) != 1)
1467                         return -EINVAL;
1468
1469                 if (intel_plane->rotation == val)
1470                         return 0;
1471
1472                 old_val = intel_plane->rotation;
1473                 intel_plane->rotation = val;
1474                 ret = intel_plane_restore(plane);
1475                 if (ret)
1476                         intel_plane->rotation = old_val;
1477         }
1478
1479         return ret;
1480 }
1481
1482 int intel_plane_restore(struct drm_plane *plane)
1483 {
1484         struct intel_plane *intel_plane = to_intel_plane(plane);
1485
1486         if (!plane->crtc || !plane->fb)
1487                 return 0;
1488
1489         return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
1490                                   intel_plane->crtc_x, intel_plane->crtc_y,
1491                                   intel_plane->crtc_w, intel_plane->crtc_h,
1492                                   intel_plane->src_x, intel_plane->src_y,
1493                                   intel_plane->src_w, intel_plane->src_h);
1494 }
1495
1496 void intel_plane_disable(struct drm_plane *plane)
1497 {
1498         if (!plane->crtc || !plane->fb)
1499                 return;
1500
1501         intel_disable_plane(plane);
1502 }
1503
1504 static const struct drm_plane_funcs intel_plane_funcs = {
1505         .update_plane = intel_update_plane,
1506         .disable_plane = intel_disable_plane,
1507         .destroy = intel_destroy_plane,
1508         .set_property = intel_plane_set_property,
1509 };
1510
1511 static uint32_t ilk_plane_formats[] = {
1512         DRM_FORMAT_XRGB8888,
1513         DRM_FORMAT_YUYV,
1514         DRM_FORMAT_YVYU,
1515         DRM_FORMAT_UYVY,
1516         DRM_FORMAT_VYUY,
1517 };
1518
1519 static uint32_t snb_plane_formats[] = {
1520         DRM_FORMAT_XBGR8888,
1521         DRM_FORMAT_XRGB8888,
1522         DRM_FORMAT_YUYV,
1523         DRM_FORMAT_YVYU,
1524         DRM_FORMAT_UYVY,
1525         DRM_FORMAT_VYUY,
1526 };
1527
1528 static uint32_t vlv_plane_formats[] = {
1529         DRM_FORMAT_RGB565,
1530         DRM_FORMAT_ABGR8888,
1531         DRM_FORMAT_ARGB8888,
1532         DRM_FORMAT_XBGR8888,
1533         DRM_FORMAT_XRGB8888,
1534         DRM_FORMAT_XBGR2101010,
1535         DRM_FORMAT_ABGR2101010,
1536         DRM_FORMAT_YUYV,
1537         DRM_FORMAT_YVYU,
1538         DRM_FORMAT_UYVY,
1539         DRM_FORMAT_VYUY,
1540 };
1541
1542 static uint32_t skl_plane_formats[] = {
1543         DRM_FORMAT_RGB565,
1544         DRM_FORMAT_ABGR8888,
1545         DRM_FORMAT_ARGB8888,
1546         DRM_FORMAT_XBGR8888,
1547         DRM_FORMAT_XRGB8888,
1548         DRM_FORMAT_YUYV,
1549         DRM_FORMAT_YVYU,
1550         DRM_FORMAT_UYVY,
1551         DRM_FORMAT_VYUY,
1552 };
1553
1554 int
1555 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1556 {
1557         struct intel_plane *intel_plane;
1558         unsigned long possible_crtcs;
1559         const uint32_t *plane_formats;
1560         int num_plane_formats;
1561         int ret;
1562
1563         if (INTEL_INFO(dev)->gen < 5)
1564                 return -ENODEV;
1565
1566         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1567         if (!intel_plane)
1568                 return -ENOMEM;
1569
1570         switch (INTEL_INFO(dev)->gen) {
1571         case 5:
1572         case 6:
1573                 intel_plane->can_scale = true;
1574                 intel_plane->max_downscale = 16;
1575                 intel_plane->update_plane = ilk_update_plane;
1576                 intel_plane->disable_plane = ilk_disable_plane;
1577                 intel_plane->update_colorkey = ilk_update_colorkey;
1578                 intel_plane->get_colorkey = ilk_get_colorkey;
1579
1580                 if (IS_GEN6(dev)) {
1581                         plane_formats = snb_plane_formats;
1582                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1583                 } else {
1584                         plane_formats = ilk_plane_formats;
1585                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1586                 }
1587                 break;
1588
1589         case 7:
1590         case 8:
1591                 if (IS_IVYBRIDGE(dev)) {
1592                         intel_plane->can_scale = true;
1593                         intel_plane->max_downscale = 2;
1594                 } else {
1595                         intel_plane->can_scale = false;
1596                         intel_plane->max_downscale = 1;
1597                 }
1598
1599                 if (IS_VALLEYVIEW(dev)) {
1600                         intel_plane->update_plane = vlv_update_plane;
1601                         intel_plane->disable_plane = vlv_disable_plane;
1602                         intel_plane->update_colorkey = vlv_update_colorkey;
1603                         intel_plane->get_colorkey = vlv_get_colorkey;
1604
1605                         plane_formats = vlv_plane_formats;
1606                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1607                 } else {
1608                         intel_plane->update_plane = ivb_update_plane;
1609                         intel_plane->disable_plane = ivb_disable_plane;
1610                         intel_plane->update_colorkey = ivb_update_colorkey;
1611                         intel_plane->get_colorkey = ivb_get_colorkey;
1612
1613                         plane_formats = snb_plane_formats;
1614                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1615                 }
1616                 break;
1617         case 9:
1618                 /*
1619                  * FIXME: Skylake planes can be scaled (with some restrictions),
1620                  * but this is for another time.
1621                  */
1622                 intel_plane->can_scale = false;
1623                 intel_plane->max_downscale = 1;
1624                 intel_plane->update_plane = skl_update_plane;
1625                 intel_plane->disable_plane = skl_disable_plane;
1626                 intel_plane->update_colorkey = skl_update_colorkey;
1627                 intel_plane->get_colorkey = skl_get_colorkey;
1628
1629                 plane_formats = skl_plane_formats;
1630                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1631                 break;
1632         default:
1633                 kfree(intel_plane);
1634                 return -ENODEV;
1635         }
1636
1637         intel_plane->pipe = pipe;
1638         intel_plane->plane = plane;
1639         intel_plane->rotation = BIT(DRM_ROTATE_0);
1640         possible_crtcs = (1 << pipe);
1641         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1642                                        &intel_plane_funcs,
1643                                        plane_formats, num_plane_formats,
1644                                        DRM_PLANE_TYPE_OVERLAY);
1645         if (ret) {
1646                 kfree(intel_plane);
1647                 goto out;
1648         }
1649
1650         if (!dev->mode_config.rotation_property)
1651                 dev->mode_config.rotation_property =
1652                         drm_mode_create_rotation_property(dev,
1653                                                           BIT(DRM_ROTATE_0) |
1654                                                           BIT(DRM_ROTATE_180));
1655
1656         if (dev->mode_config.rotation_property)
1657                 drm_object_attach_property(&intel_plane->base.base,
1658                                            dev->mode_config.rotation_property,
1659                                            intel_plane->rotation);
1660
1661  out:
1662         return ret;
1663 }