drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
  72                                     struct i915_power_well *power_well)
  73 {
  74         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  75         power_well->ops->enable(dev_priv, power_well);
  76         power_well->hw_enabled = true;
  77 }
  78
  79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
  80                                      struct i915_power_well *power_well)
  81 {
  82         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  83         power_well->hw_enabled = false;
  84         power_well->ops->disable(dev_priv, power_well);
  85 }
  86
  87 /*
  88  * We should only use the power well if we explicitly asked the hardware to
  89  * enable it, so check if it's enabled and also check if we've requested it to
  90  * be enabled.
  91  */
  92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  93                                    struct i915_power_well *power_well)
  94 {
  95         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  96                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  97 }
  98
  99 /**
 100  * __intel_display_power_is_enabled - unlocked check for a power domain
 101  * @dev_priv: i915 device instance
 102  * @domain: power domain to check
 103  *
 104  * This is the unlocked version of intel_display_power_is_enabled() and should
 105  * only be used from error capture and recovery code where deadlocks are
 106  * possible.
 107  *
 108  * Returns:
 109  * True when the power domain is enabled, false otherwise.
 110  */
 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 112                                       enum intel_display_power_domain domain)
 113 {
 114         struct i915_power_domains *power_domains;
 115         struct i915_power_well *power_well;
 116         bool is_enabled;
 117         int i;
 118
 119         if (dev_priv->pm.suspended)
 120                 return false;
 121
 122         power_domains = &dev_priv->power_domains;
 123
 124         is_enabled = true;
 125
 126         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 127                 if (power_well->always_on)
 128                         continue;
 129
 130                 if (!power_well->hw_enabled) {
 131                         is_enabled = false;
 132                         break;
 133                 }
 134         }
 135
 136         return is_enabled;
 137 }
 138
 139 /**
 140  * intel_display_power_is_enabled - check for a power domain
 141  * @dev_priv: i915 device instance
 142  * @domain: power domain to check
 143  *
 144  * This function can be used to check the hw power domain state. It is mostly
 145  * used in hardware state readout functions. Everywhere else code should rely
 146  * upon explicit power domain reference counting to ensure that the hardware
 147  * block is powered up before accessing it.
 148  *
 149  * Callers must hold the relevant modesetting locks to ensure that concurrent
 150  * threads can't disable the power well while the caller tries to read a few
 151  * registers.
 152  *
 153  * Returns:
 154  * True when the power domain is enabled, false otherwise.
 155  */
 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 157                                     enum intel_display_power_domain domain)
 158 {
 159         struct i915_power_domains *power_domains;
 160         bool ret;
 161
 162         power_domains = &dev_priv->power_domains;
 163
 164         mutex_lock(&power_domains->lock);
 165         ret = __intel_display_power_is_enabled(dev_priv, domain);
 166         mutex_unlock(&power_domains->lock);
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * intel_display_set_init_power - set the initial power domain state
 173  * @dev_priv: i915 device instance
 174  * @enable: whether to enable or disable the initial power domain state
 175  *
 176  * For simplicity our driver load/unload and system suspend/resume code assumes
 177  * that all power domains are always enabled. This functions controls the state
 178  * of this little hack. While the initial power domain state is enabled runtime
 179  * pm is effectively disabled.
 180  */
 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 182                                   bool enable)
 183 {
 184         if (dev_priv->power_domains.init_power_on == enable)
 185                 return;
 186
 187         if (enable)
 188                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 189         else
 190                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 191
 192         dev_priv->power_domains.init_power_on = enable;
 193 }
 194
 195 /*
 196  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 197  * when not needed anymore. We have 4 registers that can request the power well
 198  * to be enabled, and it will only be disabled if none of the registers is
 199  * requesting it to be enabled.
 200  */
 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 202 {
 203         struct drm_device *dev = dev_priv->dev;
 204
 205         /*
 206          * After we re-enable the power well, if we touch VGA register 0x3d5
 207          * we'll get unclaimed register interrupts. This stops after we write
 208          * anything to the VGA MSR register. The vgacon module uses this
 209          * register all the time, so if we unbind our driver and, as a
 210          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 211          * console_unlock(). So make here we touch the VGA MSR register, making
 212          * sure vgacon can keep working normally without triggering interrupts
 213          * and error messages.
 214          */
 215         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 216         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 217         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 218
 219         if (IS_BROADWELL(dev))
 220                 gen8_irq_power_well_post_enable(dev_priv,
 221                                                 1 << PIPE_C | 1 << PIPE_B);
 222 }
 223
 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 225                                        struct i915_power_well *power_well)
 226 {
 227         struct drm_device *dev = dev_priv->dev;
 228
 229         /*
 230          * After we re-enable the power well, if we touch VGA register 0x3d5
 231          * we'll get unclaimed register interrupts. This stops after we write
 232          * anything to the VGA MSR register. The vgacon module uses this
 233          * register all the time, so if we unbind our driver and, as a
 234          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 235          * console_unlock(). So make here we touch the VGA MSR register, making
 236          * sure vgacon can keep working normally without triggering interrupts
 237          * and error messages.
 238          */
 239         if (power_well->data == SKL_DISP_PW_2) {
 240                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 241                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 242                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 243
 244                 gen8_irq_power_well_post_enable(dev_priv,
 245                                                 1 << PIPE_C | 1 << PIPE_B);
 246         }
 247
 248         if (power_well->data == SKL_DISP_PW_1) {
 249                 intel_prepare_ddi(dev);
 250                 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
 251         }
 252 }
 253
 254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 255                                struct i915_power_well *power_well, bool enable)
 256 {
 257         bool is_enabled, enable_requested;
 258         uint32_t tmp;
 259
 260         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 261         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 262         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 263
 264         if (enable) {
 265                 if (!enable_requested)
 266                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 267                                    HSW_PWR_WELL_ENABLE_REQUEST);
 268
 269                 if (!is_enabled) {
 270                         DRM_DEBUG_KMS("Enabling power well\n");
 271                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 272                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 273                                 DRM_ERROR("Timeout enabling power well\n");
 274                         hsw_power_well_post_enable(dev_priv);
 275                 }
 276
 277         } else {
 278                 if (enable_requested) {
 279                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 280                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 281                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 282                 }
 283         }
 284 }
 285
 286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 287         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 288         BIT(POWER_DOMAIN_PIPE_B) |                      \
 289         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 290         BIT(POWER_DOMAIN_PIPE_C) |                      \
 291         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 292         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 293         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 294         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 295         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 296         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 297         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 298         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 299         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 300         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 301         BIT(POWER_DOMAIN_AUX_B) |                       \
 302         BIT(POWER_DOMAIN_AUX_C) |                       \
 303         BIT(POWER_DOMAIN_AUX_D) |                       \
 304         BIT(POWER_DOMAIN_AUDIO) |                       \
 305         BIT(POWER_DOMAIN_VGA) |                         \
 306         BIT(POWER_DOMAIN_INIT))
 307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 308         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 309         BIT(POWER_DOMAIN_PLLS) |                        \
 310         BIT(POWER_DOMAIN_PIPE_A) |                      \
 311         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 312         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 313         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 314         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 315         BIT(POWER_DOMAIN_AUX_A) |                       \
 316         BIT(POWER_DOMAIN_INIT))
 317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 318         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 319         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 320         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 321         BIT(POWER_DOMAIN_INIT))
 322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 323         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 324         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 325         BIT(POWER_DOMAIN_INIT))
 326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 327         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 328         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 329         BIT(POWER_DOMAIN_INIT))
 330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 331         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 332         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 333         BIT(POWER_DOMAIN_INIT))
 334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
 335         SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |         \
 336         BIT(POWER_DOMAIN_PLLS) |                        \
 337         BIT(POWER_DOMAIN_INIT))
 338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 339         (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 340         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 341         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 342         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 343         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 344         SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
 345         SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
 346         BIT(POWER_DOMAIN_INIT))
 347
 348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 349         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 350         BIT(POWER_DOMAIN_PIPE_B) |                      \
 351         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 352         BIT(POWER_DOMAIN_PIPE_C) |                      \
 353         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 354         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 355         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 356         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 357         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 358         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 359         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 360         BIT(POWER_DOMAIN_AUX_B) |                       \
 361         BIT(POWER_DOMAIN_AUX_C) |                       \
 362         BIT(POWER_DOMAIN_AUDIO) |                       \
 363         BIT(POWER_DOMAIN_VGA) |                         \
 364         BIT(POWER_DOMAIN_INIT))
 365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 366         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 367         BIT(POWER_DOMAIN_PIPE_A) |                      \
 368         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 369         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 370         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 371         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 372         BIT(POWER_DOMAIN_AUX_A) |                       \
 373         BIT(POWER_DOMAIN_PLLS) |                        \
 374         BIT(POWER_DOMAIN_INIT))
 375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 376         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 377         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 378         BIT(POWER_DOMAIN_INIT))
 379
 380 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 381 {
 382         struct drm_device *dev = dev_priv->dev;
 383
 384         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 385         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 386                 "DC9 already programmed to be enabled.\n");
 387         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 388                 "DC5 still not disabled to enable DC9.\n");
 389         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 390         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 391
 392          /*
 393           * TODO: check for the following to verify the conditions to enter DC9
 394           * state are satisfied:
 395           * 1] Check relevant display engine registers to verify if mode set
 396           * disable sequence was followed.
 397           * 2] Check if display uninitialize sequence is initialized.
 398           */
 399 }
 400
 401 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 402 {
 403         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 404         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 405                 "DC9 already programmed to be disabled.\n");
 406         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 407                 "DC5 still not disabled.\n");
 408
 409          /*
 410           * TODO: check for the following to verify DC9 state was indeed
 411           * entered before programming to disable it:
 412           * 1] Check relevant display engine registers to verify if mode
 413           *  set disable sequence was followed.
 414           * 2] Check if display uninitialize sequence is initialized.
 415           */
 416 }
 417
 418 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 419 {
 420         uint32_t val;
 421
 422         assert_can_enable_dc9(dev_priv);
 423
 424         DRM_DEBUG_KMS("Enabling DC9\n");
 425
 426         val = I915_READ(DC_STATE_EN);
 427         val |= DC_STATE_EN_DC9;
 428         I915_WRITE(DC_STATE_EN, val);
 429         POSTING_READ(DC_STATE_EN);
 430 }
 431
 432 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 433 {
 434         uint32_t val;
 435
 436         assert_can_disable_dc9(dev_priv);
 437
 438         DRM_DEBUG_KMS("Disabling DC9\n");
 439
 440         val = I915_READ(DC_STATE_EN);
 441         val &= ~DC_STATE_EN_DC9;
 442         I915_WRITE(DC_STATE_EN, val);
 443         POSTING_READ(DC_STATE_EN);
 444 }
 445
 446 static void gen9_set_dc_state_debugmask_memory_up(
 447                         struct drm_i915_private *dev_priv)
 448 {
 449         uint32_t val;
 450
 451         /* The below bit doesn't need to be cleared ever afterwards */
 452         val = I915_READ(DC_STATE_DEBUG);
 453         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 454                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 455                 I915_WRITE(DC_STATE_DEBUG, val);
 456                 POSTING_READ(DC_STATE_DEBUG);
 457         }
 458 }
 459
 460 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 461 {
 462         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 463                   "CSR program storage start is NULL\n");
 464         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 465         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 466 }
 467
 468 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 469 {
 470         struct drm_device *dev = dev_priv->dev;
 471         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 472                                         SKL_DISP_PW_2);
 473
 474         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 475         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 476         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 477
 478         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 479                   "DC5 already programmed to be enabled.\n");
 480         WARN_ONCE(dev_priv->pm.suspended,
 481                   "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 482
 483         assert_csr_loaded(dev_priv);
 484 }
 485
 486 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 487 {
 488         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 489                                         SKL_DISP_PW_2);
 490         /*
 491          * During initialization, the firmware may not be loaded yet.
 492          * We still want to make sure that the DC enabling flag is cleared.
 493          */
 494         if (dev_priv->power_domains.initializing)
 495                 return;
 496
 497         WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 498         WARN_ONCE(dev_priv->pm.suspended,
 499                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 500 }
 501
 502 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 503 {
 504         uint32_t val;
 505
 506         assert_can_enable_dc5(dev_priv);
 507
 508         DRM_DEBUG_KMS("Enabling DC5\n");
 509
 510         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 511
 512         val = I915_READ(DC_STATE_EN);
 513         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 514         val |= DC_STATE_EN_UPTO_DC5;
 515         I915_WRITE(DC_STATE_EN, val);
 516         POSTING_READ(DC_STATE_EN);
 517 }
 518
 519 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 520 {
 521         uint32_t val;
 522
 523         assert_can_disable_dc5(dev_priv);
 524
 525         DRM_DEBUG_KMS("Disabling DC5\n");
 526
 527         val = I915_READ(DC_STATE_EN);
 528         val &= ~DC_STATE_EN_UPTO_DC5;
 529         I915_WRITE(DC_STATE_EN, val);
 530         POSTING_READ(DC_STATE_EN);
 531 }
 532
 533 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 534 {
 535         struct drm_device *dev = dev_priv->dev;
 536
 537         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 538         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 539         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 540                   "Backlight is not disabled.\n");
 541         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 542                   "DC6 already programmed to be enabled.\n");
 543
 544         assert_csr_loaded(dev_priv);
 545 }
 546
 547 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 548 {
 549         /*
 550          * During initialization, the firmware may not be loaded yet.
 551          * We still want to make sure that the DC enabling flag is cleared.
 552          */
 553         if (dev_priv->power_domains.initializing)
 554                 return;
 555
 556         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 557                   "DC6 already programmed to be disabled.\n");
 558 }
 559
 560 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 561 {
 562         uint32_t val;
 563
 564         assert_can_enable_dc6(dev_priv);
 565
 566         DRM_DEBUG_KMS("Enabling DC6\n");
 567
 568         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 569
 570         val = I915_READ(DC_STATE_EN);
 571         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 572         val |= DC_STATE_EN_UPTO_DC6;
 573         I915_WRITE(DC_STATE_EN, val);
 574         POSTING_READ(DC_STATE_EN);
 575 }
 576
 577 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 578 {
 579         uint32_t val;
 580
 581         assert_can_disable_dc6(dev_priv);
 582
 583         DRM_DEBUG_KMS("Disabling DC6\n");
 584
 585         val = I915_READ(DC_STATE_EN);
 586         val &= ~DC_STATE_EN_UPTO_DC6;
 587         I915_WRITE(DC_STATE_EN, val);
 588         POSTING_READ(DC_STATE_EN);
 589 }
 590
 591 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 592                         struct i915_power_well *power_well, bool enable)
 593 {
 594         struct drm_device *dev = dev_priv->dev;
 595         uint32_t tmp, fuse_status;
 596         uint32_t req_mask, state_mask;
 597         bool is_enabled, enable_requested, check_fuse_status = false;
 598
 599         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 600         fuse_status = I915_READ(SKL_FUSE_STATUS);
 601
 602         switch (power_well->data) {
 603         case SKL_DISP_PW_1:
 604                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 605                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 606                         DRM_ERROR("PG0 not enabled\n");
 607                         return;
 608                 }
 609                 break;
 610         case SKL_DISP_PW_2:
 611                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 612                         DRM_ERROR("PG1 in disabled state\n");
 613                         return;
 614                 }
 615                 break;
 616         case SKL_DISP_PW_DDI_A_E:
 617         case SKL_DISP_PW_DDI_B:
 618         case SKL_DISP_PW_DDI_C:
 619         case SKL_DISP_PW_DDI_D:
 620         case SKL_DISP_PW_MISC_IO:
 621                 break;
 622         default:
 623                 WARN(1, "Unknown power well %lu\n", power_well->data);
 624                 return;
 625         }
 626
 627         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 628         enable_requested = tmp & req_mask;
 629         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 630         is_enabled = tmp & state_mask;
 631
 632         if (enable) {
 633                 if (!enable_requested) {
 634                         WARN((tmp & state_mask) &&
 635                                 !I915_READ(HSW_PWR_WELL_BIOS),
 636                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 637                                 when request is to disable!\n");
 638                         if (power_well->data == SKL_DISP_PW_2) {
 639                                 if (GEN9_ENABLE_DC5(dev))
 640                                         gen9_disable_dc5(dev_priv);
 641                                 if (SKL_ENABLE_DC6(dev)) {
 642                                         /*
 643                                          * DDI buffer programming unnecessary during driver-load/resume
 644                                          * as it's already done during modeset initialization then.
 645                                          * It's also invalid here as encoder list is still uninitialized.
 646                                          */
 647                                         if (!dev_priv->power_domains.initializing)
 648                                                 intel_prepare_ddi(dev);
 649                                 }
 650                         }
 651                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 652                 }
 653
 654                 if (!is_enabled) {
 655                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 656                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 657                                 state_mask), 1))
 658                                 DRM_ERROR("%s enable timeout\n",
 659                                         power_well->name);
 660                         check_fuse_status = true;
 661                 }
 662         } else {
 663                 if (enable_requested) {
 664                         if (IS_SKYLAKE(dev) &&
 665                                 (power_well->data == SKL_DISP_PW_1))
 666                                 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
 667                         else {
 668                                 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 669                                 POSTING_READ(HSW_PWR_WELL_DRIVER);
 670                                 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 671                         }
 672
 673                         if (GEN9_ENABLE_DC5(dev) &&
 674                                 power_well->data == SKL_DISP_PW_2)
 675                                         gen9_enable_dc5(dev_priv);
 676                 }
 677         }
 678
 679         if (check_fuse_status) {
 680                 if (power_well->data == SKL_DISP_PW_1) {
 681                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 682                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 683                                 DRM_ERROR("PG1 distributing status timeout\n");
 684                 } else if (power_well->data == SKL_DISP_PW_2) {
 685                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 686                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 687                                 DRM_ERROR("PG2 distributing status timeout\n");
 688                 }
 689         }
 690
 691         if (enable && !is_enabled)
 692                 skl_power_well_post_enable(dev_priv, power_well);
 693 }
 694
 695 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 696                                    struct i915_power_well *power_well)
 697 {
 698         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 699
 700         /*
 701          * We're taking over the BIOS, so clear any requests made by it since
 702          * the driver is in charge now.
 703          */
 704         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 705                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 706 }
 707
 708 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 709                                   struct i915_power_well *power_well)
 710 {
 711         hsw_set_power_well(dev_priv, power_well, true);
 712 }
 713
 714 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 715                                    struct i915_power_well *power_well)
 716 {
 717         hsw_set_power_well(dev_priv, power_well, false);
 718 }
 719
 720 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 721                                         struct i915_power_well *power_well)
 722 {
 723         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 724                 SKL_POWER_WELL_STATE(power_well->data);
 725
 726         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 727 }
 728
 729 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 730                                 struct i915_power_well *power_well)
 731 {
 732         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 733
 734         /* Clear any request made by BIOS as driver is taking over */
 735         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 736 }
 737
 738 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 739                                 struct i915_power_well *power_well)
 740 {
 741         skl_set_power_well(dev_priv, power_well, true);
 742 }
 743
 744 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 745                                 struct i915_power_well *power_well)
 746 {
 747         skl_set_power_well(dev_priv, power_well, false);
 748 }
 749
 750 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 751                                            struct i915_power_well *power_well)
 752 {
 753 }
 754
 755 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 756                                              struct i915_power_well *power_well)
 757 {
 758         return true;
 759 }
 760
 761 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 762                                struct i915_power_well *power_well, bool enable)
 763 {
 764         enum punit_power_well power_well_id = power_well->data;
 765         u32 mask;
 766         u32 state;
 767         u32 ctrl;
 768
 769         mask = PUNIT_PWRGT_MASK(power_well_id);
 770         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 771                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 772
 773         mutex_lock(&dev_priv->rps.hw_lock);
 774
 775 #define COND \
 776         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 777
 778         if (COND)
 779                 goto out;
 780
 781         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 782         ctrl &= ~mask;
 783         ctrl |= state;
 784         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 785
 786         if (wait_for(COND, 100))
 787                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 788                           state,
 789                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 790
 791 #undef COND
 792
 793 out:
 794         mutex_unlock(&dev_priv->rps.hw_lock);
 795 }
 796
 797 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 798                                    struct i915_power_well *power_well)
 799 {
 800         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 801 }
 802
 803 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 804                                   struct i915_power_well *power_well)
 805 {
 806         vlv_set_power_well(dev_priv, power_well, true);
 807 }
 808
 809 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 810                                    struct i915_power_well *power_well)
 811 {
 812         vlv_set_power_well(dev_priv, power_well, false);
 813 }
 814
 815 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 816                                    struct i915_power_well *power_well)
 817 {
 818         int power_well_id = power_well->data;
 819         bool enabled = false;
 820         u32 mask;
 821         u32 state;
 822         u32 ctrl;
 823
 824         mask = PUNIT_PWRGT_MASK(power_well_id);
 825         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 826
 827         mutex_lock(&dev_priv->rps.hw_lock);
 828
 829         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 830         /*
 831          * We only ever set the power-on and power-gate states, anything
 832          * else is unexpected.
 833          */
 834         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 835                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 836         if (state == ctrl)
 837                 enabled = true;
 838
 839         /*
 840          * A transient state at this point would mean some unexpected party
 841          * is poking at the power controls too.
 842          */
 843         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 844         WARN_ON(ctrl != state);
 845
 846         mutex_unlock(&dev_priv->rps.hw_lock);
 847
 848         return enabled;
 849 }
 850
 851 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 852 {
 853         enum pipe pipe;
 854
 855         /*
 856          * Enable the CRI clock source so we can get at the
 857          * display and the reference clock for VGA
 858          * hotplug / manual detection. Supposedly DSI also
 859          * needs the ref clock up and running.
 860          *
 861          * CHV DPLL B/C have some issues if VGA mode is enabled.
 862          */
 863         for_each_pipe(dev_priv->dev, pipe) {
 864                 u32 val = I915_READ(DPLL(pipe));
 865
 866                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 867                 if (pipe != PIPE_A)
 868                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 869
 870                 I915_WRITE(DPLL(pipe), val);
 871         }
 872
 873         spin_lock_irq(&dev_priv->irq_lock);
 874         valleyview_enable_display_irqs(dev_priv);
 875         spin_unlock_irq(&dev_priv->irq_lock);
 876
 877         /*
 878          * During driver initialization/resume we can avoid restoring the
 879          * part of the HW/SW state that will be inited anyway explicitly.
 880          */
 881         if (dev_priv->power_domains.initializing)
 882                 return;
 883
 884         intel_hpd_init(dev_priv);
 885
 886         i915_redisable_vga_power_on(dev_priv->dev);
 887 }
 888
 889 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 890 {
 891         spin_lock_irq(&dev_priv->irq_lock);
 892         valleyview_disable_display_irqs(dev_priv);
 893         spin_unlock_irq(&dev_priv->irq_lock);
 894
 895         vlv_power_sequencer_reset(dev_priv);
 896 }
 897
 898 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 899                                           struct i915_power_well *power_well)
 900 {
 901         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 902
 903         vlv_set_power_well(dev_priv, power_well, true);
 904
 905         vlv_display_power_well_init(dev_priv);
 906 }
 907
 908 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 909                                            struct i915_power_well *power_well)
 910 {
 911         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 912
 913         vlv_display_power_well_deinit(dev_priv);
 914
 915         vlv_set_power_well(dev_priv, power_well, false);
 916 }
 917
 918 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 919                                            struct i915_power_well *power_well)
 920 {
 921         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 922
 923         /* since ref/cri clock was enabled */
 924         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 925
 926         vlv_set_power_well(dev_priv, power_well, true);
 927
 928         /*
 929          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 930          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 931          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 932          *   b. The other bits such as sfr settings / modesel may all
 933          *      be set to 0.
 934          *
 935          * This should only be done on init and resume from S3 with
 936          * both PLLs disabled, or we risk losing DPIO and PLL
 937          * synchronization.
 938          */
 939         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 940 }
 941
 942 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 943                                             struct i915_power_well *power_well)
 944 {
 945         enum pipe pipe;
 946
 947         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 948
 949         for_each_pipe(dev_priv, pipe)
 950                 assert_pll_disabled(dev_priv, pipe);
 951
 952         /* Assert common reset */
 953         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 954
 955         vlv_set_power_well(dev_priv, power_well, false);
 956 }
 957
 958 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 959
 960 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
 961                                                  int power_well_id)
 962 {
 963         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 964         int i;
 965
 966         for (i = 0; i < power_domains->power_well_count; i++) {
 967                 struct i915_power_well *power_well;
 968
 969                 power_well = &power_domains->power_wells[i];
 970                 if (power_well->data == power_well_id)
 971                         return power_well;
 972         }
 973
 974         return NULL;
 975 }
 976
 977 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
 978
 979 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
 980 {
 981         struct i915_power_well *cmn_bc =
 982                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
 983         struct i915_power_well *cmn_d =
 984                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
 985         u32 phy_control = dev_priv->chv_phy_control;
 986         u32 phy_status = 0;
 987         u32 phy_status_mask = 0xffffffff;
 988         u32 tmp;
 989
 990         /*
 991          * The BIOS can leave the PHY is some weird state
 992          * where it doesn't fully power down some parts.
 993          * Disable the asserts until the PHY has been fully
 994          * reset (ie. the power well has been disabled at
 995          * least once).
 996          */
 997         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
 998                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
 999                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1000                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1001                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1002                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1003                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1004
1005         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1006                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1007                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1008                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1009
1010         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1011                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1012
1013                 /* this assumes override is only used to enable lanes */
1014                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1015                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1016
1017                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1018                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1019
1020                 /* CL1 is on whenever anything is on in either channel */
1021                 if (BITS_SET(phy_control,
1022                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1023                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1024                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1025
1026                 /*
1027                  * The DPLLB check accounts for the pipe B + port A usage
1028                  * with CL2 powered up but all the lanes in the second channel
1029                  * powered down.
1030                  */
1031                 if (BITS_SET(phy_control,
1032                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1033                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1034                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1035
1036                 if (BITS_SET(phy_control,
1037                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1038                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1039                 if (BITS_SET(phy_control,
1040                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1041                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1042
1043                 if (BITS_SET(phy_control,
1044                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1045                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1046                 if (BITS_SET(phy_control,
1047                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1048                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1049         }
1050
1051         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1052                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1053
1054                 /* this assumes override is only used to enable lanes */
1055                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1056                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1057
1058                 if (BITS_SET(phy_control,
1059                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1060                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1061
1062                 if (BITS_SET(phy_control,
1063                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1064                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1065                 if (BITS_SET(phy_control,
1066                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1067                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1068         }
1069
1070         phy_status &= phy_status_mask;
1071
1072         /*
1073          * The PHY may be busy with some initial calibration and whatnot,
1074          * so the power state can take a while to actually change.
1075          */
1076         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1077                 WARN(phy_status != tmp,
1078                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1079                      tmp, phy_status, dev_priv->chv_phy_control);
1080 }
1081
1082 #undef BITS_SET
1083
1084 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1085                                            struct i915_power_well *power_well)
1086 {
1087         enum dpio_phy phy;
1088         enum pipe pipe;
1089         uint32_t tmp;
1090
1091         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1092                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1093
1094         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1095                 pipe = PIPE_A;
1096                 phy = DPIO_PHY0;
1097         } else {
1098                 pipe = PIPE_C;
1099                 phy = DPIO_PHY1;
1100         }
1101
1102         /* since ref/cri clock was enabled */
1103         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1104         vlv_set_power_well(dev_priv, power_well, true);
1105
1106         /* Poll for phypwrgood signal */
1107         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1108                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1109
1110         mutex_lock(&dev_priv->sb_lock);
1111
1112         /* Enable dynamic power down */
1113         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1114         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1115                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1116         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1117
1118         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1119                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1120                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1121                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1122         } else {
1123                 /*
1124                  * Force the non-existing CL2 off. BXT does this
1125                  * too, so maybe it saves some power even though
1126                  * CL2 doesn't exist?
1127                  */
1128                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1129                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1130                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1131         }
1132
1133         mutex_unlock(&dev_priv->sb_lock);
1134
1135         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1136         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1137
1138         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1139                       phy, dev_priv->chv_phy_control);
1140
1141         assert_chv_phy_status(dev_priv);
1142 }
1143
1144 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1145                                             struct i915_power_well *power_well)
1146 {
1147         enum dpio_phy phy;
1148
1149         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1150                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1151
1152         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1153                 phy = DPIO_PHY0;
1154                 assert_pll_disabled(dev_priv, PIPE_A);
1155                 assert_pll_disabled(dev_priv, PIPE_B);
1156         } else {
1157                 phy = DPIO_PHY1;
1158                 assert_pll_disabled(dev_priv, PIPE_C);
1159         }
1160
1161         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1162         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1163
1164         vlv_set_power_well(dev_priv, power_well, false);
1165
1166         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1167                       phy, dev_priv->chv_phy_control);
1168
1169         /* PHY is fully reset now, so we can enable the PHY state asserts */
1170         dev_priv->chv_phy_assert[phy] = true;
1171
1172         assert_chv_phy_status(dev_priv);
1173 }
1174
1175 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1176                                      enum dpio_channel ch, bool override, unsigned int mask)
1177 {
1178         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1179         u32 reg, val, expected, actual;
1180
1181         /*
1182          * The BIOS can leave the PHY is some weird state
1183          * where it doesn't fully power down some parts.
1184          * Disable the asserts until the PHY has been fully
1185          * reset (ie. the power well has been disabled at
1186          * least once).
1187          */
1188         if (!dev_priv->chv_phy_assert[phy])
1189                 return;
1190
1191         if (ch == DPIO_CH0)
1192                 reg = _CHV_CMN_DW0_CH0;
1193         else
1194                 reg = _CHV_CMN_DW6_CH1;
1195
1196         mutex_lock(&dev_priv->sb_lock);
1197         val = vlv_dpio_read(dev_priv, pipe, reg);
1198         mutex_unlock(&dev_priv->sb_lock);
1199
1200         /*
1201          * This assumes !override is only used when the port is disabled.
1202          * All lanes should power down even without the override when
1203          * the port is disabled.
1204          */
1205         if (!override || mask == 0xf) {
1206                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1207                 /*
1208                  * If CH1 common lane is not active anymore
1209                  * (eg. for pipe B DPLL) the entire channel will
1210                  * shut down, which causes the common lane registers
1211                  * to read as 0. That means we can't actually check
1212                  * the lane power down status bits, but as the entire
1213                  * register reads as 0 it's a good indication that the
1214                  * channel is indeed entirely powered down.
1215                  */
1216                 if (ch == DPIO_CH1 && val == 0)
1217                         expected = 0;
1218         } else if (mask != 0x0) {
1219                 expected = DPIO_ANYDL_POWERDOWN;
1220         } else {
1221                 expected = 0;
1222         }
1223
1224         if (ch == DPIO_CH0)
1225                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1226         else
1227                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1228         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1229
1230         WARN(actual != expected,
1231              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1232              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1233              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1234              reg, val);
1235 }
1236
1237 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1238                           enum dpio_channel ch, bool override)
1239 {
1240         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1241         bool was_override;
1242
1243         mutex_lock(&power_domains->lock);
1244
1245         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1246
1247         if (override == was_override)
1248                 goto out;
1249
1250         if (override)
1251                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1252         else
1253                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1254
1255         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1256
1257         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1258                       phy, ch, dev_priv->chv_phy_control);
1259
1260         assert_chv_phy_status(dev_priv);
1261
1262 out:
1263         mutex_unlock(&power_domains->lock);
1264
1265         return was_override;
1266 }
1267
1268 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1269                              bool override, unsigned int mask)
1270 {
1271         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1272         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1273         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1274         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1275
1276         mutex_lock(&power_domains->lock);
1277
1278         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1279         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1280
1281         if (override)
1282                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1283         else
1284                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1285
1286         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1287
1288         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1289                       phy, ch, mask, dev_priv->chv_phy_control);
1290
1291         assert_chv_phy_status(dev_priv);
1292
1293         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1294
1295         mutex_unlock(&power_domains->lock);
1296 }
1297
1298 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1299                                         struct i915_power_well *power_well)
1300 {
1301         enum pipe pipe = power_well->data;
1302         bool enabled;
1303         u32 state, ctrl;
1304
1305         mutex_lock(&dev_priv->rps.hw_lock);
1306
1307         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1308         /*
1309          * We only ever set the power-on and power-gate states, anything
1310          * else is unexpected.
1311          */
1312         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1313         enabled = state == DP_SSS_PWR_ON(pipe);
1314
1315         /*
1316          * A transient state at this point would mean some unexpected party
1317          * is poking at the power controls too.
1318          */
1319         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1320         WARN_ON(ctrl << 16 != state);
1321
1322         mutex_unlock(&dev_priv->rps.hw_lock);
1323
1324         return enabled;
1325 }
1326
1327 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1328                                     struct i915_power_well *power_well,
1329                                     bool enable)
1330 {
1331         enum pipe pipe = power_well->data;
1332         u32 state;
1333         u32 ctrl;
1334
1335         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1336
1337         mutex_lock(&dev_priv->rps.hw_lock);
1338
1339 #define COND \
1340         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1341
1342         if (COND)
1343                 goto out;
1344
1345         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1346         ctrl &= ~DP_SSC_MASK(pipe);
1347         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1348         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1349
1350         if (wait_for(COND, 100))
1351                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1352                           state,
1353                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1354
1355 #undef COND
1356
1357 out:
1358         mutex_unlock(&dev_priv->rps.hw_lock);
1359 }
1360
1361 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1362                                         struct i915_power_well *power_well)
1363 {
1364         WARN_ON_ONCE(power_well->data != PIPE_A);
1365
1366         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1367 }
1368
1369 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1370                                        struct i915_power_well *power_well)
1371 {
1372         WARN_ON_ONCE(power_well->data != PIPE_A);
1373
1374         chv_set_pipe_power_well(dev_priv, power_well, true);
1375
1376         vlv_display_power_well_init(dev_priv);
1377 }
1378
1379 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1380                                         struct i915_power_well *power_well)
1381 {
1382         WARN_ON_ONCE(power_well->data != PIPE_A);
1383
1384         vlv_display_power_well_deinit(dev_priv);
1385
1386         chv_set_pipe_power_well(dev_priv, power_well, false);
1387 }
1388
1389 /**
1390  * intel_display_power_get - grab a power domain reference
1391  * @dev_priv: i915 device instance
1392  * @domain: power domain to reference
1393  *
1394  * This function grabs a power domain reference for @domain and ensures that the
1395  * power domain and all its parents are powered up. Therefore users should only
1396  * grab a reference to the innermost power domain they need.
1397  *
1398  * Any power domain reference obtained by this function must have a symmetric
1399  * call to intel_display_power_put() to release the reference again.
1400  */
1401 void intel_display_power_get(struct drm_i915_private *dev_priv,
1402                              enum intel_display_power_domain domain)
1403 {
1404         struct i915_power_domains *power_domains;
1405         struct i915_power_well *power_well;
1406         int i;
1407
1408         intel_runtime_pm_get(dev_priv);
1409
1410         power_domains = &dev_priv->power_domains;
1411
1412         mutex_lock(&power_domains->lock);
1413
1414         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1415                 if (!power_well->count++)
1416                         intel_power_well_enable(dev_priv, power_well);
1417         }
1418
1419         power_domains->domain_use_count[domain]++;
1420
1421         mutex_unlock(&power_domains->lock);
1422 }
1423
1424 /**
1425  * intel_display_power_put - release a power domain reference
1426  * @dev_priv: i915 device instance
1427  * @domain: power domain to reference
1428  *
1429  * This function drops the power domain reference obtained by
1430  * intel_display_power_get() and might power down the corresponding hardware
1431  * block right away if this is the last reference.
1432  */
1433 void intel_display_power_put(struct drm_i915_private *dev_priv,
1434                              enum intel_display_power_domain domain)
1435 {
1436         struct i915_power_domains *power_domains;
1437         struct i915_power_well *power_well;
1438         int i;
1439
1440         power_domains = &dev_priv->power_domains;
1441
1442         mutex_lock(&power_domains->lock);
1443
1444         WARN_ON(!power_domains->domain_use_count[domain]);
1445         power_domains->domain_use_count[domain]--;
1446
1447         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1448                 WARN_ON(!power_well->count);
1449
1450                 if (!--power_well->count && i915.disable_power_well)
1451                         intel_power_well_disable(dev_priv, power_well);
1452         }
1453
1454         mutex_unlock(&power_domains->lock);
1455
1456         intel_runtime_pm_put(dev_priv);
1457 }
1458
1459 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1460         BIT(POWER_DOMAIN_PIPE_A) |                      \
1461         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1462         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1463         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1464         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1465         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1466         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1467         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1468         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1469         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1470         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1471         BIT(POWER_DOMAIN_PLLS) |                        \
1472         BIT(POWER_DOMAIN_AUX_A) |                       \
1473         BIT(POWER_DOMAIN_AUX_B) |                       \
1474         BIT(POWER_DOMAIN_AUX_C) |                       \
1475         BIT(POWER_DOMAIN_AUX_D) |                       \
1476         BIT(POWER_DOMAIN_INIT))
1477 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1478         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1479         BIT(POWER_DOMAIN_INIT))
1480
1481 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1482         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1483         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1484 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1485         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1486         BIT(POWER_DOMAIN_INIT))
1487
1488 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1489 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1490
1491 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1492         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1493         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1494         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1495         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1496         BIT(POWER_DOMAIN_PORT_CRT) |            \
1497         BIT(POWER_DOMAIN_AUX_B) |               \
1498         BIT(POWER_DOMAIN_AUX_C) |               \
1499         BIT(POWER_DOMAIN_INIT))
1500
1501 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1502         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1503         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1504         BIT(POWER_DOMAIN_AUX_B) |               \
1505         BIT(POWER_DOMAIN_INIT))
1506
1507 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1508         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1509         BIT(POWER_DOMAIN_AUX_B) |               \
1510         BIT(POWER_DOMAIN_INIT))
1511
1512 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1513         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1514         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1515         BIT(POWER_DOMAIN_AUX_C) |               \
1516         BIT(POWER_DOMAIN_INIT))
1517
1518 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1519         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1520         BIT(POWER_DOMAIN_AUX_C) |               \
1521         BIT(POWER_DOMAIN_INIT))
1522
1523 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1524         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1525         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1526         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1527         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1528         BIT(POWER_DOMAIN_AUX_B) |               \
1529         BIT(POWER_DOMAIN_AUX_C) |               \
1530         BIT(POWER_DOMAIN_INIT))
1531
1532 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1533         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1534         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1535         BIT(POWER_DOMAIN_AUX_D) |               \
1536         BIT(POWER_DOMAIN_INIT))
1537
1538 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1539         .sync_hw = i9xx_always_on_power_well_noop,
1540         .enable = i9xx_always_on_power_well_noop,
1541         .disable = i9xx_always_on_power_well_noop,
1542         .is_enabled = i9xx_always_on_power_well_enabled,
1543 };
1544
1545 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1546         .sync_hw = chv_pipe_power_well_sync_hw,
1547         .enable = chv_pipe_power_well_enable,
1548         .disable = chv_pipe_power_well_disable,
1549         .is_enabled = chv_pipe_power_well_enabled,
1550 };
1551
1552 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1553         .sync_hw = vlv_power_well_sync_hw,
1554         .enable = chv_dpio_cmn_power_well_enable,
1555         .disable = chv_dpio_cmn_power_well_disable,
1556         .is_enabled = vlv_power_well_enabled,
1557 };
1558
1559 static struct i915_power_well i9xx_always_on_power_well[] = {
1560         {
1561                 .name = "always-on",
1562                 .always_on = 1,
1563                 .domains = POWER_DOMAIN_MASK,
1564                 .ops = &i9xx_always_on_power_well_ops,
1565         },
1566 };
1567
1568 static const struct i915_power_well_ops hsw_power_well_ops = {
1569         .sync_hw = hsw_power_well_sync_hw,
1570         .enable = hsw_power_well_enable,
1571         .disable = hsw_power_well_disable,
1572         .is_enabled = hsw_power_well_enabled,
1573 };
1574
1575 static const struct i915_power_well_ops skl_power_well_ops = {
1576         .sync_hw = skl_power_well_sync_hw,
1577         .enable = skl_power_well_enable,
1578         .disable = skl_power_well_disable,
1579         .is_enabled = skl_power_well_enabled,
1580 };
1581
1582 static struct i915_power_well hsw_power_wells[] = {
1583         {
1584                 .name = "always-on",
1585                 .always_on = 1,
1586                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1587                 .ops = &i9xx_always_on_power_well_ops,
1588         },
1589         {
1590                 .name = "display",
1591                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1592                 .ops = &hsw_power_well_ops,
1593         },
1594 };
1595
1596 static struct i915_power_well bdw_power_wells[] = {
1597         {
1598                 .name = "always-on",
1599                 .always_on = 1,
1600                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1601                 .ops = &i9xx_always_on_power_well_ops,
1602         },
1603         {
1604                 .name = "display",
1605                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1606                 .ops = &hsw_power_well_ops,
1607         },
1608 };
1609
1610 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1611         .sync_hw = vlv_power_well_sync_hw,
1612         .enable = vlv_display_power_well_enable,
1613         .disable = vlv_display_power_well_disable,
1614         .is_enabled = vlv_power_well_enabled,
1615 };
1616
1617 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1618         .sync_hw = vlv_power_well_sync_hw,
1619         .enable = vlv_dpio_cmn_power_well_enable,
1620         .disable = vlv_dpio_cmn_power_well_disable,
1621         .is_enabled = vlv_power_well_enabled,
1622 };
1623
1624 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1625         .sync_hw = vlv_power_well_sync_hw,
1626         .enable = vlv_power_well_enable,
1627         .disable = vlv_power_well_disable,
1628         .is_enabled = vlv_power_well_enabled,
1629 };
1630
1631 static struct i915_power_well vlv_power_wells[] = {
1632         {
1633                 .name = "always-on",
1634                 .always_on = 1,
1635                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1636                 .ops = &i9xx_always_on_power_well_ops,
1637                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1638         },
1639         {
1640                 .name = "display",
1641                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1642                 .data = PUNIT_POWER_WELL_DISP2D,
1643                 .ops = &vlv_display_power_well_ops,
1644         },
1645         {
1646                 .name = "dpio-tx-b-01",
1647                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1648                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1649                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1650                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1651                 .ops = &vlv_dpio_power_well_ops,
1652                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1653         },
1654         {
1655                 .name = "dpio-tx-b-23",
1656                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1657                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1658                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1659                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1660                 .ops = &vlv_dpio_power_well_ops,
1661                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1662         },
1663         {
1664                 .name = "dpio-tx-c-01",
1665                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1666                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1667                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1668                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1669                 .ops = &vlv_dpio_power_well_ops,
1670                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1671         },
1672         {
1673                 .name = "dpio-tx-c-23",
1674                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1675                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1676                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1677                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1678                 .ops = &vlv_dpio_power_well_ops,
1679                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1680         },
1681         {
1682                 .name = "dpio-common",
1683                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1684                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1685                 .ops = &vlv_dpio_cmn_power_well_ops,
1686         },
1687 };
1688
1689 static struct i915_power_well chv_power_wells[] = {
1690         {
1691                 .name = "always-on",
1692                 .always_on = 1,
1693                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1694                 .ops = &i9xx_always_on_power_well_ops,
1695         },
1696         {
1697                 .name = "display",
1698                 /*
1699                  * Pipe A power well is the new disp2d well. Pipe B and C
1700                  * power wells don't actually exist. Pipe A power well is
1701                  * required for any pipe to work.
1702                  */
1703                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1704                 .data = PIPE_A,
1705                 .ops = &chv_pipe_power_well_ops,
1706         },
1707         {
1708                 .name = "dpio-common-bc",
1709                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1710                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1711                 .ops = &chv_dpio_cmn_power_well_ops,
1712         },
1713         {
1714                 .name = "dpio-common-d",
1715                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1716                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1717                 .ops = &chv_dpio_cmn_power_well_ops,
1718         },
1719 };
1720
1721 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1722                                     int power_well_id)
1723 {
1724         struct i915_power_well *power_well;
1725         bool ret;
1726
1727         power_well = lookup_power_well(dev_priv, power_well_id);
1728         ret = power_well->ops->is_enabled(dev_priv, power_well);
1729
1730         return ret;
1731 }
1732
1733 static struct i915_power_well skl_power_wells[] = {
1734         {
1735                 .name = "always-on",
1736                 .always_on = 1,
1737                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1738                 .ops = &i9xx_always_on_power_well_ops,
1739                 .data = SKL_DISP_PW_ALWAYS_ON,
1740         },
1741         {
1742                 .name = "power well 1",
1743                 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1744                 .ops = &skl_power_well_ops,
1745                 .data = SKL_DISP_PW_1,
1746         },
1747         {
1748                 .name = "MISC IO power well",
1749                 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1750                 .ops = &skl_power_well_ops,
1751                 .data = SKL_DISP_PW_MISC_IO,
1752         },
1753         {
1754                 .name = "power well 2",
1755                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1756                 .ops = &skl_power_well_ops,
1757                 .data = SKL_DISP_PW_2,
1758         },
1759         {
1760                 .name = "DDI A/E power well",
1761                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1762                 .ops = &skl_power_well_ops,
1763                 .data = SKL_DISP_PW_DDI_A_E,
1764         },
1765         {
1766                 .name = "DDI B power well",
1767                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1768                 .ops = &skl_power_well_ops,
1769                 .data = SKL_DISP_PW_DDI_B,
1770         },
1771         {
1772                 .name = "DDI C power well",
1773                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1774                 .ops = &skl_power_well_ops,
1775                 .data = SKL_DISP_PW_DDI_C,
1776         },
1777         {
1778                 .name = "DDI D power well",
1779                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1780                 .ops = &skl_power_well_ops,
1781                 .data = SKL_DISP_PW_DDI_D,
1782         },
1783 };
1784
1785 static struct i915_power_well bxt_power_wells[] = {
1786         {
1787                 .name = "always-on",
1788                 .always_on = 1,
1789                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1790                 .ops = &i9xx_always_on_power_well_ops,
1791         },
1792         {
1793                 .name = "power well 1",
1794                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1795                 .ops = &skl_power_well_ops,
1796                 .data = SKL_DISP_PW_1,
1797         },
1798         {
1799                 .name = "power well 2",
1800                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1801                 .ops = &skl_power_well_ops,
1802                 .data = SKL_DISP_PW_2,
1803         }
1804 };
1805
1806 #define set_power_wells(power_domains, __power_wells) ({                \
1807         (power_domains)->power_wells = (__power_wells);                 \
1808         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1809 })
1810
1811 /**
1812  * intel_power_domains_init - initializes the power domain structures
1813  * @dev_priv: i915 device instance
1814  *
1815  * Initializes the power domain structures for @dev_priv depending upon the
1816  * supported platform.
1817  */
1818 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1819 {
1820         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1821
1822         mutex_init(&power_domains->lock);
1823
1824         /*
1825          * The enabling order will be from lower to higher indexed wells,
1826          * the disabling order is reversed.
1827          */
1828         if (IS_HASWELL(dev_priv->dev)) {
1829                 set_power_wells(power_domains, hsw_power_wells);
1830         } else if (IS_BROADWELL(dev_priv->dev)) {
1831                 set_power_wells(power_domains, bdw_power_wells);
1832         } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
1833                 set_power_wells(power_domains, skl_power_wells);
1834         } else if (IS_BROXTON(dev_priv->dev)) {
1835                 set_power_wells(power_domains, bxt_power_wells);
1836         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1837                 set_power_wells(power_domains, chv_power_wells);
1838         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1839                 set_power_wells(power_domains, vlv_power_wells);
1840         } else {
1841                 set_power_wells(power_domains, i9xx_always_on_power_well);
1842         }
1843
1844         return 0;
1845 }
1846
1847 /**
1848  * intel_power_domains_fini - finalizes the power domain structures
1849  * @dev_priv: i915 device instance
1850  *
1851  * Finalizes the power domain structures for @dev_priv depending upon the
1852  * supported platform. This function also disables runtime pm and ensures that
1853  * the device stays powered up so that the driver can be reloaded.
1854  */
1855 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1856 {
1857         /* The i915.ko module is still not prepared to be loaded when
1858          * the power well is not enabled, so just enable it in case
1859          * we're going to unload/reload. */
1860         intel_display_set_init_power(dev_priv, true);
1861 }
1862
1863 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1864 {
1865         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1866         struct i915_power_well *power_well;
1867         int i;
1868
1869         mutex_lock(&power_domains->lock);
1870         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1871                 power_well->ops->sync_hw(dev_priv, power_well);
1872                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1873                                                                      power_well);
1874         }
1875         mutex_unlock(&power_domains->lock);
1876 }
1877
1878 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1879 {
1880         struct i915_power_well *cmn_bc =
1881                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1882         struct i915_power_well *cmn_d =
1883                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1884
1885         /*
1886          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1887          * workaround never ever read DISPLAY_PHY_CONTROL, and
1888          * instead maintain a shadow copy ourselves. Use the actual
1889          * power well state and lane status to reconstruct the
1890          * expected initial value.
1891          */
1892         dev_priv->chv_phy_control =
1893                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1894                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1895                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1896                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1897                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1898
1899         /*
1900          * If all lanes are disabled we leave the override disabled
1901          * with all power down bits cleared to match the state we
1902          * would use after disabling the port. Otherwise enable the
1903          * override and set the lane powerdown bits accding to the
1904          * current lane status.
1905          */
1906         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1907                 uint32_t status = I915_READ(DPLL(PIPE_A));
1908                 unsigned int mask;
1909
1910                 mask = status & DPLL_PORTB_READY_MASK;
1911                 if (mask == 0xf)
1912                         mask = 0x0;
1913                 else
1914                         dev_priv->chv_phy_control |=
1915                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1916
1917                 dev_priv->chv_phy_control |=
1918                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1919
1920                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1921                 if (mask == 0xf)
1922                         mask = 0x0;
1923                 else
1924                         dev_priv->chv_phy_control |=
1925                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1926
1927                 dev_priv->chv_phy_control |=
1928                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1929
1930                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1931
1932                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
1933         } else {
1934                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
1935         }
1936
1937         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1938                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1939                 unsigned int mask;
1940
1941                 mask = status & DPLL_PORTD_READY_MASK;
1942
1943                 if (mask == 0xf)
1944                         mask = 0x0;
1945                 else
1946                         dev_priv->chv_phy_control |=
1947                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1948
1949                 dev_priv->chv_phy_control |=
1950                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1951
1952                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1953
1954                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
1955         } else {
1956                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
1957         }
1958
1959         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1960
1961         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1962                       dev_priv->chv_phy_control);
1963 }
1964
1965 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1966 {
1967         struct i915_power_well *cmn =
1968                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1969         struct i915_power_well *disp2d =
1970                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1971
1972         /* If the display might be already active skip this */
1973         if (cmn->ops->is_enabled(dev_priv, cmn) &&
1974             disp2d->ops->is_enabled(dev_priv, disp2d) &&
1975             I915_READ(DPIO_CTL) & DPIO_CMNRST)
1976                 return;
1977
1978         DRM_DEBUG_KMS("toggling display PHY side reset\n");
1979
1980         /* cmnlane needs DPLL registers */
1981         disp2d->ops->enable(dev_priv, disp2d);
1982
1983         /*
1984          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1985          * Need to assert and de-assert PHY SB reset by gating the
1986          * common lane power, then un-gating it.
1987          * Simply ungating isn't enough to reset the PHY enough to get
1988          * ports and lanes running.
1989          */
1990         cmn->ops->disable(dev_priv, cmn);
1991 }
1992
1993 /**
1994  * intel_power_domains_init_hw - initialize hardware power domain state
1995  * @dev_priv: i915 device instance
1996  *
1997  * This function initializes the hardware power domain state and enables all
1998  * power domains using intel_display_set_init_power().
1999  */
2000 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
2001 {
2002         struct drm_device *dev = dev_priv->dev;
2003         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2004
2005         power_domains->initializing = true;
2006
2007         if (IS_CHERRYVIEW(dev)) {
2008                 mutex_lock(&power_domains->lock);
2009                 chv_phy_control_init(dev_priv);
2010                 mutex_unlock(&power_domains->lock);
2011         } else if (IS_VALLEYVIEW(dev)) {
2012                 mutex_lock(&power_domains->lock);
2013                 vlv_cmnlane_wa(dev_priv);
2014                 mutex_unlock(&power_domains->lock);
2015         }
2016
2017         /* For now, we need the power well to be always enabled. */
2018         intel_display_set_init_power(dev_priv, true);
2019         intel_power_domains_resume(dev_priv);
2020         power_domains->initializing = false;
2021 }
2022
2023 /**
2024  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2025  * @dev_priv: i915 device instance
2026  *
2027  * This function grabs a power domain reference for the auxiliary power domain
2028  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2029  * parents are powered up. Therefore users should only grab a reference to the
2030  * innermost power domain they need.
2031  *
2032  * Any power domain reference obtained by this function must have a symmetric
2033  * call to intel_aux_display_runtime_put() to release the reference again.
2034  */
2035 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2036 {
2037         intel_runtime_pm_get(dev_priv);
2038 }
2039
2040 /**
2041  * intel_aux_display_runtime_put - release an auxiliary power domain reference
2042  * @dev_priv: i915 device instance
2043  *
2044  * This function drops the auxiliary power domain reference obtained by
2045  * intel_aux_display_runtime_get() and might power down the corresponding
2046  * hardware block right away if this is the last reference.
2047  */
2048 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2049 {
2050         intel_runtime_pm_put(dev_priv);
2051 }
2052
2053 /**
2054  * intel_runtime_pm_get - grab a runtime pm reference
2055  * @dev_priv: i915 device instance
2056  *
2057  * This function grabs a device-level runtime pm reference (mostly used for GEM
2058  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2059  *
2060  * Any runtime pm reference obtained by this function must have a symmetric
2061  * call to intel_runtime_pm_put() to release the reference again.
2062  */
2063 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2064 {
2065         struct drm_device *dev = dev_priv->dev;
2066         struct device *device = &dev->pdev->dev;
2067
2068         if (!HAS_RUNTIME_PM(dev))
2069                 return;
2070
2071         pm_runtime_get_sync(device);
2072         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2073 }
2074
2075 /**
2076  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2077  * @dev_priv: i915 device instance
2078  *
2079  * This function grabs a device-level runtime pm reference (mostly used for GEM
2080  * code to ensure the GTT or GT is on).
2081  *
2082  * It will _not_ power up the device but instead only check that it's powered
2083  * on.  Therefore it is only valid to call this functions from contexts where
2084  * the device is known to be powered up and where trying to power it up would
2085  * result in hilarity and deadlocks. That pretty much means only the system
2086  * suspend/resume code where this is used to grab runtime pm references for
2087  * delayed setup down in work items.
2088  *
2089  * Any runtime pm reference obtained by this function must have a symmetric
2090  * call to intel_runtime_pm_put() to release the reference again.
2091  */
2092 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2093 {
2094         struct drm_device *dev = dev_priv->dev;
2095         struct device *device = &dev->pdev->dev;
2096
2097         if (!HAS_RUNTIME_PM(dev))
2098                 return;
2099
2100         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2101         pm_runtime_get_noresume(device);
2102 }
2103
2104 /**
2105  * intel_runtime_pm_put - release a runtime pm reference
2106  * @dev_priv: i915 device instance
2107  *
2108  * This function drops the device-level runtime pm reference obtained by
2109  * intel_runtime_pm_get() and might power down the corresponding
2110  * hardware block right away if this is the last reference.
2111  */
2112 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2113 {
2114         struct drm_device *dev = dev_priv->dev;
2115         struct device *device = &dev->pdev->dev;
2116
2117         if (!HAS_RUNTIME_PM(dev))
2118                 return;
2119
2120         pm_runtime_mark_last_busy(device);
2121         pm_runtime_put_autosuspend(device);
2122 }
2123
2124 /**
2125  * intel_runtime_pm_enable - enable runtime pm
2126  * @dev_priv: i915 device instance
2127  *
2128  * This function enables runtime pm at the end of the driver load sequence.
2129  *
2130  * Note that this function does currently not enable runtime pm for the
2131  * subordinate display power domains. That is only done on the first modeset
2132  * using intel_display_set_init_power().
2133  */
2134 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2135 {
2136         struct drm_device *dev = dev_priv->dev;
2137         struct device *device = &dev->pdev->dev;
2138
2139         if (!HAS_RUNTIME_PM(dev))
2140                 return;
2141
2142         /*
2143          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2144          * requirement.
2145          */
2146         if (!intel_enable_rc6(dev)) {
2147                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2148                 return;
2149         }
2150
2151         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2152         pm_runtime_mark_last_busy(device);
2153         pm_runtime_use_autosuspend(device);
2154
2155         pm_runtime_put_autosuspend(device);
2156 }
2157