drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int link_bw;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { DP_LINK_BW_1_62,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { DP_LINK_BW_2_7,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
  99                                  243000, 270000, 324000, 405000,
 100                                  420000, 432000, 540000 };
 101 static const int default_rates[] = { 162000, 270000, 540000 };
 102
 103 /**
 104  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 105  * @intel_dp: DP struct
 106  *
 107  * If a CPU or PCH DP output is attached to an eDP panel, this function
 108  * will return true, and false otherwise.
 109  */
 110 static bool is_edp(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 115 }
 116
 117 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 118 {
 119         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 120
 121         return intel_dig_port->base.base.dev;
 122 }
 123
 124 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 125 {
 126         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 127 }
 128
 129 static void intel_dp_link_down(struct intel_dp *intel_dp);
 130 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 131 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 132 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 133 static void vlv_steal_power_sequencer(struct drm_device *dev,
 134                                       enum pipe pipe);
 135
 136 static int
 137 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 138 {
 139         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 140
 141         switch (max_link_bw) {
 142         case DP_LINK_BW_1_62:
 143         case DP_LINK_BW_2_7:
 144         case DP_LINK_BW_5_4:
 145                 break;
 146         default:
 147                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 148                      max_link_bw);
 149                 max_link_bw = DP_LINK_BW_1_62;
 150                 break;
 151         }
 152         return max_link_bw;
 153 }
 154
 155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 156 {
 157         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 158         struct drm_device *dev = intel_dig_port->base.base.dev;
 159         u8 source_max, sink_max;
 160
 161         source_max = 4;
 162         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 163             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 164                 source_max = 2;
 165
 166         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 167
 168         return min(source_max, sink_max);
 169 }
 170
 171 /*
 172  * The units on the numbers in the next two are... bizarre.  Examples will
 173  * make it clearer; this one parallels an example in the eDP spec.
 174  *
 175  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 176  *
 177  *     270000 * 1 * 8 / 10 == 216000
 178  *
 179  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 180  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 181  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 182  * 119000.  At 18bpp that's 2142000 kilobits per second.
 183  *
 184  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 185  * get the result in decakilobits instead of kilobits.
 186  */
 187
 188 static int
 189 intel_dp_link_required(int pixel_clock, int bpp)
 190 {
 191         return (pixel_clock * bpp + 9) / 10;
 192 }
 193
 194 static int
 195 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 196 {
 197         return (max_link_clock * max_lanes * 8) / 10;
 198 }
 199
 200 static enum drm_mode_status
 201 intel_dp_mode_valid(struct drm_connector *connector,
 202                     struct drm_display_mode *mode)
 203 {
 204         struct intel_dp *intel_dp = intel_attached_dp(connector);
 205         struct intel_connector *intel_connector = to_intel_connector(connector);
 206         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 207         int target_clock = mode->clock;
 208         int max_rate, mode_rate, max_lanes, max_link_clock;
 209
 210         if (is_edp(intel_dp) && fixed_mode) {
 211                 if (mode->hdisplay > fixed_mode->hdisplay)
 212                         return MODE_PANEL;
 213
 214                 if (mode->vdisplay > fixed_mode->vdisplay)
 215                         return MODE_PANEL;
 216
 217                 target_clock = fixed_mode->clock;
 218         }
 219
 220         max_link_clock = intel_dp_max_link_rate(intel_dp);
 221         max_lanes = intel_dp_max_lane_count(intel_dp);
 222
 223         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 224         mode_rate = intel_dp_link_required(target_clock, 18);
 225
 226         if (mode_rate > max_rate)
 227                 return MODE_CLOCK_HIGH;
 228
 229         if (mode->clock < 10000)
 230                 return MODE_CLOCK_LOW;
 231
 232         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 233                 return MODE_H_ILLEGAL;
 234
 235         return MODE_OK;
 236 }
 237
 238 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 239 {
 240         int     i;
 241         uint32_t v = 0;
 242
 243         if (src_bytes > 4)
 244                 src_bytes = 4;
 245         for (i = 0; i < src_bytes; i++)
 246                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 247         return v;
 248 }
 249
 250 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static void
 294 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 295                                     struct intel_dp *intel_dp);
 296 static void
 297 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 298                                               struct intel_dp *intel_dp);
 299
 300 static void pps_lock(struct intel_dp *intel_dp)
 301 {
 302         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 303         struct intel_encoder *encoder = &intel_dig_port->base;
 304         struct drm_device *dev = encoder->base.dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         enum intel_display_power_domain power_domain;
 307
 308         /*
 309          * See vlv_power_sequencer_reset() why we need
 310          * a power domain reference here.
 311          */
 312         power_domain = intel_display_port_power_domain(encoder);
 313         intel_display_power_get(dev_priv, power_domain);
 314
 315         mutex_lock(&dev_priv->pps_mutex);
 316 }
 317
 318 static void pps_unlock(struct intel_dp *intel_dp)
 319 {
 320         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 321         struct intel_encoder *encoder = &intel_dig_port->base;
 322         struct drm_device *dev = encoder->base.dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         enum intel_display_power_domain power_domain;
 325
 326         mutex_unlock(&dev_priv->pps_mutex);
 327
 328         power_domain = intel_display_port_power_domain(encoder);
 329         intel_display_power_put(dev_priv, power_domain);
 330 }
 331
 332 static void
 333 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 334 {
 335         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_device *dev = intel_dig_port->base.base.dev;
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         enum pipe pipe = intel_dp->pps_pipe;
 339         bool pll_enabled;
 340         uint32_t DP;
 341
 342         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 343                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 344                  pipe_name(pipe), port_name(intel_dig_port->port)))
 345                 return;
 346
 347         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 348                       pipe_name(pipe), port_name(intel_dig_port->port));
 349
 350         /* Preserve the BIOS-computed detected bit. This is
 351          * supposed to be read-only.
 352          */
 353         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 354         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 355         DP |= DP_PORT_WIDTH(1);
 356         DP |= DP_LINK_TRAIN_PAT_1;
 357
 358         if (IS_CHERRYVIEW(dev))
 359                 DP |= DP_PIPE_SELECT_CHV(pipe);
 360         else if (pipe == PIPE_B)
 361                 DP |= DP_PIPEB_SELECT;
 362
 363         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 364
 365         /*
 366          * The DPLL for the pipe must be enabled for this to work.
 367          * So enable temporarily it if it's not already enabled.
 368          */
 369         if (!pll_enabled)
 370                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 371                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 372
 373         /*
 374          * Similar magic as in intel_dp_enable_port().
 375          * We _must_ do this port enable + disable trick
 376          * to make this power seqeuencer lock onto the port.
 377          * Otherwise even VDD force bit won't work.
 378          */
 379         I915_WRITE(intel_dp->output_reg, DP);
 380         POSTING_READ(intel_dp->output_reg);
 381
 382         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 383         POSTING_READ(intel_dp->output_reg);
 384
 385         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 386         POSTING_READ(intel_dp->output_reg);
 387
 388         if (!pll_enabled)
 389                 vlv_force_pll_off(dev, pipe);
 390 }
 391
 392 static enum pipe
 393 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 394 {
 395         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 396         struct drm_device *dev = intel_dig_port->base.base.dev;
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         struct intel_encoder *encoder;
 399         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 400         enum pipe pipe;
 401
 402         lockdep_assert_held(&dev_priv->pps_mutex);
 403
 404         /* We should never land here with regular DP ports */
 405         WARN_ON(!is_edp(intel_dp));
 406
 407         if (intel_dp->pps_pipe != INVALID_PIPE)
 408                 return intel_dp->pps_pipe;
 409
 410         /*
 411          * We don't have power sequencer currently.
 412          * Pick one that's not used by other ports.
 413          */
 414         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 415                             base.head) {
 416                 struct intel_dp *tmp;
 417
 418                 if (encoder->type != INTEL_OUTPUT_EDP)
 419                         continue;
 420
 421                 tmp = enc_to_intel_dp(&encoder->base);
 422
 423                 if (tmp->pps_pipe != INVALID_PIPE)
 424                         pipes &= ~(1 << tmp->pps_pipe);
 425         }
 426
 427         /*
 428          * Didn't find one. This should not happen since there
 429          * are two power sequencers and up to two eDP ports.
 430          */
 431         if (WARN_ON(pipes == 0))
 432                 pipe = PIPE_A;
 433         else
 434                 pipe = ffs(pipes) - 1;
 435
 436         vlv_steal_power_sequencer(dev, pipe);
 437         intel_dp->pps_pipe = pipe;
 438
 439         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 440                       pipe_name(intel_dp->pps_pipe),
 441                       port_name(intel_dig_port->port));
 442
 443         /* init power sequencer on this pipe and port */
 444         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 445         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 446
 447         /*
 448          * Even vdd force doesn't work until we've made
 449          * the power sequencer lock in on the port.
 450          */
 451         vlv_power_sequencer_kick(intel_dp);
 452
 453         return intel_dp->pps_pipe;
 454 }
 455
 456 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 457                                enum pipe pipe);
 458
 459 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 460                                enum pipe pipe)
 461 {
 462         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 463 }
 464
 465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 466                                 enum pipe pipe)
 467 {
 468         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 469 }
 470
 471 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 472                          enum pipe pipe)
 473 {
 474         return true;
 475 }
 476
 477 static enum pipe
 478 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 479                      enum port port,
 480                      vlv_pipe_check pipe_check)
 481 {
 482         enum pipe pipe;
 483
 484         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 485                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 486                         PANEL_PORT_SELECT_MASK;
 487
 488                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 489                         continue;
 490
 491                 if (!pipe_check(dev_priv, pipe))
 492                         continue;
 493
 494                 return pipe;
 495         }
 496
 497         return INVALID_PIPE;
 498 }
 499
 500 static void
 501 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 502 {
 503         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 504         struct drm_device *dev = intel_dig_port->base.base.dev;
 505         struct drm_i915_private *dev_priv = dev->dev_private;
 506         enum port port = intel_dig_port->port;
 507
 508         lockdep_assert_held(&dev_priv->pps_mutex);
 509
 510         /* try to find a pipe with this port selected */
 511         /* first pick one where the panel is on */
 512         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 513                                                   vlv_pipe_has_pp_on);
 514         /* didn't find one? pick one where vdd is on */
 515         if (intel_dp->pps_pipe == INVALID_PIPE)
 516                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 517                                                           vlv_pipe_has_vdd_on);
 518         /* didn't find one? pick one with just the correct port */
 519         if (intel_dp->pps_pipe == INVALID_PIPE)
 520                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 521                                                           vlv_pipe_any);
 522
 523         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 524         if (intel_dp->pps_pipe == INVALID_PIPE) {
 525                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 526                               port_name(port));
 527                 return;
 528         }
 529
 530         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 531                       port_name(port), pipe_name(intel_dp->pps_pipe));
 532
 533         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 534         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 535 }
 536
 537 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 538 {
 539         struct drm_device *dev = dev_priv->dev;
 540         struct intel_encoder *encoder;
 541
 542         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 543                 return;
 544
 545         /*
 546          * We can't grab pps_mutex here due to deadlock with power_domain
 547          * mutex when power_domain functions are called while holding pps_mutex.
 548          * That also means that in order to use pps_pipe the code needs to
 549          * hold both a power domain reference and pps_mutex, and the power domain
 550          * reference get/put must be done while _not_ holding pps_mutex.
 551          * pps_{lock,unlock}() do these steps in the correct order, so one
 552          * should use them always.
 553          */
 554
 555         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 556                 struct intel_dp *intel_dp;
 557
 558                 if (encoder->type != INTEL_OUTPUT_EDP)
 559                         continue;
 560
 561                 intel_dp = enc_to_intel_dp(&encoder->base);
 562                 intel_dp->pps_pipe = INVALID_PIPE;
 563         }
 564 }
 565
 566 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 567 {
 568         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 569
 570         if (IS_BROXTON(dev))
 571                 return BXT_PP_CONTROL(0);
 572         else if (HAS_PCH_SPLIT(dev))
 573                 return PCH_PP_CONTROL;
 574         else
 575                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 576 }
 577
 578 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 579 {
 580         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 581
 582         if (IS_BROXTON(dev))
 583                 return BXT_PP_STATUS(0);
 584         else if (HAS_PCH_SPLIT(dev))
 585                 return PCH_PP_STATUS;
 586         else
 587                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 588 }
 589
 590 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 591    This function only applicable when panel PM state is not to be tracked */
 592 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 593                               void *unused)
 594 {
 595         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 596                                                  edp_notifier);
 597         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         u32 pp_div;
 600         u32 pp_ctrl_reg, pp_div_reg;
 601
 602         if (!is_edp(intel_dp) || code != SYS_RESTART)
 603                 return 0;
 604
 605         pps_lock(intel_dp);
 606
 607         if (IS_VALLEYVIEW(dev)) {
 608                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 609
 610                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 611                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 612                 pp_div = I915_READ(pp_div_reg);
 613                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 614
 615                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 616                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 617                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 618                 msleep(intel_dp->panel_power_cycle_delay);
 619         }
 620
 621         pps_unlock(intel_dp);
 622
 623         return 0;
 624 }
 625
 626 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 627 {
 628         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630
 631         lockdep_assert_held(&dev_priv->pps_mutex);
 632
 633         if (IS_VALLEYVIEW(dev) &&
 634             intel_dp->pps_pipe == INVALID_PIPE)
 635                 return false;
 636
 637         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 638 }
 639
 640 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 641 {
 642         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644
 645         lockdep_assert_held(&dev_priv->pps_mutex);
 646
 647         if (IS_VALLEYVIEW(dev) &&
 648             intel_dp->pps_pipe == INVALID_PIPE)
 649                 return false;
 650
 651         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 652 }
 653
 654 static void
 655 intel_dp_check_edp(struct intel_dp *intel_dp)
 656 {
 657         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659
 660         if (!is_edp(intel_dp))
 661                 return;
 662
 663         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 664                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 665                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 666                               I915_READ(_pp_stat_reg(intel_dp)),
 667                               I915_READ(_pp_ctrl_reg(intel_dp)));
 668         }
 669 }
 670
 671 static uint32_t
 672 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 673 {
 674         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 675         struct drm_device *dev = intel_dig_port->base.base.dev;
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 678         uint32_t status;
 679         bool done;
 680
 681 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 682         if (has_aux_irq)
 683                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 684                                           msecs_to_jiffies_timeout(10));
 685         else
 686                 done = wait_for_atomic(C, 10) == 0;
 687         if (!done)
 688                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 689                           has_aux_irq);
 690 #undef C
 691
 692         return status;
 693 }
 694
 695 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 696 {
 697         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 698         struct drm_device *dev = intel_dig_port->base.base.dev;
 699
 700         /*
 701          * The clock divider is based off the hrawclk, and would like to run at
 702          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 703          */
 704         return index ? 0 : intel_hrawclk(dev) / 2;
 705 }
 706
 707 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 708 {
 709         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 710         struct drm_device *dev = intel_dig_port->base.base.dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712
 713         if (index)
 714                 return 0;
 715
 716         if (intel_dig_port->port == PORT_A) {
 717                 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
 718
 719         } else {
 720                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 721         }
 722 }
 723
 724 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 725 {
 726         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 727         struct drm_device *dev = intel_dig_port->base.base.dev;
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729
 730         if (intel_dig_port->port == PORT_A) {
 731                 if (index)
 732                         return 0;
 733                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 734         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 735                 /* Workaround for non-ULT HSW */
 736                 switch (index) {
 737                 case 0: return 63;
 738                 case 1: return 72;
 739                 default: return 0;
 740                 }
 741         } else  {
 742                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 743         }
 744 }
 745
 746 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 747 {
 748         return index ? 0 : 100;
 749 }
 750
 751 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 752 {
 753         /*
 754          * SKL doesn't need us to program the AUX clock divider (Hardware will
 755          * derive the clock from CDCLK automatically). We still implement the
 756          * get_aux_clock_divider vfunc to plug-in into the existing code.
 757          */
 758         return index ? 0 : 1;
 759 }
 760
 761 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 762                                       bool has_aux_irq,
 763                                       int send_bytes,
 764                                       uint32_t aux_clock_divider)
 765 {
 766         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 767         struct drm_device *dev = intel_dig_port->base.base.dev;
 768         uint32_t precharge, timeout;
 769
 770         if (IS_GEN6(dev))
 771                 precharge = 3;
 772         else
 773                 precharge = 5;
 774
 775         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 776                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 777         else
 778                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 779
 780         return DP_AUX_CH_CTL_SEND_BUSY |
 781                DP_AUX_CH_CTL_DONE |
 782                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 783                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 784                timeout |
 785                DP_AUX_CH_CTL_RECEIVE_ERROR |
 786                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 787                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 788                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 789 }
 790
 791 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 792                                       bool has_aux_irq,
 793                                       int send_bytes,
 794                                       uint32_t unused)
 795 {
 796         return DP_AUX_CH_CTL_SEND_BUSY |
 797                DP_AUX_CH_CTL_DONE |
 798                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 799                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 800                DP_AUX_CH_CTL_TIME_OUT_1600us |
 801                DP_AUX_CH_CTL_RECEIVE_ERROR |
 802                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 803                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 804 }
 805
 806 static int
 807 intel_dp_aux_ch(struct intel_dp *intel_dp,
 808                 const uint8_t *send, int send_bytes,
 809                 uint8_t *recv, int recv_size)
 810 {
 811         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 812         struct drm_device *dev = intel_dig_port->base.base.dev;
 813         struct drm_i915_private *dev_priv = dev->dev_private;
 814         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 815         uint32_t ch_data = ch_ctl + 4;
 816         uint32_t aux_clock_divider;
 817         int i, ret, recv_bytes;
 818         uint32_t status;
 819         int try, clock = 0;
 820         bool has_aux_irq = HAS_AUX_IRQ(dev);
 821         bool vdd;
 822
 823         pps_lock(intel_dp);
 824
 825         /*
 826          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 827          * In such cases we want to leave VDD enabled and it's up to upper layers
 828          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 829          * ourselves.
 830          */
 831         vdd = edp_panel_vdd_on(intel_dp);
 832
 833         /* dp aux is extremely sensitive to irq latency, hence request the
 834          * lowest possible wakeup latency and so prevent the cpu from going into
 835          * deep sleep states.
 836          */
 837         pm_qos_update_request(&dev_priv->pm_qos, 0);
 838
 839         intel_dp_check_edp(intel_dp);
 840
 841         intel_aux_display_runtime_get(dev_priv);
 842
 843         /* Try to wait for any previous AUX channel activity */
 844         for (try = 0; try < 3; try++) {
 845                 status = I915_READ_NOTRACE(ch_ctl);
 846                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 847                         break;
 848                 msleep(1);
 849         }
 850
 851         if (try == 3) {
 852                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 853                      I915_READ(ch_ctl));
 854                 ret = -EBUSY;
 855                 goto out;
 856         }
 857
 858         /* Only 5 data registers! */
 859         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 860                 ret = -E2BIG;
 861                 goto out;
 862         }
 863
 864         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 865                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 866                                                           has_aux_irq,
 867                                                           send_bytes,
 868                                                           aux_clock_divider);
 869
 870                 /* Must try at least 3 times according to DP spec */
 871                 for (try = 0; try < 5; try++) {
 872                         /* Load the send data into the aux channel data registers */
 873                         for (i = 0; i < send_bytes; i += 4)
 874                                 I915_WRITE(ch_data + i,
 875                                            intel_dp_pack_aux(send + i,
 876                                                              send_bytes - i));
 877
 878                         /* Send the command and wait for it to complete */
 879                         I915_WRITE(ch_ctl, send_ctl);
 880
 881                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 882
 883                         /* Clear done status and any errors */
 884                         I915_WRITE(ch_ctl,
 885                                    status |
 886                                    DP_AUX_CH_CTL_DONE |
 887                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 888                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 889
 890                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 891                                 continue;
 892
 893                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 894                          *   400us delay required for errors and timeouts
 895                          *   Timeout errors from the HW already meet this
 896                          *   requirement so skip to next iteration
 897                          */
 898                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 899                                 usleep_range(400, 500);
 900                                 continue;
 901                         }
 902                         if (status & DP_AUX_CH_CTL_DONE)
 903                                 goto done;
 904                 }
 905         }
 906
 907         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 908                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 909                 ret = -EBUSY;
 910                 goto out;
 911         }
 912
 913 done:
 914         /* Check for timeout or receive error.
 915          * Timeouts occur when the sink is not connected
 916          */
 917         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 918                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 919                 ret = -EIO;
 920                 goto out;
 921         }
 922
 923         /* Timeouts occur when the device isn't connected, so they're
 924          * "normal" -- don't fill the kernel log with these */
 925         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 926                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 927                 ret = -ETIMEDOUT;
 928                 goto out;
 929         }
 930
 931         /* Unload any bytes sent back from the other side */
 932         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 933                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 934         if (recv_bytes > recv_size)
 935                 recv_bytes = recv_size;
 936
 937         for (i = 0; i < recv_bytes; i += 4)
 938                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 939                                     recv + i, recv_bytes - i);
 940
 941         ret = recv_bytes;
 942 out:
 943         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 944         intel_aux_display_runtime_put(dev_priv);
 945
 946         if (vdd)
 947                 edp_panel_vdd_off(intel_dp, false);
 948
 949         pps_unlock(intel_dp);
 950
 951         return ret;
 952 }
 953
 954 #define BARE_ADDRESS_SIZE       3
 955 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 956 static ssize_t
 957 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 958 {
 959         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 960         uint8_t txbuf[20], rxbuf[20];
 961         size_t txsize, rxsize;
 962         int ret;
 963
 964         txbuf[0] = (msg->request << 4) |
 965                 ((msg->address >> 16) & 0xf);
 966         txbuf[1] = (msg->address >> 8) & 0xff;
 967         txbuf[2] = msg->address & 0xff;
 968         txbuf[3] = msg->size - 1;
 969
 970         switch (msg->request & ~DP_AUX_I2C_MOT) {
 971         case DP_AUX_NATIVE_WRITE:
 972         case DP_AUX_I2C_WRITE:
 973                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 974                 rxsize = 2; /* 0 or 1 data bytes */
 975
 976                 if (WARN_ON(txsize > 20))
 977                         return -E2BIG;
 978
 979                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 980
 981                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 982                 if (ret > 0) {
 983                         msg->reply = rxbuf[0] >> 4;
 984
 985                         if (ret > 1) {
 986                                 /* Number of bytes written in a short write. */
 987                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 988                         } else {
 989                                 /* Return payload size. */
 990                                 ret = msg->size;
 991                         }
 992                 }
 993                 break;
 994
 995         case DP_AUX_NATIVE_READ:
 996         case DP_AUX_I2C_READ:
 997                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 998                 rxsize = msg->size + 1;
 999
1000                 if (WARN_ON(rxsize > 20))
1001                         return -E2BIG;
1002
1003                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1004                 if (ret > 0) {
1005                         msg->reply = rxbuf[0] >> 4;
1006                         /*
1007                          * Assume happy day, and copy the data. The caller is
1008                          * expected to check msg->reply before touching it.
1009                          *
1010                          * Return payload size.
1011                          */
1012                         ret--;
1013                         memcpy(msg->buffer, rxbuf + 1, ret);
1014                 }
1015                 break;
1016
1017         default:
1018                 ret = -EINVAL;
1019                 break;
1020         }
1021
1022         return ret;
1023 }
1024
1025 static void
1026 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1027 {
1028         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1029         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1030         enum port port = intel_dig_port->port;
1031         const char *name = NULL;
1032         int ret;
1033
1034         switch (port) {
1035         case PORT_A:
1036                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1037                 name = "DPDDC-A";
1038                 break;
1039         case PORT_B:
1040                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1041                 name = "DPDDC-B";
1042                 break;
1043         case PORT_C:
1044                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1045                 name = "DPDDC-C";
1046                 break;
1047         case PORT_D:
1048                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1049                 name = "DPDDC-D";
1050                 break;
1051         default:
1052                 BUG();
1053         }
1054
1055         /*
1056          * The AUX_CTL register is usually DP_CTL + 0x10.
1057          *
1058          * On Haswell and Broadwell though:
1059          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1060          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1061          *
1062          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1063          */
1064         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1065                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1066
1067         intel_dp->aux.name = name;
1068         intel_dp->aux.dev = dev->dev;
1069         intel_dp->aux.transfer = intel_dp_aux_transfer;
1070
1071         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1072                       connector->base.kdev->kobj.name);
1073
1074         ret = drm_dp_aux_register(&intel_dp->aux);
1075         if (ret < 0) {
1076                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1077                           name, ret);
1078                 return;
1079         }
1080
1081         ret = sysfs_create_link(&connector->base.kdev->kobj,
1082                                 &intel_dp->aux.ddc.dev.kobj,
1083                                 intel_dp->aux.ddc.dev.kobj.name);
1084         if (ret < 0) {
1085                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1086                 drm_dp_aux_unregister(&intel_dp->aux);
1087         }
1088 }
1089
1090 static void
1091 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1092 {
1093         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1094
1095         if (!intel_connector->mst_port)
1096                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1097                                   intel_dp->aux.ddc.dev.kobj.name);
1098         intel_connector_unregister(intel_connector);
1099 }
1100
1101 static void
1102 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
1103 {
1104         u32 ctrl1;
1105
1106         memset(&pipe_config->dpll_hw_state, 0,
1107                sizeof(pipe_config->dpll_hw_state));
1108
1109         pipe_config->ddi_pll_sel = SKL_DPLL0;
1110         pipe_config->dpll_hw_state.cfgcr1 = 0;
1111         pipe_config->dpll_hw_state.cfgcr2 = 0;
1112
1113         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1114         switch (link_clock / 2) {
1115         case 81000:
1116                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1117                                               SKL_DPLL0);
1118                 break;
1119         case 135000:
1120                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1121                                               SKL_DPLL0);
1122                 break;
1123         case 270000:
1124                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1125                                               SKL_DPLL0);
1126                 break;
1127         case 162000:
1128                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1129                                               SKL_DPLL0);
1130                 break;
1131         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1132         results in CDCLK change. Need to handle the change of CDCLK by
1133         disabling pipes and re-enabling them */
1134         case 108000:
1135                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1136                                               SKL_DPLL0);
1137                 break;
1138         case 216000:
1139                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1140                                               SKL_DPLL0);
1141                 break;
1142
1143         }
1144         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1145 }
1146
1147 static void
1148 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1149 {
1150         memset(&pipe_config->dpll_hw_state, 0,
1151                sizeof(pipe_config->dpll_hw_state));
1152
1153         switch (link_bw) {
1154         case DP_LINK_BW_1_62:
1155                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1156                 break;
1157         case DP_LINK_BW_2_7:
1158                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1159                 break;
1160         case DP_LINK_BW_5_4:
1161                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1162                 break;
1163         }
1164 }
1165
1166 static int
1167 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1168 {
1169         if (intel_dp->num_sink_rates) {
1170                 *sink_rates = intel_dp->sink_rates;
1171                 return intel_dp->num_sink_rates;
1172         }
1173
1174         *sink_rates = default_rates;
1175
1176         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1177 }
1178
1179 static int
1180 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1181 {
1182         if (IS_BROXTON(dev)) {
1183                 *source_rates = bxt_rates;
1184                 return ARRAY_SIZE(bxt_rates);
1185         } else if (IS_SKYLAKE(dev)) {
1186                 *source_rates = skl_rates;
1187                 return ARRAY_SIZE(skl_rates);
1188         } else if (IS_CHERRYVIEW(dev)) {
1189                 *source_rates = chv_rates;
1190                 return ARRAY_SIZE(chv_rates);
1191         }
1192
1193         *source_rates = default_rates;
1194
1195         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1196                 /* WaDisableHBR2:skl */
1197                 return (DP_LINK_BW_2_7 >> 3) + 1;
1198         else if (INTEL_INFO(dev)->gen >= 8 ||
1199             (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1200                 return (DP_LINK_BW_5_4 >> 3) + 1;
1201         else
1202                 return (DP_LINK_BW_2_7 >> 3) + 1;
1203 }
1204
1205 static void
1206 intel_dp_set_clock(struct intel_encoder *encoder,
1207                    struct intel_crtc_state *pipe_config, int link_bw)
1208 {
1209         struct drm_device *dev = encoder->base.dev;
1210         const struct dp_link_dpll *divisor = NULL;
1211         int i, count = 0;
1212
1213         if (IS_G4X(dev)) {
1214                 divisor = gen4_dpll;
1215                 count = ARRAY_SIZE(gen4_dpll);
1216         } else if (HAS_PCH_SPLIT(dev)) {
1217                 divisor = pch_dpll;
1218                 count = ARRAY_SIZE(pch_dpll);
1219         } else if (IS_CHERRYVIEW(dev)) {
1220                 divisor = chv_dpll;
1221                 count = ARRAY_SIZE(chv_dpll);
1222         } else if (IS_VALLEYVIEW(dev)) {
1223                 divisor = vlv_dpll;
1224                 count = ARRAY_SIZE(vlv_dpll);
1225         }
1226
1227         if (divisor && count) {
1228                 for (i = 0; i < count; i++) {
1229                         if (link_bw == divisor[i].link_bw) {
1230                                 pipe_config->dpll = divisor[i].dpll;
1231                                 pipe_config->clock_set = true;
1232                                 break;
1233                         }
1234                 }
1235         }
1236 }
1237
1238 static int intersect_rates(const int *source_rates, int source_len,
1239                            const int *sink_rates, int sink_len,
1240                            int *common_rates)
1241 {
1242         int i = 0, j = 0, k = 0;
1243
1244         while (i < source_len && j < sink_len) {
1245                 if (source_rates[i] == sink_rates[j]) {
1246                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1247                                 return k;
1248                         common_rates[k] = source_rates[i];
1249                         ++k;
1250                         ++i;
1251                         ++j;
1252                 } else if (source_rates[i] < sink_rates[j]) {
1253                         ++i;
1254                 } else {
1255                         ++j;
1256                 }
1257         }
1258         return k;
1259 }
1260
1261 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1262                                  int *common_rates)
1263 {
1264         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1265         const int *source_rates, *sink_rates;
1266         int source_len, sink_len;
1267
1268         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1269         source_len = intel_dp_source_rates(dev, &source_rates);
1270
1271         return intersect_rates(source_rates, source_len,
1272                                sink_rates, sink_len,
1273                                common_rates);
1274 }
1275
1276 static void snprintf_int_array(char *str, size_t len,
1277                                const int *array, int nelem)
1278 {
1279         int i;
1280
1281         str[0] = '\0';
1282
1283         for (i = 0; i < nelem; i++) {
1284                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1285                 if (r >= len)
1286                         return;
1287                 str += r;
1288                 len -= r;
1289         }
1290 }
1291
1292 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1293 {
1294         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1295         const int *source_rates, *sink_rates;
1296         int source_len, sink_len, common_len;
1297         int common_rates[DP_MAX_SUPPORTED_RATES];
1298         char str[128]; /* FIXME: too big for stack? */
1299
1300         if ((drm_debug & DRM_UT_KMS) == 0)
1301                 return;
1302
1303         source_len = intel_dp_source_rates(dev, &source_rates);
1304         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1305         DRM_DEBUG_KMS("source rates: %s\n", str);
1306
1307         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1308         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1309         DRM_DEBUG_KMS("sink rates: %s\n", str);
1310
1311         common_len = intel_dp_common_rates(intel_dp, common_rates);
1312         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1313         DRM_DEBUG_KMS("common rates: %s\n", str);
1314 }
1315
1316 static int rate_to_index(int find, const int *rates)
1317 {
1318         int i = 0;
1319
1320         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1321                 if (find == rates[i])
1322                         break;
1323
1324         return i;
1325 }
1326
1327 int
1328 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1329 {
1330         int rates[DP_MAX_SUPPORTED_RATES] = {};
1331         int len;
1332
1333         len = intel_dp_common_rates(intel_dp, rates);
1334         if (WARN_ON(len <= 0))
1335                 return 162000;
1336
1337         return rates[rate_to_index(0, rates) - 1];
1338 }
1339
1340 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1341 {
1342         return rate_to_index(rate, intel_dp->sink_rates);
1343 }
1344
1345 bool
1346 intel_dp_compute_config(struct intel_encoder *encoder,
1347                         struct intel_crtc_state *pipe_config)
1348 {
1349         struct drm_device *dev = encoder->base.dev;
1350         struct drm_i915_private *dev_priv = dev->dev_private;
1351         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1352         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1353         enum port port = dp_to_dig_port(intel_dp)->port;
1354         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1355         struct intel_connector *intel_connector = intel_dp->attached_connector;
1356         int lane_count, clock;
1357         int min_lane_count = 1;
1358         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1359         /* Conveniently, the link BW constants become indices with a shift...*/
1360         int min_clock = 0;
1361         int max_clock;
1362         int bpp, mode_rate;
1363         int link_avail, link_clock;
1364         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1365         int common_len;
1366
1367         common_len = intel_dp_common_rates(intel_dp, common_rates);
1368
1369         /* No common link rates between source and sink */
1370         WARN_ON(common_len <= 0);
1371
1372         max_clock = common_len - 1;
1373
1374         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1375                 pipe_config->has_pch_encoder = true;
1376
1377         pipe_config->has_dp_encoder = true;
1378         pipe_config->has_drrs = false;
1379         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1380
1381         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1382                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1383                                        adjusted_mode);
1384
1385                 if (INTEL_INFO(dev)->gen >= 9) {
1386                         int ret;
1387                         ret = skl_update_scaler_crtc(pipe_config);
1388                         if (ret)
1389                                 return ret;
1390                 }
1391
1392                 if (!HAS_PCH_SPLIT(dev))
1393                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1394                                                  intel_connector->panel.fitting_mode);
1395                 else
1396                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1397                                                 intel_connector->panel.fitting_mode);
1398         }
1399
1400         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1401                 return false;
1402
1403         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1404                       "max bw %d pixel clock %iKHz\n",
1405                       max_lane_count, common_rates[max_clock],
1406                       adjusted_mode->crtc_clock);
1407
1408         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1409          * bpc in between. */
1410         bpp = pipe_config->pipe_bpp;
1411         if (is_edp(intel_dp)) {
1412                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1413                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1414                                       dev_priv->vbt.edp_bpp);
1415                         bpp = dev_priv->vbt.edp_bpp;
1416                 }
1417
1418                 /*
1419                  * Use the maximum clock and number of lanes the eDP panel
1420                  * advertizes being capable of. The panels are generally
1421                  * designed to support only a single clock and lane
1422                  * configuration, and typically these values correspond to the
1423                  * native resolution of the panel.
1424                  */
1425                 min_lane_count = max_lane_count;
1426                 min_clock = max_clock;
1427         }
1428
1429         for (; bpp >= 6*3; bpp -= 2*3) {
1430                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1431                                                    bpp);
1432
1433                 for (clock = min_clock; clock <= max_clock; clock++) {
1434                         for (lane_count = min_lane_count;
1435                                 lane_count <= max_lane_count;
1436                                 lane_count <<= 1) {
1437
1438                                 link_clock = common_rates[clock];
1439                                 link_avail = intel_dp_max_data_rate(link_clock,
1440                                                                     lane_count);
1441
1442                                 if (mode_rate <= link_avail) {
1443                                         goto found;
1444                                 }
1445                         }
1446                 }
1447         }
1448
1449         return false;
1450
1451 found:
1452         if (intel_dp->color_range_auto) {
1453                 /*
1454                  * See:
1455                  * CEA-861-E - 5.1 Default Encoding Parameters
1456                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1457                  */
1458                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1459                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1460                 else
1461                         intel_dp->color_range = 0;
1462         }
1463
1464         if (intel_dp->color_range)
1465                 pipe_config->limited_color_range = true;
1466
1467         intel_dp->lane_count = lane_count;
1468
1469         if (intel_dp->num_sink_rates) {
1470                 intel_dp->link_bw = 0;
1471                 intel_dp->rate_select =
1472                         intel_dp_rate_select(intel_dp, common_rates[clock]);
1473         } else {
1474                 intel_dp->link_bw =
1475                         drm_dp_link_rate_to_bw_code(common_rates[clock]);
1476                 intel_dp->rate_select = 0;
1477         }
1478
1479         pipe_config->pipe_bpp = bpp;
1480         pipe_config->port_clock = common_rates[clock];
1481
1482         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1483                       intel_dp->link_bw, intel_dp->lane_count,
1484                       pipe_config->port_clock, bpp);
1485         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1486                       mode_rate, link_avail);
1487
1488         intel_link_compute_m_n(bpp, lane_count,
1489                                adjusted_mode->crtc_clock,
1490                                pipe_config->port_clock,
1491                                &pipe_config->dp_m_n);
1492
1493         if (intel_connector->panel.downclock_mode != NULL &&
1494                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1495                         pipe_config->has_drrs = true;
1496                         intel_link_compute_m_n(bpp, lane_count,
1497                                 intel_connector->panel.downclock_mode->clock,
1498                                 pipe_config->port_clock,
1499                                 &pipe_config->dp_m2_n2);
1500         }
1501
1502         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1503                 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
1504         else if (IS_BROXTON(dev))
1505                 /* handled in ddi */;
1506         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1507                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1508         else
1509                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1510
1511         return true;
1512 }
1513
1514 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1515 {
1516         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1517         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1518         struct drm_device *dev = crtc->base.dev;
1519         struct drm_i915_private *dev_priv = dev->dev_private;
1520         u32 dpa_ctl;
1521
1522         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1523                       crtc->config->port_clock);
1524         dpa_ctl = I915_READ(DP_A);
1525         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1526
1527         if (crtc->config->port_clock == 162000) {
1528                 /* For a long time we've carried around a ILK-DevA w/a for the
1529                  * 160MHz clock. If we're really unlucky, it's still required.
1530                  */
1531                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1532                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1533                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1534         } else {
1535                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1536                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1537         }
1538
1539         I915_WRITE(DP_A, dpa_ctl);
1540
1541         POSTING_READ(DP_A);
1542         udelay(500);
1543 }
1544
1545 static void intel_dp_prepare(struct intel_encoder *encoder)
1546 {
1547         struct drm_device *dev = encoder->base.dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1550         enum port port = dp_to_dig_port(intel_dp)->port;
1551         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1552         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1553
1554         /*
1555          * There are four kinds of DP registers:
1556          *
1557          *      IBX PCH
1558          *      SNB CPU
1559          *      IVB CPU
1560          *      CPT PCH
1561          *
1562          * IBX PCH and CPU are the same for almost everything,
1563          * except that the CPU DP PLL is configured in this
1564          * register
1565          *
1566          * CPT PCH is quite different, having many bits moved
1567          * to the TRANS_DP_CTL register instead. That
1568          * configuration happens (oddly) in ironlake_pch_enable
1569          */
1570
1571         /* Preserve the BIOS-computed detected bit. This is
1572          * supposed to be read-only.
1573          */
1574         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1575
1576         /* Handle DP bits in common between all three register formats */
1577         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1578         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1579
1580         if (crtc->config->has_audio)
1581                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1582
1583         /* Split out the IBX/CPU vs CPT settings */
1584
1585         if (IS_GEN7(dev) && port == PORT_A) {
1586                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1587                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1588                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1589                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1590                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1591
1592                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1593                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1594
1595                 intel_dp->DP |= crtc->pipe << 29;
1596         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1597                 u32 trans_dp;
1598
1599                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1600
1601                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1602                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1603                         trans_dp |= TRANS_DP_ENH_FRAMING;
1604                 else
1605                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1606                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1607         } else {
1608                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1609                         intel_dp->DP |= intel_dp->color_range;
1610
1611                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1612                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1613                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1614                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1615                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1616
1617                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1618                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1619
1620                 if (IS_CHERRYVIEW(dev))
1621                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1622                 else if (crtc->pipe == PIPE_B)
1623                         intel_dp->DP |= DP_PIPEB_SELECT;
1624         }
1625 }
1626
1627 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1628 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1629
1630 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1631 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1632
1633 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1634 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1635
1636 static void wait_panel_status(struct intel_dp *intel_dp,
1637                                        u32 mask,
1638                                        u32 value)
1639 {
1640         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         u32 pp_stat_reg, pp_ctrl_reg;
1643
1644         lockdep_assert_held(&dev_priv->pps_mutex);
1645
1646         pp_stat_reg = _pp_stat_reg(intel_dp);
1647         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1648
1649         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1650                         mask, value,
1651                         I915_READ(pp_stat_reg),
1652                         I915_READ(pp_ctrl_reg));
1653
1654         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1655                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1656                                 I915_READ(pp_stat_reg),
1657                                 I915_READ(pp_ctrl_reg));
1658         }
1659
1660         DRM_DEBUG_KMS("Wait complete\n");
1661 }
1662
1663 static void wait_panel_on(struct intel_dp *intel_dp)
1664 {
1665         DRM_DEBUG_KMS("Wait for panel power on\n");
1666         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1667 }
1668
1669 static void wait_panel_off(struct intel_dp *intel_dp)
1670 {
1671         DRM_DEBUG_KMS("Wait for panel power off time\n");
1672         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1673 }
1674
1675 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1676 {
1677         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1678
1679         /* When we disable the VDD override bit last we have to do the manual
1680          * wait. */
1681         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1682                                        intel_dp->panel_power_cycle_delay);
1683
1684         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1685 }
1686
1687 static void wait_backlight_on(struct intel_dp *intel_dp)
1688 {
1689         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1690                                        intel_dp->backlight_on_delay);
1691 }
1692
1693 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1694 {
1695         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1696                                        intel_dp->backlight_off_delay);
1697 }
1698
1699 /* Read the current pp_control value, unlocking the register if it
1700  * is locked
1701  */
1702
1703 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1704 {
1705         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         u32 control;
1708
1709         lockdep_assert_held(&dev_priv->pps_mutex);
1710
1711         control = I915_READ(_pp_ctrl_reg(intel_dp));
1712         if (!IS_BROXTON(dev)) {
1713                 control &= ~PANEL_UNLOCK_MASK;
1714                 control |= PANEL_UNLOCK_REGS;
1715         }
1716         return control;
1717 }
1718
1719 /*
1720  * Must be paired with edp_panel_vdd_off().
1721  * Must hold pps_mutex around the whole on/off sequence.
1722  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1723  */
1724 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1725 {
1726         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1727         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1728         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         enum intel_display_power_domain power_domain;
1731         u32 pp;
1732         u32 pp_stat_reg, pp_ctrl_reg;
1733         bool need_to_disable = !intel_dp->want_panel_vdd;
1734
1735         lockdep_assert_held(&dev_priv->pps_mutex);
1736
1737         if (!is_edp(intel_dp))
1738                 return false;
1739
1740         cancel_delayed_work(&intel_dp->panel_vdd_work);
1741         intel_dp->want_panel_vdd = true;
1742
1743         if (edp_have_panel_vdd(intel_dp))
1744                 return need_to_disable;
1745
1746         power_domain = intel_display_port_power_domain(intel_encoder);
1747         intel_display_power_get(dev_priv, power_domain);
1748
1749         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1750                       port_name(intel_dig_port->port));
1751
1752         if (!edp_have_panel_power(intel_dp))
1753                 wait_panel_power_cycle(intel_dp);
1754
1755         pp = ironlake_get_pp_control(intel_dp);
1756         pp |= EDP_FORCE_VDD;
1757
1758         pp_stat_reg = _pp_stat_reg(intel_dp);
1759         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1760
1761         I915_WRITE(pp_ctrl_reg, pp);
1762         POSTING_READ(pp_ctrl_reg);
1763         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1764                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1765         /*
1766          * If the panel wasn't on, delay before accessing aux channel
1767          */
1768         if (!edp_have_panel_power(intel_dp)) {
1769                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1770                               port_name(intel_dig_port->port));
1771                 msleep(intel_dp->panel_power_up_delay);
1772         }
1773
1774         return need_to_disable;
1775 }
1776
1777 /*
1778  * Must be paired with intel_edp_panel_vdd_off() or
1779  * intel_edp_panel_off().
1780  * Nested calls to these functions are not allowed since
1781  * we drop the lock. Caller must use some higher level
1782  * locking to prevent nested calls from other threads.
1783  */
1784 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1785 {
1786         bool vdd;
1787
1788         if (!is_edp(intel_dp))
1789                 return;
1790
1791         pps_lock(intel_dp);
1792         vdd = edp_panel_vdd_on(intel_dp);
1793         pps_unlock(intel_dp);
1794
1795         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1796              port_name(dp_to_dig_port(intel_dp)->port));
1797 }
1798
1799 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1800 {
1801         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803         struct intel_digital_port *intel_dig_port =
1804                 dp_to_dig_port(intel_dp);
1805         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1806         enum intel_display_power_domain power_domain;
1807         u32 pp;
1808         u32 pp_stat_reg, pp_ctrl_reg;
1809
1810         lockdep_assert_held(&dev_priv->pps_mutex);
1811
1812         WARN_ON(intel_dp->want_panel_vdd);
1813
1814         if (!edp_have_panel_vdd(intel_dp))
1815                 return;
1816
1817         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1818                       port_name(intel_dig_port->port));
1819
1820         pp = ironlake_get_pp_control(intel_dp);
1821         pp &= ~EDP_FORCE_VDD;
1822
1823         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1824         pp_stat_reg = _pp_stat_reg(intel_dp);
1825
1826         I915_WRITE(pp_ctrl_reg, pp);
1827         POSTING_READ(pp_ctrl_reg);
1828
1829         /* Make sure sequencer is idle before allowing subsequent activity */
1830         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1831         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1832
1833         if ((pp & POWER_TARGET_ON) == 0)
1834                 intel_dp->last_power_cycle = jiffies;
1835
1836         power_domain = intel_display_port_power_domain(intel_encoder);
1837         intel_display_power_put(dev_priv, power_domain);
1838 }
1839
1840 static void edp_panel_vdd_work(struct work_struct *__work)
1841 {
1842         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1843                                                  struct intel_dp, panel_vdd_work);
1844
1845         pps_lock(intel_dp);
1846         if (!intel_dp->want_panel_vdd)
1847                 edp_panel_vdd_off_sync(intel_dp);
1848         pps_unlock(intel_dp);
1849 }
1850
1851 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1852 {
1853         unsigned long delay;
1854
1855         /*
1856          * Queue the timer to fire a long time from now (relative to the power
1857          * down delay) to keep the panel power up across a sequence of
1858          * operations.
1859          */
1860         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1861         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1862 }
1863
1864 /*
1865  * Must be paired with edp_panel_vdd_on().
1866  * Must hold pps_mutex around the whole on/off sequence.
1867  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1868  */
1869 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1870 {
1871         struct drm_i915_private *dev_priv =
1872                 intel_dp_to_dev(intel_dp)->dev_private;
1873
1874         lockdep_assert_held(&dev_priv->pps_mutex);
1875
1876         if (!is_edp(intel_dp))
1877                 return;
1878
1879         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1880              port_name(dp_to_dig_port(intel_dp)->port));
1881
1882         intel_dp->want_panel_vdd = false;
1883
1884         if (sync)
1885                 edp_panel_vdd_off_sync(intel_dp);
1886         else
1887                 edp_panel_vdd_schedule_off(intel_dp);
1888 }
1889
1890 static void edp_panel_on(struct intel_dp *intel_dp)
1891 {
1892         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1893         struct drm_i915_private *dev_priv = dev->dev_private;
1894         u32 pp;
1895         u32 pp_ctrl_reg;
1896
1897         lockdep_assert_held(&dev_priv->pps_mutex);
1898
1899         if (!is_edp(intel_dp))
1900                 return;
1901
1902         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1903                       port_name(dp_to_dig_port(intel_dp)->port));
1904
1905         if (WARN(edp_have_panel_power(intel_dp),
1906                  "eDP port %c panel power already on\n",
1907                  port_name(dp_to_dig_port(intel_dp)->port)))
1908                 return;
1909
1910         wait_panel_power_cycle(intel_dp);
1911
1912         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1913         pp = ironlake_get_pp_control(intel_dp);
1914         if (IS_GEN5(dev)) {
1915                 /* ILK workaround: disable reset around power sequence */
1916                 pp &= ~PANEL_POWER_RESET;
1917                 I915_WRITE(pp_ctrl_reg, pp);
1918                 POSTING_READ(pp_ctrl_reg);
1919         }
1920
1921         pp |= POWER_TARGET_ON;
1922         if (!IS_GEN5(dev))
1923                 pp |= PANEL_POWER_RESET;
1924
1925         I915_WRITE(pp_ctrl_reg, pp);
1926         POSTING_READ(pp_ctrl_reg);
1927
1928         wait_panel_on(intel_dp);
1929         intel_dp->last_power_on = jiffies;
1930
1931         if (IS_GEN5(dev)) {
1932                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1933                 I915_WRITE(pp_ctrl_reg, pp);
1934                 POSTING_READ(pp_ctrl_reg);
1935         }
1936 }
1937
1938 void intel_edp_panel_on(struct intel_dp *intel_dp)
1939 {
1940         if (!is_edp(intel_dp))
1941                 return;
1942
1943         pps_lock(intel_dp);
1944         edp_panel_on(intel_dp);
1945         pps_unlock(intel_dp);
1946 }
1947
1948
1949 static void edp_panel_off(struct intel_dp *intel_dp)
1950 {
1951         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1952         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1953         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1954         struct drm_i915_private *dev_priv = dev->dev_private;
1955         enum intel_display_power_domain power_domain;
1956         u32 pp;
1957         u32 pp_ctrl_reg;
1958
1959         lockdep_assert_held(&dev_priv->pps_mutex);
1960
1961         if (!is_edp(intel_dp))
1962                 return;
1963
1964         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1965                       port_name(dp_to_dig_port(intel_dp)->port));
1966
1967         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1968              port_name(dp_to_dig_port(intel_dp)->port));
1969
1970         pp = ironlake_get_pp_control(intel_dp);
1971         /* We need to switch off panel power _and_ force vdd, for otherwise some
1972          * panels get very unhappy and cease to work. */
1973         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1974                 EDP_BLC_ENABLE);
1975
1976         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1977
1978         intel_dp->want_panel_vdd = false;
1979
1980         I915_WRITE(pp_ctrl_reg, pp);
1981         POSTING_READ(pp_ctrl_reg);
1982
1983         intel_dp->last_power_cycle = jiffies;
1984         wait_panel_off(intel_dp);
1985
1986         /* We got a reference when we enabled the VDD. */
1987         power_domain = intel_display_port_power_domain(intel_encoder);
1988         intel_display_power_put(dev_priv, power_domain);
1989 }
1990
1991 void intel_edp_panel_off(struct intel_dp *intel_dp)
1992 {
1993         if (!is_edp(intel_dp))
1994                 return;
1995
1996         pps_lock(intel_dp);
1997         edp_panel_off(intel_dp);
1998         pps_unlock(intel_dp);
1999 }
2000
2001 /* Enable backlight in the panel power control. */
2002 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2003 {
2004         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2005         struct drm_device *dev = intel_dig_port->base.base.dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         u32 pp;
2008         u32 pp_ctrl_reg;
2009
2010         /*
2011          * If we enable the backlight right away following a panel power
2012          * on, we may see slight flicker as the panel syncs with the eDP
2013          * link.  So delay a bit to make sure the image is solid before
2014          * allowing it to appear.
2015          */
2016         wait_backlight_on(intel_dp);
2017
2018         pps_lock(intel_dp);
2019
2020         pp = ironlake_get_pp_control(intel_dp);
2021         pp |= EDP_BLC_ENABLE;
2022
2023         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2024
2025         I915_WRITE(pp_ctrl_reg, pp);
2026         POSTING_READ(pp_ctrl_reg);
2027
2028         pps_unlock(intel_dp);
2029 }
2030
2031 /* Enable backlight PWM and backlight PP control. */
2032 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2033 {
2034         if (!is_edp(intel_dp))
2035                 return;
2036
2037         DRM_DEBUG_KMS("\n");
2038
2039         intel_panel_enable_backlight(intel_dp->attached_connector);
2040         _intel_edp_backlight_on(intel_dp);
2041 }
2042
2043 /* Disable backlight in the panel power control. */
2044 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2045 {
2046         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         u32 pp;
2049         u32 pp_ctrl_reg;
2050
2051         if (!is_edp(intel_dp))
2052                 return;
2053
2054         pps_lock(intel_dp);
2055
2056         pp = ironlake_get_pp_control(intel_dp);
2057         pp &= ~EDP_BLC_ENABLE;
2058
2059         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2060
2061         I915_WRITE(pp_ctrl_reg, pp);
2062         POSTING_READ(pp_ctrl_reg);
2063
2064         pps_unlock(intel_dp);
2065
2066         intel_dp->last_backlight_off = jiffies;
2067         edp_wait_backlight_off(intel_dp);
2068 }
2069
2070 /* Disable backlight PP control and backlight PWM. */
2071 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2072 {
2073         if (!is_edp(intel_dp))
2074                 return;
2075
2076         DRM_DEBUG_KMS("\n");
2077
2078         _intel_edp_backlight_off(intel_dp);
2079         intel_panel_disable_backlight(intel_dp->attached_connector);
2080 }
2081
2082 /*
2083  * Hook for controlling the panel power control backlight through the bl_power
2084  * sysfs attribute. Take care to handle multiple calls.
2085  */
2086 static void intel_edp_backlight_power(struct intel_connector *connector,
2087                                       bool enable)
2088 {
2089         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2090         bool is_enabled;
2091
2092         pps_lock(intel_dp);
2093         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2094         pps_unlock(intel_dp);
2095
2096         if (is_enabled == enable)
2097                 return;
2098
2099         DRM_DEBUG_KMS("panel power control backlight %s\n",
2100                       enable ? "enable" : "disable");
2101
2102         if (enable)
2103                 _intel_edp_backlight_on(intel_dp);
2104         else
2105                 _intel_edp_backlight_off(intel_dp);
2106 }
2107
2108 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2109 {
2110         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2111         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2112         struct drm_device *dev = crtc->dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114         u32 dpa_ctl;
2115
2116         assert_pipe_disabled(dev_priv,
2117                              to_intel_crtc(crtc)->pipe);
2118
2119         DRM_DEBUG_KMS("\n");
2120         dpa_ctl = I915_READ(DP_A);
2121         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2122         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2123
2124         /* We don't adjust intel_dp->DP while tearing down the link, to
2125          * facilitate link retraining (e.g. after hotplug). Hence clear all
2126          * enable bits here to ensure that we don't enable too much. */
2127         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2128         intel_dp->DP |= DP_PLL_ENABLE;
2129         I915_WRITE(DP_A, intel_dp->DP);
2130         POSTING_READ(DP_A);
2131         udelay(200);
2132 }
2133
2134 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2135 {
2136         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2137         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2138         struct drm_device *dev = crtc->dev;
2139         struct drm_i915_private *dev_priv = dev->dev_private;
2140         u32 dpa_ctl;
2141
2142         assert_pipe_disabled(dev_priv,
2143                              to_intel_crtc(crtc)->pipe);
2144
2145         dpa_ctl = I915_READ(DP_A);
2146         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2147              "dp pll off, should be on\n");
2148         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2149
2150         /* We can't rely on the value tracked for the DP register in
2151          * intel_dp->DP because link_down must not change that (otherwise link
2152          * re-training will fail. */
2153         dpa_ctl &= ~DP_PLL_ENABLE;
2154         I915_WRITE(DP_A, dpa_ctl);
2155         POSTING_READ(DP_A);
2156         udelay(200);
2157 }
2158
2159 /* If the sink supports it, try to set the power state appropriately */
2160 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2161 {
2162         int ret, i;
2163
2164         /* Should have a valid DPCD by this point */
2165         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2166                 return;
2167
2168         if (mode != DRM_MODE_DPMS_ON) {
2169                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2170                                          DP_SET_POWER_D3);
2171         } else {
2172                 /*
2173                  * When turning on, we need to retry for 1ms to give the sink
2174                  * time to wake up.
2175                  */
2176                 for (i = 0; i < 3; i++) {
2177                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2178                                                  DP_SET_POWER_D0);
2179                         if (ret == 1)
2180                                 break;
2181                         msleep(1);
2182                 }
2183         }
2184
2185         if (ret != 1)
2186                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2187                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2188 }
2189
2190 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2191                                   enum pipe *pipe)
2192 {
2193         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2194         enum port port = dp_to_dig_port(intel_dp)->port;
2195         struct drm_device *dev = encoder->base.dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         enum intel_display_power_domain power_domain;
2198         u32 tmp;
2199
2200         power_domain = intel_display_port_power_domain(encoder);
2201         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2202                 return false;
2203
2204         tmp = I915_READ(intel_dp->output_reg);
2205
2206         if (!(tmp & DP_PORT_EN))
2207                 return false;
2208
2209         if (IS_GEN7(dev) && port == PORT_A) {
2210                 *pipe = PORT_TO_PIPE_CPT(tmp);
2211         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2212                 enum pipe p;
2213
2214                 for_each_pipe(dev_priv, p) {
2215                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2216                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2217                                 *pipe = p;
2218                                 return true;
2219                         }
2220                 }
2221
2222                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2223                               intel_dp->output_reg);
2224         } else if (IS_CHERRYVIEW(dev)) {
2225                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2226         } else {
2227                 *pipe = PORT_TO_PIPE(tmp);
2228         }
2229
2230         return true;
2231 }
2232
2233 static void intel_dp_get_config(struct intel_encoder *encoder,
2234                                 struct intel_crtc_state *pipe_config)
2235 {
2236         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2237         u32 tmp, flags = 0;
2238         struct drm_device *dev = encoder->base.dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         enum port port = dp_to_dig_port(intel_dp)->port;
2241         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2242         int dotclock;
2243
2244         tmp = I915_READ(intel_dp->output_reg);
2245
2246         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2247
2248         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2249                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2250                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2251                         flags |= DRM_MODE_FLAG_PHSYNC;
2252                 else
2253                         flags |= DRM_MODE_FLAG_NHSYNC;
2254
2255                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2256                         flags |= DRM_MODE_FLAG_PVSYNC;
2257                 else
2258                         flags |= DRM_MODE_FLAG_NVSYNC;
2259         } else {
2260                 if (tmp & DP_SYNC_HS_HIGH)
2261                         flags |= DRM_MODE_FLAG_PHSYNC;
2262                 else
2263                         flags |= DRM_MODE_FLAG_NHSYNC;
2264
2265                 if (tmp & DP_SYNC_VS_HIGH)
2266                         flags |= DRM_MODE_FLAG_PVSYNC;
2267                 else
2268                         flags |= DRM_MODE_FLAG_NVSYNC;
2269         }
2270
2271         pipe_config->base.adjusted_mode.flags |= flags;
2272
2273         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2274             tmp & DP_COLOR_RANGE_16_235)
2275                 pipe_config->limited_color_range = true;
2276
2277         pipe_config->has_dp_encoder = true;
2278
2279         intel_dp_get_m_n(crtc, pipe_config);
2280
2281         if (port == PORT_A) {
2282                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2283                         pipe_config->port_clock = 162000;
2284                 else
2285                         pipe_config->port_clock = 270000;
2286         }
2287
2288         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2289                                             &pipe_config->dp_m_n);
2290
2291         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2292                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2293
2294         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2295
2296         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2297             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2298                 /*
2299                  * This is a big fat ugly hack.
2300                  *
2301                  * Some machines in UEFI boot mode provide us a VBT that has 18
2302                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2303                  * unknown we fail to light up. Yet the same BIOS boots up with
2304                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2305                  * max, not what it tells us to use.
2306                  *
2307                  * Note: This will still be broken if the eDP panel is not lit
2308                  * up by the BIOS, and thus we can't get the mode at module
2309                  * load.
2310                  */
2311                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2312                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2313                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2314         }
2315 }
2316
2317 static void intel_disable_dp(struct intel_encoder *encoder)
2318 {
2319         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2320         struct drm_device *dev = encoder->base.dev;
2321         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2322
2323         if (crtc->config->has_audio)
2324                 intel_audio_codec_disable(encoder);
2325
2326         if (HAS_PSR(dev) && !HAS_DDI(dev))
2327                 intel_psr_disable(intel_dp);
2328
2329         /* Make sure the panel is off before trying to change the mode. But also
2330          * ensure that we have vdd while we switch off the panel. */
2331         intel_edp_panel_vdd_on(intel_dp);
2332         intel_edp_backlight_off(intel_dp);
2333         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2334         intel_edp_panel_off(intel_dp);
2335
2336         /* disable the port before the pipe on g4x */
2337         if (INTEL_INFO(dev)->gen < 5)
2338                 intel_dp_link_down(intel_dp);
2339 }
2340
2341 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2342 {
2343         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2344         enum port port = dp_to_dig_port(intel_dp)->port;
2345
2346         intel_dp_link_down(intel_dp);
2347         if (port == PORT_A)
2348                 ironlake_edp_pll_off(intel_dp);
2349 }
2350
2351 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2352 {
2353         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2354
2355         intel_dp_link_down(intel_dp);
2356 }
2357
2358 static void chv_post_disable_dp(struct intel_encoder *encoder)
2359 {
2360         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2361         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2362         struct drm_device *dev = encoder->base.dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         struct intel_crtc *intel_crtc =
2365                 to_intel_crtc(encoder->base.crtc);
2366         enum dpio_channel ch = vlv_dport_to_channel(dport);
2367         enum pipe pipe = intel_crtc->pipe;
2368         u32 val;
2369
2370         intel_dp_link_down(intel_dp);
2371
2372         mutex_lock(&dev_priv->sb_lock);
2373
2374         /* Propagate soft reset to data lane reset */
2375         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2376         val |= CHV_PCS_REQ_SOFTRESET_EN;
2377         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2378
2379         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2380         val |= CHV_PCS_REQ_SOFTRESET_EN;
2381         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2382
2383         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2384         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2385         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2386
2387         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2388         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2389         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2390
2391         mutex_unlock(&dev_priv->sb_lock);
2392 }
2393
2394 static void
2395 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2396                          uint32_t *DP,
2397                          uint8_t dp_train_pat)
2398 {
2399         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2400         struct drm_device *dev = intel_dig_port->base.base.dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         enum port port = intel_dig_port->port;
2403
2404         if (HAS_DDI(dev)) {
2405                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2406
2407                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2408                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2409                 else
2410                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2411
2412                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2413                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2414                 case DP_TRAINING_PATTERN_DISABLE:
2415                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2416
2417                         break;
2418                 case DP_TRAINING_PATTERN_1:
2419                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2420                         break;
2421                 case DP_TRAINING_PATTERN_2:
2422                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2423                         break;
2424                 case DP_TRAINING_PATTERN_3:
2425                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2426                         break;
2427                 }
2428                 I915_WRITE(DP_TP_CTL(port), temp);
2429
2430         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2431                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2432                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2433
2434                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2435                 case DP_TRAINING_PATTERN_DISABLE:
2436                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2437                         break;
2438                 case DP_TRAINING_PATTERN_1:
2439                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2440                         break;
2441                 case DP_TRAINING_PATTERN_2:
2442                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2443                         break;
2444                 case DP_TRAINING_PATTERN_3:
2445                         DRM_ERROR("DP training pattern 3 not supported\n");
2446                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2447                         break;
2448                 }
2449
2450         } else {
2451                 if (IS_CHERRYVIEW(dev))
2452                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2453                 else
2454                         *DP &= ~DP_LINK_TRAIN_MASK;
2455
2456                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2457                 case DP_TRAINING_PATTERN_DISABLE:
2458                         *DP |= DP_LINK_TRAIN_OFF;
2459                         break;
2460                 case DP_TRAINING_PATTERN_1:
2461                         *DP |= DP_LINK_TRAIN_PAT_1;
2462                         break;
2463                 case DP_TRAINING_PATTERN_2:
2464                         *DP |= DP_LINK_TRAIN_PAT_2;
2465                         break;
2466                 case DP_TRAINING_PATTERN_3:
2467                         if (IS_CHERRYVIEW(dev)) {
2468                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2469                         } else {
2470                                 DRM_ERROR("DP training pattern 3 not supported\n");
2471                                 *DP |= DP_LINK_TRAIN_PAT_2;
2472                         }
2473                         break;
2474                 }
2475         }
2476 }
2477
2478 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2479 {
2480         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2481         struct drm_i915_private *dev_priv = dev->dev_private;
2482
2483         /* enable with pattern 1 (as per spec) */
2484         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2485                                  DP_TRAINING_PATTERN_1);
2486
2487         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2488         POSTING_READ(intel_dp->output_reg);
2489
2490         /*
2491          * Magic for VLV/CHV. We _must_ first set up the register
2492          * without actually enabling the port, and then do another
2493          * write to enable the port. Otherwise link training will
2494          * fail when the power sequencer is freshly used for this port.
2495          */
2496         intel_dp->DP |= DP_PORT_EN;
2497
2498         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2499         POSTING_READ(intel_dp->output_reg);
2500 }
2501
2502 static void intel_enable_dp(struct intel_encoder *encoder)
2503 {
2504         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2505         struct drm_device *dev = encoder->base.dev;
2506         struct drm_i915_private *dev_priv = dev->dev_private;
2507         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2508         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2509         unsigned int lane_mask = 0x0;
2510
2511         if (WARN_ON(dp_reg & DP_PORT_EN))
2512                 return;
2513
2514         pps_lock(intel_dp);
2515
2516         if (IS_VALLEYVIEW(dev))
2517                 vlv_init_panel_power_sequencer(intel_dp);
2518
2519         intel_dp_enable_port(intel_dp);
2520
2521         edp_panel_vdd_on(intel_dp);
2522         edp_panel_on(intel_dp);
2523         edp_panel_vdd_off(intel_dp, true);
2524
2525         pps_unlock(intel_dp);
2526
2527         if (IS_VALLEYVIEW(dev))
2528                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2529                                     lane_mask);
2530
2531         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2532         intel_dp_start_link_train(intel_dp);
2533         intel_dp_complete_link_train(intel_dp);
2534         intel_dp_stop_link_train(intel_dp);
2535
2536         if (crtc->config->has_audio) {
2537                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2538                                  pipe_name(crtc->pipe));
2539                 intel_audio_codec_enable(encoder);
2540         }
2541 }
2542
2543 static void g4x_enable_dp(struct intel_encoder *encoder)
2544 {
2545         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2546
2547         intel_enable_dp(encoder);
2548         intel_edp_backlight_on(intel_dp);
2549 }
2550
2551 static void vlv_enable_dp(struct intel_encoder *encoder)
2552 {
2553         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2554
2555         intel_edp_backlight_on(intel_dp);
2556         intel_psr_enable(intel_dp);
2557 }
2558
2559 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2560 {
2561         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2562         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2563
2564         intel_dp_prepare(encoder);
2565
2566         /* Only ilk+ has port A */
2567         if (dport->port == PORT_A) {
2568                 ironlake_set_pll_cpu_edp(intel_dp);
2569                 ironlake_edp_pll_on(intel_dp);
2570         }
2571 }
2572
2573 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2574 {
2575         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2576         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2577         enum pipe pipe = intel_dp->pps_pipe;
2578         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2579
2580         edp_panel_vdd_off_sync(intel_dp);
2581
2582         /*
2583          * VLV seems to get confused when multiple power seqeuencers
2584          * have the same port selected (even if only one has power/vdd
2585          * enabled). The failure manifests as vlv_wait_port_ready() failing
2586          * CHV on the other hand doesn't seem to mind having the same port
2587          * selected in multiple power seqeuencers, but let's clear the
2588          * port select always when logically disconnecting a power sequencer
2589          * from a port.
2590          */
2591         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2592                       pipe_name(pipe), port_name(intel_dig_port->port));
2593         I915_WRITE(pp_on_reg, 0);
2594         POSTING_READ(pp_on_reg);
2595
2596         intel_dp->pps_pipe = INVALID_PIPE;
2597 }
2598
2599 static void vlv_steal_power_sequencer(struct drm_device *dev,
2600                                       enum pipe pipe)
2601 {
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         struct intel_encoder *encoder;
2604
2605         lockdep_assert_held(&dev_priv->pps_mutex);
2606
2607         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2608                 return;
2609
2610         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2611                             base.head) {
2612                 struct intel_dp *intel_dp;
2613                 enum port port;
2614
2615                 if (encoder->type != INTEL_OUTPUT_EDP)
2616                         continue;
2617
2618                 intel_dp = enc_to_intel_dp(&encoder->base);
2619                 port = dp_to_dig_port(intel_dp)->port;
2620
2621                 if (intel_dp->pps_pipe != pipe)
2622                         continue;
2623
2624                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2625                               pipe_name(pipe), port_name(port));
2626
2627                 WARN(encoder->connectors_active,
2628                      "stealing pipe %c power sequencer from active eDP port %c\n",
2629                      pipe_name(pipe), port_name(port));
2630
2631                 /* make sure vdd is off before we steal it */
2632                 vlv_detach_power_sequencer(intel_dp);
2633         }
2634 }
2635
2636 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2637 {
2638         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2639         struct intel_encoder *encoder = &intel_dig_port->base;
2640         struct drm_device *dev = encoder->base.dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2643
2644         lockdep_assert_held(&dev_priv->pps_mutex);
2645
2646         if (!is_edp(intel_dp))
2647                 return;
2648
2649         if (intel_dp->pps_pipe == crtc->pipe)
2650                 return;
2651
2652         /*
2653          * If another power sequencer was being used on this
2654          * port previously make sure to turn off vdd there while
2655          * we still have control of it.
2656          */
2657         if (intel_dp->pps_pipe != INVALID_PIPE)
2658                 vlv_detach_power_sequencer(intel_dp);
2659
2660         /*
2661          * We may be stealing the power
2662          * sequencer from another port.
2663          */
2664         vlv_steal_power_sequencer(dev, crtc->pipe);
2665
2666         /* now it's all ours */
2667         intel_dp->pps_pipe = crtc->pipe;
2668
2669         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2670                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2671
2672         /* init power sequencer on this pipe and port */
2673         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2674         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2675 }
2676
2677 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2678 {
2679         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2681         struct drm_device *dev = encoder->base.dev;
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2684         enum dpio_channel port = vlv_dport_to_channel(dport);
2685         int pipe = intel_crtc->pipe;
2686         u32 val;
2687
2688         mutex_lock(&dev_priv->sb_lock);
2689
2690         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2691         val = 0;
2692         if (pipe)
2693                 val |= (1<<21);
2694         else
2695                 val &= ~(1<<21);
2696         val |= 0x001000c4;
2697         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2698         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2699         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2700
2701         mutex_unlock(&dev_priv->sb_lock);
2702
2703         intel_enable_dp(encoder);
2704 }
2705
2706 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2707 {
2708         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2709         struct drm_device *dev = encoder->base.dev;
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         struct intel_crtc *intel_crtc =
2712                 to_intel_crtc(encoder->base.crtc);
2713         enum dpio_channel port = vlv_dport_to_channel(dport);
2714         int pipe = intel_crtc->pipe;
2715
2716         intel_dp_prepare(encoder);
2717
2718         /* Program Tx lane resets to default */
2719         mutex_lock(&dev_priv->sb_lock);
2720         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2721                          DPIO_PCS_TX_LANE2_RESET |
2722                          DPIO_PCS_TX_LANE1_RESET);
2723         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2724                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2725                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2726                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2727                                  DPIO_PCS_CLK_SOFT_RESET);
2728
2729         /* Fix up inter-pair skew failure */
2730         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2731         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2732         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2733         mutex_unlock(&dev_priv->sb_lock);
2734 }
2735
2736 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2737 {
2738         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2739         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2740         struct drm_device *dev = encoder->base.dev;
2741         struct drm_i915_private *dev_priv = dev->dev_private;
2742         struct intel_crtc *intel_crtc =
2743                 to_intel_crtc(encoder->base.crtc);
2744         enum dpio_channel ch = vlv_dport_to_channel(dport);
2745         int pipe = intel_crtc->pipe;
2746         int data, i, stagger;
2747         u32 val;
2748
2749         mutex_lock(&dev_priv->sb_lock);
2750
2751         /* allow hardware to manage TX FIFO reset source */
2752         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2753         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2754         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2755
2756         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2757         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2758         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2759
2760         /* Deassert soft data lane reset*/
2761         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2762         val |= CHV_PCS_REQ_SOFTRESET_EN;
2763         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2764
2765         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2766         val |= CHV_PCS_REQ_SOFTRESET_EN;
2767         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2768
2769         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2770         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2771         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2772
2773         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2774         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2775         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2776
2777         /* Program Tx lane latency optimal setting*/
2778         for (i = 0; i < 4; i++) {
2779                 /* Set the upar bit */
2780                 data = (i == 1) ? 0x0 : 0x1;
2781                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2782                                 data << DPIO_UPAR_SHIFT);
2783         }
2784
2785         /* Data lane stagger programming */
2786         if (intel_crtc->config->port_clock > 270000)
2787                 stagger = 0x18;
2788         else if (intel_crtc->config->port_clock > 135000)
2789                 stagger = 0xd;
2790         else if (intel_crtc->config->port_clock > 67500)
2791                 stagger = 0x7;
2792         else if (intel_crtc->config->port_clock > 33750)
2793                 stagger = 0x4;
2794         else
2795                 stagger = 0x2;
2796
2797         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2798         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2799         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2800
2801         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2802         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2803         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2804
2805         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2806                        DPIO_LANESTAGGER_STRAP(stagger) |
2807                        DPIO_LANESTAGGER_STRAP_OVRD |
2808                        DPIO_TX1_STAGGER_MASK(0x1f) |
2809                        DPIO_TX1_STAGGER_MULT(6) |
2810                        DPIO_TX2_STAGGER_MULT(0));
2811
2812         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2813                        DPIO_LANESTAGGER_STRAP(stagger) |
2814                        DPIO_LANESTAGGER_STRAP_OVRD |
2815                        DPIO_TX1_STAGGER_MASK(0x1f) |
2816                        DPIO_TX1_STAGGER_MULT(7) |
2817                        DPIO_TX2_STAGGER_MULT(5));
2818
2819         mutex_unlock(&dev_priv->sb_lock);
2820
2821         intel_enable_dp(encoder);
2822 }
2823
2824 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2825 {
2826         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2827         struct drm_device *dev = encoder->base.dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc =
2830                 to_intel_crtc(encoder->base.crtc);
2831         enum dpio_channel ch = vlv_dport_to_channel(dport);
2832         enum pipe pipe = intel_crtc->pipe;
2833         u32 val;
2834
2835         intel_dp_prepare(encoder);
2836
2837         mutex_lock(&dev_priv->sb_lock);
2838
2839         /* program left/right clock distribution */
2840         if (pipe != PIPE_B) {
2841                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2842                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2843                 if (ch == DPIO_CH0)
2844                         val |= CHV_BUFLEFTENA1_FORCE;
2845                 if (ch == DPIO_CH1)
2846                         val |= CHV_BUFRIGHTENA1_FORCE;
2847                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2848         } else {
2849                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2850                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2851                 if (ch == DPIO_CH0)
2852                         val |= CHV_BUFLEFTENA2_FORCE;
2853                 if (ch == DPIO_CH1)
2854                         val |= CHV_BUFRIGHTENA2_FORCE;
2855                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2856         }
2857
2858         /* program clock channel usage */
2859         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2860         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2861         if (pipe != PIPE_B)
2862                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2863         else
2864                 val |= CHV_PCS_USEDCLKCHANNEL;
2865         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2866
2867         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2868         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2869         if (pipe != PIPE_B)
2870                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2871         else
2872                 val |= CHV_PCS_USEDCLKCHANNEL;
2873         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2874
2875         /*
2876          * This a a bit weird since generally CL
2877          * matches the pipe, but here we need to
2878          * pick the CL based on the port.
2879          */
2880         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2881         if (pipe != PIPE_B)
2882                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2883         else
2884                 val |= CHV_CMN_USEDCLKCHANNEL;
2885         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2886
2887         mutex_unlock(&dev_priv->sb_lock);
2888 }
2889
2890 /*
2891  * Native read with retry for link status and receiver capability reads for
2892  * cases where the sink may still be asleep.
2893  *
2894  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2895  * supposed to retry 3 times per the spec.
2896  */
2897 static ssize_t
2898 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2899                         void *buffer, size_t size)
2900 {
2901         ssize_t ret;
2902         int i;
2903
2904         /*
2905          * Sometime we just get the same incorrect byte repeated
2906          * over the entire buffer. Doing just one throw away read
2907          * initially seems to "solve" it.
2908          */
2909         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2910
2911         for (i = 0; i < 3; i++) {
2912                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2913                 if (ret == size)
2914                         return ret;
2915                 msleep(1);
2916         }
2917
2918         return ret;
2919 }
2920
2921 /*
2922  * Fetch AUX CH registers 0x202 - 0x207 which contain
2923  * link status information
2924  */
2925 static bool
2926 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2927 {
2928         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2929                                        DP_LANE0_1_STATUS,
2930                                        link_status,
2931                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2932 }
2933
2934 /* These are source-specific values. */
2935 static uint8_t
2936 intel_dp_voltage_max(struct intel_dp *intel_dp)
2937 {
2938         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2939         struct drm_i915_private *dev_priv = dev->dev_private;
2940         enum port port = dp_to_dig_port(intel_dp)->port;
2941
2942         if (IS_BROXTON(dev))
2943                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2944         else if (INTEL_INFO(dev)->gen >= 9) {
2945                 if (dev_priv->edp_low_vswing && port == PORT_A)
2946                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2947                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2948         } else if (IS_VALLEYVIEW(dev))
2949                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2950         else if (IS_GEN7(dev) && port == PORT_A)
2951                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2952         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2953                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2954         else
2955                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2956 }
2957
2958 static uint8_t
2959 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2960 {
2961         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2962         enum port port = dp_to_dig_port(intel_dp)->port;
2963
2964         if (INTEL_INFO(dev)->gen >= 9) {
2965                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2966                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2967                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2968                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2969                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2970                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2971                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2972                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2973                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2974                 default:
2975                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2976                 }
2977         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2978                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2979                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2980                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2981                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2982                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2983                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2984                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2985                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2986                 default:
2987                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2988                 }
2989         } else if (IS_VALLEYVIEW(dev)) {
2990                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2991                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2992                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2993                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2994                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2995                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2996                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2997                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2998                 default:
2999                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3000                 }
3001         } else if (IS_GEN7(dev) && port == PORT_A) {
3002                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3003                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3004                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3005                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3006                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3007                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3008                 default:
3009                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3010                 }
3011         } else {
3012                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3013                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3014                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3016                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3017                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3018                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3019                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3020                 default:
3021                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3022                 }
3023         }
3024 }
3025
3026 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3027 {
3028         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3031         struct intel_crtc *intel_crtc =
3032                 to_intel_crtc(dport->base.base.crtc);
3033         unsigned long demph_reg_value, preemph_reg_value,
3034                 uniqtranscale_reg_value;
3035         uint8_t train_set = intel_dp->train_set[0];
3036         enum dpio_channel port = vlv_dport_to_channel(dport);
3037         int pipe = intel_crtc->pipe;
3038
3039         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3040         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3041                 preemph_reg_value = 0x0004000;
3042                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3043                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044                         demph_reg_value = 0x2B405555;
3045                         uniqtranscale_reg_value = 0x552AB83A;
3046                         break;
3047                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3048                         demph_reg_value = 0x2B404040;
3049                         uniqtranscale_reg_value = 0x5548B83A;
3050                         break;
3051                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3052                         demph_reg_value = 0x2B245555;
3053                         uniqtranscale_reg_value = 0x5560B83A;
3054                         break;
3055                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3056                         demph_reg_value = 0x2B405555;
3057                         uniqtranscale_reg_value = 0x5598DA3A;
3058                         break;
3059                 default:
3060                         return 0;
3061                 }
3062                 break;
3063         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3064                 preemph_reg_value = 0x0002000;
3065                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3066                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3067                         demph_reg_value = 0x2B404040;
3068                         uniqtranscale_reg_value = 0x5552B83A;
3069                         break;
3070                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3071                         demph_reg_value = 0x2B404848;
3072                         uniqtranscale_reg_value = 0x5580B83A;
3073                         break;
3074                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3075                         demph_reg_value = 0x2B404040;
3076                         uniqtranscale_reg_value = 0x55ADDA3A;
3077                         break;
3078                 default:
3079                         return 0;
3080                 }
3081                 break;
3082         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3083                 preemph_reg_value = 0x0000000;
3084                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3085                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3086                         demph_reg_value = 0x2B305555;
3087                         uniqtranscale_reg_value = 0x5570B83A;
3088                         break;
3089                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3090                         demph_reg_value = 0x2B2B4040;
3091                         uniqtranscale_reg_value = 0x55ADDA3A;
3092                         break;
3093                 default:
3094                         return 0;
3095                 }
3096                 break;
3097         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3098                 preemph_reg_value = 0x0006000;
3099                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3100                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3101                         demph_reg_value = 0x1B405555;
3102                         uniqtranscale_reg_value = 0x55ADDA3A;
3103                         break;
3104                 default:
3105                         return 0;
3106                 }
3107                 break;
3108         default:
3109                 return 0;
3110         }
3111
3112         mutex_lock(&dev_priv->sb_lock);
3113         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3114         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3115         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3116                          uniqtranscale_reg_value);
3117         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3118         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3119         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3120         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3121         mutex_unlock(&dev_priv->sb_lock);
3122
3123         return 0;
3124 }
3125
3126 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3127 {
3128         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3129         struct drm_i915_private *dev_priv = dev->dev_private;
3130         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3131         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3132         u32 deemph_reg_value, margin_reg_value, val;
3133         uint8_t train_set = intel_dp->train_set[0];
3134         enum dpio_channel ch = vlv_dport_to_channel(dport);
3135         enum pipe pipe = intel_crtc->pipe;
3136         int i;
3137
3138         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3139         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3140                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3141                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3142                         deemph_reg_value = 128;
3143                         margin_reg_value = 52;
3144                         break;
3145                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146                         deemph_reg_value = 128;
3147                         margin_reg_value = 77;
3148                         break;
3149                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3150                         deemph_reg_value = 128;
3151                         margin_reg_value = 102;
3152                         break;
3153                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3154                         deemph_reg_value = 128;
3155                         margin_reg_value = 154;
3156                         /* FIXME extra to set for 1200 */
3157                         break;
3158                 default:
3159                         return 0;
3160                 }
3161                 break;
3162         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3163                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3164                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3165                         deemph_reg_value = 85;
3166                         margin_reg_value = 78;
3167                         break;
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3169                         deemph_reg_value = 85;
3170                         margin_reg_value = 116;
3171                         break;
3172                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3173                         deemph_reg_value = 85;
3174                         margin_reg_value = 154;
3175                         break;
3176                 default:
3177                         return 0;
3178                 }
3179                 break;
3180         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3181                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3183                         deemph_reg_value = 64;
3184                         margin_reg_value = 104;
3185                         break;
3186                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3187                         deemph_reg_value = 64;
3188                         margin_reg_value = 154;
3189                         break;
3190                 default:
3191                         return 0;
3192                 }
3193                 break;
3194         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3195                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3197                         deemph_reg_value = 43;
3198                         margin_reg_value = 154;
3199                         break;
3200                 default:
3201                         return 0;
3202                 }
3203                 break;
3204         default:
3205                 return 0;
3206         }
3207
3208         mutex_lock(&dev_priv->sb_lock);
3209
3210         /* Clear calc init */
3211         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3212         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3213         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3214         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3215         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3216
3217         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3218         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3219         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3220         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3221         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3222
3223         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3224         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3225         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3226         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3227
3228         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3229         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3230         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3231         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3232
3233         /* Program swing deemph */
3234         for (i = 0; i < 4; i++) {
3235                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3236                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3237                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3238                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3239         }
3240
3241         /* Program swing margin */
3242         for (i = 0; i < 4; i++) {
3243                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3244                 val &= ~DPIO_SWING_MARGIN000_MASK;
3245                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3246                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3247         }
3248
3249         /* Disable unique transition scale */
3250         for (i = 0; i < 4; i++) {
3251                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3252                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3253                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3254         }
3255
3256         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3257                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3258                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3259                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3260
3261                 /*
3262                  * The document said it needs to set bit 27 for ch0 and bit 26
3263                  * for ch1. Might be a typo in the doc.
3264                  * For now, for this unique transition scale selection, set bit
3265                  * 27 for ch0 and ch1.
3266                  */
3267                 for (i = 0; i < 4; i++) {
3268                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3269                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3270                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3271                 }
3272
3273                 for (i = 0; i < 4; i++) {
3274                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3275                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3276                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3277                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3278                 }
3279         }
3280
3281         /* Start swing calculation */
3282         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3283         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3284         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3285
3286         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3287         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3288         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3289
3290         /* LRC Bypass */
3291         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3292         val |= DPIO_LRC_BYPASS;
3293         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3294
3295         mutex_unlock(&dev_priv->sb_lock);
3296
3297         return 0;
3298 }
3299
3300 static void
3301 intel_get_adjust_train(struct intel_dp *intel_dp,
3302                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3303 {
3304         uint8_t v = 0;
3305         uint8_t p = 0;
3306         int lane;
3307         uint8_t voltage_max;
3308         uint8_t preemph_max;
3309
3310         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3311                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3312                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3313
3314                 if (this_v > v)
3315                         v = this_v;
3316                 if (this_p > p)
3317                         p = this_p;
3318         }
3319
3320         voltage_max = intel_dp_voltage_max(intel_dp);
3321         if (v >= voltage_max)
3322                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3323
3324         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3325         if (p >= preemph_max)
3326                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3327
3328         for (lane = 0; lane < 4; lane++)
3329                 intel_dp->train_set[lane] = v | p;
3330 }
3331
3332 static uint32_t
3333 gen4_signal_levels(uint8_t train_set)
3334 {
3335         uint32_t        signal_levels = 0;
3336
3337         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3338         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3339         default:
3340                 signal_levels |= DP_VOLTAGE_0_4;
3341                 break;
3342         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3343                 signal_levels |= DP_VOLTAGE_0_6;
3344                 break;
3345         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3346                 signal_levels |= DP_VOLTAGE_0_8;
3347                 break;
3348         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3349                 signal_levels |= DP_VOLTAGE_1_2;
3350                 break;
3351         }
3352         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3353         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3354         default:
3355                 signal_levels |= DP_PRE_EMPHASIS_0;
3356                 break;
3357         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3358                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3359                 break;
3360         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3361                 signal_levels |= DP_PRE_EMPHASIS_6;
3362                 break;
3363         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3364                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3365                 break;
3366         }
3367         return signal_levels;
3368 }
3369
3370 /* Gen6's DP voltage swing and pre-emphasis control */
3371 static uint32_t
3372 gen6_edp_signal_levels(uint8_t train_set)
3373 {
3374         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3375                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3376         switch (signal_levels) {
3377         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3378         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3379                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3380         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3381                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3382         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3383         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3384                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3385         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3386         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3387                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3388         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3390                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3391         default:
3392                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3393                               "0x%x\n", signal_levels);
3394                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3395         }
3396 }
3397
3398 /* Gen7's DP voltage swing and pre-emphasis control */
3399 static uint32_t
3400 gen7_edp_signal_levels(uint8_t train_set)
3401 {
3402         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3403                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3404         switch (signal_levels) {
3405         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3406                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3407         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3408                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3409         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3410                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3411
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3413                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3414         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3415                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3416
3417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3418                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3419         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3420                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3421
3422         default:
3423                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3424                               "0x%x\n", signal_levels);
3425                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3426         }
3427 }
3428
3429 /* Properly updates "DP" with the correct signal levels. */
3430 static void
3431 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3432 {
3433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3434         enum port port = intel_dig_port->port;
3435         struct drm_device *dev = intel_dig_port->base.base.dev;
3436         uint32_t signal_levels, mask = 0;
3437         uint8_t train_set = intel_dp->train_set[0];
3438
3439         if (HAS_DDI(dev)) {
3440                 signal_levels = ddi_signal_levels(intel_dp);
3441
3442                 if (IS_BROXTON(dev))
3443                         signal_levels = 0;
3444                 else
3445                         mask = DDI_BUF_EMP_MASK;
3446         } else if (IS_CHERRYVIEW(dev)) {
3447                 signal_levels = chv_signal_levels(intel_dp);
3448         } else if (IS_VALLEYVIEW(dev)) {
3449                 signal_levels = vlv_signal_levels(intel_dp);
3450         } else if (IS_GEN7(dev) && port == PORT_A) {
3451                 signal_levels = gen7_edp_signal_levels(train_set);
3452                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3453         } else if (IS_GEN6(dev) && port == PORT_A) {
3454                 signal_levels = gen6_edp_signal_levels(train_set);
3455                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3456         } else {
3457                 signal_levels = gen4_signal_levels(train_set);
3458                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3459         }
3460
3461         if (mask)
3462                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3463
3464         DRM_DEBUG_KMS("Using vswing level %d\n",
3465                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3466         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3467                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3468                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3469
3470         *DP = (*DP & ~mask) | signal_levels;
3471 }
3472
3473 static bool
3474 intel_dp_set_link_train(struct intel_dp *intel_dp,
3475                         uint32_t *DP,
3476                         uint8_t dp_train_pat)
3477 {
3478         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3479         struct drm_device *dev = intel_dig_port->base.base.dev;
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3482         int ret, len;
3483
3484         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3485
3486         I915_WRITE(intel_dp->output_reg, *DP);
3487         POSTING_READ(intel_dp->output_reg);
3488
3489         buf[0] = dp_train_pat;
3490         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3491             DP_TRAINING_PATTERN_DISABLE) {
3492                 /* don't write DP_TRAINING_LANEx_SET on disable */
3493                 len = 1;
3494         } else {
3495                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3496                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3497                 len = intel_dp->lane_count + 1;
3498         }
3499
3500         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3501                                 buf, len);
3502
3503         return ret == len;
3504 }
3505
3506 static bool
3507 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3508                         uint8_t dp_train_pat)
3509 {
3510         if (!intel_dp->train_set_valid)
3511                 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3512         intel_dp_set_signal_levels(intel_dp, DP);
3513         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3514 }
3515
3516 static bool
3517 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3518                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3519 {
3520         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3521         struct drm_device *dev = intel_dig_port->base.base.dev;
3522         struct drm_i915_private *dev_priv = dev->dev_private;
3523         int ret;
3524
3525         intel_get_adjust_train(intel_dp, link_status);
3526         intel_dp_set_signal_levels(intel_dp, DP);
3527
3528         I915_WRITE(intel_dp->output_reg, *DP);
3529         POSTING_READ(intel_dp->output_reg);
3530
3531         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3532                                 intel_dp->train_set, intel_dp->lane_count);
3533
3534         return ret == intel_dp->lane_count;
3535 }
3536
3537 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3538 {
3539         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3540         struct drm_device *dev = intel_dig_port->base.base.dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         enum port port = intel_dig_port->port;
3543         uint32_t val;
3544
3545         if (!HAS_DDI(dev))
3546                 return;
3547
3548         val = I915_READ(DP_TP_CTL(port));
3549         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3550         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3551         I915_WRITE(DP_TP_CTL(port), val);
3552
3553         /*
3554          * On PORT_A we can have only eDP in SST mode. There the only reason
3555          * we need to set idle transmission mode is to work around a HW issue
3556          * where we enable the pipe while not in idle link-training mode.
3557          * In this case there is requirement to wait for a minimum number of
3558          * idle patterns to be sent.
3559          */
3560         if (port == PORT_A)
3561                 return;
3562
3563         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3564                      1))
3565                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3566 }
3567
3568 /* Enable corresponding port and start training pattern 1 */
3569 void
3570 intel_dp_start_link_train(struct intel_dp *intel_dp)
3571 {
3572         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3573         struct drm_device *dev = encoder->dev;
3574         int i;
3575         uint8_t voltage;
3576         int voltage_tries, loop_tries;
3577         uint32_t DP = intel_dp->DP;
3578         uint8_t link_config[2];
3579
3580         if (HAS_DDI(dev))
3581                 intel_ddi_prepare_link_retrain(encoder);
3582
3583         /* Write the link configuration data */
3584         link_config[0] = intel_dp->link_bw;
3585         link_config[1] = intel_dp->lane_count;
3586         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3587                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3588         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3589         if (intel_dp->num_sink_rates)
3590                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3591                                 &intel_dp->rate_select, 1);
3592
3593         link_config[0] = 0;
3594         link_config[1] = DP_SET_ANSI_8B10B;
3595         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3596
3597         DP |= DP_PORT_EN;
3598
3599         /* clock recovery */
3600         if (!intel_dp_reset_link_train(intel_dp, &DP,
3601                                        DP_TRAINING_PATTERN_1 |
3602                                        DP_LINK_SCRAMBLING_DISABLE)) {
3603                 DRM_ERROR("failed to enable link training\n");
3604                 return;
3605         }
3606
3607         voltage = 0xff;
3608         voltage_tries = 0;
3609         loop_tries = 0;
3610         for (;;) {
3611                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3612
3613                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3614                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3615                         DRM_ERROR("failed to get link status\n");
3616                         break;
3617                 }
3618
3619                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3620                         DRM_DEBUG_KMS("clock recovery OK\n");
3621                         break;
3622                 }
3623
3624                 /*
3625                  * if we used previously trained voltage and pre-emphasis values
3626                  * and we don't get clock recovery, reset link training values
3627                  */
3628                 if (intel_dp->train_set_valid) {
3629                         DRM_DEBUG_KMS("clock recovery not ok, reset");
3630                         /* clear the flag as we are not reusing train set */
3631                         intel_dp->train_set_valid = false;
3632                         if (!intel_dp_reset_link_train(intel_dp, &DP,
3633                                                        DP_TRAINING_PATTERN_1 |
3634                                                        DP_LINK_SCRAMBLING_DISABLE)) {
3635                                 DRM_ERROR("failed to enable link training\n");
3636                                 return;
3637                         }
3638                         continue;
3639                 }
3640
3641                 /* Check to see if we've tried the max voltage */
3642                 for (i = 0; i < intel_dp->lane_count; i++)
3643                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3644                                 break;
3645                 if (i == intel_dp->lane_count) {
3646                         ++loop_tries;
3647                         if (loop_tries == 5) {
3648                                 DRM_ERROR("too many full retries, give up\n");
3649                                 break;
3650                         }
3651                         intel_dp_reset_link_train(intel_dp, &DP,
3652                                                   DP_TRAINING_PATTERN_1 |
3653                                                   DP_LINK_SCRAMBLING_DISABLE);
3654                         voltage_tries = 0;
3655                         continue;
3656                 }
3657
3658                 /* Check to see if we've tried the same voltage 5 times */
3659                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3660                         ++voltage_tries;
3661                         if (voltage_tries == 5) {
3662                                 DRM_ERROR("too many voltage retries, give up\n");
3663                                 break;
3664                         }
3665                 } else
3666                         voltage_tries = 0;
3667                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3668
3669                 /* Update training set as requested by target */
3670                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3671                         DRM_ERROR("failed to update link training\n");
3672                         break;
3673                 }
3674         }
3675
3676         intel_dp->DP = DP;
3677 }
3678
3679 void
3680 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3681 {
3682         bool channel_eq = false;
3683         int tries, cr_tries;
3684         uint32_t DP = intel_dp->DP;
3685         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3686
3687         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3688         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3689                 training_pattern = DP_TRAINING_PATTERN_3;
3690
3691         /* channel equalization */
3692         if (!intel_dp_set_link_train(intel_dp, &DP,
3693                                      training_pattern |
3694                                      DP_LINK_SCRAMBLING_DISABLE)) {
3695                 DRM_ERROR("failed to start channel equalization\n");
3696                 return;
3697         }
3698
3699         tries = 0;
3700         cr_tries = 0;
3701         channel_eq = false;
3702         for (;;) {
3703                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3704
3705                 if (cr_tries > 5) {
3706                         DRM_ERROR("failed to train DP, aborting\n");
3707                         break;
3708                 }
3709
3710                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3711                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3712                         DRM_ERROR("failed to get link status\n");
3713                         break;
3714                 }
3715
3716                 /* Make sure clock is still ok */
3717                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3718                         intel_dp->train_set_valid = false;
3719                         intel_dp_start_link_train(intel_dp);
3720                         intel_dp_set_link_train(intel_dp, &DP,
3721                                                 training_pattern |
3722                                                 DP_LINK_SCRAMBLING_DISABLE);
3723                         cr_tries++;
3724                         continue;
3725                 }
3726
3727                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3728                         channel_eq = true;
3729                         break;
3730                 }
3731
3732                 /* Try 5 times, then try clock recovery if that fails */
3733                 if (tries > 5) {
3734                         intel_dp->train_set_valid = false;
3735                         intel_dp_start_link_train(intel_dp);
3736                         intel_dp_set_link_train(intel_dp, &DP,
3737                                                 training_pattern |
3738                                                 DP_LINK_SCRAMBLING_DISABLE);
3739                         tries = 0;
3740                         cr_tries++;
3741                         continue;
3742                 }
3743
3744                 /* Update training set as requested by target */
3745                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3746                         DRM_ERROR("failed to update link training\n");
3747                         break;
3748                 }
3749                 ++tries;
3750         }
3751
3752         intel_dp_set_idle_link_train(intel_dp);
3753
3754         intel_dp->DP = DP;
3755
3756         if (channel_eq) {
3757                 intel_dp->train_set_valid = true;
3758                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3759         }
3760 }
3761
3762 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3763 {
3764         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3765                                 DP_TRAINING_PATTERN_DISABLE);
3766 }
3767
3768 static void
3769 intel_dp_link_down(struct intel_dp *intel_dp)
3770 {
3771         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3772         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3773         enum port port = intel_dig_port->port;
3774         struct drm_device *dev = intel_dig_port->base.base.dev;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         uint32_t DP = intel_dp->DP;
3777
3778         if (WARN_ON(HAS_DDI(dev)))
3779                 return;
3780
3781         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3782                 return;
3783
3784         DRM_DEBUG_KMS("\n");
3785
3786         if ((IS_GEN7(dev) && port == PORT_A) ||
3787             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3788                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3789                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3790         } else {
3791                 if (IS_CHERRYVIEW(dev))
3792                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3793                 else
3794                         DP &= ~DP_LINK_TRAIN_MASK;
3795                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3796         }
3797         I915_WRITE(intel_dp->output_reg, DP);
3798         POSTING_READ(intel_dp->output_reg);
3799
3800         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3801         I915_WRITE(intel_dp->output_reg, DP);
3802         POSTING_READ(intel_dp->output_reg);
3803
3804         /*
3805          * HW workaround for IBX, we need to move the port
3806          * to transcoder A after disabling it to allow the
3807          * matching HDMI port to be enabled on transcoder A.
3808          */
3809         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3810                 /* always enable with pattern 1 (as per spec) */
3811                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3812                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3813                 I915_WRITE(intel_dp->output_reg, DP);
3814                 POSTING_READ(intel_dp->output_reg);
3815
3816                 DP &= ~DP_PORT_EN;
3817                 I915_WRITE(intel_dp->output_reg, DP);
3818                 POSTING_READ(intel_dp->output_reg);
3819         }
3820
3821         msleep(intel_dp->panel_power_down_delay);
3822 }
3823
3824 static bool
3825 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3826 {
3827         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3828         struct drm_device *dev = dig_port->base.base.dev;
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         uint8_t rev;
3831
3832         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3833                                     sizeof(intel_dp->dpcd)) < 0)
3834                 return false; /* aux transfer failed */
3835
3836         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3837
3838         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3839                 return false; /* DPCD not present */
3840
3841         /* Check if the panel supports PSR */
3842         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3843         if (is_edp(intel_dp)) {
3844                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3845                                         intel_dp->psr_dpcd,
3846                                         sizeof(intel_dp->psr_dpcd));
3847                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3848                         dev_priv->psr.sink_support = true;
3849                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3850                 }
3851
3852                 if (INTEL_INFO(dev)->gen >= 9 &&
3853                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3854                         uint8_t frame_sync_cap;
3855
3856                         dev_priv->psr.sink_support = true;
3857                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3858                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3859                                         &frame_sync_cap, 1);
3860                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3861                         /* PSR2 needs frame sync as well */
3862                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3863                         DRM_DEBUG_KMS("PSR2 %s on sink",
3864                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3865                 }
3866         }
3867
3868         /* Training Pattern 3 support, both source and sink */
3869         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3870             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3871             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3872                 intel_dp->use_tps3 = true;
3873                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3874         } else
3875                 intel_dp->use_tps3 = false;
3876
3877         /* Intermediate frequency support */
3878         if (is_edp(intel_dp) &&
3879             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3880             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3881             (rev >= 0x03)) { /* eDp v1.4 or higher */
3882                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3883                 int i;
3884
3885                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3886                                 DP_SUPPORTED_LINK_RATES,
3887                                 sink_rates,
3888                                 sizeof(sink_rates));
3889
3890                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3891                         int val = le16_to_cpu(sink_rates[i]);
3892
3893                         if (val == 0)
3894                                 break;
3895
3896                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3897                         intel_dp->sink_rates[i] = (val * 200) / 10;
3898                 }
3899                 intel_dp->num_sink_rates = i;
3900         }
3901
3902         intel_dp_print_rates(intel_dp);
3903
3904         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3905               DP_DWN_STRM_PORT_PRESENT))
3906                 return true; /* native DP sink */
3907
3908         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3909                 return true; /* no per-port downstream info */
3910
3911         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3912                                     intel_dp->downstream_ports,
3913                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3914                 return false; /* downstream port status fetch failed */
3915
3916         return true;
3917 }
3918
3919 static void
3920 intel_dp_probe_oui(struct intel_dp *intel_dp)
3921 {
3922         u8 buf[3];
3923
3924         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3925                 return;
3926
3927         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3928                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3929                               buf[0], buf[1], buf[2]);
3930
3931         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3932                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3933                               buf[0], buf[1], buf[2]);
3934 }
3935
3936 static bool
3937 intel_dp_probe_mst(struct intel_dp *intel_dp)
3938 {
3939         u8 buf[1];
3940
3941         if (!intel_dp->can_mst)
3942                 return false;
3943
3944         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3945                 return false;
3946
3947         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3948                 if (buf[0] & DP_MST_CAP) {
3949                         DRM_DEBUG_KMS("Sink is MST capable\n");
3950                         intel_dp->is_mst = true;
3951                 } else {
3952                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3953                         intel_dp->is_mst = false;
3954                 }
3955         }
3956
3957         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3958         return intel_dp->is_mst;
3959 }
3960
3961 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3962 {
3963         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3964         struct drm_device *dev = intel_dig_port->base.base.dev;
3965         struct intel_crtc *intel_crtc =
3966                 to_intel_crtc(intel_dig_port->base.base.crtc);
3967         u8 buf;
3968         int test_crc_count;
3969         int attempts = 6;
3970         int ret = 0;
3971
3972         hsw_disable_ips(intel_crtc);
3973
3974         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
3975                 ret = -EIO;
3976                 goto out;
3977         }
3978
3979         if (!(buf & DP_TEST_CRC_SUPPORTED)) {
3980                 ret = -ENOTTY;
3981                 goto out;
3982         }
3983
3984         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3985                 ret = -EIO;
3986                 goto out;
3987         }
3988
3989         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3990                                 buf | DP_TEST_SINK_START) < 0) {
3991                 ret = -EIO;
3992                 goto out;
3993         }
3994
3995         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
3996                 ret = -EIO;
3997                 goto out;
3998         }
3999
4000         test_crc_count = buf & DP_TEST_COUNT_MASK;
4001
4002         do {
4003                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4004                                       DP_TEST_SINK_MISC, &buf) < 0) {
4005                         ret = -EIO;
4006                         goto out;
4007                 }
4008                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4009         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4010
4011         if (attempts == 0) {
4012                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4013                 ret = -ETIMEDOUT;
4014                 goto out;
4015         }
4016
4017         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4018                 ret = -EIO;
4019                 goto out;
4020         }
4021
4022         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4023                 ret = -EIO;
4024                 goto out;
4025         }
4026         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4027                                buf & ~DP_TEST_SINK_START) < 0) {
4028                 ret = -EIO;
4029                 goto out;
4030         }
4031 out:
4032         hsw_enable_ips(intel_crtc);
4033         return ret;
4034 }
4035
4036 static bool
4037 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4038 {
4039         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4040                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4041                                        sink_irq_vector, 1) == 1;
4042 }
4043
4044 static bool
4045 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4046 {
4047         int ret;
4048
4049         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4050                                              DP_SINK_COUNT_ESI,
4051                                              sink_irq_vector, 14);
4052         if (ret != 14)
4053                 return false;
4054
4055         return true;
4056 }
4057
4058 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4059 {
4060         uint8_t test_result = DP_TEST_ACK;
4061         return test_result;
4062 }
4063
4064 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4065 {
4066         uint8_t test_result = DP_TEST_NAK;
4067         return test_result;
4068 }
4069
4070 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4071 {
4072         uint8_t test_result = DP_TEST_NAK;
4073         struct intel_connector *intel_connector = intel_dp->attached_connector;
4074         struct drm_connector *connector = &intel_connector->base;
4075
4076         if (intel_connector->detect_edid == NULL ||
4077             connector->edid_corrupt ||
4078             intel_dp->aux.i2c_defer_count > 6) {
4079                 /* Check EDID read for NACKs, DEFERs and corruption
4080                  * (DP CTS 1.2 Core r1.1)
4081                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4082                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4083                  *    4.2.2.6 : EDID corruption detected
4084                  * Use failsafe mode for all cases
4085                  */
4086                 if (intel_dp->aux.i2c_nack_count > 0 ||
4087                         intel_dp->aux.i2c_defer_count > 0)
4088                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4089                                       intel_dp->aux.i2c_nack_count,
4090                                       intel_dp->aux.i2c_defer_count);
4091                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4092         } else {
4093                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4094                                         DP_TEST_EDID_CHECKSUM,
4095                                         &intel_connector->detect_edid->checksum,
4096                                         1))
4097                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4098
4099                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4100                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4101         }
4102
4103         /* Set test active flag here so userspace doesn't interrupt things */
4104         intel_dp->compliance_test_active = 1;
4105
4106         return test_result;
4107 }
4108
4109 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4110 {
4111         uint8_t test_result = DP_TEST_NAK;
4112         return test_result;
4113 }
4114
4115 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4116 {
4117         uint8_t response = DP_TEST_NAK;
4118         uint8_t rxdata = 0;
4119         int status = 0;
4120
4121         intel_dp->compliance_test_active = 0;
4122         intel_dp->compliance_test_type = 0;
4123         intel_dp->compliance_test_data = 0;
4124
4125         intel_dp->aux.i2c_nack_count = 0;
4126         intel_dp->aux.i2c_defer_count = 0;
4127
4128         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4129         if (status <= 0) {
4130                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4131                 goto update_status;
4132         }
4133
4134         switch (rxdata) {
4135         case DP_TEST_LINK_TRAINING:
4136                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4137                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4138                 response = intel_dp_autotest_link_training(intel_dp);
4139                 break;
4140         case DP_TEST_LINK_VIDEO_PATTERN:
4141                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4142                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4143                 response = intel_dp_autotest_video_pattern(intel_dp);
4144                 break;
4145         case DP_TEST_LINK_EDID_READ:
4146                 DRM_DEBUG_KMS("EDID test requested\n");
4147                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4148                 response = intel_dp_autotest_edid(intel_dp);
4149                 break;
4150         case DP_TEST_LINK_PHY_TEST_PATTERN:
4151                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4152                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4153                 response = intel_dp_autotest_phy_pattern(intel_dp);
4154                 break;
4155         default:
4156                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4157                 break;
4158         }
4159
4160 update_status:
4161         status = drm_dp_dpcd_write(&intel_dp->aux,
4162                                    DP_TEST_RESPONSE,
4163                                    &response, 1);
4164         if (status <= 0)
4165                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4166 }
4167
4168 static int
4169 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4170 {
4171         bool bret;
4172
4173         if (intel_dp->is_mst) {
4174                 u8 esi[16] = { 0 };
4175                 int ret = 0;
4176                 int retry;
4177                 bool handled;
4178                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4179 go_again:
4180                 if (bret == true) {
4181
4182                         /* check link status - esi[10] = 0x200c */
4183                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4184                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4185                                 intel_dp_start_link_train(intel_dp);
4186                                 intel_dp_complete_link_train(intel_dp);
4187                                 intel_dp_stop_link_train(intel_dp);
4188                         }
4189
4190                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4191                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4192
4193                         if (handled) {
4194                                 for (retry = 0; retry < 3; retry++) {
4195                                         int wret;
4196                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4197                                                                  DP_SINK_COUNT_ESI+1,
4198                                                                  &esi[1], 3);
4199                                         if (wret == 3) {
4200                                                 break;
4201                                         }
4202                                 }
4203
4204                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4205                                 if (bret == true) {
4206                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4207                                         goto go_again;
4208                                 }
4209                         } else
4210                                 ret = 0;
4211
4212                         return ret;
4213                 } else {
4214                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4215                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4216                         intel_dp->is_mst = false;
4217                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4218                         /* send a hotplug event */
4219                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4220                 }
4221         }
4222         return -EINVAL;
4223 }
4224
4225 /*
4226  * According to DP spec
4227  * 5.1.2:
4228  *  1. Read DPCD
4229  *  2. Configure link according to Receiver Capabilities
4230  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4231  *  4. Check link status on receipt of hot-plug interrupt
4232  */
4233 static void
4234 intel_dp_check_link_status(struct intel_dp *intel_dp)
4235 {
4236         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4237         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4238         u8 sink_irq_vector;
4239         u8 link_status[DP_LINK_STATUS_SIZE];
4240
4241         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4242
4243         if (!intel_encoder->connectors_active)
4244                 return;
4245
4246         if (WARN_ON(!intel_encoder->base.crtc))
4247                 return;
4248
4249         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4250                 return;
4251
4252         /* Try to read receiver status if the link appears to be up */
4253         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4254                 return;
4255         }
4256
4257         /* Now read the DPCD to see if it's actually running */
4258         if (!intel_dp_get_dpcd(intel_dp)) {
4259                 return;
4260         }
4261
4262         /* Try to read the source of the interrupt */
4263         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4264             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4265                 /* Clear interrupt source */
4266                 drm_dp_dpcd_writeb(&intel_dp->aux,
4267                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4268                                    sink_irq_vector);
4269
4270                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4271                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4272                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4273                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4274         }
4275
4276         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4277                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4278                               intel_encoder->base.name);
4279                 intel_dp_start_link_train(intel_dp);
4280                 intel_dp_complete_link_train(intel_dp);
4281                 intel_dp_stop_link_train(intel_dp);
4282         }
4283 }
4284
4285 /* XXX this is probably wrong for multiple downstream ports */
4286 static enum drm_connector_status
4287 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4288 {
4289         uint8_t *dpcd = intel_dp->dpcd;
4290         uint8_t type;
4291
4292         if (!intel_dp_get_dpcd(intel_dp))
4293                 return connector_status_disconnected;
4294
4295         /* if there's no downstream port, we're done */
4296         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4297                 return connector_status_connected;
4298
4299         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4300         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4301             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4302                 uint8_t reg;
4303
4304                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4305                                             &reg, 1) < 0)
4306                         return connector_status_unknown;
4307
4308                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4309                                               : connector_status_disconnected;
4310         }
4311
4312         /* If no HPD, poke DDC gently */
4313         if (drm_probe_ddc(&intel_dp->aux.ddc))
4314                 return connector_status_connected;
4315
4316         /* Well we tried, say unknown for unreliable port types */
4317         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4318                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4319                 if (type == DP_DS_PORT_TYPE_VGA ||
4320                     type == DP_DS_PORT_TYPE_NON_EDID)
4321                         return connector_status_unknown;
4322         } else {
4323                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4324                         DP_DWN_STRM_PORT_TYPE_MASK;
4325                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4326                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4327                         return connector_status_unknown;
4328         }
4329
4330         /* Anything else is out of spec, warn and ignore */
4331         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4332         return connector_status_disconnected;
4333 }
4334
4335 static enum drm_connector_status
4336 edp_detect(struct intel_dp *intel_dp)
4337 {
4338         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4339         enum drm_connector_status status;
4340
4341         status = intel_panel_detect(dev);
4342         if (status == connector_status_unknown)
4343                 status = connector_status_connected;
4344
4345         return status;
4346 }
4347
4348 static enum drm_connector_status
4349 ironlake_dp_detect(struct intel_dp *intel_dp)
4350 {
4351         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4354
4355         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4356                 return connector_status_disconnected;
4357
4358         return intel_dp_detect_dpcd(intel_dp);
4359 }
4360
4361 static int g4x_digital_port_connected(struct drm_device *dev,
4362                                        struct intel_digital_port *intel_dig_port)
4363 {
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         uint32_t bit;
4366
4367         if (IS_VALLEYVIEW(dev)) {
4368                 switch (intel_dig_port->port) {
4369                 case PORT_B:
4370                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4371                         break;
4372                 case PORT_C:
4373                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4374                         break;
4375                 case PORT_D:
4376                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4377                         break;
4378                 default:
4379                         return -EINVAL;
4380                 }
4381         } else {
4382                 switch (intel_dig_port->port) {
4383                 case PORT_B:
4384                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4385                         break;
4386                 case PORT_C:
4387                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4388                         break;
4389                 case PORT_D:
4390                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4391                         break;
4392                 default:
4393                         return -EINVAL;
4394                 }
4395         }
4396
4397         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4398                 return 0;
4399         return 1;
4400 }
4401
4402 static enum drm_connector_status
4403 g4x_dp_detect(struct intel_dp *intel_dp)
4404 {
4405         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4406         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4407         int ret;
4408
4409         /* Can't disconnect eDP, but you can close the lid... */
4410         if (is_edp(intel_dp)) {
4411                 enum drm_connector_status status;
4412
4413                 status = intel_panel_detect(dev);
4414                 if (status == connector_status_unknown)
4415                         status = connector_status_connected;
4416                 return status;
4417         }
4418
4419         ret = g4x_digital_port_connected(dev, intel_dig_port);
4420         if (ret == -EINVAL)
4421                 return connector_status_unknown;
4422         else if (ret == 0)
4423                 return connector_status_disconnected;
4424
4425         return intel_dp_detect_dpcd(intel_dp);
4426 }
4427
4428 static struct edid *
4429 intel_dp_get_edid(struct intel_dp *intel_dp)
4430 {
4431         struct intel_connector *intel_connector = intel_dp->attached_connector;
4432
4433         /* use cached edid if we have one */
4434         if (intel_connector->edid) {
4435                 /* invalid edid */
4436                 if (IS_ERR(intel_connector->edid))
4437                         return NULL;
4438
4439                 return drm_edid_duplicate(intel_connector->edid);
4440         } else
4441                 return drm_get_edid(&intel_connector->base,
4442                                     &intel_dp->aux.ddc);
4443 }
4444
4445 static void
4446 intel_dp_set_edid(struct intel_dp *intel_dp)
4447 {
4448         struct intel_connector *intel_connector = intel_dp->attached_connector;
4449         struct edid *edid;
4450
4451         edid = intel_dp_get_edid(intel_dp);
4452         intel_connector->detect_edid = edid;
4453
4454         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4455                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4456         else
4457                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4458 }
4459
4460 static void
4461 intel_dp_unset_edid(struct intel_dp *intel_dp)
4462 {
4463         struct intel_connector *intel_connector = intel_dp->attached_connector;
4464
4465         kfree(intel_connector->detect_edid);
4466         intel_connector->detect_edid = NULL;
4467
4468         intel_dp->has_audio = false;
4469 }
4470
4471 static enum intel_display_power_domain
4472 intel_dp_power_get(struct intel_dp *dp)
4473 {
4474         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4475         enum intel_display_power_domain power_domain;
4476
4477         power_domain = intel_display_port_power_domain(encoder);
4478         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4479
4480         return power_domain;
4481 }
4482
4483 static void
4484 intel_dp_power_put(struct intel_dp *dp,
4485                    enum intel_display_power_domain power_domain)
4486 {
4487         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4488         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4489 }
4490
4491 static enum drm_connector_status
4492 intel_dp_detect(struct drm_connector *connector, bool force)
4493 {
4494         struct intel_dp *intel_dp = intel_attached_dp(connector);
4495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4496         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4497         struct drm_device *dev = connector->dev;
4498         enum drm_connector_status status;
4499         enum intel_display_power_domain power_domain;
4500         bool ret;
4501         u8 sink_irq_vector;
4502
4503         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4504                       connector->base.id, connector->name);
4505         intel_dp_unset_edid(intel_dp);
4506
4507         if (intel_dp->is_mst) {
4508                 /* MST devices are disconnected from a monitor POV */
4509                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4510                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4511                 return connector_status_disconnected;
4512         }
4513
4514         power_domain = intel_dp_power_get(intel_dp);
4515
4516         /* Can't disconnect eDP, but you can close the lid... */
4517         if (is_edp(intel_dp))
4518                 status = edp_detect(intel_dp);
4519         else if (HAS_PCH_SPLIT(dev))
4520                 status = ironlake_dp_detect(intel_dp);
4521         else
4522                 status = g4x_dp_detect(intel_dp);
4523         if (status != connector_status_connected)
4524                 goto out;
4525
4526         intel_dp_probe_oui(intel_dp);
4527
4528         ret = intel_dp_probe_mst(intel_dp);
4529         if (ret) {
4530                 /* if we are in MST mode then this connector
4531                    won't appear connected or have anything with EDID on it */
4532                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4533                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4534                 status = connector_status_disconnected;
4535                 goto out;
4536         }
4537
4538         intel_dp_set_edid(intel_dp);
4539
4540         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4541                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4542         status = connector_status_connected;
4543
4544         /* Try to read the source of the interrupt */
4545         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4546             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4547                 /* Clear interrupt source */
4548                 drm_dp_dpcd_writeb(&intel_dp->aux,
4549                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4550                                    sink_irq_vector);
4551
4552                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4553                         intel_dp_handle_test_request(intel_dp);
4554                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4555                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4556         }
4557
4558 out:
4559         intel_dp_power_put(intel_dp, power_domain);
4560         return status;
4561 }
4562
4563 static void
4564 intel_dp_force(struct drm_connector *connector)
4565 {
4566         struct intel_dp *intel_dp = intel_attached_dp(connector);
4567         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4568         enum intel_display_power_domain power_domain;
4569
4570         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4571                       connector->base.id, connector->name);
4572         intel_dp_unset_edid(intel_dp);
4573
4574         if (connector->status != connector_status_connected)
4575                 return;
4576
4577         power_domain = intel_dp_power_get(intel_dp);
4578
4579         intel_dp_set_edid(intel_dp);
4580
4581         intel_dp_power_put(intel_dp, power_domain);
4582
4583         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4584                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4585 }
4586
4587 static int intel_dp_get_modes(struct drm_connector *connector)
4588 {
4589         struct intel_connector *intel_connector = to_intel_connector(connector);
4590         struct edid *edid;
4591
4592         edid = intel_connector->detect_edid;
4593         if (edid) {
4594                 int ret = intel_connector_update_modes(connector, edid);
4595                 if (ret)
4596                         return ret;
4597         }
4598
4599         /* if eDP has no EDID, fall back to fixed mode */
4600         if (is_edp(intel_attached_dp(connector)) &&
4601             intel_connector->panel.fixed_mode) {
4602                 struct drm_display_mode *mode;
4603
4604                 mode = drm_mode_duplicate(connector->dev,
4605                                           intel_connector->panel.fixed_mode);
4606                 if (mode) {
4607                         drm_mode_probed_add(connector, mode);
4608                         return 1;
4609                 }
4610         }
4611
4612         return 0;
4613 }
4614
4615 static bool
4616 intel_dp_detect_audio(struct drm_connector *connector)
4617 {
4618         bool has_audio = false;
4619         struct edid *edid;
4620
4621         edid = to_intel_connector(connector)->detect_edid;
4622         if (edid)
4623                 has_audio = drm_detect_monitor_audio(edid);
4624
4625         return has_audio;
4626 }
4627
4628 static int
4629 intel_dp_set_property(struct drm_connector *connector,
4630                       struct drm_property *property,
4631                       uint64_t val)
4632 {
4633         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4634         struct intel_connector *intel_connector = to_intel_connector(connector);
4635         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4636         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4637         int ret;
4638
4639         ret = drm_object_property_set_value(&connector->base, property, val);
4640         if (ret)
4641                 return ret;
4642
4643         if (property == dev_priv->force_audio_property) {
4644                 int i = val;
4645                 bool has_audio;
4646
4647                 if (i == intel_dp->force_audio)
4648                         return 0;
4649
4650                 intel_dp->force_audio = i;
4651
4652                 if (i == HDMI_AUDIO_AUTO)
4653                         has_audio = intel_dp_detect_audio(connector);
4654                 else
4655                         has_audio = (i == HDMI_AUDIO_ON);
4656
4657                 if (has_audio == intel_dp->has_audio)
4658                         return 0;
4659
4660                 intel_dp->has_audio = has_audio;
4661                 goto done;
4662         }
4663
4664         if (property == dev_priv->broadcast_rgb_property) {
4665                 bool old_auto = intel_dp->color_range_auto;
4666                 uint32_t old_range = intel_dp->color_range;
4667
4668                 switch (val) {
4669                 case INTEL_BROADCAST_RGB_AUTO:
4670                         intel_dp->color_range_auto = true;
4671                         break;
4672                 case INTEL_BROADCAST_RGB_FULL:
4673                         intel_dp->color_range_auto = false;
4674                         intel_dp->color_range = 0;
4675                         break;
4676                 case INTEL_BROADCAST_RGB_LIMITED:
4677                         intel_dp->color_range_auto = false;
4678                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4679                         break;
4680                 default:
4681                         return -EINVAL;
4682                 }
4683
4684                 if (old_auto == intel_dp->color_range_auto &&
4685                     old_range == intel_dp->color_range)
4686                         return 0;
4687
4688                 goto done;
4689         }
4690
4691         if (is_edp(intel_dp) &&
4692             property == connector->dev->mode_config.scaling_mode_property) {
4693                 if (val == DRM_MODE_SCALE_NONE) {
4694                         DRM_DEBUG_KMS("no scaling not supported\n");
4695                         return -EINVAL;
4696                 }
4697
4698                 if (intel_connector->panel.fitting_mode == val) {
4699                         /* the eDP scaling property is not changed */
4700                         return 0;
4701                 }
4702                 intel_connector->panel.fitting_mode = val;
4703
4704                 goto done;
4705         }
4706
4707         return -EINVAL;
4708
4709 done:
4710         if (intel_encoder->base.crtc)
4711                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4712
4713         return 0;
4714 }
4715
4716 static void
4717 intel_dp_connector_destroy(struct drm_connector *connector)
4718 {
4719         struct intel_connector *intel_connector = to_intel_connector(connector);
4720
4721         kfree(intel_connector->detect_edid);
4722
4723         if (!IS_ERR_OR_NULL(intel_connector->edid))
4724                 kfree(intel_connector->edid);
4725
4726         /* Can't call is_edp() since the encoder may have been destroyed
4727          * already. */
4728         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4729                 intel_panel_fini(&intel_connector->panel);
4730
4731         drm_connector_cleanup(connector);
4732         kfree(connector);
4733 }
4734
4735 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4736 {
4737         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4738         struct intel_dp *intel_dp = &intel_dig_port->dp;
4739
4740         drm_dp_aux_unregister(&intel_dp->aux);
4741         intel_dp_mst_encoder_cleanup(intel_dig_port);
4742         if (is_edp(intel_dp)) {
4743                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4744                 /*
4745                  * vdd might still be enabled do to the delayed vdd off.
4746                  * Make sure vdd is actually turned off here.
4747                  */
4748                 pps_lock(intel_dp);
4749                 edp_panel_vdd_off_sync(intel_dp);
4750                 pps_unlock(intel_dp);
4751
4752                 if (intel_dp->edp_notifier.notifier_call) {
4753                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4754                         intel_dp->edp_notifier.notifier_call = NULL;
4755                 }
4756         }
4757         drm_encoder_cleanup(encoder);
4758         kfree(intel_dig_port);
4759 }
4760
4761 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4762 {
4763         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4764
4765         if (!is_edp(intel_dp))
4766                 return;
4767
4768         /*
4769          * vdd might still be enabled do to the delayed vdd off.
4770          * Make sure vdd is actually turned off here.
4771          */
4772         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4773         pps_lock(intel_dp);
4774         edp_panel_vdd_off_sync(intel_dp);
4775         pps_unlock(intel_dp);
4776 }
4777
4778 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4779 {
4780         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4781         struct drm_device *dev = intel_dig_port->base.base.dev;
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783         enum intel_display_power_domain power_domain;
4784
4785         lockdep_assert_held(&dev_priv->pps_mutex);
4786
4787         if (!edp_have_panel_vdd(intel_dp))
4788                 return;
4789
4790         /*
4791          * The VDD bit needs a power domain reference, so if the bit is
4792          * already enabled when we boot or resume, grab this reference and
4793          * schedule a vdd off, so we don't hold on to the reference
4794          * indefinitely.
4795          */
4796         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4797         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4798         intel_display_power_get(dev_priv, power_domain);
4799
4800         edp_panel_vdd_schedule_off(intel_dp);
4801 }
4802
4803 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4804 {
4805         struct intel_dp *intel_dp;
4806
4807         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4808                 return;
4809
4810         intel_dp = enc_to_intel_dp(encoder);
4811
4812         pps_lock(intel_dp);
4813
4814         /*
4815          * Read out the current power sequencer assignment,
4816          * in case the BIOS did something with it.
4817          */
4818         if (IS_VALLEYVIEW(encoder->dev))
4819                 vlv_initial_power_sequencer_setup(intel_dp);
4820
4821         intel_edp_panel_vdd_sanitize(intel_dp);
4822
4823         pps_unlock(intel_dp);
4824 }
4825
4826 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4827         .dpms = intel_connector_dpms,
4828         .detect = intel_dp_detect,
4829         .force = intel_dp_force,
4830         .fill_modes = drm_helper_probe_single_connector_modes,
4831         .set_property = intel_dp_set_property,
4832         .atomic_get_property = intel_connector_atomic_get_property,
4833         .destroy = intel_dp_connector_destroy,
4834         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4835         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4836 };
4837
4838 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4839         .get_modes = intel_dp_get_modes,
4840         .mode_valid = intel_dp_mode_valid,
4841         .best_encoder = intel_best_encoder,
4842 };
4843
4844 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4845         .reset = intel_dp_encoder_reset,
4846         .destroy = intel_dp_encoder_destroy,
4847 };
4848
4849 enum irqreturn
4850 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4851 {
4852         struct intel_dp *intel_dp = &intel_dig_port->dp;
4853         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4854         struct drm_device *dev = intel_dig_port->base.base.dev;
4855         struct drm_i915_private *dev_priv = dev->dev_private;
4856         enum intel_display_power_domain power_domain;
4857         enum irqreturn ret = IRQ_NONE;
4858
4859         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4860                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4861
4862         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4863                 /*
4864                  * vdd off can generate a long pulse on eDP which
4865                  * would require vdd on to handle it, and thus we
4866                  * would end up in an endless cycle of
4867                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4868                  */
4869                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4870                               port_name(intel_dig_port->port));
4871                 return IRQ_HANDLED;
4872         }
4873
4874         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4875                       port_name(intel_dig_port->port),
4876                       long_hpd ? "long" : "short");
4877
4878         power_domain = intel_display_port_power_domain(intel_encoder);
4879         intel_display_power_get(dev_priv, power_domain);
4880
4881         if (long_hpd) {
4882                 /* indicate that we need to restart link training */
4883                 intel_dp->train_set_valid = false;
4884
4885                 if (HAS_PCH_SPLIT(dev)) {
4886                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4887                                 goto mst_fail;
4888                 } else {
4889                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4890                                 goto mst_fail;
4891                 }
4892
4893                 if (!intel_dp_get_dpcd(intel_dp)) {
4894                         goto mst_fail;
4895                 }
4896
4897                 intel_dp_probe_oui(intel_dp);
4898
4899                 if (!intel_dp_probe_mst(intel_dp))
4900                         goto mst_fail;
4901
4902         } else {
4903                 if (intel_dp->is_mst) {
4904                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4905                                 goto mst_fail;
4906                 }
4907
4908                 if (!intel_dp->is_mst) {
4909                         /*
4910                          * we'll check the link status via the normal hot plug path later -
4911                          * but for short hpds we should check it now
4912                          */
4913                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4914                         intel_dp_check_link_status(intel_dp);
4915                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4916                 }
4917         }
4918
4919         ret = IRQ_HANDLED;
4920
4921         goto put_power;
4922 mst_fail:
4923         /* if we were in MST mode, and device is not there get out of MST mode */
4924         if (intel_dp->is_mst) {
4925                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4926                 intel_dp->is_mst = false;
4927                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4928         }
4929 put_power:
4930         intel_display_power_put(dev_priv, power_domain);
4931
4932         return ret;
4933 }
4934
4935 /* Return which DP Port should be selected for Transcoder DP control */
4936 int
4937 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct intel_encoder *intel_encoder;
4941         struct intel_dp *intel_dp;
4942
4943         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4944                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4945
4946                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4947                     intel_encoder->type == INTEL_OUTPUT_EDP)
4948                         return intel_dp->output_reg;
4949         }
4950
4951         return -1;
4952 }
4953
4954 /* check the VBT to see whether the eDP is on DP-D port */
4955 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4956 {
4957         struct drm_i915_private *dev_priv = dev->dev_private;
4958         union child_device_config *p_child;
4959         int i;
4960         static const short port_mapping[] = {
4961                 [PORT_B] = PORT_IDPB,
4962                 [PORT_C] = PORT_IDPC,
4963                 [PORT_D] = PORT_IDPD,
4964         };
4965
4966         if (port == PORT_A)
4967                 return true;
4968
4969         if (!dev_priv->vbt.child_dev_num)
4970                 return false;
4971
4972         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4973                 p_child = dev_priv->vbt.child_dev + i;
4974
4975                 if (p_child->common.dvo_port == port_mapping[port] &&
4976                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4977                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4978                         return true;
4979         }
4980         return false;
4981 }
4982
4983 void
4984 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4985 {
4986         struct intel_connector *intel_connector = to_intel_connector(connector);
4987
4988         intel_attach_force_audio_property(connector);
4989         intel_attach_broadcast_rgb_property(connector);
4990         intel_dp->color_range_auto = true;
4991
4992         if (is_edp(intel_dp)) {
4993                 drm_mode_create_scaling_mode_property(connector->dev);
4994                 drm_object_attach_property(
4995                         &connector->base,
4996                         connector->dev->mode_config.scaling_mode_property,
4997                         DRM_MODE_SCALE_ASPECT);
4998                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4999         }
5000 }
5001
5002 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5003 {
5004         intel_dp->last_power_cycle = jiffies;
5005         intel_dp->last_power_on = jiffies;
5006         intel_dp->last_backlight_off = jiffies;
5007 }
5008
5009 static void
5010 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5011                                     struct intel_dp *intel_dp)
5012 {
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         struct edp_power_seq cur, vbt, spec,
5015                 *final = &intel_dp->pps_delays;
5016         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5017         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5018
5019         lockdep_assert_held(&dev_priv->pps_mutex);
5020
5021         /* already initialized? */
5022         if (final->t11_t12 != 0)
5023                 return;
5024
5025         if (IS_BROXTON(dev)) {
5026                 /*
5027                  * TODO: BXT has 2 sets of PPS registers.
5028                  * Correct Register for Broxton need to be identified
5029                  * using VBT. hardcoding for now
5030                  */
5031                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5032                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5033                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5034         } else if (HAS_PCH_SPLIT(dev)) {
5035                 pp_ctrl_reg = PCH_PP_CONTROL;
5036                 pp_on_reg = PCH_PP_ON_DELAYS;
5037                 pp_off_reg = PCH_PP_OFF_DELAYS;
5038                 pp_div_reg = PCH_PP_DIVISOR;
5039         } else {
5040                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5041
5042                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5043                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5044                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5045                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5046         }
5047
5048         /* Workaround: Need to write PP_CONTROL with the unlock key as
5049          * the very first thing. */
5050         pp_ctl = ironlake_get_pp_control(intel_dp);
5051
5052         pp_on = I915_READ(pp_on_reg);
5053         pp_off = I915_READ(pp_off_reg);
5054         if (!IS_BROXTON(dev)) {
5055                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5056                 pp_div = I915_READ(pp_div_reg);
5057         }
5058
5059         /* Pull timing values out of registers */
5060         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5061                 PANEL_POWER_UP_DELAY_SHIFT;
5062
5063         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5064                 PANEL_LIGHT_ON_DELAY_SHIFT;
5065
5066         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5067                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5068
5069         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5070                 PANEL_POWER_DOWN_DELAY_SHIFT;
5071
5072         if (IS_BROXTON(dev)) {
5073                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5074                         BXT_POWER_CYCLE_DELAY_SHIFT;
5075                 if (tmp > 0)
5076                         cur.t11_t12 = (tmp - 1) * 1000;
5077                 else
5078                         cur.t11_t12 = 0;
5079         } else {
5080                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5081                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5082         }
5083
5084         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5085                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5086
5087         vbt = dev_priv->vbt.edp_pps;
5088
5089         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5090          * our hw here, which are all in 100usec. */
5091         spec.t1_t3 = 210 * 10;
5092         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5093         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5094         spec.t10 = 500 * 10;
5095         /* This one is special and actually in units of 100ms, but zero
5096          * based in the hw (so we need to add 100 ms). But the sw vbt
5097          * table multiplies it with 1000 to make it in units of 100usec,
5098          * too. */
5099         spec.t11_t12 = (510 + 100) * 10;
5100
5101         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5102                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5103
5104         /* Use the max of the register settings and vbt. If both are
5105          * unset, fall back to the spec limits. */
5106 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5107                                        spec.field : \
5108                                        max(cur.field, vbt.field))
5109         assign_final(t1_t3);
5110         assign_final(t8);
5111         assign_final(t9);
5112         assign_final(t10);
5113         assign_final(t11_t12);
5114 #undef assign_final
5115
5116 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5117         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5118         intel_dp->backlight_on_delay = get_delay(t8);
5119         intel_dp->backlight_off_delay = get_delay(t9);
5120         intel_dp->panel_power_down_delay = get_delay(t10);
5121         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5122 #undef get_delay
5123
5124         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5125                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5126                       intel_dp->panel_power_cycle_delay);
5127
5128         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5129                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5130 }
5131
5132 static void
5133 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5134                                               struct intel_dp *intel_dp)
5135 {
5136         struct drm_i915_private *dev_priv = dev->dev_private;
5137         u32 pp_on, pp_off, pp_div, port_sel = 0;
5138         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5139         int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5140         enum port port = dp_to_dig_port(intel_dp)->port;
5141         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5142
5143         lockdep_assert_held(&dev_priv->pps_mutex);
5144
5145         if (IS_BROXTON(dev)) {
5146                 /*
5147                  * TODO: BXT has 2 sets of PPS registers.
5148                  * Correct Register for Broxton need to be identified
5149                  * using VBT. hardcoding for now
5150                  */
5151                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5152                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5153                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5154
5155         } else if (HAS_PCH_SPLIT(dev)) {
5156                 pp_on_reg = PCH_PP_ON_DELAYS;
5157                 pp_off_reg = PCH_PP_OFF_DELAYS;
5158                 pp_div_reg = PCH_PP_DIVISOR;
5159         } else {
5160                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5161
5162                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5163                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5164                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5165         }
5166
5167         /*
5168          * And finally store the new values in the power sequencer. The
5169          * backlight delays are set to 1 because we do manual waits on them. For
5170          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5171          * we'll end up waiting for the backlight off delay twice: once when we
5172          * do the manual sleep, and once when we disable the panel and wait for
5173          * the PP_STATUS bit to become zero.
5174          */
5175         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5176                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5177         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5178                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5179         /* Compute the divisor for the pp clock, simply match the Bspec
5180          * formula. */
5181         if (IS_BROXTON(dev)) {
5182                 pp_div = I915_READ(pp_ctrl_reg);
5183                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5184                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5185                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5186         } else {
5187                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5188                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5189                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5190         }
5191
5192         /* Haswell doesn't have any port selection bits for the panel
5193          * power sequencer any more. */
5194         if (IS_VALLEYVIEW(dev)) {
5195                 port_sel = PANEL_PORT_SELECT_VLV(port);
5196         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5197                 if (port == PORT_A)
5198                         port_sel = PANEL_PORT_SELECT_DPA;
5199                 else
5200                         port_sel = PANEL_PORT_SELECT_DPD;
5201         }
5202
5203         pp_on |= port_sel;
5204
5205         I915_WRITE(pp_on_reg, pp_on);
5206         I915_WRITE(pp_off_reg, pp_off);
5207         if (IS_BROXTON(dev))
5208                 I915_WRITE(pp_ctrl_reg, pp_div);
5209         else
5210                 I915_WRITE(pp_div_reg, pp_div);
5211
5212         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5213                       I915_READ(pp_on_reg),
5214                       I915_READ(pp_off_reg),
5215                       IS_BROXTON(dev) ?
5216                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5217                       I915_READ(pp_div_reg));
5218 }
5219
5220 /**
5221  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5222  * @dev: DRM device
5223  * @refresh_rate: RR to be programmed
5224  *
5225  * This function gets called when refresh rate (RR) has to be changed from
5226  * one frequency to another. Switches can be between high and low RR
5227  * supported by the panel or to any other RR based on media playback (in
5228  * this case, RR value needs to be passed from user space).
5229  *
5230  * The caller of this function needs to take a lock on dev_priv->drrs.
5231  */
5232 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5233 {
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         struct intel_encoder *encoder;
5236         struct intel_digital_port *dig_port = NULL;
5237         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5238         struct intel_crtc_state *config = NULL;
5239         struct intel_crtc *intel_crtc = NULL;
5240         u32 reg, val;
5241         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5242
5243         if (refresh_rate <= 0) {
5244                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5245                 return;
5246         }
5247
5248         if (intel_dp == NULL) {
5249                 DRM_DEBUG_KMS("DRRS not supported.\n");
5250                 return;
5251         }
5252
5253         /*
5254          * FIXME: This needs proper synchronization with psr state for some
5255          * platforms that cannot have PSR and DRRS enabled at the same time.
5256          */
5257
5258         dig_port = dp_to_dig_port(intel_dp);
5259         encoder = &dig_port->base;
5260         intel_crtc = to_intel_crtc(encoder->base.crtc);
5261
5262         if (!intel_crtc) {
5263                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5264                 return;
5265         }
5266
5267         config = intel_crtc->config;
5268
5269         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5270                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5271                 return;
5272         }
5273
5274         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5275                         refresh_rate)
5276                 index = DRRS_LOW_RR;
5277
5278         if (index == dev_priv->drrs.refresh_rate_type) {
5279                 DRM_DEBUG_KMS(
5280                         "DRRS requested for previously set RR...ignoring\n");
5281                 return;
5282         }
5283
5284         if (!intel_crtc->active) {
5285                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5286                 return;
5287         }
5288
5289         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5290                 switch (index) {
5291                 case DRRS_HIGH_RR:
5292                         intel_dp_set_m_n(intel_crtc, M1_N1);
5293                         break;
5294                 case DRRS_LOW_RR:
5295                         intel_dp_set_m_n(intel_crtc, M2_N2);
5296                         break;
5297                 case DRRS_MAX_RR:
5298                 default:
5299                         DRM_ERROR("Unsupported refreshrate type\n");
5300                 }
5301         } else if (INTEL_INFO(dev)->gen > 6) {
5302                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5303                 val = I915_READ(reg);
5304
5305                 if (index > DRRS_HIGH_RR) {
5306                         if (IS_VALLEYVIEW(dev))
5307                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5308                         else
5309                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5310                 } else {
5311                         if (IS_VALLEYVIEW(dev))
5312                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5313                         else
5314                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5315                 }
5316                 I915_WRITE(reg, val);
5317         }
5318
5319         dev_priv->drrs.refresh_rate_type = index;
5320
5321         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5322 }
5323
5324 /**
5325  * intel_edp_drrs_enable - init drrs struct if supported
5326  * @intel_dp: DP struct
5327  *
5328  * Initializes frontbuffer_bits and drrs.dp
5329  */
5330 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5331 {
5332         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5333         struct drm_i915_private *dev_priv = dev->dev_private;
5334         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5335         struct drm_crtc *crtc = dig_port->base.base.crtc;
5336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5337
5338         if (!intel_crtc->config->has_drrs) {
5339                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5340                 return;
5341         }
5342
5343         mutex_lock(&dev_priv->drrs.mutex);
5344         if (WARN_ON(dev_priv->drrs.dp)) {
5345                 DRM_ERROR("DRRS already enabled\n");
5346                 goto unlock;
5347         }
5348
5349         dev_priv->drrs.busy_frontbuffer_bits = 0;
5350
5351         dev_priv->drrs.dp = intel_dp;
5352
5353 unlock:
5354         mutex_unlock(&dev_priv->drrs.mutex);
5355 }
5356
5357 /**
5358  * intel_edp_drrs_disable - Disable DRRS
5359  * @intel_dp: DP struct
5360  *
5361  */
5362 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5363 {
5364         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5365         struct drm_i915_private *dev_priv = dev->dev_private;
5366         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5367         struct drm_crtc *crtc = dig_port->base.base.crtc;
5368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369
5370         if (!intel_crtc->config->has_drrs)
5371                 return;
5372
5373         mutex_lock(&dev_priv->drrs.mutex);
5374         if (!dev_priv->drrs.dp) {
5375                 mutex_unlock(&dev_priv->drrs.mutex);
5376                 return;
5377         }
5378
5379         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5380                 intel_dp_set_drrs_state(dev_priv->dev,
5381                         intel_dp->attached_connector->panel.
5382                         fixed_mode->vrefresh);
5383
5384         dev_priv->drrs.dp = NULL;
5385         mutex_unlock(&dev_priv->drrs.mutex);
5386
5387         cancel_delayed_work_sync(&dev_priv->drrs.work);
5388 }
5389
5390 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5391 {
5392         struct drm_i915_private *dev_priv =
5393                 container_of(work, typeof(*dev_priv), drrs.work.work);
5394         struct intel_dp *intel_dp;
5395
5396         mutex_lock(&dev_priv->drrs.mutex);
5397
5398         intel_dp = dev_priv->drrs.dp;
5399
5400         if (!intel_dp)
5401                 goto unlock;
5402
5403         /*
5404          * The delayed work can race with an invalidate hence we need to
5405          * recheck.
5406          */
5407
5408         if (dev_priv->drrs.busy_frontbuffer_bits)
5409                 goto unlock;
5410
5411         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5412                 intel_dp_set_drrs_state(dev_priv->dev,
5413                         intel_dp->attached_connector->panel.
5414                         downclock_mode->vrefresh);
5415
5416 unlock:
5417         mutex_unlock(&dev_priv->drrs.mutex);
5418 }
5419
5420 /**
5421  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5422  * @dev: DRM device
5423  * @frontbuffer_bits: frontbuffer plane tracking bits
5424  *
5425  * This function gets called everytime rendering on the given planes start.
5426  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5427  *
5428  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5429  */
5430 void intel_edp_drrs_invalidate(struct drm_device *dev,
5431                 unsigned frontbuffer_bits)
5432 {
5433         struct drm_i915_private *dev_priv = dev->dev_private;
5434         struct drm_crtc *crtc;
5435         enum pipe pipe;
5436
5437         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5438                 return;
5439
5440         cancel_delayed_work(&dev_priv->drrs.work);
5441
5442         mutex_lock(&dev_priv->drrs.mutex);
5443         if (!dev_priv->drrs.dp) {
5444                 mutex_unlock(&dev_priv->drrs.mutex);
5445                 return;
5446         }
5447
5448         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5449         pipe = to_intel_crtc(crtc)->pipe;
5450
5451         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5452         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5453
5454         /* invalidate means busy screen hence upclock */
5455         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5456                 intel_dp_set_drrs_state(dev_priv->dev,
5457                                 dev_priv->drrs.dp->attached_connector->panel.
5458                                 fixed_mode->vrefresh);
5459
5460         mutex_unlock(&dev_priv->drrs.mutex);
5461 }
5462
5463 /**
5464  * intel_edp_drrs_flush - Restart Idleness DRRS
5465  * @dev: DRM device
5466  * @frontbuffer_bits: frontbuffer plane tracking bits
5467  *
5468  * This function gets called every time rendering on the given planes has
5469  * completed or flip on a crtc is completed. So DRRS should be upclocked
5470  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5471  * if no other planes are dirty.
5472  *
5473  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5474  */
5475 void intel_edp_drrs_flush(struct drm_device *dev,
5476                 unsigned frontbuffer_bits)
5477 {
5478         struct drm_i915_private *dev_priv = dev->dev_private;
5479         struct drm_crtc *crtc;
5480         enum pipe pipe;
5481
5482         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5483                 return;
5484
5485         cancel_delayed_work(&dev_priv->drrs.work);
5486
5487         mutex_lock(&dev_priv->drrs.mutex);
5488         if (!dev_priv->drrs.dp) {
5489                 mutex_unlock(&dev_priv->drrs.mutex);
5490                 return;
5491         }
5492
5493         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5494         pipe = to_intel_crtc(crtc)->pipe;
5495
5496         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5497         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5498
5499         /* flush means busy screen hence upclock */
5500         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5501                 intel_dp_set_drrs_state(dev_priv->dev,
5502                                 dev_priv->drrs.dp->attached_connector->panel.
5503                                 fixed_mode->vrefresh);
5504
5505         /*
5506          * flush also means no more activity hence schedule downclock, if all
5507          * other fbs are quiescent too
5508          */
5509         if (!dev_priv->drrs.busy_frontbuffer_bits)
5510                 schedule_delayed_work(&dev_priv->drrs.work,
5511                                 msecs_to_jiffies(1000));
5512         mutex_unlock(&dev_priv->drrs.mutex);
5513 }
5514
5515 /**
5516  * DOC: Display Refresh Rate Switching (DRRS)
5517  *
5518  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5519  * which enables swtching between low and high refresh rates,
5520  * dynamically, based on the usage scenario. This feature is applicable
5521  * for internal panels.
5522  *
5523  * Indication that the panel supports DRRS is given by the panel EDID, which
5524  * would list multiple refresh rates for one resolution.
5525  *
5526  * DRRS is of 2 types - static and seamless.
5527  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5528  * (may appear as a blink on screen) and is used in dock-undock scenario.
5529  * Seamless DRRS involves changing RR without any visual effect to the user
5530  * and can be used during normal system usage. This is done by programming
5531  * certain registers.
5532  *
5533  * Support for static/seamless DRRS may be indicated in the VBT based on
5534  * inputs from the panel spec.
5535  *
5536  * DRRS saves power by switching to low RR based on usage scenarios.
5537  *
5538  * eDP DRRS:-
5539  *        The implementation is based on frontbuffer tracking implementation.
5540  * When there is a disturbance on the screen triggered by user activity or a
5541  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5542  * When there is no movement on screen, after a timeout of 1 second, a switch
5543  * to low RR is made.
5544  *        For integration with frontbuffer tracking code,
5545  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5546  *
5547  * DRRS can be further extended to support other internal panels and also
5548  * the scenario of video playback wherein RR is set based on the rate
5549  * requested by userspace.
5550  */
5551
5552 /**
5553  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5554  * @intel_connector: eDP connector
5555  * @fixed_mode: preferred mode of panel
5556  *
5557  * This function is  called only once at driver load to initialize basic
5558  * DRRS stuff.
5559  *
5560  * Returns:
5561  * Downclock mode if panel supports it, else return NULL.
5562  * DRRS support is determined by the presence of downclock mode (apart
5563  * from VBT setting).
5564  */
5565 static struct drm_display_mode *
5566 intel_dp_drrs_init(struct intel_connector *intel_connector,
5567                 struct drm_display_mode *fixed_mode)
5568 {
5569         struct drm_connector *connector = &intel_connector->base;
5570         struct drm_device *dev = connector->dev;
5571         struct drm_i915_private *dev_priv = dev->dev_private;
5572         struct drm_display_mode *downclock_mode = NULL;
5573
5574         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5575         mutex_init(&dev_priv->drrs.mutex);
5576
5577         if (INTEL_INFO(dev)->gen <= 6) {
5578                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5579                 return NULL;
5580         }
5581
5582         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5583                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5584                 return NULL;
5585         }
5586
5587         downclock_mode = intel_find_panel_downclock
5588                                         (dev, fixed_mode, connector);
5589
5590         if (!downclock_mode) {
5591                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5592                 return NULL;
5593         }
5594
5595         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5596
5597         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5598         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5599         return downclock_mode;
5600 }
5601
5602 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5603                                      struct intel_connector *intel_connector)
5604 {
5605         struct drm_connector *connector = &intel_connector->base;
5606         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5607         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5608         struct drm_device *dev = intel_encoder->base.dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         struct drm_display_mode *fixed_mode = NULL;
5611         struct drm_display_mode *downclock_mode = NULL;
5612         bool has_dpcd;
5613         struct drm_display_mode *scan;
5614         struct edid *edid;
5615         enum pipe pipe = INVALID_PIPE;
5616
5617         if (!is_edp(intel_dp))
5618                 return true;
5619
5620         pps_lock(intel_dp);
5621         intel_edp_panel_vdd_sanitize(intel_dp);
5622         pps_unlock(intel_dp);
5623
5624         /* Cache DPCD and EDID for edp. */
5625         has_dpcd = intel_dp_get_dpcd(intel_dp);
5626
5627         if (has_dpcd) {
5628                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5629                         dev_priv->no_aux_handshake =
5630                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5631                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5632         } else {
5633                 /* if this fails, presume the device is a ghost */
5634                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5635                 return false;
5636         }
5637
5638         /* We now know it's not a ghost, init power sequence regs. */
5639         pps_lock(intel_dp);
5640         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5641         pps_unlock(intel_dp);
5642
5643         mutex_lock(&dev->mode_config.mutex);
5644         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5645         if (edid) {
5646                 if (drm_add_edid_modes(connector, edid)) {
5647                         drm_mode_connector_update_edid_property(connector,
5648                                                                 edid);
5649                         drm_edid_to_eld(connector, edid);
5650                 } else {
5651                         kfree(edid);
5652                         edid = ERR_PTR(-EINVAL);
5653                 }
5654         } else {
5655                 edid = ERR_PTR(-ENOENT);
5656         }
5657         intel_connector->edid = edid;
5658
5659         /* prefer fixed mode from EDID if available */
5660         list_for_each_entry(scan, &connector->probed_modes, head) {
5661                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5662                         fixed_mode = drm_mode_duplicate(dev, scan);
5663                         downclock_mode = intel_dp_drrs_init(
5664                                                 intel_connector, fixed_mode);
5665                         break;
5666                 }
5667         }
5668
5669         /* fallback to VBT if available for eDP */
5670         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5671                 fixed_mode = drm_mode_duplicate(dev,
5672                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5673                 if (fixed_mode)
5674                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5675         }
5676         mutex_unlock(&dev->mode_config.mutex);
5677
5678         if (IS_VALLEYVIEW(dev)) {
5679                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5680                 register_reboot_notifier(&intel_dp->edp_notifier);
5681
5682                 /*
5683                  * Figure out the current pipe for the initial backlight setup.
5684                  * If the current pipe isn't valid, try the PPS pipe, and if that
5685                  * fails just assume pipe A.
5686                  */
5687                 if (IS_CHERRYVIEW(dev))
5688                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5689                 else
5690                         pipe = PORT_TO_PIPE(intel_dp->DP);
5691
5692                 if (pipe != PIPE_A && pipe != PIPE_B)
5693                         pipe = intel_dp->pps_pipe;
5694
5695                 if (pipe != PIPE_A && pipe != PIPE_B)
5696                         pipe = PIPE_A;
5697
5698                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5699                               pipe_name(pipe));
5700         }
5701
5702         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5703         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5704         intel_panel_setup_backlight(connector, pipe);
5705
5706         return true;
5707 }
5708
5709 bool
5710 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5711                         struct intel_connector *intel_connector)
5712 {
5713         struct drm_connector *connector = &intel_connector->base;
5714         struct intel_dp *intel_dp = &intel_dig_port->dp;
5715         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5716         struct drm_device *dev = intel_encoder->base.dev;
5717         struct drm_i915_private *dev_priv = dev->dev_private;
5718         enum port port = intel_dig_port->port;
5719         int type;
5720
5721         intel_dp->pps_pipe = INVALID_PIPE;
5722
5723         /* intel_dp vfuncs */
5724         if (INTEL_INFO(dev)->gen >= 9)
5725                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5726         else if (IS_VALLEYVIEW(dev))
5727                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5728         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5729                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5730         else if (HAS_PCH_SPLIT(dev))
5731                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5732         else
5733                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5734
5735         if (INTEL_INFO(dev)->gen >= 9)
5736                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5737         else
5738                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5739
5740         /* Preserve the current hw state. */
5741         intel_dp->DP = I915_READ(intel_dp->output_reg);
5742         intel_dp->attached_connector = intel_connector;
5743
5744         if (intel_dp_is_edp(dev, port))
5745                 type = DRM_MODE_CONNECTOR_eDP;
5746         else
5747                 type = DRM_MODE_CONNECTOR_DisplayPort;
5748
5749         /*
5750          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5751          * for DP the encoder type can be set by the caller to
5752          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5753          */
5754         if (type == DRM_MODE_CONNECTOR_eDP)
5755                 intel_encoder->type = INTEL_OUTPUT_EDP;
5756
5757         /* eDP only on port B and/or C on vlv/chv */
5758         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5759                     port != PORT_B && port != PORT_C))
5760                 return false;
5761
5762         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5763                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5764                         port_name(port));
5765
5766         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5767         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5768
5769         connector->interlace_allowed = true;
5770         connector->doublescan_allowed = 0;
5771
5772         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5773                           edp_panel_vdd_work);
5774
5775         intel_connector_attach_encoder(intel_connector, intel_encoder);
5776         drm_connector_register(connector);
5777
5778         if (HAS_DDI(dev))
5779                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5780         else
5781                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5782         intel_connector->unregister = intel_dp_connector_unregister;
5783
5784         /* Set up the hotplug pin. */
5785         switch (port) {
5786         case PORT_A:
5787                 intel_encoder->hpd_pin = HPD_PORT_A;
5788                 break;
5789         case PORT_B:
5790                 intel_encoder->hpd_pin = HPD_PORT_B;
5791                 break;
5792         case PORT_C:
5793                 intel_encoder->hpd_pin = HPD_PORT_C;
5794                 break;
5795         case PORT_D:
5796                 intel_encoder->hpd_pin = HPD_PORT_D;
5797                 break;
5798         default:
5799                 BUG();
5800         }
5801
5802         if (is_edp(intel_dp)) {
5803                 pps_lock(intel_dp);
5804                 intel_dp_init_panel_power_timestamps(intel_dp);
5805                 if (IS_VALLEYVIEW(dev))
5806                         vlv_initial_power_sequencer_setup(intel_dp);
5807                 else
5808                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5809                 pps_unlock(intel_dp);
5810         }
5811
5812         intel_dp_aux_init(intel_dp, intel_connector);
5813
5814         /* init MST on ports that can support it */
5815         if (HAS_DP_MST(dev) &&
5816             (port == PORT_B || port == PORT_C || port == PORT_D))
5817                 intel_dp_mst_encoder_init(intel_dig_port,
5818                                           intel_connector->base.base.id);
5819
5820         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5821                 drm_dp_aux_unregister(&intel_dp->aux);
5822                 if (is_edp(intel_dp)) {
5823                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5824                         /*
5825                          * vdd might still be enabled do to the delayed vdd off.
5826                          * Make sure vdd is actually turned off here.
5827                          */
5828                         pps_lock(intel_dp);
5829                         edp_panel_vdd_off_sync(intel_dp);
5830                         pps_unlock(intel_dp);
5831                 }
5832                 drm_connector_unregister(connector);
5833                 drm_connector_cleanup(connector);
5834                 return false;
5835         }
5836
5837         intel_dp_add_properties(intel_dp, connector);
5838
5839         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5840          * 0xd.  Failure to do so will result in spurious interrupts being
5841          * generated on the port when a cable is not attached.
5842          */
5843         if (IS_G4X(dev) && !IS_GM45(dev)) {
5844                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5845                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5846         }
5847
5848         i915_debugfs_connector_add(connector);
5849
5850         return true;
5851 }
5852
5853 void
5854 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5855 {
5856         struct drm_i915_private *dev_priv = dev->dev_private;
5857         struct intel_digital_port *intel_dig_port;
5858         struct intel_encoder *intel_encoder;
5859         struct drm_encoder *encoder;
5860         struct intel_connector *intel_connector;
5861
5862         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5863         if (!intel_dig_port)
5864                 return;
5865
5866         intel_connector = intel_connector_alloc();
5867         if (!intel_connector) {
5868                 kfree(intel_dig_port);
5869                 return;
5870         }
5871
5872         intel_encoder = &intel_dig_port->base;
5873         encoder = &intel_encoder->base;
5874
5875         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5876                          DRM_MODE_ENCODER_TMDS);
5877
5878         intel_encoder->compute_config = intel_dp_compute_config;
5879         intel_encoder->disable = intel_disable_dp;
5880         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5881         intel_encoder->get_config = intel_dp_get_config;
5882         intel_encoder->suspend = intel_dp_encoder_suspend;
5883         if (IS_CHERRYVIEW(dev)) {
5884                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5885                 intel_encoder->pre_enable = chv_pre_enable_dp;
5886                 intel_encoder->enable = vlv_enable_dp;
5887                 intel_encoder->post_disable = chv_post_disable_dp;
5888         } else if (IS_VALLEYVIEW(dev)) {
5889                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5890                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5891                 intel_encoder->enable = vlv_enable_dp;
5892                 intel_encoder->post_disable = vlv_post_disable_dp;
5893         } else {
5894                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5895                 intel_encoder->enable = g4x_enable_dp;
5896                 if (INTEL_INFO(dev)->gen >= 5)
5897                         intel_encoder->post_disable = ilk_post_disable_dp;
5898         }
5899
5900         intel_dig_port->port = port;
5901         intel_dig_port->dp.output_reg = output_reg;
5902
5903         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5904         if (IS_CHERRYVIEW(dev)) {
5905                 if (port == PORT_D)
5906                         intel_encoder->crtc_mask = 1 << 2;
5907                 else
5908                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5909         } else {
5910                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5911         }
5912         intel_encoder->cloneable = 0;
5913
5914         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5915         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5916
5917         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5918                 drm_encoder_cleanup(encoder);
5919                 kfree(intel_dig_port);
5920                 kfree(intel_connector);
5921         }
5922 }
5923
5924 void intel_dp_mst_suspend(struct drm_device *dev)
5925 {
5926         struct drm_i915_private *dev_priv = dev->dev_private;
5927         int i;
5928
5929         /* disable MST */
5930         for (i = 0; i < I915_MAX_PORTS; i++) {
5931                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5932                 if (!intel_dig_port)
5933                         continue;
5934
5935                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5936                         if (!intel_dig_port->dp.can_mst)
5937                                 continue;
5938                         if (intel_dig_port->dp.is_mst)
5939                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5940                 }
5941         }
5942 }
5943
5944 void intel_dp_mst_resume(struct drm_device *dev)
5945 {
5946         struct drm_i915_private *dev_priv = dev->dev_private;
5947         int i;
5948
5949         for (i = 0; i < I915_MAX_PORTS; i++) {
5950                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5951                 if (!intel_dig_port)
5952                         continue;
5953                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5954                         int ret;
5955
5956                         if (!intel_dig_port->dp.can_mst)
5957                                 continue;
5958
5959                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5960                         if (ret != 0) {
5961                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5962                         }
5963                 }
5964         }
5965 }