drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 /* FDI */
  73 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  74
  75 int
  76 intel_pch_rawclk(struct drm_device *dev)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         WARN_ON(!HAS_PCH_SPLIT(dev));
  81
  82         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  83 }
  84
  85 static inline u32 /* units of 100MHz */
  86 intel_fdi_link_freq(struct drm_device *dev)
  87 {
  88         if (IS_GEN5(dev)) {
  89                 struct drm_i915_private *dev_priv = dev->dev_private;
  90                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  91         } else
  92                 return 27;
  93 }
  94
  95 static const intel_limit_t intel_limits_i8xx_dac = {
  96         .dot = { .min = 25000, .max = 350000 },
  97         .vco = { .min = 930000, .max = 1400000 },
  98         .n = { .min = 3, .max = 16 },
  99         .m = { .min = 96, .max = 140 },
 100         .m1 = { .min = 18, .max = 26 },
 101         .m2 = { .min = 6, .max = 16 },
 102         .p = { .min = 4, .max = 128 },
 103         .p1 = { .min = 2, .max = 33 },
 104         .p2 = { .dot_limit = 165000,
 105                 .p2_slow = 4, .p2_fast = 2 },
 106 };
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 4 },
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 8, .max = 18 },
 140         .m2 = { .min = 3, .max = 7 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_lvds = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 7, .max = 98 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 112000,
 157                 .p2_slow = 14, .p2_fast = 7 },
 158 };
 159
 160
 161 static const intel_limit_t intel_limits_g4x_sdvo = {
 162         .dot = { .min = 25000, .max = 270000 },
 163         .vco = { .min = 1750000, .max = 3500000},
 164         .n = { .min = 1, .max = 4 },
 165         .m = { .min = 104, .max = 138 },
 166         .m1 = { .min = 17, .max = 23 },
 167         .m2 = { .min = 5, .max = 11 },
 168         .p = { .min = 10, .max = 30 },
 169         .p1 = { .min = 1, .max = 3},
 170         .p2 = { .dot_limit = 270000,
 171                 .p2_slow = 10,
 172                 .p2_fast = 10
 173         },
 174 };
 175
 176 static const intel_limit_t intel_limits_g4x_hdmi = {
 177         .dot = { .min = 22000, .max = 400000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 16, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 5, .max = 80 },
 184         .p1 = { .min = 1, .max = 8},
 185         .p2 = { .dot_limit = 165000,
 186                 .p2_slow = 10, .p2_fast = 5 },
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 190         .dot = { .min = 20000, .max = 115000 },
 191         .vco = { .min = 1750000, .max = 3500000 },
 192         .n = { .min = 1, .max = 3 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 17, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 28, .max = 112 },
 197         .p1 = { .min = 2, .max = 8 },
 198         .p2 = { .dot_limit = 0,
 199                 .p2_slow = 14, .p2_fast = 14
 200         },
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 204         .dot = { .min = 80000, .max = 224000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 14, .max = 42 },
 211         .p1 = { .min = 2, .max = 6 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 7, .p2_fast = 7
 214         },
 215 };
 216
 217 static const intel_limit_t intel_limits_pineview_sdvo = {
 218         .dot = { .min = 20000, .max = 400000},
 219         .vco = { .min = 1700000, .max = 3500000 },
 220         /* Pineview's Ncounter is a ring counter */
 221         .n = { .min = 3, .max = 6 },
 222         .m = { .min = 2, .max = 256 },
 223         /* Pineview only has one combined m divider, which we treat as m2. */
 224         .m1 = { .min = 0, .max = 0 },
 225         .m2 = { .min = 0, .max = 254 },
 226         .p = { .min = 5, .max = 80 },
 227         .p1 = { .min = 1, .max = 8 },
 228         .p2 = { .dot_limit = 200000,
 229                 .p2_slow = 10, .p2_fast = 5 },
 230 };
 231
 232 static const intel_limit_t intel_limits_pineview_lvds = {
 233         .dot = { .min = 20000, .max = 400000 },
 234         .vco = { .min = 1700000, .max = 3500000 },
 235         .n = { .min = 3, .max = 6 },
 236         .m = { .min = 2, .max = 256 },
 237         .m1 = { .min = 0, .max = 0 },
 238         .m2 = { .min = 0, .max = 254 },
 239         .p = { .min = 7, .max = 112 },
 240         .p1 = { .min = 1, .max = 8 },
 241         .p2 = { .dot_limit = 112000,
 242                 .p2_slow = 14, .p2_fast = 14 },
 243 };
 244
 245 /* Ironlake / Sandybridge
 246  *
 247  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 248  * the range value for them is (actual_value - 2).
 249  */
 250 static const intel_limit_t intel_limits_ironlake_dac = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 1760000, .max = 3510000 },
 253         .n = { .min = 1, .max = 5 },
 254         .m = { .min = 79, .max = 127 },
 255         .m1 = { .min = 12, .max = 22 },
 256         .m2 = { .min = 5, .max = 9 },
 257         .p = { .min = 5, .max = 80 },
 258         .p1 = { .min = 1, .max = 8 },
 259         .p2 = { .dot_limit = 225000,
 260                 .p2_slow = 10, .p2_fast = 5 },
 261 };
 262
 263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 1760000, .max = 3510000 },
 266         .n = { .min = 1, .max = 3 },
 267         .m = { .min = 79, .max = 118 },
 268         .m1 = { .min = 12, .max = 22 },
 269         .m2 = { .min = 5, .max = 9 },
 270         .p = { .min = 28, .max = 112 },
 271         .p1 = { .min = 2, .max = 8 },
 272         .p2 = { .dot_limit = 225000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274 };
 275
 276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 1760000, .max = 3510000 },
 279         .n = { .min = 1, .max = 3 },
 280         .m = { .min = 79, .max = 127 },
 281         .m1 = { .min = 12, .max = 22 },
 282         .m2 = { .min = 5, .max = 9 },
 283         .p = { .min = 14, .max = 56 },
 284         .p1 = { .min = 2, .max = 8 },
 285         .p2 = { .dot_limit = 225000,
 286                 .p2_slow = 7, .p2_fast = 7 },
 287 };
 288
 289 /* LVDS 100mhz refclk limits. */
 290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 2 },
 294         .m = { .min = 79, .max = 126 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 28, .max = 112 },
 298         .p1 = { .min = 2, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 14, .p2_fast = 14 },
 301 };
 302
 303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 3 },
 307         .m = { .min = 79, .max = 126 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 14, .max = 42 },
 311         .p1 = { .min = 2, .max = 6 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 7, .p2_fast = 7 },
 314 };
 315
 316 static const intel_limit_t intel_limits_vlv_dac = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 4000000, .max = 6000000 },
 319         .n = { .min = 1, .max = 7 },
 320         .m = { .min = 22, .max = 450 }, /* guess */
 321         .m1 = { .min = 2, .max = 3 },
 322         .m2 = { .min = 11, .max = 156 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3 },
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 2, .p2_fast = 20 },
 327 };
 328
 329 static const intel_limit_t intel_limits_vlv_hdmi = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 4000000, .max = 6000000 },
 332         .n = { .min = 1, .max = 7 },
 333         .m = { .min = 60, .max = 300 }, /* guess */
 334         .m1 = { .min = 2, .max = 3 },
 335         .m2 = { .min = 11, .max = 156 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 2, .max = 3 },
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 2, .p2_fast = 20 },
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dp = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 },
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353 };
 354
 355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 356                                                 int refclk)
 357 {
 358         struct drm_device *dev = crtc->dev;
 359         const intel_limit_t *limit;
 360
 361         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 362                 if (intel_is_dual_link_lvds(dev)) {
 363                         if (refclk == 100000)
 364                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 365                         else
 366                                 limit = &intel_limits_ironlake_dual_lvds;
 367                 } else {
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_single_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_single_lvds;
 372                 }
 373         } else
 374                 limit = &intel_limits_ironlake_dac;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 385                 if (intel_is_dual_link_lvds(dev))
 386                         limit = &intel_limits_g4x_dual_channel_lvds;
 387                 else
 388                         limit = &intel_limits_g4x_single_channel_lvds;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 390                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 391                 limit = &intel_limits_g4x_hdmi;
 392         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 393                 limit = &intel_limits_g4x_sdvo;
 394         } else /* The option is for other outputs */
 395                 limit = &intel_limits_i9xx_sdvo;
 396
 397         return limit;
 398 }
 399
 400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 401 {
 402         struct drm_device *dev = crtc->dev;
 403         const intel_limit_t *limit;
 404
 405         if (HAS_PCH_SPLIT(dev))
 406                 limit = intel_ironlake_limit(crtc, refclk);
 407         else if (IS_G4X(dev)) {
 408                 limit = intel_g4x_limit(crtc);
 409         } else if (IS_PINEVIEW(dev)) {
 410                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 411                         limit = &intel_limits_pineview_lvds;
 412                 else
 413                         limit = &intel_limits_pineview_sdvo;
 414         } else if (IS_VALLEYVIEW(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 416                         limit = &intel_limits_vlv_dac;
 417                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 418                         limit = &intel_limits_vlv_hdmi;
 419                 else
 420                         limit = &intel_limits_vlv_dp;
 421         } else if (!IS_GEN2(dev)) {
 422                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 423                         limit = &intel_limits_i9xx_lvds;
 424                 else
 425                         limit = &intel_limits_i9xx_sdvo;
 426         } else {
 427                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 428                         limit = &intel_limits_i8xx_lvds;
 429                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 430                         limit = &intel_limits_i8xx_dvo;
 431                 else
 432                         limit = &intel_limits_i8xx_dac;
 433         }
 434         return limit;
 435 }
 436
 437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 438 static void pineview_clock(int refclk, intel_clock_t *clock)
 439 {
 440         clock->m = clock->m2 + 2;
 441         clock->p = clock->p1 * clock->p2;
 442         clock->vco = refclk * clock->m / clock->n;
 443         clock->dot = clock->vco / clock->p;
 444 }
 445
 446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 447 {
 448         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 449 }
 450
 451 static void i9xx_clock(int refclk, intel_clock_t *clock)
 452 {
 453         clock->m = i9xx_dpll_compute_m(clock);
 454         clock->p = clock->p1 * clock->p2;
 455         clock->vco = refclk * clock->m / (clock->n + 2);
 456         clock->dot = clock->vco / clock->p;
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 463 {
 464         struct drm_device *dev = crtc->dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, crtc, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 475 /**
 476  * Returns whether the given set of divisors are valid for a given refclk with
 477  * the given connectors.
 478  */
 479
 480 static bool intel_PLL_is_valid(struct drm_device *dev,
 481                                const intel_limit_t *limit,
 482                                const intel_clock_t *clock)
 483 {
 484         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 485                 INTELPllInvalid("p1 out of range\n");
 486         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 487                 INTELPllInvalid("p out of range\n");
 488         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 489                 INTELPllInvalid("m2 out of range\n");
 490         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 491                 INTELPllInvalid("m1 out of range\n");
 492         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 493                 INTELPllInvalid("m1 <= m2\n");
 494         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 495                 INTELPllInvalid("m out of range\n");
 496         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 497                 INTELPllInvalid("n out of range\n");
 498         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 499                 INTELPllInvalid("vco out of range\n");
 500         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 501          * connector, etc., rather than just a single range.
 502          */
 503         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 504                 INTELPllInvalid("dot out of range\n");
 505
 506         return true;
 507 }
 508
 509 static bool
 510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 511                     int target, int refclk, intel_clock_t *match_clock,
 512                     intel_clock_t *best_clock)
 513 {
 514         struct drm_device *dev = crtc->dev;
 515         intel_clock_t clock;
 516         int err = target;
 517
 518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 519                 /*
 520                  * For LVDS just rely on its current settings for dual-channel.
 521                  * We haven't figured out how to reliably set up different
 522                  * single/dual channel state, if we even can.
 523                  */
 524                 if (intel_is_dual_link_lvds(dev))
 525                         clock.p2 = limit->p2.p2_fast;
 526                 else
 527                         clock.p2 = limit->p2.p2_slow;
 528         } else {
 529                 if (target < limit->p2.dot_limit)
 530                         clock.p2 = limit->p2.p2_slow;
 531                 else
 532                         clock.p2 = limit->p2.p2_fast;
 533         }
 534
 535         memset(best_clock, 0, sizeof(*best_clock));
 536
 537         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 538              clock.m1++) {
 539                 for (clock.m2 = limit->m2.min;
 540                      clock.m2 <= limit->m2.max; clock.m2++) {
 541                         if (clock.m2 >= clock.m1)
 542                                 break;
 543                         for (clock.n = limit->n.min;
 544                              clock.n <= limit->n.max; clock.n++) {
 545                                 for (clock.p1 = limit->p1.min;
 546                                         clock.p1 <= limit->p1.max; clock.p1++) {
 547                                         int this_err;
 548
 549                                         i9xx_clock(refclk, &clock);
 550                                         if (!intel_PLL_is_valid(dev, limit,
 551                                                                 &clock))
 552                                                 continue;
 553                                         if (match_clock &&
 554                                             clock.p != match_clock->p)
 555                                                 continue;
 556
 557                                         this_err = abs(clock.dot - target);
 558                                         if (this_err < err) {
 559                                                 *best_clock = clock;
 560                                                 err = this_err;
 561                                         }
 562                                 }
 563                         }
 564                 }
 565         }
 566
 567         return (err != target);
 568 }
 569
 570 static bool
 571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 572                    int target, int refclk, intel_clock_t *match_clock,
 573                    intel_clock_t *best_clock)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         intel_clock_t clock;
 577         int err = target;
 578
 579         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 580                 /*
 581                  * For LVDS just rely on its current settings for dual-channel.
 582                  * We haven't figured out how to reliably set up different
 583                  * single/dual channel state, if we even can.
 584                  */
 585                 if (intel_is_dual_link_lvds(dev))
 586                         clock.p2 = limit->p2.p2_fast;
 587                 else
 588                         clock.p2 = limit->p2.p2_slow;
 589         } else {
 590                 if (target < limit->p2.dot_limit)
 591                         clock.p2 = limit->p2.p2_slow;
 592                 else
 593                         clock.p2 = limit->p2.p2_fast;
 594         }
 595
 596         memset(best_clock, 0, sizeof(*best_clock));
 597
 598         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 599              clock.m1++) {
 600                 for (clock.m2 = limit->m2.min;
 601                      clock.m2 <= limit->m2.max; clock.m2++) {
 602                         for (clock.n = limit->n.min;
 603                              clock.n <= limit->n.max; clock.n++) {
 604                                 for (clock.p1 = limit->p1.min;
 605                                         clock.p1 <= limit->p1.max; clock.p1++) {
 606                                         int this_err;
 607
 608                                         pineview_clock(refclk, &clock);
 609                                         if (!intel_PLL_is_valid(dev, limit,
 610                                                                 &clock))
 611                                                 continue;
 612                                         if (match_clock &&
 613                                             clock.p != match_clock->p)
 614                                                 continue;
 615
 616                                         this_err = abs(clock.dot - target);
 617                                         if (this_err < err) {
 618                                                 *best_clock = clock;
 619                                                 err = this_err;
 620                                         }
 621                                 }
 622                         }
 623                 }
 624         }
 625
 626         return (err != target);
 627 }
 628
 629 static bool
 630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 631                    int target, int refclk, intel_clock_t *match_clock,
 632                    intel_clock_t *best_clock)
 633 {
 634         struct drm_device *dev = crtc->dev;
 635         intel_clock_t clock;
 636         int max_n;
 637         bool found;
 638         /* approximately equals target * 0.00585 */
 639         int err_most = (target >> 8) + (target >> 9);
 640         found = false;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (intel_is_dual_link_lvds(dev))
 644                         clock.p2 = limit->p2.p2_fast;
 645                 else
 646                         clock.p2 = limit->p2.p2_slow;
 647         } else {
 648                 if (target < limit->p2.dot_limit)
 649                         clock.p2 = limit->p2.p2_slow;
 650                 else
 651                         clock.p2 = limit->p2.p2_fast;
 652         }
 653
 654         memset(best_clock, 0, sizeof(*best_clock));
 655         max_n = limit->n.max;
 656         /* based on hardware requirement, prefer smaller n to precision */
 657         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 658                 /* based on hardware requirement, prefere larger m1,m2 */
 659                 for (clock.m1 = limit->m1.max;
 660                      clock.m1 >= limit->m1.min; clock.m1--) {
 661                         for (clock.m2 = limit->m2.max;
 662                              clock.m2 >= limit->m2.min; clock.m2--) {
 663                                 for (clock.p1 = limit->p1.max;
 664                                      clock.p1 >= limit->p1.min; clock.p1--) {
 665                                         int this_err;
 666
 667                                         i9xx_clock(refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671
 672                                         this_err = abs(clock.dot - target);
 673                                         if (this_err < err_most) {
 674                                                 *best_clock = clock;
 675                                                 err_most = this_err;
 676                                                 max_n = clock.n;
 677                                                 found = true;
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683         return found;
 684 }
 685
 686 static bool
 687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 688                    int target, int refclk, intel_clock_t *match_clock,
 689                    intel_clock_t *best_clock)
 690 {
 691         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 692         u32 m, n, fastclk;
 693         u32 updrate, minupdate, p;
 694         unsigned long bestppm, ppm, absppm;
 695         int dotclk, flag;
 696
 697         flag = 0;
 698         dotclk = target * 1000;
 699         bestppm = 1000000;
 700         ppm = absppm = 0;
 701         fastclk = dotclk / (2*100);
 702         updrate = 0;
 703         minupdate = 19200;
 704         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 705         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 706
 707         /* based on hardware requirement, prefer smaller n to precision */
 708         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 709                 updrate = refclk / n;
 710                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 711                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 712                                 if (p2 > 10)
 713                                         p2 = p2 - 1;
 714                                 p = p1 * p2;
 715                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 716                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 717                                         m2 = (((2*(fastclk * p * n / m1 )) +
 718                                                refclk) / (2*refclk));
 719                                         m = m1 * m2;
 720                                         vco = updrate * m;
 721                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 722                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 723                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 724                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 725                                                         bestppm = 0;
 726                                                         flag = 1;
 727                                                 }
 728                                                 if (absppm < bestppm - 10) {
 729                                                         bestppm = absppm;
 730                                                         flag = 1;
 731                                                 }
 732                                                 if (flag) {
 733                                                         bestn = n;
 734                                                         bestm1 = m1;
 735                                                         bestm2 = m2;
 736                                                         bestp1 = p1;
 737                                                         bestp2 = p2;
 738                                                         flag = 0;
 739                                                 }
 740                                         }
 741                                 }
 742                         }
 743                 }
 744         }
 745         best_clock->n = bestn;
 746         best_clock->m1 = bestm1;
 747         best_clock->m2 = bestm2;
 748         best_clock->p1 = bestp1;
 749         best_clock->p2 = bestp2;
 750
 751         return true;
 752 }
 753
 754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 755                                              enum pipe pipe)
 756 {
 757         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 759
 760         return intel_crtc->config.cpu_transcoder;
 761 }
 762
 763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 764 {
 765         struct drm_i915_private *dev_priv = dev->dev_private;
 766         u32 frame, frame_reg = PIPEFRAME(pipe);
 767
 768         frame = I915_READ(frame_reg);
 769
 770         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 771                 DRM_DEBUG_KMS("vblank wait timed out\n");
 772 }
 773
 774 /**
 775  * intel_wait_for_vblank - wait for vblank on a given pipe
 776  * @dev: drm device
 777  * @pipe: pipe to wait for
 778  *
 779  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 780  * mode setting code.
 781  */
 782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 783 {
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         int pipestat_reg = PIPESTAT(pipe);
 786
 787         if (INTEL_INFO(dev)->gen >= 5) {
 788                 ironlake_wait_for_vblank(dev, pipe);
 789                 return;
 790         }
 791
 792         /* Clear existing vblank status. Note this will clear any other
 793          * sticky status fields as well.
 794          *
 795          * This races with i915_driver_irq_handler() with the result
 796          * that either function could miss a vblank event.  Here it is not
 797          * fatal, as we will either wait upon the next vblank interrupt or
 798          * timeout.  Generally speaking intel_wait_for_vblank() is only
 799          * called during modeset at which time the GPU should be idle and
 800          * should *not* be performing page flips and thus not waiting on
 801          * vblanks...
 802          * Currently, the result of us stealing a vblank from the irq
 803          * handler is that a single frame will be skipped during swapbuffers.
 804          */
 805         I915_WRITE(pipestat_reg,
 806                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 807
 808         /* Wait for vblank interrupt bit to set */
 809         if (wait_for(I915_READ(pipestat_reg) &
 810                      PIPE_VBLANK_INTERRUPT_STATUS,
 811                      50))
 812                 DRM_DEBUG_KMS("vblank wait timed out\n");
 813 }
 814
 815 /*
 816  * intel_wait_for_pipe_off - wait for pipe to turn off
 817  * @dev: drm device
 818  * @pipe: pipe to wait for
 819  *
 820  * After disabling a pipe, we can't wait for vblank in the usual way,
 821  * spinning on the vblank interrupt status bit, since we won't actually
 822  * see an interrupt when the pipe is disabled.
 823  *
 824  * On Gen4 and above:
 825  *   wait for the pipe register state bit to turn off
 826  *
 827  * Otherwise:
 828  *   wait for the display line value to settle (it usually
 829  *   ends up stopping at the start of the next frame).
 830  *
 831  */
 832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 836                                                                       pipe);
 837
 838         if (INTEL_INFO(dev)->gen >= 4) {
 839                 int reg = PIPECONF(cpu_transcoder);
 840
 841                 /* Wait for the Pipe State to go off */
 842                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 843                              100))
 844                         WARN(1, "pipe_off wait timed out\n");
 845         } else {
 846                 u32 last_line, line_mask;
 847                 int reg = PIPEDSL(pipe);
 848                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 849
 850                 if (IS_GEN2(dev))
 851                         line_mask = DSL_LINEMASK_GEN2;
 852                 else
 853                         line_mask = DSL_LINEMASK_GEN3;
 854
 855                 /* Wait for the display line to settle */
 856                 do {
 857                         last_line = I915_READ(reg) & line_mask;
 858                         mdelay(5);
 859                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 860                          time_after(timeout, jiffies));
 861                 if (time_after(jiffies, timeout))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         }
 864 }
 865
 866 /*
 867  * ibx_digital_port_connected - is the specified port connected?
 868  * @dev_priv: i915 private structure
 869  * @port: the port to test
 870  *
 871  * Returns true if @port is connected, false otherwise.
 872  */
 873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 874                                 struct intel_digital_port *port)
 875 {
 876         u32 bit;
 877
 878         if (HAS_PCH_IBX(dev_priv->dev)) {
 879                 switch(port->port) {
 880                 case PORT_B:
 881                         bit = SDE_PORTB_HOTPLUG;
 882                         break;
 883                 case PORT_C:
 884                         bit = SDE_PORTC_HOTPLUG;
 885                         break;
 886                 case PORT_D:
 887                         bit = SDE_PORTD_HOTPLUG;
 888                         break;
 889                 default:
 890                         return true;
 891                 }
 892         } else {
 893                 switch(port->port) {
 894                 case PORT_B:
 895                         bit = SDE_PORTB_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_C:
 898                         bit = SDE_PORTC_HOTPLUG_CPT;
 899                         break;
 900                 case PORT_D:
 901                         bit = SDE_PORTD_HOTPLUG_CPT;
 902                         break;
 903                 default:
 904                         return true;
 905                 }
 906         }
 907
 908         return I915_READ(SDEISR) & bit;
 909 }
 910
 911 static const char *state_string(bool enabled)
 912 {
 913         return enabled ? "on" : "off";
 914 }
 915
 916 /* Only for pre-ILK configs */
 917 void assert_pll(struct drm_i915_private *dev_priv,
 918                 enum pipe pipe, bool state)
 919 {
 920         int reg;
 921         u32 val;
 922         bool cur_state;
 923
 924         reg = DPLL(pipe);
 925         val = I915_READ(reg);
 926         cur_state = !!(val & DPLL_VCO_ENABLE);
 927         WARN(cur_state != state,
 928              "PLL state assertion failure (expected %s, current %s)\n",
 929              state_string(state), state_string(cur_state));
 930 }
 931
 932 struct intel_shared_dpll *
 933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 934 {
 935         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 936
 937         if (crtc->config.shared_dpll < 0)
 938                 return NULL;
 939
 940         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 941 }
 942
 943 /* For ILK+ */
 944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 945                         struct intel_shared_dpll *pll,
 946                         bool state)
 947 {
 948         bool cur_state;
 949         struct intel_dpll_hw_state hw_state;
 950
 951         if (HAS_PCH_LPT(dev_priv->dev)) {
 952                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 953                 return;
 954         }
 955
 956         if (WARN (!pll,
 957                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 958                 return;
 959
 960         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 961         WARN(cur_state != state,
 962              "%s assertion failure (expected %s, current %s)\n",
 963              pll->name, state_string(state), state_string(cur_state));
 964 }
 965
 966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 967                           enum pipe pipe, bool state)
 968 {
 969         int reg;
 970         u32 val;
 971         bool cur_state;
 972         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 973                                                                       pipe);
 974
 975         if (HAS_DDI(dev_priv->dev)) {
 976                 /* DDI does not have a specific FDI_TX register */
 977                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 978                 val = I915_READ(reg);
 979                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 980         } else {
 981                 reg = FDI_TX_CTL(pipe);
 982                 val = I915_READ(reg);
 983                 cur_state = !!(val & FDI_TX_ENABLE);
 984         }
 985         WARN(cur_state != state,
 986              "FDI TX state assertion failure (expected %s, current %s)\n",
 987              state_string(state), state_string(cur_state));
 988 }
 989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 991
 992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 993                           enum pipe pipe, bool state)
 994 {
 995         int reg;
 996         u32 val;
 997         bool cur_state;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         cur_state = !!(val & FDI_RX_ENABLE);
1002         WARN(cur_state != state,
1003              "FDI RX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010                                       enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014
1015         /* ILK FDI PLL is always enabled */
1016         if (dev_priv->info->gen == 5)
1017                 return;
1018
1019         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020         if (HAS_DDI(dev_priv->dev))
1021                 return;
1022
1023         reg = FDI_TX_CTL(pipe);
1024         val = I915_READ(reg);
1025         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029                        enum pipe pipe, bool state)
1030 {
1031         int reg;
1032         u32 val;
1033         bool cur_state;
1034
1035         reg = FDI_RX_CTL(pipe);
1036         val = I915_READ(reg);
1037         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038         WARN(cur_state != state,
1039              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044                                   enum pipe pipe)
1045 {
1046         int pp_reg, lvds_reg;
1047         u32 val;
1048         enum pipe panel_pipe = PIPE_A;
1049         bool locked = true;
1050
1051         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052                 pp_reg = PCH_PP_CONTROL;
1053                 lvds_reg = PCH_LVDS;
1054         } else {
1055                 pp_reg = PP_CONTROL;
1056                 lvds_reg = LVDS;
1057         }
1058
1059         val = I915_READ(pp_reg);
1060         if (!(val & PANEL_POWER_ON) ||
1061             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062                 locked = false;
1063
1064         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065                 panel_pipe = PIPE_B;
1066
1067         WARN(panel_pipe == pipe && locked,
1068              "panel assertion failure, pipe %c regs locked\n",
1069              pipe_name(pipe));
1070 }
1071
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073                  enum pipe pipe, bool state)
1074 {
1075         int reg;
1076         u32 val;
1077         bool cur_state;
1078         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079                                                                       pipe);
1080
1081         /* if we need the pipe A quirk it must be always on */
1082         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083                 state = true;
1084
1085         if (!intel_display_power_enabled(dev_priv->dev,
1086                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1087                 cur_state = false;
1088         } else {
1089                 reg = PIPECONF(cpu_transcoder);
1090                 val = I915_READ(reg);
1091                 cur_state = !!(val & PIPECONF_ENABLE);
1092         }
1093
1094         WARN(cur_state != state,
1095              "pipe %c assertion failure (expected %s, current %s)\n",
1096              pipe_name(pipe), state_string(state), state_string(cur_state));
1097 }
1098
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100                          enum plane plane, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105
1106         reg = DSPCNTR(plane);
1107         val = I915_READ(reg);
1108         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109         WARN(cur_state != state,
1110              "plane %c assertion failure (expected %s, current %s)\n",
1111              plane_name(plane), state_string(state), state_string(cur_state));
1112 }
1113
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118                                    enum pipe pipe)
1119 {
1120         struct drm_device *dev = dev_priv->dev;
1121         int reg, i;
1122         u32 val;
1123         int cur_pipe;
1124
1125         /* Primary planes are fixed to pipes on gen4+ */
1126         if (INTEL_INFO(dev)->gen >= 4) {
1127                 reg = DSPCNTR(pipe);
1128                 val = I915_READ(reg);
1129                 WARN((val & DISPLAY_PLANE_ENABLE),
1130                      "plane %c assertion failure, should be disabled but not\n",
1131                      plane_name(pipe));
1132                 return;
1133         }
1134
1135         /* Need to check both planes against the pipe */
1136         for_each_pipe(i) {
1137                 reg = DSPCNTR(i);
1138                 val = I915_READ(reg);
1139                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140                         DISPPLANE_SEL_PIPE_SHIFT;
1141                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143                      plane_name(i), pipe_name(pipe));
1144         }
1145 }
1146
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148                                     enum pipe pipe)
1149 {
1150         struct drm_device *dev = dev_priv->dev;
1151         int reg, i;
1152         u32 val;
1153
1154         if (IS_VALLEYVIEW(dev)) {
1155                 for (i = 0; i < dev_priv->num_plane; i++) {
1156                         reg = SPCNTR(pipe, i);
1157                         val = I915_READ(reg);
1158                         WARN((val & SP_ENABLE),
1159                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160                              sprite_name(pipe, i), pipe_name(pipe));
1161                 }
1162         } else if (INTEL_INFO(dev)->gen >= 7) {
1163                 reg = SPRCTL(pipe);
1164                 val = I915_READ(reg);
1165                 WARN((val & SPRITE_ENABLE),
1166                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167                      plane_name(pipe), pipe_name(pipe));
1168         } else if (INTEL_INFO(dev)->gen >= 5) {
1169                 reg = DVSCNTR(pipe);
1170                 val = I915_READ(reg);
1171                 WARN((val & DVS_ENABLE),
1172                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173                      plane_name(pipe), pipe_name(pipe));
1174         }
1175 }
1176
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178 {
1179         u32 val;
1180         bool enabled;
1181
1182         if (HAS_PCH_LPT(dev_priv->dev)) {
1183                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184                 return;
1185         }
1186
1187         val = I915_READ(PCH_DREF_CONTROL);
1188         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189                             DREF_SUPERSPREAD_SOURCE_MASK));
1190         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191 }
1192
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194                                            enum pipe pipe)
1195 {
1196         int reg;
1197         u32 val;
1198         bool enabled;
1199
1200         reg = PCH_TRANSCONF(pipe);
1201         val = I915_READ(reg);
1202         enabled = !!(val & TRANS_ENABLE);
1203         WARN(enabled,
1204              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205              pipe_name(pipe));
1206 }
1207
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209                             enum pipe pipe, u32 port_sel, u32 val)
1210 {
1211         if ((val & DP_PORT_EN) == 0)
1212                 return false;
1213
1214         if (HAS_PCH_CPT(dev_priv->dev)) {
1215                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218                         return false;
1219         } else {
1220                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221                         return false;
1222         }
1223         return true;
1224 }
1225
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227                               enum pipe pipe, u32 val)
1228 {
1229         if ((val & SDVO_ENABLE) == 0)
1230                 return false;
1231
1232         if (HAS_PCH_CPT(dev_priv->dev)) {
1233                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1234                         return false;
1235         } else {
1236                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & LVDS_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & ADPA_DAC_ENABLE) == 0)
1262                 return false;
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274                                    enum pipe pipe, int reg, u32 port_sel)
1275 {
1276         u32 val = I915_READ(reg);
1277         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279              reg, pipe_name(pipe));
1280
1281         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282              && (val & DP_PIPEB_SELECT),
1283              "IBX PCH dp port still using transcoder B\n");
1284 }
1285
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287                                      enum pipe pipe, int reg)
1288 {
1289         u32 val = I915_READ(reg);
1290         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292              reg, pipe_name(pipe));
1293
1294         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295              && (val & SDVO_PIPE_B_SELECT),
1296              "IBX PCH hdmi port still using transcoder B\n");
1297 }
1298
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300                                       enum pipe pipe)
1301 {
1302         int reg;
1303         u32 val;
1304
1305         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1308
1309         reg = PCH_ADPA;
1310         val = I915_READ(reg);
1311         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312              "PCH VGA enabled on transcoder %c, should be disabled\n",
1313              pipe_name(pipe));
1314
1315         reg = PCH_LVDS;
1316         val = I915_READ(reg);
1317         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319              pipe_name(pipe));
1320
1321         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1324 }
1325
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1327 {
1328         struct drm_device *dev = crtc->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         int reg = DPLL(crtc->pipe);
1331         u32 dpll = crtc->config.dpll_hw_state.dpll;
1332
1333         assert_pipe_disabled(dev_priv, crtc->pipe);
1334
1335         /* No really, not for ILK+ */
1336         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338         /* PLL is protected by panel, make sure we can write it */
1339         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340                 assert_panel_unlocked(dev_priv, crtc->pipe);
1341
1342         I915_WRITE(reg, dpll);
1343         POSTING_READ(reg);
1344         udelay(150);
1345
1346         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350         POSTING_READ(DPLL_MD(crtc->pipe));
1351
1352         /* We do this three times for luck */
1353         I915_WRITE(reg, dpll);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, dpll);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359         I915_WRITE(reg, dpll);
1360         POSTING_READ(reg);
1361         udelay(150); /* wait for warmup */
1362 }
1363
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1365 {
1366         struct drm_device *dev = crtc->base.dev;
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         int reg = DPLL(crtc->pipe);
1369         u32 dpll = crtc->config.dpll_hw_state.dpll;
1370
1371         assert_pipe_disabled(dev_priv, crtc->pipe);
1372
1373         /* No really, not for ILK+ */
1374         BUG_ON(dev_priv->info->gen >= 5);
1375
1376         /* PLL is protected by panel, make sure we can write it */
1377         if (IS_MOBILE(dev) && !IS_I830(dev))
1378                 assert_panel_unlocked(dev_priv, crtc->pipe);
1379
1380         I915_WRITE(reg, dpll);
1381
1382         /* Wait for the clocks to stabilize. */
1383         POSTING_READ(reg);
1384         udelay(150);
1385
1386         if (INTEL_INFO(dev)->gen >= 4) {
1387                 I915_WRITE(DPLL_MD(crtc->pipe),
1388                            crtc->config.dpll_hw_state.dpll_md);
1389         } else {
1390                 /* The pixel multiplier can only be updated once the
1391                  * DPLL is enabled and the clocks are stable.
1392                  *
1393                  * So write it again.
1394                  */
1395                 I915_WRITE(reg, dpll);
1396         }
1397
1398         /* We do this three times for luck */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405         I915_WRITE(reg, dpll);
1406         POSTING_READ(reg);
1407         udelay(150); /* wait for warmup */
1408 }
1409
1410 /**
1411  * i9xx_disable_pll - disable a PLL
1412  * @dev_priv: i915 private structure
1413  * @pipe: pipe PLL to disable
1414  *
1415  * Disable the PLL for @pipe, making sure the pipe is off first.
1416  *
1417  * Note!  This is for pre-ILK only.
1418  */
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1420 {
1421         /* Don't disable pipe A or pipe A PLLs if needed */
1422         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423                 return;
1424
1425         /* Make sure the pipe isn't still relying on us */
1426         assert_pipe_disabled(dev_priv, pipe);
1427
1428         I915_WRITE(DPLL(pipe), 0);
1429         POSTING_READ(DPLL(pipe));
1430 }
1431
1432 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433 {
1434         u32 port_mask;
1435
1436         if (!port)
1437                 port_mask = DPLL_PORTB_READY_MASK;
1438         else
1439                 port_mask = DPLL_PORTC_READY_MASK;
1440
1441         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443                      'B' + port, I915_READ(DPLL(0)));
1444 }
1445
1446 /**
1447  * ironlake_enable_shared_dpll - enable PCH PLL
1448  * @dev_priv: i915 private structure
1449  * @pipe: pipe PLL to enable
1450  *
1451  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452  * drives the transcoder clock.
1453  */
1454 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1455 {
1456         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1458
1459         /* PCH PLLs only available on ILK, SNB and IVB */
1460         BUG_ON(dev_priv->info->gen < 5);
1461         if (WARN_ON(pll == NULL))
1462                 return;
1463
1464         if (WARN_ON(pll->refcount == 0))
1465                 return;
1466
1467         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468                       pll->name, pll->active, pll->on,
1469                       crtc->base.base.id);
1470
1471         if (pll->active++) {
1472                 WARN_ON(!pll->on);
1473                 assert_shared_dpll_enabled(dev_priv, pll);
1474                 return;
1475         }
1476         WARN_ON(pll->on);
1477
1478         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479         pll->enable(dev_priv, pll);
1480         pll->on = true;
1481 }
1482
1483 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1484 {
1485         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1487
1488         /* PCH only available on ILK+ */
1489         BUG_ON(dev_priv->info->gen < 5);
1490         if (WARN_ON(pll == NULL))
1491                return;
1492
1493         if (WARN_ON(pll->refcount == 0))
1494                 return;
1495
1496         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497                       pll->name, pll->active, pll->on,
1498                       crtc->base.base.id);
1499
1500         if (WARN_ON(pll->active == 0)) {
1501                 assert_shared_dpll_disabled(dev_priv, pll);
1502                 return;
1503         }
1504
1505         assert_shared_dpll_enabled(dev_priv, pll);
1506         WARN_ON(!pll->on);
1507         if (--pll->active)
1508                 return;
1509
1510         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511         pll->disable(dev_priv, pll);
1512         pll->on = false;
1513 }
1514
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516                                            enum pipe pipe)
1517 {
1518         struct drm_device *dev = dev_priv->dev;
1519         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521         uint32_t reg, val, pipeconf_val;
1522
1523         /* PCH only available on ILK+ */
1524         BUG_ON(dev_priv->info->gen < 5);
1525
1526         /* Make sure PCH DPLL is enabled */
1527         assert_shared_dpll_enabled(dev_priv,
1528                                    intel_crtc_to_shared_dpll(intel_crtc));
1529
1530         /* FDI must be feeding us bits for PCH ports */
1531         assert_fdi_tx_enabled(dev_priv, pipe);
1532         assert_fdi_rx_enabled(dev_priv, pipe);
1533
1534         if (HAS_PCH_CPT(dev)) {
1535                 /* Workaround: Set the timing override bit before enabling the
1536                  * pch transcoder. */
1537                 reg = TRANS_CHICKEN2(pipe);
1538                 val = I915_READ(reg);
1539                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540                 I915_WRITE(reg, val);
1541         }
1542
1543         reg = PCH_TRANSCONF(pipe);
1544         val = I915_READ(reg);
1545         pipeconf_val = I915_READ(PIPECONF(pipe));
1546
1547         if (HAS_PCH_IBX(dev_priv->dev)) {
1548                 /*
1549                  * make the BPC in transcoder be consistent with
1550                  * that in pipeconf reg.
1551                  */
1552                 val &= ~PIPECONF_BPC_MASK;
1553                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1554         }
1555
1556         val &= ~TRANS_INTERLACE_MASK;
1557         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558                 if (HAS_PCH_IBX(dev_priv->dev) &&
1559                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560                         val |= TRANS_LEGACY_INTERLACED_ILK;
1561                 else
1562                         val |= TRANS_INTERLACED;
1563         else
1564                 val |= TRANS_PROGRESSIVE;
1565
1566         I915_WRITE(reg, val | TRANS_ENABLE);
1567         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1569 }
1570
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572                                       enum transcoder cpu_transcoder)
1573 {
1574         u32 val, pipeconf_val;
1575
1576         /* PCH only available on ILK+ */
1577         BUG_ON(dev_priv->info->gen < 5);
1578
1579         /* FDI must be feeding us bits for PCH ports */
1580         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1582
1583         /* Workaround: set timing override bit. */
1584         val = I915_READ(_TRANSA_CHICKEN2);
1585         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586         I915_WRITE(_TRANSA_CHICKEN2, val);
1587
1588         val = TRANS_ENABLE;
1589         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1590
1591         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592             PIPECONF_INTERLACED_ILK)
1593                 val |= TRANS_INTERLACED;
1594         else
1595                 val |= TRANS_PROGRESSIVE;
1596
1597         I915_WRITE(LPT_TRANSCONF, val);
1598         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599                 DRM_ERROR("Failed to enable PCH transcoder\n");
1600 }
1601
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603                                             enum pipe pipe)
1604 {
1605         struct drm_device *dev = dev_priv->dev;
1606         uint32_t reg, val;
1607
1608         /* FDI relies on the transcoder */
1609         assert_fdi_tx_disabled(dev_priv, pipe);
1610         assert_fdi_rx_disabled(dev_priv, pipe);
1611
1612         /* Ports must be off as well */
1613         assert_pch_ports_disabled(dev_priv, pipe);
1614
1615         reg = PCH_TRANSCONF(pipe);
1616         val = I915_READ(reg);
1617         val &= ~TRANS_ENABLE;
1618         I915_WRITE(reg, val);
1619         /* wait for PCH transcoder off, transcoder state */
1620         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1622
1623         if (!HAS_PCH_IBX(dev)) {
1624                 /* Workaround: Clear the timing override chicken bit again. */
1625                 reg = TRANS_CHICKEN2(pipe);
1626                 val = I915_READ(reg);
1627                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628                 I915_WRITE(reg, val);
1629         }
1630 }
1631
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1633 {
1634         u32 val;
1635
1636         val = I915_READ(LPT_TRANSCONF);
1637         val &= ~TRANS_ENABLE;
1638         I915_WRITE(LPT_TRANSCONF, val);
1639         /* wait for PCH transcoder off, transcoder state */
1640         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641                 DRM_ERROR("Failed to disable PCH transcoder\n");
1642
1643         /* Workaround: clear timing override bit. */
1644         val = I915_READ(_TRANSA_CHICKEN2);
1645         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646         I915_WRITE(_TRANSA_CHICKEN2, val);
1647 }
1648
1649 /**
1650  * intel_enable_pipe - enable a pipe, asserting requirements
1651  * @dev_priv: i915 private structure
1652  * @pipe: pipe to enable
1653  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1654  *
1655  * Enable @pipe, making sure that various hardware specific requirements
1656  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657  *
1658  * @pipe should be %PIPE_A or %PIPE_B.
1659  *
1660  * Will wait until the pipe is actually running (i.e. first vblank) before
1661  * returning.
1662  */
1663 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1664                               bool pch_port)
1665 {
1666         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667                                                                       pipe);
1668         enum pipe pch_transcoder;
1669         int reg;
1670         u32 val;
1671
1672         assert_planes_disabled(dev_priv, pipe);
1673         assert_sprites_disabled(dev_priv, pipe);
1674
1675         if (HAS_PCH_LPT(dev_priv->dev))
1676                 pch_transcoder = TRANSCODER_A;
1677         else
1678                 pch_transcoder = pipe;
1679
1680         /*
1681          * A pipe without a PLL won't actually be able to drive bits from
1682          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1683          * need the check.
1684          */
1685         if (!HAS_PCH_SPLIT(dev_priv->dev))
1686                 assert_pll_enabled(dev_priv, pipe);
1687         else {
1688                 if (pch_port) {
1689                         /* if driving the PCH, we need FDI enabled */
1690                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1691                         assert_fdi_tx_pll_enabled(dev_priv,
1692                                                   (enum pipe) cpu_transcoder);
1693                 }
1694                 /* FIXME: assert CPU port conditions for SNB+ */
1695         }
1696
1697         reg = PIPECONF(cpu_transcoder);
1698         val = I915_READ(reg);
1699         if (val & PIPECONF_ENABLE)
1700                 return;
1701
1702         I915_WRITE(reg, val | PIPECONF_ENABLE);
1703         intel_wait_for_vblank(dev_priv->dev, pipe);
1704 }
1705
1706 /**
1707  * intel_disable_pipe - disable a pipe, asserting requirements
1708  * @dev_priv: i915 private structure
1709  * @pipe: pipe to disable
1710  *
1711  * Disable @pipe, making sure that various hardware specific requirements
1712  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1713  *
1714  * @pipe should be %PIPE_A or %PIPE_B.
1715  *
1716  * Will wait until the pipe has shut down before returning.
1717  */
1718 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1719                                enum pipe pipe)
1720 {
1721         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1722                                                                       pipe);
1723         int reg;
1724         u32 val;
1725
1726         /*
1727          * Make sure planes won't keep trying to pump pixels to us,
1728          * or we might hang the display.
1729          */
1730         assert_planes_disabled(dev_priv, pipe);
1731         assert_sprites_disabled(dev_priv, pipe);
1732
1733         /* Don't disable pipe A or pipe A PLLs if needed */
1734         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1735                 return;
1736
1737         reg = PIPECONF(cpu_transcoder);
1738         val = I915_READ(reg);
1739         if ((val & PIPECONF_ENABLE) == 0)
1740                 return;
1741
1742         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1744 }
1745
1746 /*
1747  * Plane regs are double buffered, going from enabled->disabled needs a
1748  * trigger in order to latch.  The display address reg provides this.
1749  */
1750 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1751                                       enum plane plane)
1752 {
1753         if (dev_priv->info->gen >= 4)
1754                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1755         else
1756                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1757 }
1758
1759 /**
1760  * intel_enable_plane - enable a display plane on a given pipe
1761  * @dev_priv: i915 private structure
1762  * @plane: plane to enable
1763  * @pipe: pipe being fed
1764  *
1765  * Enable @plane on @pipe, making sure that @pipe is running first.
1766  */
1767 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768                                enum plane plane, enum pipe pipe)
1769 {
1770         int reg;
1771         u32 val;
1772
1773         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774         assert_pipe_enabled(dev_priv, pipe);
1775
1776         reg = DSPCNTR(plane);
1777         val = I915_READ(reg);
1778         if (val & DISPLAY_PLANE_ENABLE)
1779                 return;
1780
1781         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782         intel_flush_display_plane(dev_priv, plane);
1783         intel_wait_for_vblank(dev_priv->dev, pipe);
1784 }
1785
1786 /**
1787  * intel_disable_plane - disable a display plane
1788  * @dev_priv: i915 private structure
1789  * @plane: plane to disable
1790  * @pipe: pipe consuming the data
1791  *
1792  * Disable @plane; should be an independent operation.
1793  */
1794 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795                                 enum plane plane, enum pipe pipe)
1796 {
1797         int reg;
1798         u32 val;
1799
1800         reg = DSPCNTR(plane);
1801         val = I915_READ(reg);
1802         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1803                 return;
1804
1805         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806         intel_flush_display_plane(dev_priv, plane);
1807         intel_wait_for_vblank(dev_priv->dev, pipe);
1808 }
1809
1810 static bool need_vtd_wa(struct drm_device *dev)
1811 {
1812 #ifdef CONFIG_INTEL_IOMMU
1813         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1814                 return true;
1815 #endif
1816         return false;
1817 }
1818
1819 int
1820 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821                            struct drm_i915_gem_object *obj,
1822                            struct intel_ring_buffer *pipelined)
1823 {
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         u32 alignment;
1826         int ret;
1827
1828         switch (obj->tiling_mode) {
1829         case I915_TILING_NONE:
1830                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831                         alignment = 128 * 1024;
1832                 else if (INTEL_INFO(dev)->gen >= 4)
1833                         alignment = 4 * 1024;
1834                 else
1835                         alignment = 64 * 1024;
1836                 break;
1837         case I915_TILING_X:
1838                 /* pin() will align the object as required by fence */
1839                 alignment = 0;
1840                 break;
1841         case I915_TILING_Y:
1842                 /* Despite that we check this in framebuffer_init userspace can
1843                  * screw us over and change the tiling after the fact. Only
1844                  * pinned buffers can't change their tiling. */
1845                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1846                 return -EINVAL;
1847         default:
1848                 BUG();
1849         }
1850
1851         /* Note that the w/a also requires 64 PTE of padding following the
1852          * bo. We currently fill all unused PTE with the shadow page and so
1853          * we should always have valid PTE following the scanout preventing
1854          * the VT-d warning.
1855          */
1856         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857                 alignment = 256 * 1024;
1858
1859         dev_priv->mm.interruptible = false;
1860         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1861         if (ret)
1862                 goto err_interruptible;
1863
1864         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865          * fence, whereas 965+ only requires a fence if using
1866          * framebuffer compression.  For simplicity, we always install
1867          * a fence as the cost is not that onerous.
1868          */
1869         ret = i915_gem_object_get_fence(obj);
1870         if (ret)
1871                 goto err_unpin;
1872
1873         i915_gem_object_pin_fence(obj);
1874
1875         dev_priv->mm.interruptible = true;
1876         return 0;
1877
1878 err_unpin:
1879         i915_gem_object_unpin_from_display_plane(obj);
1880 err_interruptible:
1881         dev_priv->mm.interruptible = true;
1882         return ret;
1883 }
1884
1885 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1886 {
1887         i915_gem_object_unpin_fence(obj);
1888         i915_gem_object_unpin_from_display_plane(obj);
1889 }
1890
1891 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892  * is assumed to be a power-of-two. */
1893 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894                                              unsigned int tiling_mode,
1895                                              unsigned int cpp,
1896                                              unsigned int pitch)
1897 {
1898         if (tiling_mode != I915_TILING_NONE) {
1899                 unsigned int tile_rows, tiles;
1900
1901                 tile_rows = *y / 8;
1902                 *y %= 8;
1903
1904                 tiles = *x / (512/cpp);
1905                 *x %= 512/cpp;
1906
1907                 return tile_rows * pitch * 8 + tiles * 4096;
1908         } else {
1909                 unsigned int offset;
1910
1911                 offset = *y * pitch + *x * cpp;
1912                 *y = 0;
1913                 *x = (offset & 4095) / cpp;
1914                 return offset & -4096;
1915         }
1916 }
1917
1918 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1919                              int x, int y)
1920 {
1921         struct drm_device *dev = crtc->dev;
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924         struct intel_framebuffer *intel_fb;
1925         struct drm_i915_gem_object *obj;
1926         int plane = intel_crtc->plane;
1927         unsigned long linear_offset;
1928         u32 dspcntr;
1929         u32 reg;
1930
1931         switch (plane) {
1932         case 0:
1933         case 1:
1934                 break;
1935         default:
1936                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1937                 return -EINVAL;
1938         }
1939
1940         intel_fb = to_intel_framebuffer(fb);
1941         obj = intel_fb->obj;
1942
1943         reg = DSPCNTR(plane);
1944         dspcntr = I915_READ(reg);
1945         /* Mask out pixel format bits in case we change it */
1946         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947         switch (fb->pixel_format) {
1948         case DRM_FORMAT_C8:
1949                 dspcntr |= DISPPLANE_8BPP;
1950                 break;
1951         case DRM_FORMAT_XRGB1555:
1952         case DRM_FORMAT_ARGB1555:
1953                 dspcntr |= DISPPLANE_BGRX555;
1954                 break;
1955         case DRM_FORMAT_RGB565:
1956                 dspcntr |= DISPPLANE_BGRX565;
1957                 break;
1958         case DRM_FORMAT_XRGB8888:
1959         case DRM_FORMAT_ARGB8888:
1960                 dspcntr |= DISPPLANE_BGRX888;
1961                 break;
1962         case DRM_FORMAT_XBGR8888:
1963         case DRM_FORMAT_ABGR8888:
1964                 dspcntr |= DISPPLANE_RGBX888;
1965                 break;
1966         case DRM_FORMAT_XRGB2101010:
1967         case DRM_FORMAT_ARGB2101010:
1968                 dspcntr |= DISPPLANE_BGRX101010;
1969                 break;
1970         case DRM_FORMAT_XBGR2101010:
1971         case DRM_FORMAT_ABGR2101010:
1972                 dspcntr |= DISPPLANE_RGBX101010;
1973                 break;
1974         default:
1975                 BUG();
1976         }
1977
1978         if (INTEL_INFO(dev)->gen >= 4) {
1979                 if (obj->tiling_mode != I915_TILING_NONE)
1980                         dspcntr |= DISPPLANE_TILED;
1981                 else
1982                         dspcntr &= ~DISPPLANE_TILED;
1983         }
1984
1985         if (IS_G4X(dev))
1986                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1987
1988         I915_WRITE(reg, dspcntr);
1989
1990         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1991
1992         if (INTEL_INFO(dev)->gen >= 4) {
1993                 intel_crtc->dspaddr_offset =
1994                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995                                                        fb->bits_per_pixel / 8,
1996                                                        fb->pitches[0]);
1997                 linear_offset -= intel_crtc->dspaddr_offset;
1998         } else {
1999                 intel_crtc->dspaddr_offset = linear_offset;
2000         }
2001
2002         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2004                       fb->pitches[0]);
2005         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006         if (INTEL_INFO(dev)->gen >= 4) {
2007                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2008                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2011         } else
2012                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2013         POSTING_READ(reg);
2014
2015         return 0;
2016 }
2017
2018 static int ironlake_update_plane(struct drm_crtc *crtc,
2019                                  struct drm_framebuffer *fb, int x, int y)
2020 {
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024         struct intel_framebuffer *intel_fb;
2025         struct drm_i915_gem_object *obj;
2026         int plane = intel_crtc->plane;
2027         unsigned long linear_offset;
2028         u32 dspcntr;
2029         u32 reg;
2030
2031         switch (plane) {
2032         case 0:
2033         case 1:
2034         case 2:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->pixel_format) {
2049         case DRM_FORMAT_C8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case DRM_FORMAT_RGB565:
2053                 dspcntr |= DISPPLANE_BGRX565;
2054                 break;
2055         case DRM_FORMAT_XRGB8888:
2056         case DRM_FORMAT_ARGB8888:
2057                 dspcntr |= DISPPLANE_BGRX888;
2058                 break;
2059         case DRM_FORMAT_XBGR8888:
2060         case DRM_FORMAT_ABGR8888:
2061                 dspcntr |= DISPPLANE_RGBX888;
2062                 break;
2063         case DRM_FORMAT_XRGB2101010:
2064         case DRM_FORMAT_ARGB2101010:
2065                 dspcntr |= DISPPLANE_BGRX101010;
2066                 break;
2067         case DRM_FORMAT_XBGR2101010:
2068         case DRM_FORMAT_ABGR2101010:
2069                 dspcntr |= DISPPLANE_RGBX101010;
2070                 break;
2071         default:
2072                 BUG();
2073         }
2074
2075         if (obj->tiling_mode != I915_TILING_NONE)
2076                 dspcntr |= DISPPLANE_TILED;
2077         else
2078                 dspcntr &= ~DISPPLANE_TILED;
2079
2080         if (IS_HASWELL(dev))
2081                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2082         else
2083                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2084
2085         I915_WRITE(reg, dspcntr);
2086
2087         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2088         intel_crtc->dspaddr_offset =
2089                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2090                                                fb->bits_per_pixel / 8,
2091                                                fb->pitches[0]);
2092         linear_offset -= intel_crtc->dspaddr_offset;
2093
2094         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2095                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2096                       fb->pitches[0]);
2097         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2098         I915_MODIFY_DISPBASE(DSPSURF(plane),
2099                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2100         if (IS_HASWELL(dev)) {
2101                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2102         } else {
2103                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2104                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2105         }
2106         POSTING_READ(reg);
2107
2108         return 0;
2109 }
2110
2111 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2112 static int
2113 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2114                            int x, int y, enum mode_set_atomic state)
2115 {
2116         struct drm_device *dev = crtc->dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118
2119         if (dev_priv->display.disable_fbc)
2120                 dev_priv->display.disable_fbc(dev);
2121         intel_increase_pllclock(crtc);
2122
2123         return dev_priv->display.update_plane(crtc, fb, x, y);
2124 }
2125
2126 void intel_display_handle_reset(struct drm_device *dev)
2127 {
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         struct drm_crtc *crtc;
2130
2131         /*
2132          * Flips in the rings have been nuked by the reset,
2133          * so complete all pending flips so that user space
2134          * will get its events and not get stuck.
2135          *
2136          * Also update the base address of all primary
2137          * planes to the the last fb to make sure we're
2138          * showing the correct fb after a reset.
2139          *
2140          * Need to make two loops over the crtcs so that we
2141          * don't try to grab a crtc mutex before the
2142          * pending_flip_queue really got woken up.
2143          */
2144
2145         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2146                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2147                 enum plane plane = intel_crtc->plane;
2148
2149                 intel_prepare_page_flip(dev, plane);
2150                 intel_finish_page_flip_plane(dev, plane);
2151         }
2152
2153         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2154                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2155
2156                 mutex_lock(&crtc->mutex);
2157                 if (intel_crtc->active)
2158                         dev_priv->display.update_plane(crtc, crtc->fb,
2159                                                        crtc->x, crtc->y);
2160                 mutex_unlock(&crtc->mutex);
2161         }
2162 }
2163
2164 static int
2165 intel_finish_fb(struct drm_framebuffer *old_fb)
2166 {
2167         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2168         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2169         bool was_interruptible = dev_priv->mm.interruptible;
2170         int ret;
2171
2172         /* Big Hammer, we also need to ensure that any pending
2173          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2174          * current scanout is retired before unpinning the old
2175          * framebuffer.
2176          *
2177          * This should only fail upon a hung GPU, in which case we
2178          * can safely continue.
2179          */
2180         dev_priv->mm.interruptible = false;
2181         ret = i915_gem_object_finish_gpu(obj);
2182         dev_priv->mm.interruptible = was_interruptible;
2183
2184         return ret;
2185 }
2186
2187 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2188 {
2189         struct drm_device *dev = crtc->dev;
2190         struct drm_i915_master_private *master_priv;
2191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2192
2193         if (!dev->primary->master)
2194                 return;
2195
2196         master_priv = dev->primary->master->driver_priv;
2197         if (!master_priv->sarea_priv)
2198                 return;
2199
2200         switch (intel_crtc->pipe) {
2201         case 0:
2202                 master_priv->sarea_priv->pipeA_x = x;
2203                 master_priv->sarea_priv->pipeA_y = y;
2204                 break;
2205         case 1:
2206                 master_priv->sarea_priv->pipeB_x = x;
2207                 master_priv->sarea_priv->pipeB_y = y;
2208                 break;
2209         default:
2210                 break;
2211         }
2212 }
2213
2214 static int
2215 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2216                     struct drm_framebuffer *fb)
2217 {
2218         struct drm_device *dev = crtc->dev;
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2221         struct drm_framebuffer *old_fb;
2222         int ret;
2223
2224         /* no fb bound */
2225         if (!fb) {
2226                 DRM_ERROR("No FB bound\n");
2227                 return 0;
2228         }
2229
2230         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2231                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2232                           plane_name(intel_crtc->plane),
2233                           INTEL_INFO(dev)->num_pipes);
2234                 return -EINVAL;
2235         }
2236
2237         mutex_lock(&dev->struct_mutex);
2238         ret = intel_pin_and_fence_fb_obj(dev,
2239                                          to_intel_framebuffer(fb)->obj,
2240                                          NULL);
2241         if (ret != 0) {
2242                 mutex_unlock(&dev->struct_mutex);
2243                 DRM_ERROR("pin & fence failed\n");
2244                 return ret;
2245         }
2246
2247         /* Update pipe size and adjust fitter if needed */
2248         if (i915_fastboot) {
2249                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2250                            ((crtc->mode.hdisplay - 1) << 16) |
2251                            (crtc->mode.vdisplay - 1));
2252                 if (!intel_crtc->config.pch_pfit.enabled &&
2253                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2254                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2255                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2256                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2257                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2258                 }
2259         }
2260
2261         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2262         if (ret) {
2263                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2264                 mutex_unlock(&dev->struct_mutex);
2265                 DRM_ERROR("failed to update base address\n");
2266                 return ret;
2267         }
2268
2269         old_fb = crtc->fb;
2270         crtc->fb = fb;
2271         crtc->x = x;
2272         crtc->y = y;
2273
2274         if (old_fb) {
2275                 if (intel_crtc->active && old_fb != fb)
2276                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2277                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2278         }
2279
2280         intel_update_fbc(dev);
2281         intel_edp_psr_update(dev);
2282         mutex_unlock(&dev->struct_mutex);
2283
2284         intel_crtc_update_sarea_pos(crtc, x, y);
2285
2286         return 0;
2287 }
2288
2289 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         int pipe = intel_crtc->pipe;
2295         u32 reg, temp;
2296
2297         /* enable normal train */
2298         reg = FDI_TX_CTL(pipe);
2299         temp = I915_READ(reg);
2300         if (IS_IVYBRIDGE(dev)) {
2301                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2302                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2303         } else {
2304                 temp &= ~FDI_LINK_TRAIN_NONE;
2305                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2306         }
2307         I915_WRITE(reg, temp);
2308
2309         reg = FDI_RX_CTL(pipe);
2310         temp = I915_READ(reg);
2311         if (HAS_PCH_CPT(dev)) {
2312                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2313                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2314         } else {
2315                 temp &= ~FDI_LINK_TRAIN_NONE;
2316                 temp |= FDI_LINK_TRAIN_NONE;
2317         }
2318         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2319
2320         /* wait one idle pattern time */
2321         POSTING_READ(reg);
2322         udelay(1000);
2323
2324         /* IVB wants error correction enabled */
2325         if (IS_IVYBRIDGE(dev))
2326                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2327                            FDI_FE_ERRC_ENABLE);
2328 }
2329
2330 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2331 {
2332         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2333 }
2334
2335 static void ivb_modeset_global_resources(struct drm_device *dev)
2336 {
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct intel_crtc *pipe_B_crtc =
2339                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2340         struct intel_crtc *pipe_C_crtc =
2341                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2342         uint32_t temp;
2343
2344         /*
2345          * When everything is off disable fdi C so that we could enable fdi B
2346          * with all lanes. Note that we don't care about enabled pipes without
2347          * an enabled pch encoder.
2348          */
2349         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2350             !pipe_has_enabled_pch(pipe_C_crtc)) {
2351                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2352                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2353
2354                 temp = I915_READ(SOUTH_CHICKEN1);
2355                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2356                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2357                 I915_WRITE(SOUTH_CHICKEN1, temp);
2358         }
2359 }
2360
2361 /* The FDI link training functions for ILK/Ibexpeak. */
2362 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2363 {
2364         struct drm_device *dev = crtc->dev;
2365         struct drm_i915_private *dev_priv = dev->dev_private;
2366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367         int pipe = intel_crtc->pipe;
2368         int plane = intel_crtc->plane;
2369         u32 reg, temp, tries;
2370
2371         /* FDI needs bits from pipe & plane first */
2372         assert_pipe_enabled(dev_priv, pipe);
2373         assert_plane_enabled(dev_priv, plane);
2374
2375         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2376            for train result */
2377         reg = FDI_RX_IMR(pipe);
2378         temp = I915_READ(reg);
2379         temp &= ~FDI_RX_SYMBOL_LOCK;
2380         temp &= ~FDI_RX_BIT_LOCK;
2381         I915_WRITE(reg, temp);
2382         I915_READ(reg);
2383         udelay(150);
2384
2385         /* enable CPU FDI TX and PCH FDI RX */
2386         reg = FDI_TX_CTL(pipe);
2387         temp = I915_READ(reg);
2388         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2389         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2390         temp &= ~FDI_LINK_TRAIN_NONE;
2391         temp |= FDI_LINK_TRAIN_PATTERN_1;
2392         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2393
2394         reg = FDI_RX_CTL(pipe);
2395         temp = I915_READ(reg);
2396         temp &= ~FDI_LINK_TRAIN_NONE;
2397         temp |= FDI_LINK_TRAIN_PATTERN_1;
2398         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2399
2400         POSTING_READ(reg);
2401         udelay(150);
2402
2403         /* Ironlake workaround, enable clock pointer after FDI enable*/
2404         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406                    FDI_RX_PHASE_SYNC_POINTER_EN);
2407
2408         reg = FDI_RX_IIR(pipe);
2409         for (tries = 0; tries < 5; tries++) {
2410                 temp = I915_READ(reg);
2411                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413                 if ((temp & FDI_RX_BIT_LOCK)) {
2414                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2415                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2416                         break;
2417                 }
2418         }
2419         if (tries == 5)
2420                 DRM_ERROR("FDI train 1 fail!\n");
2421
2422         /* Train 2 */
2423         reg = FDI_TX_CTL(pipe);
2424         temp = I915_READ(reg);
2425         temp &= ~FDI_LINK_TRAIN_NONE;
2426         temp |= FDI_LINK_TRAIN_PATTERN_2;
2427         I915_WRITE(reg, temp);
2428
2429         reg = FDI_RX_CTL(pipe);
2430         temp = I915_READ(reg);
2431         temp &= ~FDI_LINK_TRAIN_NONE;
2432         temp |= FDI_LINK_TRAIN_PATTERN_2;
2433         I915_WRITE(reg, temp);
2434
2435         POSTING_READ(reg);
2436         udelay(150);
2437
2438         reg = FDI_RX_IIR(pipe);
2439         for (tries = 0; tries < 5; tries++) {
2440                 temp = I915_READ(reg);
2441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2442
2443                 if (temp & FDI_RX_SYMBOL_LOCK) {
2444                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2445                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2446                         break;
2447                 }
2448         }
2449         if (tries == 5)
2450                 DRM_ERROR("FDI train 2 fail!\n");
2451
2452         DRM_DEBUG_KMS("FDI train done\n");
2453
2454 }
2455
2456 static const int snb_b_fdi_train_param[] = {
2457         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2458         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2459         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2460         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2461 };
2462
2463 /* The FDI link training functions for SNB/Cougarpoint. */
2464 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2465 {
2466         struct drm_device *dev = crtc->dev;
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469         int pipe = intel_crtc->pipe;
2470         u32 reg, temp, i, retry;
2471
2472         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2473            for train result */
2474         reg = FDI_RX_IMR(pipe);
2475         temp = I915_READ(reg);
2476         temp &= ~FDI_RX_SYMBOL_LOCK;
2477         temp &= ~FDI_RX_BIT_LOCK;
2478         I915_WRITE(reg, temp);
2479
2480         POSTING_READ(reg);
2481         udelay(150);
2482
2483         /* enable CPU FDI TX and PCH FDI RX */
2484         reg = FDI_TX_CTL(pipe);
2485         temp = I915_READ(reg);
2486         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2487         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2488         temp &= ~FDI_LINK_TRAIN_NONE;
2489         temp |= FDI_LINK_TRAIN_PATTERN_1;
2490         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2491         /* SNB-B */
2492         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         I915_WRITE(FDI_RX_MISC(pipe),
2496                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         for (i = 0; i < 4; i++) {
2513                 reg = FDI_TX_CTL(pipe);
2514                 temp = I915_READ(reg);
2515                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516                 temp |= snb_b_fdi_train_param[i];
2517                 I915_WRITE(reg, temp);
2518
2519                 POSTING_READ(reg);
2520                 udelay(500);
2521
2522                 for (retry = 0; retry < 5; retry++) {
2523                         reg = FDI_RX_IIR(pipe);
2524                         temp = I915_READ(reg);
2525                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2526                         if (temp & FDI_RX_BIT_LOCK) {
2527                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2529                                 break;
2530                         }
2531                         udelay(50);
2532                 }
2533                 if (retry < 5)
2534                         break;
2535         }
2536         if (i == 4)
2537                 DRM_ERROR("FDI train 1 fail!\n");
2538
2539         /* Train 2 */
2540         reg = FDI_TX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         temp &= ~FDI_LINK_TRAIN_NONE;
2543         temp |= FDI_LINK_TRAIN_PATTERN_2;
2544         if (IS_GEN6(dev)) {
2545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546                 /* SNB-B */
2547                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548         }
2549         I915_WRITE(reg, temp);
2550
2551         reg = FDI_RX_CTL(pipe);
2552         temp = I915_READ(reg);
2553         if (HAS_PCH_CPT(dev)) {
2554                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2555                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2556         } else {
2557                 temp &= ~FDI_LINK_TRAIN_NONE;
2558                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559         }
2560         I915_WRITE(reg, temp);
2561
2562         POSTING_READ(reg);
2563         udelay(150);
2564
2565         for (i = 0; i < 4; i++) {
2566                 reg = FDI_TX_CTL(pipe);
2567                 temp = I915_READ(reg);
2568                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2569                 temp |= snb_b_fdi_train_param[i];
2570                 I915_WRITE(reg, temp);
2571
2572                 POSTING_READ(reg);
2573                 udelay(500);
2574
2575                 for (retry = 0; retry < 5; retry++) {
2576                         reg = FDI_RX_IIR(pipe);
2577                         temp = I915_READ(reg);
2578                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2579                         if (temp & FDI_RX_SYMBOL_LOCK) {
2580                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2581                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2582                                 break;
2583                         }
2584                         udelay(50);
2585                 }
2586                 if (retry < 5)
2587                         break;
2588         }
2589         if (i == 4)
2590                 DRM_ERROR("FDI train 2 fail!\n");
2591
2592         DRM_DEBUG_KMS("FDI train done.\n");
2593 }
2594
2595 /* Manual link training for Ivy Bridge A0 parts */
2596 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598         struct drm_device *dev = crtc->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601         int pipe = intel_crtc->pipe;
2602         u32 reg, temp, i, j;
2603
2604         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605            for train result */
2606         reg = FDI_RX_IMR(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_RX_SYMBOL_LOCK;
2609         temp &= ~FDI_RX_BIT_LOCK;
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2616                       I915_READ(FDI_RX_IIR(pipe)));
2617
2618         /* Try each vswing and preemphasis setting twice before moving on */
2619         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2620                 /* disable first in case we need to retry */
2621                 reg = FDI_TX_CTL(pipe);
2622                 temp = I915_READ(reg);
2623                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624                 temp &= ~FDI_TX_ENABLE;
2625                 I915_WRITE(reg, temp);
2626
2627                 reg = FDI_RX_CTL(pipe);
2628                 temp = I915_READ(reg);
2629                 temp &= ~FDI_LINK_TRAIN_AUTO;
2630                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631                 temp &= ~FDI_RX_ENABLE;
2632                 I915_WRITE(reg, temp);
2633
2634                 /* enable CPU FDI TX and PCH FDI RX */
2635                 reg = FDI_TX_CTL(pipe);
2636                 temp = I915_READ(reg);
2637                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2638                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2639                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2640                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641                 temp |= snb_b_fdi_train_param[j/2];
2642                 temp |= FDI_COMPOSITE_SYNC;
2643                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2644
2645                 I915_WRITE(FDI_RX_MISC(pipe),
2646                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2647
2648                 reg = FDI_RX_CTL(pipe);
2649                 temp = I915_READ(reg);
2650                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2651                 temp |= FDI_COMPOSITE_SYNC;
2652                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653
2654                 POSTING_READ(reg);
2655                 udelay(1); /* should be 0.5us */
2656
2657                 for (i = 0; i < 4; i++) {
2658                         reg = FDI_RX_IIR(pipe);
2659                         temp = I915_READ(reg);
2660                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662                         if (temp & FDI_RX_BIT_LOCK ||
2663                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2666                                               i);
2667                                 break;
2668                         }
2669                         udelay(1); /* should be 0.5us */
2670                 }
2671                 if (i == 4) {
2672                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2673                         continue;
2674                 }
2675
2676                 /* Train 2 */
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2680                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2681                 I915_WRITE(reg, temp);
2682
2683                 reg = FDI_RX_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2686                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2687                 I915_WRITE(reg, temp);
2688
2689                 POSTING_READ(reg);
2690                 udelay(2); /* should be 1.5us */
2691
2692                 for (i = 0; i < 4; i++) {
2693                         reg = FDI_RX_IIR(pipe);
2694                         temp = I915_READ(reg);
2695                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2696
2697                         if (temp & FDI_RX_SYMBOL_LOCK ||
2698                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2699                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2701                                               i);
2702                                 goto train_done;
2703                         }
2704                         udelay(2); /* should be 1.5us */
2705                 }
2706                 if (i == 4)
2707                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2708         }
2709
2710 train_done:
2711         DRM_DEBUG_KMS("FDI train done.\n");
2712 }
2713
2714 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2715 {
2716         struct drm_device *dev = intel_crtc->base.dev;
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         int pipe = intel_crtc->pipe;
2719         u32 reg, temp;
2720
2721
2722         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2723         reg = FDI_RX_CTL(pipe);
2724         temp = I915_READ(reg);
2725         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2726         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2727         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2728         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Switch from Rawclk to PCDclk */
2734         temp = I915_READ(reg);
2735         I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737         POSTING_READ(reg);
2738         udelay(200);
2739
2740         /* Enable CPU FDI TX PLL, always on for Ironlake */
2741         reg = FDI_TX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2744                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2745
2746                 POSTING_READ(reg);
2747                 udelay(100);
2748         }
2749 }
2750
2751 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2752 {
2753         struct drm_device *dev = intel_crtc->base.dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         int pipe = intel_crtc->pipe;
2756         u32 reg, temp;
2757
2758         /* Switch from PCDclk to Rawclk */
2759         reg = FDI_RX_CTL(pipe);
2760         temp = I915_READ(reg);
2761         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2762
2763         /* Disable CPU FDI TX PLL */
2764         reg = FDI_TX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2767
2768         POSTING_READ(reg);
2769         udelay(100);
2770
2771         reg = FDI_RX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2774
2775         /* Wait for the clocks to turn off. */
2776         POSTING_READ(reg);
2777         udelay(100);
2778 }
2779
2780 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2781 {
2782         struct drm_device *dev = crtc->dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785         int pipe = intel_crtc->pipe;
2786         u32 reg, temp;
2787
2788         /* disable CPU FDI tx and PCH FDI rx */
2789         reg = FDI_TX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2792         POSTING_READ(reg);
2793
2794         reg = FDI_RX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~(0x7 << 16);
2797         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2798         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2799
2800         POSTING_READ(reg);
2801         udelay(100);
2802
2803         /* Ironlake workaround, disable clock pointer after downing FDI */
2804         if (HAS_PCH_IBX(dev)) {
2805                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2806         }
2807
2808         /* still set train pattern 1 */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         temp &= ~FDI_LINK_TRAIN_NONE;
2812         temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         I915_WRITE(reg, temp);
2814
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         if (HAS_PCH_CPT(dev)) {
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2820         } else {
2821                 temp &= ~FDI_LINK_TRAIN_NONE;
2822                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2823         }
2824         /* BPC in FDI rx is consistent with that in PIPECONF */
2825         temp &= ~(0x07 << 16);
2826         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2827         I915_WRITE(reg, temp);
2828
2829         POSTING_READ(reg);
2830         udelay(100);
2831 }
2832
2833 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2834 {
2835         struct drm_device *dev = crtc->dev;
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838         unsigned long flags;
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irqsave(&dev->event_lock, flags);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irqrestore(&dev->event_lock, flags);
2848
2849         return pending;
2850 }
2851
2852 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857         if (crtc->fb == NULL)
2858                 return;
2859
2860         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2861
2862         wait_event(dev_priv->pending_flip_queue,
2863                    !intel_crtc_has_pending_flip(crtc));
2864
2865         mutex_lock(&dev->struct_mutex);
2866         intel_finish_fb(crtc->fb);
2867         mutex_unlock(&dev->struct_mutex);
2868 }
2869
2870 /* Program iCLKIP clock to the desired frequency */
2871 static void lpt_program_iclkip(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_i915_private *dev_priv = dev->dev_private;
2875         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2876         u32 temp;
2877
2878         mutex_lock(&dev_priv->dpio_lock);
2879
2880         /* It is necessary to ungate the pixclk gate prior to programming
2881          * the divisors, and gate it back when it is done.
2882          */
2883         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2884
2885         /* Disable SSCCTL */
2886         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2887                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2888                                 SBI_SSCCTL_DISABLE,
2889                         SBI_ICLK);
2890
2891         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2892         if (crtc->mode.clock == 20000) {
2893                 auxdiv = 1;
2894                 divsel = 0x41;
2895                 phaseinc = 0x20;
2896         } else {
2897                 /* The iCLK virtual clock root frequency is in MHz,
2898                  * but the crtc->mode.clock in in KHz. To get the divisors,
2899                  * it is necessary to divide one by another, so we
2900                  * convert the virtual clock precision to KHz here for higher
2901                  * precision.
2902                  */
2903                 u32 iclk_virtual_root_freq = 172800 * 1000;
2904                 u32 iclk_pi_range = 64;
2905                 u32 desired_divisor, msb_divisor_value, pi_value;
2906
2907                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2908                 msb_divisor_value = desired_divisor / iclk_pi_range;
2909                 pi_value = desired_divisor % iclk_pi_range;
2910
2911                 auxdiv = 0;
2912                 divsel = msb_divisor_value - 2;
2913                 phaseinc = pi_value;
2914         }
2915
2916         /* This should not happen with any sane values */
2917         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2918                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2919         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2920                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2921
2922         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2923                         crtc->mode.clock,
2924                         auxdiv,
2925                         divsel,
2926                         phasedir,
2927                         phaseinc);
2928
2929         /* Program SSCDIVINTPHASE6 */
2930         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2931         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2932         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2933         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2934         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2935         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2936         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2937         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2938
2939         /* Program SSCAUXDIV */
2940         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2941         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2942         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2943         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2944
2945         /* Enable modulator and associated divider */
2946         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2947         temp &= ~SBI_SSCCTL_DISABLE;
2948         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2949
2950         /* Wait for initialization time */
2951         udelay(24);
2952
2953         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2954
2955         mutex_unlock(&dev_priv->dpio_lock);
2956 }
2957
2958 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2959                                                 enum pipe pch_transcoder)
2960 {
2961         struct drm_device *dev = crtc->base.dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2964
2965         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2966                    I915_READ(HTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2968                    I915_READ(HBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2970                    I915_READ(HSYNC(cpu_transcoder)));
2971
2972         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2973                    I915_READ(VTOTAL(cpu_transcoder)));
2974         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2975                    I915_READ(VBLANK(cpu_transcoder)));
2976         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2977                    I915_READ(VSYNC(cpu_transcoder)));
2978         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2979                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2980 }
2981
2982 /*
2983  * Enable PCH resources required for PCH ports:
2984  *   - PCH PLLs
2985  *   - FDI training & RX/TX
2986  *   - update transcoder timings
2987  *   - DP transcoding bits
2988  *   - transcoder
2989  */
2990 static void ironlake_pch_enable(struct drm_crtc *crtc)
2991 {
2992         struct drm_device *dev = crtc->dev;
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995         int pipe = intel_crtc->pipe;
2996         u32 reg, temp;
2997
2998         assert_pch_transcoder_disabled(dev_priv, pipe);
2999
3000         /* Write the TU size bits before fdi link training, so that error
3001          * detection works. */
3002         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3003                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3004
3005         /* For PCH output, training FDI link */
3006         dev_priv->display.fdi_link_train(crtc);
3007
3008         /* We need to program the right clock selection before writing the pixel
3009          * mutliplier into the DPLL. */
3010         if (HAS_PCH_CPT(dev)) {
3011                 u32 sel;
3012
3013                 temp = I915_READ(PCH_DPLL_SEL);
3014                 temp |= TRANS_DPLL_ENABLE(pipe);
3015                 sel = TRANS_DPLLB_SEL(pipe);
3016                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3017                         temp |= sel;
3018                 else
3019                         temp &= ~sel;
3020                 I915_WRITE(PCH_DPLL_SEL, temp);
3021         }
3022
3023         /* XXX: pch pll's can be enabled any time before we enable the PCH
3024          * transcoder, and we actually should do this to not upset any PCH
3025          * transcoder that already use the clock when we share it.
3026          *
3027          * Note that enable_shared_dpll tries to do the right thing, but
3028          * get_shared_dpll unconditionally resets the pll - we need that to have
3029          * the right LVDS enable sequence. */
3030         ironlake_enable_shared_dpll(intel_crtc);
3031
3032         /* set transcoder timing, panel must allow it */
3033         assert_panel_unlocked(dev_priv, pipe);
3034         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3035
3036         intel_fdi_normal_train(crtc);
3037
3038         /* For PCH DP, enable TRANS_DP_CTL */
3039         if (HAS_PCH_CPT(dev) &&
3040             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3041              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3042                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3043                 reg = TRANS_DP_CTL(pipe);
3044                 temp = I915_READ(reg);
3045                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3046                           TRANS_DP_SYNC_MASK |
3047                           TRANS_DP_BPC_MASK);
3048                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3049                          TRANS_DP_ENH_FRAMING);
3050                 temp |= bpc << 9; /* same format but at 11:9 */
3051
3052                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3053                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3054                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3055                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3056
3057                 switch (intel_trans_dp_port_sel(crtc)) {
3058                 case PCH_DP_B:
3059                         temp |= TRANS_DP_PORT_SEL_B;
3060                         break;
3061                 case PCH_DP_C:
3062                         temp |= TRANS_DP_PORT_SEL_C;
3063                         break;
3064                 case PCH_DP_D:
3065                         temp |= TRANS_DP_PORT_SEL_D;
3066                         break;
3067                 default:
3068                         BUG();
3069                 }
3070
3071                 I915_WRITE(reg, temp);
3072         }
3073
3074         ironlake_enable_pch_transcoder(dev_priv, pipe);
3075 }
3076
3077 static void lpt_pch_enable(struct drm_crtc *crtc)
3078 {
3079         struct drm_device *dev = crtc->dev;
3080         struct drm_i915_private *dev_priv = dev->dev_private;
3081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3083
3084         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3085
3086         lpt_program_iclkip(crtc);
3087
3088         /* Set transcoder timing. */
3089         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3090
3091         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3092 }
3093
3094 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3095 {
3096         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3097
3098         if (pll == NULL)
3099                 return;
3100
3101         if (pll->refcount == 0) {
3102                 WARN(1, "bad %s refcount\n", pll->name);
3103                 return;
3104         }
3105
3106         if (--pll->refcount == 0) {
3107                 WARN_ON(pll->on);
3108                 WARN_ON(pll->active);
3109         }
3110
3111         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3112 }
3113
3114 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3115 {
3116         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3117         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3118         enum intel_dpll_id i;
3119
3120         if (pll) {
3121                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3122                               crtc->base.base.id, pll->name);
3123                 intel_put_shared_dpll(crtc);
3124         }
3125
3126         if (HAS_PCH_IBX(dev_priv->dev)) {
3127                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3128                 i = (enum intel_dpll_id) crtc->pipe;
3129                 pll = &dev_priv->shared_dplls[i];
3130
3131                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3132                               crtc->base.base.id, pll->name);
3133
3134                 goto found;
3135         }
3136
3137         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3138                 pll = &dev_priv->shared_dplls[i];
3139
3140                 /* Only want to check enabled timings first */
3141                 if (pll->refcount == 0)
3142                         continue;
3143
3144                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3145                            sizeof(pll->hw_state)) == 0) {
3146                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3147                                       crtc->base.base.id,
3148                                       pll->name, pll->refcount, pll->active);
3149
3150                         goto found;
3151                 }
3152         }
3153
3154         /* Ok no matching timings, maybe there's a free one? */
3155         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3156                 pll = &dev_priv->shared_dplls[i];
3157                 if (pll->refcount == 0) {
3158                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3159                                       crtc->base.base.id, pll->name);
3160                         goto found;
3161                 }
3162         }
3163
3164         return NULL;
3165
3166 found:
3167         crtc->config.shared_dpll = i;
3168         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3169                          pipe_name(crtc->pipe));
3170
3171         if (pll->active == 0) {
3172                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3173                        sizeof(pll->hw_state));
3174
3175                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3176                 WARN_ON(pll->on);
3177                 assert_shared_dpll_disabled(dev_priv, pll);
3178
3179                 pll->mode_set(dev_priv, pll);
3180         }
3181         pll->refcount++;
3182
3183         return pll;
3184 }
3185
3186 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3187 {
3188         struct drm_i915_private *dev_priv = dev->dev_private;
3189         int dslreg = PIPEDSL(pipe);
3190         u32 temp;
3191
3192         temp = I915_READ(dslreg);
3193         udelay(500);
3194         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3195                 if (wait_for(I915_READ(dslreg) != temp, 5))
3196                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3197         }
3198 }
3199
3200 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->base.dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         int pipe = crtc->pipe;
3205
3206         if (crtc->config.pch_pfit.enabled) {
3207                 /* Force use of hard-coded filter coefficients
3208                  * as some pre-programmed values are broken,
3209                  * e.g. x201.
3210                  */
3211                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3212                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3213                                                  PF_PIPE_SEL_IVB(pipe));
3214                 else
3215                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3216                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3217                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3218         }
3219 }
3220
3221 static void intel_enable_planes(struct drm_crtc *crtc)
3222 {
3223         struct drm_device *dev = crtc->dev;
3224         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3225         struct intel_plane *intel_plane;
3226
3227         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3228                 if (intel_plane->pipe == pipe)
3229                         intel_plane_restore(&intel_plane->base);
3230 }
3231
3232 static void intel_disable_planes(struct drm_crtc *crtc)
3233 {
3234         struct drm_device *dev = crtc->dev;
3235         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3236         struct intel_plane *intel_plane;
3237
3238         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3239                 if (intel_plane->pipe == pipe)
3240                         intel_plane_disable(&intel_plane->base);
3241 }
3242
3243 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248         struct intel_encoder *encoder;
3249         int pipe = intel_crtc->pipe;
3250         int plane = intel_crtc->plane;
3251
3252         WARN_ON(!crtc->enabled);
3253
3254         if (intel_crtc->active)
3255                 return;
3256
3257         intel_crtc->active = true;
3258
3259         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3260         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3261
3262         intel_update_watermarks(dev);
3263
3264         for_each_encoder_on_crtc(dev, crtc, encoder)
3265                 if (encoder->pre_enable)
3266                         encoder->pre_enable(encoder);
3267
3268         if (intel_crtc->config.has_pch_encoder) {
3269                 /* Note: FDI PLL enabling _must_ be done before we enable the
3270                  * cpu pipes, hence this is separate from all the other fdi/pch
3271                  * enabling. */
3272                 ironlake_fdi_pll_enable(intel_crtc);
3273         } else {
3274                 assert_fdi_tx_disabled(dev_priv, pipe);
3275                 assert_fdi_rx_disabled(dev_priv, pipe);
3276         }
3277
3278         ironlake_pfit_enable(intel_crtc);
3279
3280         /*
3281          * On ILK+ LUT must be loaded before the pipe is running but with
3282          * clocks enabled
3283          */
3284         intel_crtc_load_lut(crtc);
3285
3286         intel_enable_pipe(dev_priv, pipe,
3287                           intel_crtc->config.has_pch_encoder);
3288         intel_enable_plane(dev_priv, plane, pipe);
3289         intel_enable_planes(crtc);
3290         intel_crtc_update_cursor(crtc, true);
3291
3292         if (intel_crtc->config.has_pch_encoder)
3293                 ironlake_pch_enable(crtc);
3294
3295         mutex_lock(&dev->struct_mutex);
3296         intel_update_fbc(dev);
3297         mutex_unlock(&dev->struct_mutex);
3298
3299         for_each_encoder_on_crtc(dev, crtc, encoder)
3300                 encoder->enable(encoder);
3301
3302         if (HAS_PCH_CPT(dev))
3303                 cpt_verify_modeset(dev, intel_crtc->pipe);
3304
3305         /*
3306          * There seems to be a race in PCH platform hw (at least on some
3307          * outputs) where an enabled pipe still completes any pageflip right
3308          * away (as if the pipe is off) instead of waiting for vblank. As soon
3309          * as the first vblank happend, everything works as expected. Hence just
3310          * wait for one vblank before returning to avoid strange things
3311          * happening.
3312          */
3313         intel_wait_for_vblank(dev, intel_crtc->pipe);
3314 }
3315
3316 /* IPS only exists on ULT machines and is tied to pipe A. */
3317 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3318 {
3319         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3320 }
3321
3322 static void hsw_enable_ips(struct intel_crtc *crtc)
3323 {
3324         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3325
3326         if (!crtc->config.ips_enabled)
3327                 return;
3328
3329         /* We can only enable IPS after we enable a plane and wait for a vblank.
3330          * We guarantee that the plane is enabled by calling intel_enable_ips
3331          * only after intel_enable_plane. And intel_enable_plane already waits
3332          * for a vblank, so all we need to do here is to enable the IPS bit. */
3333         assert_plane_enabled(dev_priv, crtc->plane);
3334         I915_WRITE(IPS_CTL, IPS_ENABLE);
3335 }
3336
3337 static void hsw_disable_ips(struct intel_crtc *crtc)
3338 {
3339         struct drm_device *dev = crtc->base.dev;
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341
3342         if (!crtc->config.ips_enabled)
3343                 return;
3344
3345         assert_plane_enabled(dev_priv, crtc->plane);
3346         I915_WRITE(IPS_CTL, 0);
3347
3348         /* We need to wait for a vblank before we can disable the plane. */
3349         intel_wait_for_vblank(dev, crtc->pipe);
3350 }
3351
3352 static void haswell_crtc_enable(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         struct intel_encoder *encoder;
3358         int pipe = intel_crtc->pipe;
3359         int plane = intel_crtc->plane;
3360
3361         WARN_ON(!crtc->enabled);
3362
3363         if (intel_crtc->active)
3364                 return;
3365
3366         intel_crtc->active = true;
3367
3368         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3369         if (intel_crtc->config.has_pch_encoder)
3370                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3371
3372         intel_update_watermarks(dev);
3373
3374         if (intel_crtc->config.has_pch_encoder)
3375                 dev_priv->display.fdi_link_train(crtc);
3376
3377         for_each_encoder_on_crtc(dev, crtc, encoder)
3378                 if (encoder->pre_enable)
3379                         encoder->pre_enable(encoder);
3380
3381         intel_ddi_enable_pipe_clock(intel_crtc);
3382
3383         ironlake_pfit_enable(intel_crtc);
3384
3385         /*
3386          * On ILK+ LUT must be loaded before the pipe is running but with
3387          * clocks enabled
3388          */
3389         intel_crtc_load_lut(crtc);
3390
3391         intel_ddi_set_pipe_settings(crtc);
3392         intel_ddi_enable_transcoder_func(crtc);
3393
3394         intel_enable_pipe(dev_priv, pipe,
3395                           intel_crtc->config.has_pch_encoder);
3396         intel_enable_plane(dev_priv, plane, pipe);
3397         intel_enable_planes(crtc);
3398         intel_crtc_update_cursor(crtc, true);
3399
3400         hsw_enable_ips(intel_crtc);
3401
3402         if (intel_crtc->config.has_pch_encoder)
3403                 lpt_pch_enable(crtc);
3404
3405         mutex_lock(&dev->struct_mutex);
3406         intel_update_fbc(dev);
3407         mutex_unlock(&dev->struct_mutex);
3408
3409         for_each_encoder_on_crtc(dev, crtc, encoder)
3410                 encoder->enable(encoder);
3411
3412         /*
3413          * There seems to be a race in PCH platform hw (at least on some
3414          * outputs) where an enabled pipe still completes any pageflip right
3415          * away (as if the pipe is off) instead of waiting for vblank. As soon
3416          * as the first vblank happend, everything works as expected. Hence just
3417          * wait for one vblank before returning to avoid strange things
3418          * happening.
3419          */
3420         intel_wait_for_vblank(dev, intel_crtc->pipe);
3421 }
3422
3423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3424 {
3425         struct drm_device *dev = crtc->base.dev;
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427         int pipe = crtc->pipe;
3428
3429         /* To avoid upsetting the power well on haswell only disable the pfit if
3430          * it's in use. The hw state code will make sure we get this right. */
3431         if (crtc->config.pch_pfit.enabled) {
3432                 I915_WRITE(PF_CTL(pipe), 0);
3433                 I915_WRITE(PF_WIN_POS(pipe), 0);
3434                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3435         }
3436 }
3437
3438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3439 {
3440         struct drm_device *dev = crtc->dev;
3441         struct drm_i915_private *dev_priv = dev->dev_private;
3442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3443         struct intel_encoder *encoder;
3444         int pipe = intel_crtc->pipe;
3445         int plane = intel_crtc->plane;
3446         u32 reg, temp;
3447
3448
3449         if (!intel_crtc->active)
3450                 return;
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 encoder->disable(encoder);
3454
3455         intel_crtc_wait_for_pending_flips(crtc);
3456         drm_vblank_off(dev, pipe);
3457
3458         if (dev_priv->fbc.plane == plane)
3459                 intel_disable_fbc(dev);
3460
3461         intel_crtc_update_cursor(crtc, false);
3462         intel_disable_planes(crtc);
3463         intel_disable_plane(dev_priv, plane, pipe);
3464
3465         if (intel_crtc->config.has_pch_encoder)
3466                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3467
3468         intel_disable_pipe(dev_priv, pipe);
3469
3470         ironlake_pfit_disable(intel_crtc);
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 if (encoder->post_disable)
3474                         encoder->post_disable(encoder);
3475
3476         if (intel_crtc->config.has_pch_encoder) {
3477                 ironlake_fdi_disable(crtc);
3478
3479                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3480                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3481
3482                 if (HAS_PCH_CPT(dev)) {
3483                         /* disable TRANS_DP_CTL */
3484                         reg = TRANS_DP_CTL(pipe);
3485                         temp = I915_READ(reg);
3486                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3487                                   TRANS_DP_PORT_SEL_MASK);
3488                         temp |= TRANS_DP_PORT_SEL_NONE;
3489                         I915_WRITE(reg, temp);
3490
3491                         /* disable DPLL_SEL */
3492                         temp = I915_READ(PCH_DPLL_SEL);
3493                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3494                         I915_WRITE(PCH_DPLL_SEL, temp);
3495                 }
3496
3497                 /* disable PCH DPLL */
3498                 intel_disable_shared_dpll(intel_crtc);
3499
3500                 ironlake_fdi_pll_disable(intel_crtc);
3501         }
3502
3503         intel_crtc->active = false;
3504         intel_update_watermarks(dev);
3505
3506         mutex_lock(&dev->struct_mutex);
3507         intel_update_fbc(dev);
3508         mutex_unlock(&dev->struct_mutex);
3509 }
3510
3511 static void haswell_crtc_disable(struct drm_crtc *crtc)
3512 {
3513         struct drm_device *dev = crtc->dev;
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         struct intel_encoder *encoder;
3517         int pipe = intel_crtc->pipe;
3518         int plane = intel_crtc->plane;
3519         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3520
3521         if (!intel_crtc->active)
3522                 return;
3523
3524         for_each_encoder_on_crtc(dev, crtc, encoder)
3525                 encoder->disable(encoder);
3526
3527         intel_crtc_wait_for_pending_flips(crtc);
3528         drm_vblank_off(dev, pipe);
3529
3530         /* FBC must be disabled before disabling the plane on HSW. */
3531         if (dev_priv->fbc.plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         hsw_disable_ips(intel_crtc);
3535
3536         intel_crtc_update_cursor(crtc, false);
3537         intel_disable_planes(crtc);
3538         intel_disable_plane(dev_priv, plane, pipe);
3539
3540         if (intel_crtc->config.has_pch_encoder)
3541                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3542         intel_disable_pipe(dev_priv, pipe);
3543
3544         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3545
3546         ironlake_pfit_disable(intel_crtc);
3547
3548         intel_ddi_disable_pipe_clock(intel_crtc);
3549
3550         for_each_encoder_on_crtc(dev, crtc, encoder)
3551                 if (encoder->post_disable)
3552                         encoder->post_disable(encoder);
3553
3554         if (intel_crtc->config.has_pch_encoder) {
3555                 lpt_disable_pch_transcoder(dev_priv);
3556                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3557                 intel_ddi_fdi_disable(crtc);
3558         }
3559
3560         intel_crtc->active = false;
3561         intel_update_watermarks(dev);
3562
3563         mutex_lock(&dev->struct_mutex);
3564         intel_update_fbc(dev);
3565         mutex_unlock(&dev->struct_mutex);
3566 }
3567
3568 static void ironlake_crtc_off(struct drm_crtc *crtc)
3569 {
3570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571         intel_put_shared_dpll(intel_crtc);
3572 }
3573
3574 static void haswell_crtc_off(struct drm_crtc *crtc)
3575 {
3576         intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581         if (!enable && intel_crtc->overlay) {
3582                 struct drm_device *dev = intel_crtc->base.dev;
3583                 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585                 mutex_lock(&dev->struct_mutex);
3586                 dev_priv->mm.interruptible = false;
3587                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588                 dev_priv->mm.interruptible = true;
3589                 mutex_unlock(&dev->struct_mutex);
3590         }
3591
3592         /* Let userspace switch the overlay on again. In most cases userspace
3593          * has to recompute where to put it anyway.
3594          */
3595 }
3596
3597 /**
3598  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599  * cursor plane briefly if not already running after enabling the display
3600  * plane.
3601  * This workaround avoids occasional blank screens when self refresh is
3602  * enabled.
3603  */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607         u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609         if ((cntl & CURSOR_MODE) == 0) {
3610                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614                 intel_wait_for_vblank(dev_priv->dev, pipe);
3615                 I915_WRITE(CURCNTR(pipe), cntl);
3616                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618         }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->base.dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627         if (!crtc->config.gmch_pfit.control)
3628                 return;
3629
3630         /*
3631          * The panel fitter should only be adjusted whilst the pipe is disabled,
3632          * according to register description and PRM.
3633          */
3634         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3635         assert_pipe_disabled(dev_priv, crtc->pipe);
3636
3637         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3638         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3639
3640         /* Border color in case we don't scale up to the full screen. Black by
3641          * default, change to something else for debugging. */
3642         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3643 }
3644
3645 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->dev;
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         struct intel_encoder *encoder;
3651         int pipe = intel_crtc->pipe;
3652         int plane = intel_crtc->plane;
3653
3654         WARN_ON(!crtc->enabled);
3655
3656         if (intel_crtc->active)
3657                 return;
3658
3659         intel_crtc->active = true;
3660         intel_update_watermarks(dev);
3661
3662         for_each_encoder_on_crtc(dev, crtc, encoder)
3663                 if (encoder->pre_pll_enable)
3664                         encoder->pre_pll_enable(encoder);
3665
3666         vlv_enable_pll(intel_crtc);
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 if (encoder->pre_enable)
3670                         encoder->pre_enable(encoder);
3671
3672         i9xx_pfit_enable(intel_crtc);
3673
3674         intel_crtc_load_lut(crtc);
3675
3676         intel_enable_pipe(dev_priv, pipe, false);
3677         intel_enable_plane(dev_priv, plane, pipe);
3678         intel_enable_planes(crtc);
3679         intel_crtc_update_cursor(crtc, true);
3680
3681         intel_update_fbc(dev);
3682
3683         for_each_encoder_on_crtc(dev, crtc, encoder)
3684                 encoder->enable(encoder);
3685 }
3686
3687 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3688 {
3689         struct drm_device *dev = crtc->dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692         struct intel_encoder *encoder;
3693         int pipe = intel_crtc->pipe;
3694         int plane = intel_crtc->plane;
3695
3696         WARN_ON(!crtc->enabled);
3697
3698         if (intel_crtc->active)
3699                 return;
3700
3701         intel_crtc->active = true;
3702         intel_update_watermarks(dev);
3703
3704         for_each_encoder_on_crtc(dev, crtc, encoder)
3705                 if (encoder->pre_enable)
3706                         encoder->pre_enable(encoder);
3707
3708         i9xx_enable_pll(intel_crtc);
3709
3710         i9xx_pfit_enable(intel_crtc);
3711
3712         intel_crtc_load_lut(crtc);
3713
3714         intel_enable_pipe(dev_priv, pipe, false);
3715         intel_enable_plane(dev_priv, plane, pipe);
3716         intel_enable_planes(crtc);
3717         /* The fixup needs to happen before cursor is enabled */
3718         if (IS_G4X(dev))
3719                 g4x_fixup_plane(dev_priv, pipe);
3720         intel_crtc_update_cursor(crtc, true);
3721
3722         /* Give the overlay scaler a chance to enable if it's on this pipe */
3723         intel_crtc_dpms_overlay(intel_crtc, true);
3724
3725         intel_update_fbc(dev);
3726
3727         for_each_encoder_on_crtc(dev, crtc, encoder)
3728                 encoder->enable(encoder);
3729 }
3730
3731 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->base.dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736         if (!crtc->config.gmch_pfit.control)
3737                 return;
3738
3739         assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3742                          I915_READ(PFIT_CONTROL));
3743         I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745
3746 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3747 {
3748         struct drm_device *dev = crtc->dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         struct intel_encoder *encoder;
3752         int pipe = intel_crtc->pipe;
3753         int plane = intel_crtc->plane;
3754
3755         if (!intel_crtc->active)
3756                 return;
3757
3758         for_each_encoder_on_crtc(dev, crtc, encoder)
3759                 encoder->disable(encoder);
3760
3761         /* Give the overlay scaler a chance to disable if it's on this pipe */
3762         intel_crtc_wait_for_pending_flips(crtc);
3763         drm_vblank_off(dev, pipe);
3764
3765         if (dev_priv->fbc.plane == plane)
3766                 intel_disable_fbc(dev);
3767
3768         intel_crtc_dpms_overlay(intel_crtc, false);
3769         intel_crtc_update_cursor(crtc, false);
3770         intel_disable_planes(crtc);
3771         intel_disable_plane(dev_priv, plane, pipe);
3772
3773         intel_disable_pipe(dev_priv, pipe);
3774
3775         i9xx_pfit_disable(intel_crtc);
3776
3777         for_each_encoder_on_crtc(dev, crtc, encoder)
3778                 if (encoder->post_disable)
3779                         encoder->post_disable(encoder);
3780
3781         i9xx_disable_pll(dev_priv, pipe);
3782
3783         intel_crtc->active = false;
3784         intel_update_fbc(dev);
3785         intel_update_watermarks(dev);
3786 }
3787
3788 static void i9xx_crtc_off(struct drm_crtc *crtc)
3789 {
3790 }
3791
3792 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793                                     bool enabled)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_master_private *master_priv;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         int pipe = intel_crtc->pipe;
3799
3800         if (!dev->primary->master)
3801                 return;
3802
3803         master_priv = dev->primary->master->driver_priv;
3804         if (!master_priv->sarea_priv)
3805                 return;
3806
3807         switch (pipe) {
3808         case 0:
3809                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811                 break;
3812         case 1:
3813                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815                 break;
3816         default:
3817                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3818                 break;
3819         }
3820 }
3821
3822 /**
3823  * Sets the power management mode of the pipe and plane.
3824  */
3825 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_encoder *intel_encoder;
3830         bool enable = false;
3831
3832         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833                 enable |= intel_encoder->connectors_active;
3834
3835         if (enable)
3836                 dev_priv->display.crtc_enable(crtc);
3837         else
3838                 dev_priv->display.crtc_disable(crtc);
3839
3840         intel_crtc_update_sarea(crtc, enable);
3841 }
3842
3843 static void intel_crtc_disable(struct drm_crtc *crtc)
3844 {
3845         struct drm_device *dev = crtc->dev;
3846         struct drm_connector *connector;
3847         struct drm_i915_private *dev_priv = dev->dev_private;
3848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849
3850         /* crtc should still be enabled when we disable it. */
3851         WARN_ON(!crtc->enabled);
3852
3853         dev_priv->display.crtc_disable(crtc);
3854         intel_crtc->eld_vld = false;
3855         intel_crtc_update_sarea(crtc, false);
3856         dev_priv->display.off(crtc);
3857
3858         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3860
3861         if (crtc->fb) {
3862                 mutex_lock(&dev->struct_mutex);
3863                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3864                 mutex_unlock(&dev->struct_mutex);
3865                 crtc->fb = NULL;
3866         }
3867
3868         /* Update computed state. */
3869         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870                 if (!connector->encoder || !connector->encoder->crtc)
3871                         continue;
3872
3873                 if (connector->encoder->crtc != crtc)
3874                         continue;
3875
3876                 connector->dpms = DRM_MODE_DPMS_OFF;
3877                 to_intel_encoder(connector->encoder)->connectors_active = false;
3878         }
3879 }
3880
3881 void intel_encoder_destroy(struct drm_encoder *encoder)
3882 {
3883         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3884
3885         drm_encoder_cleanup(encoder);
3886         kfree(intel_encoder);
3887 }
3888
3889 /* Simple dpms helper for encoders with just one connector, no cloning and only
3890  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3891  * state of the entire output pipe. */
3892 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3893 {
3894         if (mode == DRM_MODE_DPMS_ON) {
3895                 encoder->connectors_active = true;
3896
3897                 intel_crtc_update_dpms(encoder->base.crtc);
3898         } else {
3899                 encoder->connectors_active = false;
3900
3901                 intel_crtc_update_dpms(encoder->base.crtc);
3902         }
3903 }
3904
3905 /* Cross check the actual hw state with our own modeset state tracking (and it's
3906  * internal consistency). */
3907 static void intel_connector_check_state(struct intel_connector *connector)
3908 {
3909         if (connector->get_hw_state(connector)) {
3910                 struct intel_encoder *encoder = connector->encoder;
3911                 struct drm_crtc *crtc;
3912                 bool encoder_enabled;
3913                 enum pipe pipe;
3914
3915                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3916                               connector->base.base.id,
3917                               drm_get_connector_name(&connector->base));
3918
3919                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3920                      "wrong connector dpms state\n");
3921                 WARN(connector->base.encoder != &encoder->base,
3922                      "active connector not linked to encoder\n");
3923                 WARN(!encoder->connectors_active,
3924                      "encoder->connectors_active not set\n");
3925
3926                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3927                 WARN(!encoder_enabled, "encoder not enabled\n");
3928                 if (WARN_ON(!encoder->base.crtc))
3929                         return;
3930
3931                 crtc = encoder->base.crtc;
3932
3933                 WARN(!crtc->enabled, "crtc not enabled\n");
3934                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3935                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3936                      "encoder active on the wrong pipe\n");
3937         }
3938 }
3939
3940 /* Even simpler default implementation, if there's really no special case to
3941  * consider. */
3942 void intel_connector_dpms(struct drm_connector *connector, int mode)
3943 {
3944         /* All the simple cases only support two dpms states. */
3945         if (mode != DRM_MODE_DPMS_ON)
3946                 mode = DRM_MODE_DPMS_OFF;
3947
3948         if (mode == connector->dpms)
3949                 return;
3950
3951         connector->dpms = mode;
3952
3953         /* Only need to change hw state when actually enabled */
3954         if (connector->encoder)
3955                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3956
3957         intel_modeset_check_state(connector->dev);
3958 }
3959
3960 /* Simple connector->get_hw_state implementation for encoders that support only
3961  * one connector and no cloning and hence the encoder state determines the state
3962  * of the connector. */
3963 bool intel_connector_get_hw_state(struct intel_connector *connector)
3964 {
3965         enum pipe pipe = 0;
3966         struct intel_encoder *encoder = connector->encoder;
3967
3968         return encoder->get_hw_state(encoder, &pipe);
3969 }
3970
3971 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3972                                      struct intel_crtc_config *pipe_config)
3973 {
3974         struct drm_i915_private *dev_priv = dev->dev_private;
3975         struct intel_crtc *pipe_B_crtc =
3976                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3977
3978         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3979                       pipe_name(pipe), pipe_config->fdi_lanes);
3980         if (pipe_config->fdi_lanes > 4) {
3981                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3982                               pipe_name(pipe), pipe_config->fdi_lanes);
3983                 return false;
3984         }
3985
3986         if (IS_HASWELL(dev)) {
3987                 if (pipe_config->fdi_lanes > 2) {
3988                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3989                                       pipe_config->fdi_lanes);
3990                         return false;
3991                 } else {
3992                         return true;
3993                 }
3994         }
3995
3996         if (INTEL_INFO(dev)->num_pipes == 2)
3997                 return true;
3998
3999         /* Ivybridge 3 pipe is really complicated */
4000         switch (pipe) {
4001         case PIPE_A:
4002                 return true;
4003         case PIPE_B:
4004                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4005                     pipe_config->fdi_lanes > 2) {
4006                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007                                       pipe_name(pipe), pipe_config->fdi_lanes);
4008                         return false;
4009                 }
4010                 return true;
4011         case PIPE_C:
4012                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4013                     pipe_B_crtc->config.fdi_lanes <= 2) {
4014                         if (pipe_config->fdi_lanes > 2) {
4015                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4016                                               pipe_name(pipe), pipe_config->fdi_lanes);
4017                                 return false;
4018                         }
4019                 } else {
4020                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4021                         return false;
4022                 }
4023                 return true;
4024         default:
4025                 BUG();
4026         }
4027 }
4028
4029 #define RETRY 1
4030 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4031                                        struct intel_crtc_config *pipe_config)
4032 {
4033         struct drm_device *dev = intel_crtc->base.dev;
4034         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4035         int lane, link_bw, fdi_dotclock;
4036         bool setup_ok, needs_recompute = false;
4037
4038 retry:
4039         /* FDI is a binary signal running at ~2.7GHz, encoding
4040          * each output octet as 10 bits. The actual frequency
4041          * is stored as a divider into a 100MHz clock, and the
4042          * mode pixel clock is stored in units of 1KHz.
4043          * Hence the bw of each lane in terms of the mode signal
4044          * is:
4045          */
4046         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4047
4048         fdi_dotclock = adjusted_mode->clock;
4049         fdi_dotclock /= pipe_config->pixel_multiplier;
4050
4051         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4052                                            pipe_config->pipe_bpp);
4053
4054         pipe_config->fdi_lanes = lane;
4055
4056         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4057                                link_bw, &pipe_config->fdi_m_n);
4058
4059         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4060                                             intel_crtc->pipe, pipe_config);
4061         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4062                 pipe_config->pipe_bpp -= 2*3;
4063                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4064                               pipe_config->pipe_bpp);
4065                 needs_recompute = true;
4066                 pipe_config->bw_constrained = true;
4067
4068                 goto retry;
4069         }
4070
4071         if (needs_recompute)
4072                 return RETRY;
4073
4074         return setup_ok ? 0 : -EINVAL;
4075 }
4076
4077 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4078                                    struct intel_crtc_config *pipe_config)
4079 {
4080         pipe_config->ips_enabled = i915_enable_ips &&
4081                                    hsw_crtc_supports_ips(crtc) &&
4082                                    pipe_config->pipe_bpp <= 24;
4083 }
4084
4085 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4086                                      struct intel_crtc_config *pipe_config)
4087 {
4088         struct drm_device *dev = crtc->base.dev;
4089         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4090
4091         if (HAS_PCH_SPLIT(dev)) {
4092                 /* FDI link clock is fixed at 2.7G */
4093                 if (pipe_config->requested_mode.clock * 3
4094                     > IRONLAKE_FDI_FREQ * 4)
4095                         return -EINVAL;
4096         }
4097
4098         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4099          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4100          */
4101         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4102                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4103                 return -EINVAL;
4104
4105         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4106                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4107         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4108                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4109                  * for lvds. */
4110                 pipe_config->pipe_bpp = 8*3;
4111         }
4112
4113         if (HAS_IPS(dev))
4114                 hsw_compute_ips_config(crtc, pipe_config);
4115
4116         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4117          * clock survives for now. */
4118         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4119                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4120
4121         if (pipe_config->has_pch_encoder)
4122                 return ironlake_fdi_compute_config(crtc, pipe_config);
4123
4124         return 0;
4125 }
4126
4127 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4128 {
4129         return 400000; /* FIXME */
4130 }
4131
4132 static int i945_get_display_clock_speed(struct drm_device *dev)
4133 {
4134         return 400000;
4135 }
4136
4137 static int i915_get_display_clock_speed(struct drm_device *dev)
4138 {
4139         return 333000;
4140 }
4141
4142 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4143 {
4144         return 200000;
4145 }
4146
4147 static int pnv_get_display_clock_speed(struct drm_device *dev)
4148 {
4149         u16 gcfgc = 0;
4150
4151         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4152
4153         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4155                 return 267000;
4156         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4157                 return 333000;
4158         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4159                 return 444000;
4160         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4161                 return 200000;
4162         default:
4163                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4164         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4165                 return 133000;
4166         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4167                 return 167000;
4168         }
4169 }
4170
4171 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4172 {
4173         u16 gcfgc = 0;
4174
4175         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4176
4177         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4178                 return 133000;
4179         else {
4180                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4181                 case GC_DISPLAY_CLOCK_333_MHZ:
4182                         return 333000;
4183                 default:
4184                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4185                         return 190000;
4186                 }
4187         }
4188 }
4189
4190 static int i865_get_display_clock_speed(struct drm_device *dev)
4191 {
4192         return 266000;
4193 }
4194
4195 static int i855_get_display_clock_speed(struct drm_device *dev)
4196 {
4197         u16 hpllcc = 0;
4198         /* Assume that the hardware is in the high speed state.  This
4199          * should be the default.
4200          */
4201         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4202         case GC_CLOCK_133_200:
4203         case GC_CLOCK_100_200:
4204                 return 200000;
4205         case GC_CLOCK_166_250:
4206                 return 250000;
4207         case GC_CLOCK_100_133:
4208                 return 133000;
4209         }
4210
4211         /* Shouldn't happen */
4212         return 0;
4213 }
4214
4215 static int i830_get_display_clock_speed(struct drm_device *dev)
4216 {
4217         return 133000;
4218 }
4219
4220 static void
4221 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4222 {
4223         while (*num > DATA_LINK_M_N_MASK ||
4224                *den > DATA_LINK_M_N_MASK) {
4225                 *num >>= 1;
4226                 *den >>= 1;
4227         }
4228 }
4229
4230 static void compute_m_n(unsigned int m, unsigned int n,
4231                         uint32_t *ret_m, uint32_t *ret_n)
4232 {
4233         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4234         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4235         intel_reduce_m_n_ratio(ret_m, ret_n);
4236 }
4237
4238 void
4239 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4240                        int pixel_clock, int link_clock,
4241                        struct intel_link_m_n *m_n)
4242 {
4243         m_n->tu = 64;
4244
4245         compute_m_n(bits_per_pixel * pixel_clock,
4246                     link_clock * nlanes * 8,
4247                     &m_n->gmch_m, &m_n->gmch_n);
4248
4249         compute_m_n(pixel_clock, link_clock,
4250                     &m_n->link_m, &m_n->link_n);
4251 }
4252
4253 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4254 {
4255         if (i915_panel_use_ssc >= 0)
4256                 return i915_panel_use_ssc != 0;
4257         return dev_priv->vbt.lvds_use_ssc
4258                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4259 }
4260
4261 static int vlv_get_refclk(struct drm_crtc *crtc)
4262 {
4263         struct drm_device *dev = crtc->dev;
4264         struct drm_i915_private *dev_priv = dev->dev_private;
4265         int refclk = 27000; /* for DP & HDMI */
4266
4267         return 100000; /* only one validated so far */
4268
4269         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4270                 refclk = 96000;
4271         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4272                 if (intel_panel_use_ssc(dev_priv))
4273                         refclk = 100000;
4274                 else
4275                         refclk = 96000;
4276         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4277                 refclk = 100000;
4278         }
4279
4280         return refclk;
4281 }
4282
4283 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4284 {
4285         struct drm_device *dev = crtc->dev;
4286         struct drm_i915_private *dev_priv = dev->dev_private;
4287         int refclk;
4288
4289         if (IS_VALLEYVIEW(dev)) {
4290                 refclk = vlv_get_refclk(crtc);
4291         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4292             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4293                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4294                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4295                               refclk / 1000);
4296         } else if (!IS_GEN2(dev)) {
4297                 refclk = 96000;
4298         } else {
4299                 refclk = 48000;
4300         }
4301
4302         return refclk;
4303 }
4304
4305 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4306 {
4307         return (1 << dpll->n) << 16 | dpll->m2;
4308 }
4309
4310 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4311 {
4312         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4313 }
4314
4315 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4316                                      intel_clock_t *reduced_clock)
4317 {
4318         struct drm_device *dev = crtc->base.dev;
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         int pipe = crtc->pipe;
4321         u32 fp, fp2 = 0;
4322
4323         if (IS_PINEVIEW(dev)) {
4324                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4325                 if (reduced_clock)
4326                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4327         } else {
4328                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4329                 if (reduced_clock)
4330                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4331         }
4332
4333         I915_WRITE(FP0(pipe), fp);
4334         crtc->config.dpll_hw_state.fp0 = fp;
4335
4336         crtc->lowfreq_avail = false;
4337         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4338             reduced_clock && i915_powersave) {
4339                 I915_WRITE(FP1(pipe), fp2);
4340                 crtc->config.dpll_hw_state.fp1 = fp2;
4341                 crtc->lowfreq_avail = true;
4342         } else {
4343                 I915_WRITE(FP1(pipe), fp);
4344                 crtc->config.dpll_hw_state.fp1 = fp;
4345         }
4346 }
4347
4348 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4349 {
4350         u32 reg_val;
4351
4352         /*
4353          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4354          * and set it to a reasonable value instead.
4355          */
4356         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4357         reg_val &= 0xffffff00;
4358         reg_val |= 0x00000030;
4359         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4360
4361         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4362         reg_val &= 0x8cffffff;
4363         reg_val = 0x8c000000;
4364         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4365
4366         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4367         reg_val &= 0xffffff00;
4368         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4369
4370         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4371         reg_val &= 0x00ffffff;
4372         reg_val |= 0xb0000000;
4373         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4374 }
4375
4376 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4377                                          struct intel_link_m_n *m_n)
4378 {
4379         struct drm_device *dev = crtc->base.dev;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381         int pipe = crtc->pipe;
4382
4383         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4385         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4386         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4387 }
4388
4389 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4390                                          struct intel_link_m_n *m_n)
4391 {
4392         struct drm_device *dev = crtc->base.dev;
4393         struct drm_i915_private *dev_priv = dev->dev_private;
4394         int pipe = crtc->pipe;
4395         enum transcoder transcoder = crtc->config.cpu_transcoder;
4396
4397         if (INTEL_INFO(dev)->gen >= 5) {
4398                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4399                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4400                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4401                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4402         } else {
4403                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4404                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4405                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4406                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4407         }
4408 }
4409
4410 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4411 {
4412         if (crtc->config.has_pch_encoder)
4413                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4414         else
4415                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4416 }
4417
4418 static void vlv_update_pll(struct intel_crtc *crtc)
4419 {
4420         struct drm_device *dev = crtc->base.dev;
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         int pipe = crtc->pipe;
4423         u32 dpll, mdiv;
4424         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4425         u32 coreclk, reg_val, dpll_md;
4426
4427         mutex_lock(&dev_priv->dpio_lock);
4428
4429         bestn = crtc->config.dpll.n;
4430         bestm1 = crtc->config.dpll.m1;
4431         bestm2 = crtc->config.dpll.m2;
4432         bestp1 = crtc->config.dpll.p1;
4433         bestp2 = crtc->config.dpll.p2;
4434
4435         /* See eDP HDMI DPIO driver vbios notes doc */
4436
4437         /* PLL B needs special handling */
4438         if (pipe)
4439                 vlv_pllb_recal_opamp(dev_priv);
4440
4441         /* Set up Tx target for periodic Rcomp update */
4442         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4443
4444         /* Disable target IRef on PLL */
4445         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4446         reg_val &= 0x00ffffff;
4447         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4448
4449         /* Disable fast lock */
4450         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4451
4452         /* Set idtafcrecal before PLL is enabled */
4453         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4454         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4455         mdiv |= ((bestn << DPIO_N_SHIFT));
4456         mdiv |= (1 << DPIO_K_SHIFT);
4457
4458         /*
4459          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4460          * but we don't support that).
4461          * Note: don't use the DAC post divider as it seems unstable.
4462          */
4463         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4464         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4465
4466         mdiv |= DPIO_ENABLE_CALIBRATION;
4467         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4468
4469         /* Set HBR and RBR LPF coefficients */
4470         if (crtc->config.port_clock == 162000 ||
4471             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4472             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4473                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4474                                  0x009f0003);
4475         else
4476                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4477                                  0x00d0000f);
4478
4479         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4480             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4481                 /* Use SSC source */
4482                 if (!pipe)
4483                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4484                                          0x0df40000);
4485                 else
4486                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4487                                          0x0df70000);
4488         } else { /* HDMI or VGA */
4489                 /* Use bend source */
4490                 if (!pipe)
4491                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4492                                          0x0df70000);
4493                 else
4494                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4495                                          0x0df40000);
4496         }
4497
4498         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4499         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4500         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4501             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4502                 coreclk |= 0x01000000;
4503         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4504
4505         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4506
4507         /* Enable DPIO clock input */
4508         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4509                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4510         if (pipe)
4511                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4512
4513         dpll |= DPLL_VCO_ENABLE;
4514         crtc->config.dpll_hw_state.dpll = dpll;
4515
4516         dpll_md = (crtc->config.pixel_multiplier - 1)
4517                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4518         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4519
4520         if (crtc->config.has_dp_encoder)
4521                 intel_dp_set_m_n(crtc);
4522
4523         mutex_unlock(&dev_priv->dpio_lock);
4524 }
4525
4526 static void i9xx_update_pll(struct intel_crtc *crtc,
4527                             intel_clock_t *reduced_clock,
4528                             int num_connectors)
4529 {
4530         struct drm_device *dev = crtc->base.dev;
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532         u32 dpll;
4533         bool is_sdvo;
4534         struct dpll *clock = &crtc->config.dpll;
4535
4536         i9xx_update_pll_dividers(crtc, reduced_clock);
4537
4538         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4540
4541         dpll = DPLL_VGA_MODE_DIS;
4542
4543         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4544                 dpll |= DPLLB_MODE_LVDS;
4545         else
4546                 dpll |= DPLLB_MODE_DAC_SERIAL;
4547
4548         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4549                 dpll |= (crtc->config.pixel_multiplier - 1)
4550                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4551         }
4552
4553         if (is_sdvo)
4554                 dpll |= DPLL_SDVO_HIGH_SPEED;
4555
4556         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4557                 dpll |= DPLL_SDVO_HIGH_SPEED;
4558
4559         /* compute bitmask from p1 value */
4560         if (IS_PINEVIEW(dev))
4561                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4562         else {
4563                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564                 if (IS_G4X(dev) && reduced_clock)
4565                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4566         }
4567         switch (clock->p2) {
4568         case 5:
4569                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4570                 break;
4571         case 7:
4572                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4573                 break;
4574         case 10:
4575                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4576                 break;
4577         case 14:
4578                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4579                 break;
4580         }
4581         if (INTEL_INFO(dev)->gen >= 4)
4582                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4583
4584         if (crtc->config.sdvo_tv_clock)
4585                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4586         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4587                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4588                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4589         else
4590                 dpll |= PLL_REF_INPUT_DREFCLK;
4591
4592         dpll |= DPLL_VCO_ENABLE;
4593         crtc->config.dpll_hw_state.dpll = dpll;
4594
4595         if (INTEL_INFO(dev)->gen >= 4) {
4596                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4597                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4598                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4599         }
4600
4601         if (crtc->config.has_dp_encoder)
4602                 intel_dp_set_m_n(crtc);
4603 }
4604
4605 static void i8xx_update_pll(struct intel_crtc *crtc,
4606                             intel_clock_t *reduced_clock,
4607                             int num_connectors)
4608 {
4609         struct drm_device *dev = crtc->base.dev;
4610         struct drm_i915_private *dev_priv = dev->dev_private;
4611         u32 dpll;
4612         struct dpll *clock = &crtc->config.dpll;
4613
4614         i9xx_update_pll_dividers(crtc, reduced_clock);
4615
4616         dpll = DPLL_VGA_MODE_DIS;
4617
4618         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4619                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620         } else {
4621                 if (clock->p1 == 2)
4622                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4623                 else
4624                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625                 if (clock->p2 == 4)
4626                         dpll |= PLL_P2_DIVIDE_BY_4;
4627         }
4628
4629         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4630                 dpll |= DPLL_DVO_2X_MODE;
4631
4632         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4633                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4634                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4635         else
4636                 dpll |= PLL_REF_INPUT_DREFCLK;
4637
4638         dpll |= DPLL_VCO_ENABLE;
4639         crtc->config.dpll_hw_state.dpll = dpll;
4640 }
4641
4642 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4643 {
4644         struct drm_device *dev = intel_crtc->base.dev;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         enum pipe pipe = intel_crtc->pipe;
4647         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4648         struct drm_display_mode *adjusted_mode =
4649                 &intel_crtc->config.adjusted_mode;
4650         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4651         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4652
4653         /* We need to be careful not to changed the adjusted mode, for otherwise
4654          * the hw state checker will get angry at the mismatch. */
4655         crtc_vtotal = adjusted_mode->crtc_vtotal;
4656         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4657
4658         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4659                 /* the chip adds 2 halflines automatically */
4660                 crtc_vtotal -= 1;
4661                 crtc_vblank_end -= 1;
4662                 vsyncshift = adjusted_mode->crtc_hsync_start
4663                              - adjusted_mode->crtc_htotal / 2;
4664         } else {
4665                 vsyncshift = 0;
4666         }
4667
4668         if (INTEL_INFO(dev)->gen > 3)
4669                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4670
4671         I915_WRITE(HTOTAL(cpu_transcoder),
4672                    (adjusted_mode->crtc_hdisplay - 1) |
4673                    ((adjusted_mode->crtc_htotal - 1) << 16));
4674         I915_WRITE(HBLANK(cpu_transcoder),
4675                    (adjusted_mode->crtc_hblank_start - 1) |
4676                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4677         I915_WRITE(HSYNC(cpu_transcoder),
4678                    (adjusted_mode->crtc_hsync_start - 1) |
4679                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4680
4681         I915_WRITE(VTOTAL(cpu_transcoder),
4682                    (adjusted_mode->crtc_vdisplay - 1) |
4683                    ((crtc_vtotal - 1) << 16));
4684         I915_WRITE(VBLANK(cpu_transcoder),
4685                    (adjusted_mode->crtc_vblank_start - 1) |
4686                    ((crtc_vblank_end - 1) << 16));
4687         I915_WRITE(VSYNC(cpu_transcoder),
4688                    (adjusted_mode->crtc_vsync_start - 1) |
4689                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4690
4691         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4692          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4693          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4694          * bits. */
4695         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4696             (pipe == PIPE_B || pipe == PIPE_C))
4697                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4698
4699         /* pipesrc controls the size that is scaled from, which should
4700          * always be the user's requested size.
4701          */
4702         I915_WRITE(PIPESRC(pipe),
4703                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4704 }
4705
4706 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4707                                    struct intel_crtc_config *pipe_config)
4708 {
4709         struct drm_device *dev = crtc->base.dev;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4712         uint32_t tmp;
4713
4714         tmp = I915_READ(HTOTAL(cpu_transcoder));
4715         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4716         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4717         tmp = I915_READ(HBLANK(cpu_transcoder));
4718         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4719         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4720         tmp = I915_READ(HSYNC(cpu_transcoder));
4721         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4722         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4723
4724         tmp = I915_READ(VTOTAL(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4727         tmp = I915_READ(VBLANK(cpu_transcoder));
4728         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4729         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4730         tmp = I915_READ(VSYNC(cpu_transcoder));
4731         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4732         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4733
4734         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4735                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4736                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4737                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4738         }
4739
4740         tmp = I915_READ(PIPESRC(crtc->pipe));
4741         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4742         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4743 }
4744
4745 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4746                                              struct intel_crtc_config *pipe_config)
4747 {
4748         struct drm_crtc *crtc = &intel_crtc->base;
4749
4750         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4751         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4752         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4753         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4754
4755         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4756         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4757         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4758         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4759
4760         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4761
4762         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4763         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4764 }
4765
4766 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4767 {
4768         struct drm_device *dev = intel_crtc->base.dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         uint32_t pipeconf;
4771
4772         pipeconf = 0;
4773
4774         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4775             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4776                 pipeconf |= PIPECONF_ENABLE;
4777
4778         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4779                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4780                  * core speed.
4781                  *
4782                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4783                  * pipe == 0 check?
4784                  */
4785                 if (intel_crtc->config.requested_mode.clock >
4786                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4787                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4788         }
4789
4790         /* only g4x and later have fancy bpc/dither controls */
4791         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4792                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4793                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4794                         pipeconf |= PIPECONF_DITHER_EN |
4795                                     PIPECONF_DITHER_TYPE_SP;
4796
4797                 switch (intel_crtc->config.pipe_bpp) {
4798                 case 18:
4799                         pipeconf |= PIPECONF_6BPC;
4800                         break;
4801                 case 24:
4802                         pipeconf |= PIPECONF_8BPC;
4803                         break;
4804                 case 30:
4805                         pipeconf |= PIPECONF_10BPC;
4806                         break;
4807                 default:
4808                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4809                         BUG();
4810                 }
4811         }
4812
4813         if (HAS_PIPE_CXSR(dev)) {
4814                 if (intel_crtc->lowfreq_avail) {
4815                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4816                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4817                 } else {
4818                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4819                 }
4820         }
4821
4822         if (!IS_GEN2(dev) &&
4823             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4824                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4825         else
4826                 pipeconf |= PIPECONF_PROGRESSIVE;
4827
4828         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4829                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4830
4831         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4832         POSTING_READ(PIPECONF(intel_crtc->pipe));
4833 }
4834
4835 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4836                               int x, int y,
4837                               struct drm_framebuffer *fb)
4838 {
4839         struct drm_device *dev = crtc->dev;
4840         struct drm_i915_private *dev_priv = dev->dev_private;
4841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4843         int pipe = intel_crtc->pipe;
4844         int plane = intel_crtc->plane;
4845         int refclk, num_connectors = 0;
4846         intel_clock_t clock, reduced_clock;
4847         u32 dspcntr;
4848         bool ok, has_reduced_clock = false;
4849         bool is_lvds = false;
4850         struct intel_encoder *encoder;
4851         const intel_limit_t *limit;
4852         int ret;
4853
4854         for_each_encoder_on_crtc(dev, crtc, encoder) {
4855                 switch (encoder->type) {
4856                 case INTEL_OUTPUT_LVDS:
4857                         is_lvds = true;
4858                         break;
4859                 }
4860
4861                 num_connectors++;
4862         }
4863
4864         refclk = i9xx_get_refclk(crtc, num_connectors);
4865
4866         /*
4867          * Returns a set of divisors for the desired target clock with the given
4868          * refclk, or FALSE.  The returned values represent the clock equation:
4869          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4870          */
4871         limit = intel_limit(crtc, refclk);
4872         ok = dev_priv->display.find_dpll(limit, crtc,
4873                                          intel_crtc->config.port_clock,
4874                                          refclk, NULL, &clock);
4875         if (!ok && !intel_crtc->config.clock_set) {
4876                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4877                 return -EINVAL;
4878         }
4879
4880         if (is_lvds && dev_priv->lvds_downclock_avail) {
4881                 /*
4882                  * Ensure we match the reduced clock's P to the target clock.
4883                  * If the clocks don't match, we can't switch the display clock
4884                  * by using the FP0/FP1. In such case we will disable the LVDS
4885                  * downclock feature.
4886                 */
4887                 has_reduced_clock =
4888                         dev_priv->display.find_dpll(limit, crtc,
4889                                                     dev_priv->lvds_downclock,
4890                                                     refclk, &clock,
4891                                                     &reduced_clock);
4892         }
4893         /* Compat-code for transition, will disappear. */
4894         if (!intel_crtc->config.clock_set) {
4895                 intel_crtc->config.dpll.n = clock.n;
4896                 intel_crtc->config.dpll.m1 = clock.m1;
4897                 intel_crtc->config.dpll.m2 = clock.m2;
4898                 intel_crtc->config.dpll.p1 = clock.p1;
4899                 intel_crtc->config.dpll.p2 = clock.p2;
4900         }
4901
4902         if (IS_GEN2(dev))
4903                 i8xx_update_pll(intel_crtc,
4904                                 has_reduced_clock ? &reduced_clock : NULL,
4905                                 num_connectors);
4906         else if (IS_VALLEYVIEW(dev))
4907                 vlv_update_pll(intel_crtc);
4908         else
4909                 i9xx_update_pll(intel_crtc,
4910                                 has_reduced_clock ? &reduced_clock : NULL,
4911                                 num_connectors);
4912
4913         /* Set up the display plane register */
4914         dspcntr = DISPPLANE_GAMMA_ENABLE;
4915
4916         if (!IS_VALLEYVIEW(dev)) {
4917                 if (pipe == 0)
4918                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919                 else
4920                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4921         }
4922
4923         intel_set_pipe_timings(intel_crtc);
4924
4925         /* pipesrc and dspsize control the size that is scaled from,
4926          * which should always be the user's requested size.
4927          */
4928         I915_WRITE(DSPSIZE(plane),
4929                    ((mode->vdisplay - 1) << 16) |
4930                    (mode->hdisplay - 1));
4931         I915_WRITE(DSPPOS(plane), 0);
4932
4933         i9xx_set_pipeconf(intel_crtc);
4934
4935         I915_WRITE(DSPCNTR(plane), dspcntr);
4936         POSTING_READ(DSPCNTR(plane));
4937
4938         ret = intel_pipe_set_base(crtc, x, y, fb);
4939
4940         intel_update_watermarks(dev);
4941
4942         return ret;
4943 }
4944
4945 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4946                                  struct intel_crtc_config *pipe_config)
4947 {
4948         struct drm_device *dev = crtc->base.dev;
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         uint32_t tmp;
4951
4952         tmp = I915_READ(PFIT_CONTROL);
4953         if (!(tmp & PFIT_ENABLE))
4954                 return;
4955
4956         /* Check whether the pfit is attached to our pipe. */
4957         if (INTEL_INFO(dev)->gen < 4) {
4958                 if (crtc->pipe != PIPE_B)
4959                         return;
4960         } else {
4961                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4962                         return;
4963         }
4964
4965         pipe_config->gmch_pfit.control = tmp;
4966         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4967         if (INTEL_INFO(dev)->gen < 5)
4968                 pipe_config->gmch_pfit.lvds_border_bits =
4969                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4970 }
4971
4972 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4973                                  struct intel_crtc_config *pipe_config)
4974 {
4975         struct drm_device *dev = crtc->base.dev;
4976         struct drm_i915_private *dev_priv = dev->dev_private;
4977         uint32_t tmp;
4978
4979         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4980         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4981
4982         tmp = I915_READ(PIPECONF(crtc->pipe));
4983         if (!(tmp & PIPECONF_ENABLE))
4984                 return false;
4985
4986         intel_get_pipe_timings(crtc, pipe_config);
4987
4988         i9xx_get_pfit_config(crtc, pipe_config);
4989
4990         if (INTEL_INFO(dev)->gen >= 4) {
4991                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4992                 pipe_config->pixel_multiplier =
4993                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4994                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4995                 pipe_config->dpll_hw_state.dpll_md = tmp;
4996         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4997                 tmp = I915_READ(DPLL(crtc->pipe));
4998                 pipe_config->pixel_multiplier =
4999                         ((tmp & SDVO_MULTIPLIER_MASK)
5000                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5001         } else {
5002                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5003                  * port and will be fixed up in the encoder->get_config
5004                  * function. */
5005                 pipe_config->pixel_multiplier = 1;
5006         }
5007         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5008         if (!IS_VALLEYVIEW(dev)) {
5009                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5010                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5011         } else {
5012                 /* Mask out read-only status bits. */
5013                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5014                                                      DPLL_PORTC_READY_MASK |
5015                                                      DPLL_PORTB_READY_MASK);
5016         }
5017
5018         return true;
5019 }
5020
5021 static void ironlake_init_pch_refclk(struct drm_device *dev)
5022 {
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct drm_mode_config *mode_config = &dev->mode_config;
5025         struct intel_encoder *encoder;
5026         u32 val, final;
5027         bool has_lvds = false;
5028         bool has_cpu_edp = false;
5029         bool has_panel = false;
5030         bool has_ck505 = false;
5031         bool can_ssc = false;
5032
5033         /* We need to take the global config into account */
5034         list_for_each_entry(encoder, &mode_config->encoder_list,
5035                             base.head) {
5036                 switch (encoder->type) {
5037                 case INTEL_OUTPUT_LVDS:
5038                         has_panel = true;
5039                         has_lvds = true;
5040                         break;
5041                 case INTEL_OUTPUT_EDP:
5042                         has_panel = true;
5043                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5044                                 has_cpu_edp = true;
5045                         break;
5046                 }
5047         }
5048
5049         if (HAS_PCH_IBX(dev)) {
5050                 has_ck505 = dev_priv->vbt.display_clock_mode;
5051                 can_ssc = has_ck505;
5052         } else {
5053                 has_ck505 = false;
5054                 can_ssc = true;
5055         }
5056
5057         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5058                       has_panel, has_lvds, has_ck505);
5059
5060         /* Ironlake: try to setup display ref clock before DPLL
5061          * enabling. This is only under driver's control after
5062          * PCH B stepping, previous chipset stepping should be
5063          * ignoring this setting.
5064          */
5065         val = I915_READ(PCH_DREF_CONTROL);
5066
5067         /* As we must carefully and slowly disable/enable each source in turn,
5068          * compute the final state we want first and check if we need to
5069          * make any changes at all.
5070          */
5071         final = val;
5072         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5073         if (has_ck505)
5074                 final |= DREF_NONSPREAD_CK505_ENABLE;
5075         else
5076                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5077
5078         final &= ~DREF_SSC_SOURCE_MASK;
5079         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5080         final &= ~DREF_SSC1_ENABLE;
5081
5082         if (has_panel) {
5083                 final |= DREF_SSC_SOURCE_ENABLE;
5084
5085                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5086                         final |= DREF_SSC1_ENABLE;
5087
5088                 if (has_cpu_edp) {
5089                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5090                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091                         else
5092                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5093                 } else
5094                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095         } else {
5096                 final |= DREF_SSC_SOURCE_DISABLE;
5097                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098         }
5099
5100         if (final == val)
5101                 return;
5102
5103         /* Always enable nonspread source */
5104         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5105
5106         if (has_ck505)
5107                 val |= DREF_NONSPREAD_CK505_ENABLE;
5108         else
5109                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5110
5111         if (has_panel) {
5112                 val &= ~DREF_SSC_SOURCE_MASK;
5113                 val |= DREF_SSC_SOURCE_ENABLE;
5114
5115                 /* SSC must be turned on before enabling the CPU output  */
5116                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5117                         DRM_DEBUG_KMS("Using SSC on panel\n");
5118                         val |= DREF_SSC1_ENABLE;
5119                 } else
5120                         val &= ~DREF_SSC1_ENABLE;
5121
5122                 /* Get SSC going before enabling the outputs */
5123                 I915_WRITE(PCH_DREF_CONTROL, val);
5124                 POSTING_READ(PCH_DREF_CONTROL);
5125                 udelay(200);
5126
5127                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5128
5129                 /* Enable CPU source on CPU attached eDP */
5130                 if (has_cpu_edp) {
5131                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5132                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5133                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5134                         }
5135                         else
5136                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5137                 } else
5138                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5139
5140                 I915_WRITE(PCH_DREF_CONTROL, val);
5141                 POSTING_READ(PCH_DREF_CONTROL);
5142                 udelay(200);
5143         } else {
5144                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5145
5146                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5147
5148                 /* Turn off CPU output */
5149                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5150
5151                 I915_WRITE(PCH_DREF_CONTROL, val);
5152                 POSTING_READ(PCH_DREF_CONTROL);
5153                 udelay(200);
5154
5155                 /* Turn off the SSC source */
5156                 val &= ~DREF_SSC_SOURCE_MASK;
5157                 val |= DREF_SSC_SOURCE_DISABLE;
5158
5159                 /* Turn off SSC1 */
5160                 val &= ~DREF_SSC1_ENABLE;
5161
5162                 I915_WRITE(PCH_DREF_CONTROL, val);
5163                 POSTING_READ(PCH_DREF_CONTROL);
5164                 udelay(200);
5165         }
5166
5167         BUG_ON(val != final);
5168 }
5169
5170 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5171 {
5172         uint32_t tmp;
5173
5174         tmp = I915_READ(SOUTH_CHICKEN2);
5175         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5176         I915_WRITE(SOUTH_CHICKEN2, tmp);
5177
5178         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5179                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5180                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5181
5182         tmp = I915_READ(SOUTH_CHICKEN2);
5183         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5184         I915_WRITE(SOUTH_CHICKEN2, tmp);
5185
5186         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5187                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5188                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5189 }
5190
5191 /* WaMPhyProgramming:hsw */
5192 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5193 {
5194         uint32_t tmp;
5195
5196         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5197         tmp &= ~(0xFF << 24);
5198         tmp |= (0x12 << 24);
5199         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5200
5201         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5202         tmp |= (1 << 11);
5203         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5204
5205         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5206         tmp |= (1 << 11);
5207         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5208
5209         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5210         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5211         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212
5213         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5214         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216
5217         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5218         tmp &= ~(7 << 13);
5219         tmp |= (5 << 13);
5220         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5221
5222         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5223         tmp &= ~(7 << 13);
5224         tmp |= (5 << 13);
5225         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5226
5227         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5228         tmp &= ~0xFF;
5229         tmp |= 0x1C;
5230         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5231
5232         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5233         tmp &= ~0xFF;
5234         tmp |= 0x1C;
5235         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5236
5237         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5238         tmp &= ~(0xFF << 16);
5239         tmp |= (0x1C << 16);
5240         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5241
5242         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5243         tmp &= ~(0xFF << 16);
5244         tmp |= (0x1C << 16);
5245         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5246
5247         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5248         tmp |= (1 << 27);
5249         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5252         tmp |= (1 << 27);
5253         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5254
5255         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5256         tmp &= ~(0xF << 28);
5257         tmp |= (4 << 28);
5258         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5259
5260         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5261         tmp &= ~(0xF << 28);
5262         tmp |= (4 << 28);
5263         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5264 }
5265
5266 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5267  * Programming" based on the parameters passed:
5268  * - Sequence to enable CLKOUT_DP
5269  * - Sequence to enable CLKOUT_DP without spread
5270  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5271  */
5272 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5273                                  bool with_fdi)
5274 {
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276         uint32_t reg, tmp;
5277
5278         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5279                 with_spread = true;
5280         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5281                  with_fdi, "LP PCH doesn't have FDI\n"))
5282                 with_fdi = false;
5283
5284         mutex_lock(&dev_priv->dpio_lock);
5285
5286         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5287         tmp &= ~SBI_SSCCTL_DISABLE;
5288         tmp |= SBI_SSCCTL_PATHALT;
5289         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5290
5291         udelay(24);
5292
5293         if (with_spread) {
5294                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5295                 tmp &= ~SBI_SSCCTL_PATHALT;
5296                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5297
5298                 if (with_fdi) {
5299                         lpt_reset_fdi_mphy(dev_priv);
5300                         lpt_program_fdi_mphy(dev_priv);
5301                 }
5302         }
5303
5304         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5305                SBI_GEN0 : SBI_DBUFF0;
5306         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5307         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5308         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5309
5310         mutex_unlock(&dev_priv->dpio_lock);
5311 }
5312
5313 /* Sequence to disable CLKOUT_DP */
5314 static void lpt_disable_clkout_dp(struct drm_device *dev)
5315 {
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317         uint32_t reg, tmp;
5318
5319         mutex_lock(&dev_priv->dpio_lock);
5320
5321         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5322                SBI_GEN0 : SBI_DBUFF0;
5323         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5324         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5325         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5326
5327         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5328         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5329                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5330                         tmp |= SBI_SSCCTL_PATHALT;
5331                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5332                         udelay(32);
5333                 }
5334                 tmp |= SBI_SSCCTL_DISABLE;
5335                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5336         }
5337
5338         mutex_unlock(&dev_priv->dpio_lock);
5339 }
5340
5341 static void lpt_init_pch_refclk(struct drm_device *dev)
5342 {
5343         struct drm_mode_config *mode_config = &dev->mode_config;
5344         struct intel_encoder *encoder;
5345         bool has_vga = false;
5346
5347         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5348                 switch (encoder->type) {
5349                 case INTEL_OUTPUT_ANALOG:
5350                         has_vga = true;
5351                         break;
5352                 }
5353         }
5354
5355         if (has_vga)
5356                 lpt_enable_clkout_dp(dev, true, true);
5357         else
5358                 lpt_disable_clkout_dp(dev);
5359 }
5360
5361 /*
5362  * Initialize reference clocks when the driver loads
5363  */
5364 void intel_init_pch_refclk(struct drm_device *dev)
5365 {
5366         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5367                 ironlake_init_pch_refclk(dev);
5368         else if (HAS_PCH_LPT(dev))
5369                 lpt_init_pch_refclk(dev);
5370 }
5371
5372 static int ironlake_get_refclk(struct drm_crtc *crtc)
5373 {
5374         struct drm_device *dev = crtc->dev;
5375         struct drm_i915_private *dev_priv = dev->dev_private;
5376         struct intel_encoder *encoder;
5377         int num_connectors = 0;
5378         bool is_lvds = false;
5379
5380         for_each_encoder_on_crtc(dev, crtc, encoder) {
5381                 switch (encoder->type) {
5382                 case INTEL_OUTPUT_LVDS:
5383                         is_lvds = true;
5384                         break;
5385                 }
5386                 num_connectors++;
5387         }
5388
5389         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5390                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5391                               dev_priv->vbt.lvds_ssc_freq);
5392                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5393         }
5394
5395         return 120000;
5396 }
5397
5398 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5399 {
5400         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402         int pipe = intel_crtc->pipe;
5403         uint32_t val;
5404
5405         val = 0;
5406
5407         switch (intel_crtc->config.pipe_bpp) {
5408         case 18:
5409                 val |= PIPECONF_6BPC;
5410                 break;
5411         case 24:
5412                 val |= PIPECONF_8BPC;
5413                 break;
5414         case 30:
5415                 val |= PIPECONF_10BPC;
5416                 break;
5417         case 36:
5418                 val |= PIPECONF_12BPC;
5419                 break;
5420         default:
5421                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5422                 BUG();
5423         }
5424
5425         if (intel_crtc->config.dither)
5426                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5427
5428         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5429                 val |= PIPECONF_INTERLACED_ILK;
5430         else
5431                 val |= PIPECONF_PROGRESSIVE;
5432
5433         if (intel_crtc->config.limited_color_range)
5434                 val |= PIPECONF_COLOR_RANGE_SELECT;
5435
5436         I915_WRITE(PIPECONF(pipe), val);
5437         POSTING_READ(PIPECONF(pipe));
5438 }
5439
5440 /*
5441  * Set up the pipe CSC unit.
5442  *
5443  * Currently only full range RGB to limited range RGB conversion
5444  * is supported, but eventually this should handle various
5445  * RGB<->YCbCr scenarios as well.
5446  */
5447 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5448 {
5449         struct drm_device *dev = crtc->dev;
5450         struct drm_i915_private *dev_priv = dev->dev_private;
5451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5452         int pipe = intel_crtc->pipe;
5453         uint16_t coeff = 0x7800; /* 1.0 */
5454
5455         /*
5456          * TODO: Check what kind of values actually come out of the pipe
5457          * with these coeff/postoff values and adjust to get the best
5458          * accuracy. Perhaps we even need to take the bpc value into
5459          * consideration.
5460          */
5461
5462         if (intel_crtc->config.limited_color_range)
5463                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5464
5465         /*
5466          * GY/GU and RY/RU should be the other way around according
5467          * to BSpec, but reality doesn't agree. Just set them up in
5468          * a way that results in the correct picture.
5469          */
5470         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5471         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5472
5473         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5474         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5475
5476         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5477         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5478
5479         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5480         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5481         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5482
5483         if (INTEL_INFO(dev)->gen > 6) {
5484                 uint16_t postoff = 0;
5485
5486                 if (intel_crtc->config.limited_color_range)
5487                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5488
5489                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5490                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5491                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5492
5493                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5494         } else {
5495                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5496
5497                 if (intel_crtc->config.limited_color_range)
5498                         mode |= CSC_BLACK_SCREEN_OFFSET;
5499
5500                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5501         }
5502 }
5503
5504 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5505 {
5506         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5509         uint32_t val;
5510
5511         val = 0;
5512
5513         if (intel_crtc->config.dither)
5514                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5515
5516         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5517                 val |= PIPECONF_INTERLACED_ILK;
5518         else
5519                 val |= PIPECONF_PROGRESSIVE;
5520
5521         I915_WRITE(PIPECONF(cpu_transcoder), val);
5522         POSTING_READ(PIPECONF(cpu_transcoder));
5523
5524         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5525         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5526 }
5527
5528 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5529                                     intel_clock_t *clock,
5530                                     bool *has_reduced_clock,
5531                                     intel_clock_t *reduced_clock)
5532 {
5533         struct drm_device *dev = crtc->dev;
5534         struct drm_i915_private *dev_priv = dev->dev_private;
5535         struct intel_encoder *intel_encoder;
5536         int refclk;
5537         const intel_limit_t *limit;
5538         bool ret, is_lvds = false;
5539
5540         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5541                 switch (intel_encoder->type) {
5542                 case INTEL_OUTPUT_LVDS:
5543                         is_lvds = true;
5544                         break;
5545                 }
5546         }
5547
5548         refclk = ironlake_get_refclk(crtc);
5549
5550         /*
5551          * Returns a set of divisors for the desired target clock with the given
5552          * refclk, or FALSE.  The returned values represent the clock equation:
5553          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5554          */
5555         limit = intel_limit(crtc, refclk);
5556         ret = dev_priv->display.find_dpll(limit, crtc,
5557                                           to_intel_crtc(crtc)->config.port_clock,
5558                                           refclk, NULL, clock);
5559         if (!ret)
5560                 return false;
5561
5562         if (is_lvds && dev_priv->lvds_downclock_avail) {
5563                 /*
5564                  * Ensure we match the reduced clock's P to the target clock.
5565                  * If the clocks don't match, we can't switch the display clock
5566                  * by using the FP0/FP1. In such case we will disable the LVDS
5567                  * downclock feature.
5568                 */
5569                 *has_reduced_clock =
5570                         dev_priv->display.find_dpll(limit, crtc,
5571                                                     dev_priv->lvds_downclock,
5572                                                     refclk, clock,
5573                                                     reduced_clock);
5574         }
5575
5576         return true;
5577 }
5578
5579 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5580 {
5581         struct drm_i915_private *dev_priv = dev->dev_private;
5582         uint32_t temp;
5583
5584         temp = I915_READ(SOUTH_CHICKEN1);
5585         if (temp & FDI_BC_BIFURCATION_SELECT)
5586                 return;
5587
5588         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5589         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5590
5591         temp |= FDI_BC_BIFURCATION_SELECT;
5592         DRM_DEBUG_KMS("enabling fdi C rx\n");
5593         I915_WRITE(SOUTH_CHICKEN1, temp);
5594         POSTING_READ(SOUTH_CHICKEN1);
5595 }
5596
5597 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5598 {
5599         struct drm_device *dev = intel_crtc->base.dev;
5600         struct drm_i915_private *dev_priv = dev->dev_private;
5601
5602         switch (intel_crtc->pipe) {
5603         case PIPE_A:
5604                 break;
5605         case PIPE_B:
5606                 if (intel_crtc->config.fdi_lanes > 2)
5607                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5608                 else
5609                         cpt_enable_fdi_bc_bifurcation(dev);
5610
5611                 break;
5612         case PIPE_C:
5613                 cpt_enable_fdi_bc_bifurcation(dev);
5614
5615                 break;
5616         default:
5617                 BUG();
5618         }
5619 }
5620
5621 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5622 {
5623         /*
5624          * Account for spread spectrum to avoid
5625          * oversubscribing the link. Max center spread
5626          * is 2.5%; use 5% for safety's sake.
5627          */
5628         u32 bps = target_clock * bpp * 21 / 20;
5629         return bps / (link_bw * 8) + 1;
5630 }
5631
5632 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5633 {
5634         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5635 }
5636
5637 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5638                                       u32 *fp,
5639                                       intel_clock_t *reduced_clock, u32 *fp2)
5640 {
5641         struct drm_crtc *crtc = &intel_crtc->base;
5642         struct drm_device *dev = crtc->dev;
5643         struct drm_i915_private *dev_priv = dev->dev_private;
5644         struct intel_encoder *intel_encoder;
5645         uint32_t dpll;
5646         int factor, num_connectors = 0;
5647         bool is_lvds = false, is_sdvo = false;
5648
5649         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5650                 switch (intel_encoder->type) {
5651                 case INTEL_OUTPUT_LVDS:
5652                         is_lvds = true;
5653                         break;
5654                 case INTEL_OUTPUT_SDVO:
5655                 case INTEL_OUTPUT_HDMI:
5656                         is_sdvo = true;
5657                         break;
5658                 }
5659
5660                 num_connectors++;
5661         }
5662
5663         /* Enable autotuning of the PLL clock (if permissible) */
5664         factor = 21;
5665         if (is_lvds) {
5666                 if ((intel_panel_use_ssc(dev_priv) &&
5667                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5668                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5669                         factor = 25;
5670         } else if (intel_crtc->config.sdvo_tv_clock)
5671                 factor = 20;
5672
5673         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5674                 *fp |= FP_CB_TUNE;
5675
5676         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5677                 *fp2 |= FP_CB_TUNE;
5678
5679         dpll = 0;
5680
5681         if (is_lvds)
5682                 dpll |= DPLLB_MODE_LVDS;
5683         else
5684                 dpll |= DPLLB_MODE_DAC_SERIAL;
5685
5686         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5687                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5688
5689         if (is_sdvo)
5690                 dpll |= DPLL_SDVO_HIGH_SPEED;
5691         if (intel_crtc->config.has_dp_encoder)
5692                 dpll |= DPLL_SDVO_HIGH_SPEED;
5693
5694         /* compute bitmask from p1 value */
5695         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5696         /* also FPA1 */
5697         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5698
5699         switch (intel_crtc->config.dpll.p2) {
5700         case 5:
5701                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5702                 break;
5703         case 7:
5704                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5705                 break;
5706         case 10:
5707                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5708                 break;
5709         case 14:
5710                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5711                 break;
5712         }
5713
5714         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5715                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5716         else
5717                 dpll |= PLL_REF_INPUT_DREFCLK;
5718
5719         return dpll | DPLL_VCO_ENABLE;
5720 }
5721
5722 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5723                                   int x, int y,
5724                                   struct drm_framebuffer *fb)
5725 {
5726         struct drm_device *dev = crtc->dev;
5727         struct drm_i915_private *dev_priv = dev->dev_private;
5728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729         int pipe = intel_crtc->pipe;
5730         int plane = intel_crtc->plane;
5731         int num_connectors = 0;
5732         intel_clock_t clock, reduced_clock;
5733         u32 dpll = 0, fp = 0, fp2 = 0;
5734         bool ok, has_reduced_clock = false;
5735         bool is_lvds = false;
5736         struct intel_encoder *encoder;
5737         struct intel_shared_dpll *pll;
5738         int ret;
5739
5740         for_each_encoder_on_crtc(dev, crtc, encoder) {
5741                 switch (encoder->type) {
5742                 case INTEL_OUTPUT_LVDS:
5743                         is_lvds = true;
5744                         break;
5745                 }
5746
5747                 num_connectors++;
5748         }
5749
5750         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5751              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5752
5753         ok = ironlake_compute_clocks(crtc, &clock,
5754                                      &has_reduced_clock, &reduced_clock);
5755         if (!ok && !intel_crtc->config.clock_set) {
5756                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5757                 return -EINVAL;
5758         }
5759         /* Compat-code for transition, will disappear. */
5760         if (!intel_crtc->config.clock_set) {
5761                 intel_crtc->config.dpll.n = clock.n;
5762                 intel_crtc->config.dpll.m1 = clock.m1;
5763                 intel_crtc->config.dpll.m2 = clock.m2;
5764                 intel_crtc->config.dpll.p1 = clock.p1;
5765                 intel_crtc->config.dpll.p2 = clock.p2;
5766         }
5767
5768         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5769         if (intel_crtc->config.has_pch_encoder) {
5770                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5771                 if (has_reduced_clock)
5772                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5773
5774                 dpll = ironlake_compute_dpll(intel_crtc,
5775                                              &fp, &reduced_clock,
5776                                              has_reduced_clock ? &fp2 : NULL);
5777
5778                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5779                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5780                 if (has_reduced_clock)
5781                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5782                 else
5783                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5784
5785                 pll = intel_get_shared_dpll(intel_crtc);
5786                 if (pll == NULL) {
5787                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5788                                          pipe_name(pipe));
5789                         return -EINVAL;
5790                 }
5791         } else
5792                 intel_put_shared_dpll(intel_crtc);
5793
5794         if (intel_crtc->config.has_dp_encoder)
5795                 intel_dp_set_m_n(intel_crtc);
5796
5797         if (is_lvds && has_reduced_clock && i915_powersave)
5798                 intel_crtc->lowfreq_avail = true;
5799         else
5800                 intel_crtc->lowfreq_avail = false;
5801
5802         if (intel_crtc->config.has_pch_encoder) {
5803                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5804
5805         }
5806
5807         intel_set_pipe_timings(intel_crtc);
5808
5809         if (intel_crtc->config.has_pch_encoder) {
5810                 intel_cpu_transcoder_set_m_n(intel_crtc,
5811                                              &intel_crtc->config.fdi_m_n);
5812         }
5813
5814         if (IS_IVYBRIDGE(dev))
5815                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5816
5817         ironlake_set_pipeconf(crtc);
5818
5819         /* Set up the display plane register */
5820         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5821         POSTING_READ(DSPCNTR(plane));
5822
5823         ret = intel_pipe_set_base(crtc, x, y, fb);
5824
5825         intel_update_watermarks(dev);
5826
5827         return ret;
5828 }
5829
5830 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5831                                         struct intel_crtc_config *pipe_config)
5832 {
5833         struct drm_device *dev = crtc->base.dev;
5834         struct drm_i915_private *dev_priv = dev->dev_private;
5835         enum transcoder transcoder = pipe_config->cpu_transcoder;
5836
5837         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5838         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5839         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5840                                         & ~TU_SIZE_MASK;
5841         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5842         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5843                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5844 }
5845
5846 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5847                                      struct intel_crtc_config *pipe_config)
5848 {
5849         struct drm_device *dev = crtc->base.dev;
5850         struct drm_i915_private *dev_priv = dev->dev_private;
5851         uint32_t tmp;
5852
5853         tmp = I915_READ(PF_CTL(crtc->pipe));
5854
5855         if (tmp & PF_ENABLE) {
5856                 pipe_config->pch_pfit.enabled = true;
5857                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5858                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5859
5860                 /* We currently do not free assignements of panel fitters on
5861                  * ivb/hsw (since we don't use the higher upscaling modes which
5862                  * differentiates them) so just WARN about this case for now. */
5863                 if (IS_GEN7(dev)) {
5864                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5865                                 PF_PIPE_SEL_IVB(crtc->pipe));
5866                 }
5867         }
5868 }
5869
5870 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5871                                      struct intel_crtc_config *pipe_config)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         uint32_t tmp;
5876
5877         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5878         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5879
5880         tmp = I915_READ(PIPECONF(crtc->pipe));
5881         if (!(tmp & PIPECONF_ENABLE))
5882                 return false;
5883
5884         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5885                 struct intel_shared_dpll *pll;
5886
5887                 pipe_config->has_pch_encoder = true;
5888
5889                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5890                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5891                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5892
5893                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5894
5895                 if (HAS_PCH_IBX(dev_priv->dev)) {
5896                         pipe_config->shared_dpll =
5897                                 (enum intel_dpll_id) crtc->pipe;
5898                 } else {
5899                         tmp = I915_READ(PCH_DPLL_SEL);
5900                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5901                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5902                         else
5903                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5904                 }
5905
5906                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5907
5908                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5909                                            &pipe_config->dpll_hw_state));
5910
5911                 tmp = pipe_config->dpll_hw_state.dpll;
5912                 pipe_config->pixel_multiplier =
5913                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5914                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5915         } else {
5916                 pipe_config->pixel_multiplier = 1;
5917         }
5918
5919         intel_get_pipe_timings(crtc, pipe_config);
5920
5921         ironlake_get_pfit_config(crtc, pipe_config);
5922
5923         return true;
5924 }
5925
5926 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5927 {
5928         struct drm_device *dev = dev_priv->dev;
5929         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5930         struct intel_crtc *crtc;
5931         unsigned long irqflags;
5932         uint32_t val;
5933
5934         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5935                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5936                      pipe_name(crtc->pipe));
5937
5938         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5939         WARN(plls->spll_refcount, "SPLL enabled\n");
5940         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5941         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5942         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5943         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5944              "CPU PWM1 enabled\n");
5945         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5946              "CPU PWM2 enabled\n");
5947         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5948              "PCH PWM1 enabled\n");
5949         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5950              "Utility pin enabled\n");
5951         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5952
5953         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5954         val = I915_READ(DEIMR);
5955         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5956              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5957         val = I915_READ(SDEIMR);
5958         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5959              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5960         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5961 }
5962
5963 /*
5964  * This function implements pieces of two sequences from BSpec:
5965  * - Sequence for display software to disable LCPLL
5966  * - Sequence for display software to allow package C8+
5967  * The steps implemented here are just the steps that actually touch the LCPLL
5968  * register. Callers should take care of disabling all the display engine
5969  * functions, doing the mode unset, fixing interrupts, etc.
5970  */
5971 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5972                        bool switch_to_fclk, bool allow_power_down)
5973 {
5974         uint32_t val;
5975
5976         assert_can_disable_lcpll(dev_priv);
5977
5978         val = I915_READ(LCPLL_CTL);
5979
5980         if (switch_to_fclk) {
5981                 val |= LCPLL_CD_SOURCE_FCLK;
5982                 I915_WRITE(LCPLL_CTL, val);
5983
5984                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5985                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
5986                         DRM_ERROR("Switching to FCLK failed\n");
5987
5988                 val = I915_READ(LCPLL_CTL);
5989         }
5990
5991         val |= LCPLL_PLL_DISABLE;
5992         I915_WRITE(LCPLL_CTL, val);
5993         POSTING_READ(LCPLL_CTL);
5994
5995         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
5996                 DRM_ERROR("LCPLL still locked\n");
5997
5998         val = I915_READ(D_COMP);
5999         val |= D_COMP_COMP_DISABLE;
6000         I915_WRITE(D_COMP, val);
6001         POSTING_READ(D_COMP);
6002         ndelay(100);
6003
6004         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6005                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6006
6007         if (allow_power_down) {
6008                 val = I915_READ(LCPLL_CTL);
6009                 val |= LCPLL_POWER_DOWN_ALLOW;
6010                 I915_WRITE(LCPLL_CTL, val);
6011                 POSTING_READ(LCPLL_CTL);
6012         }
6013 }
6014
6015 /*
6016  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6017  * source.
6018  */
6019 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6020 {
6021         uint32_t val;
6022
6023         val = I915_READ(LCPLL_CTL);
6024
6025         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6026                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6027                 return;
6028
6029         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6030          * we'll hang the machine! */
6031         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6032
6033         if (val & LCPLL_POWER_DOWN_ALLOW) {
6034                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6035                 I915_WRITE(LCPLL_CTL, val);
6036                 POSTING_READ(LCPLL_CTL);
6037         }
6038
6039         val = I915_READ(D_COMP);
6040         val |= D_COMP_COMP_FORCE;
6041         val &= ~D_COMP_COMP_DISABLE;
6042         I915_WRITE(D_COMP, val);
6043         POSTING_READ(D_COMP);
6044
6045         val = I915_READ(LCPLL_CTL);
6046         val &= ~LCPLL_PLL_DISABLE;
6047         I915_WRITE(LCPLL_CTL, val);
6048
6049         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6050                 DRM_ERROR("LCPLL not locked yet\n");
6051
6052         if (val & LCPLL_CD_SOURCE_FCLK) {
6053                 val = I915_READ(LCPLL_CTL);
6054                 val &= ~LCPLL_CD_SOURCE_FCLK;
6055                 I915_WRITE(LCPLL_CTL, val);
6056
6057                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6058                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6059                         DRM_ERROR("Switching back to LCPLL failed\n");
6060         }
6061
6062         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6063 }
6064
6065 void hsw_enable_pc8_work(struct work_struct *__work)
6066 {
6067         struct drm_i915_private *dev_priv =
6068                 container_of(to_delayed_work(__work), struct drm_i915_private,
6069                              pc8.enable_work);
6070         struct drm_device *dev = dev_priv->dev;
6071         uint32_t val;
6072
6073         if (dev_priv->pc8.enabled)
6074                 return;
6075
6076         DRM_DEBUG_KMS("Enabling package C8+\n");
6077
6078         dev_priv->pc8.enabled = true;
6079
6080         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6081                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6082                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6083                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6084         }
6085
6086         lpt_disable_clkout_dp(dev);
6087         hsw_pc8_disable_interrupts(dev);
6088         hsw_disable_lcpll(dev_priv, true, true);
6089 }
6090
6091 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6092 {
6093         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6094         WARN(dev_priv->pc8.disable_count < 1,
6095              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6096
6097         dev_priv->pc8.disable_count--;
6098         if (dev_priv->pc8.disable_count != 0)
6099                 return;
6100
6101         schedule_delayed_work(&dev_priv->pc8.enable_work,
6102                               msecs_to_jiffies(i915_pc8_timeout));
6103 }
6104
6105 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6106 {
6107         struct drm_device *dev = dev_priv->dev;
6108         uint32_t val;
6109
6110         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6111         WARN(dev_priv->pc8.disable_count < 0,
6112              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6113
6114         dev_priv->pc8.disable_count++;
6115         if (dev_priv->pc8.disable_count != 1)
6116                 return;
6117
6118         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6119         if (!dev_priv->pc8.enabled)
6120                 return;
6121
6122         DRM_DEBUG_KMS("Disabling package C8+\n");
6123
6124         hsw_restore_lcpll(dev_priv);
6125         hsw_pc8_restore_interrupts(dev);
6126         lpt_init_pch_refclk(dev);
6127
6128         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6129                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6130                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6131                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6132         }
6133
6134         intel_prepare_ddi(dev);
6135         i915_gem_init_swizzling(dev);
6136         mutex_lock(&dev_priv->rps.hw_lock);
6137         gen6_update_ring_freq(dev);
6138         mutex_unlock(&dev_priv->rps.hw_lock);
6139         dev_priv->pc8.enabled = false;
6140 }
6141
6142 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6143 {
6144         mutex_lock(&dev_priv->pc8.lock);
6145         __hsw_enable_package_c8(dev_priv);
6146         mutex_unlock(&dev_priv->pc8.lock);
6147 }
6148
6149 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6150 {
6151         mutex_lock(&dev_priv->pc8.lock);
6152         __hsw_disable_package_c8(dev_priv);
6153         mutex_unlock(&dev_priv->pc8.lock);
6154 }
6155
6156 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6157 {
6158         struct drm_device *dev = dev_priv->dev;
6159         struct intel_crtc *crtc;
6160         uint32_t val;
6161
6162         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6163                 if (crtc->base.enabled)
6164                         return false;
6165
6166         /* This case is still possible since we have the i915.disable_power_well
6167          * parameter and also the KVMr or something else might be requesting the
6168          * power well. */
6169         val = I915_READ(HSW_PWR_WELL_DRIVER);
6170         if (val != 0) {
6171                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6172                 return false;
6173         }
6174
6175         return true;
6176 }
6177
6178 /* Since we're called from modeset_global_resources there's no way to
6179  * symmetrically increase and decrease the refcount, so we use
6180  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6181  * or not.
6182  */
6183 static void hsw_update_package_c8(struct drm_device *dev)
6184 {
6185         struct drm_i915_private *dev_priv = dev->dev_private;
6186         bool allow;
6187
6188         if (!i915_enable_pc8)
6189                 return;
6190
6191         mutex_lock(&dev_priv->pc8.lock);
6192
6193         allow = hsw_can_enable_package_c8(dev_priv);
6194
6195         if (allow == dev_priv->pc8.requirements_met)
6196                 goto done;
6197
6198         dev_priv->pc8.requirements_met = allow;
6199
6200         if (allow)
6201                 __hsw_enable_package_c8(dev_priv);
6202         else
6203                 __hsw_disable_package_c8(dev_priv);
6204
6205 done:
6206         mutex_unlock(&dev_priv->pc8.lock);
6207 }
6208
6209 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6210 {
6211         if (!dev_priv->pc8.gpu_idle) {
6212                 dev_priv->pc8.gpu_idle = true;
6213                 hsw_enable_package_c8(dev_priv);
6214         }
6215 }
6216
6217 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6218 {
6219         if (dev_priv->pc8.gpu_idle) {
6220                 dev_priv->pc8.gpu_idle = false;
6221                 hsw_disable_package_c8(dev_priv);
6222         }
6223 }
6224
6225 static void haswell_modeset_global_resources(struct drm_device *dev)
6226 {
6227         bool enable = false;
6228         struct intel_crtc *crtc;
6229
6230         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6231                 if (!crtc->base.enabled)
6232                         continue;
6233
6234                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6235                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6236                         enable = true;
6237         }
6238
6239         intel_set_power_well(dev, enable);
6240
6241         hsw_update_package_c8(dev);
6242 }
6243
6244 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6245                                  int x, int y,
6246                                  struct drm_framebuffer *fb)
6247 {
6248         struct drm_device *dev = crtc->dev;
6249         struct drm_i915_private *dev_priv = dev->dev_private;
6250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251         int plane = intel_crtc->plane;
6252         int ret;
6253
6254         if (!intel_ddi_pll_mode_set(crtc))
6255                 return -EINVAL;
6256
6257         if (intel_crtc->config.has_dp_encoder)
6258                 intel_dp_set_m_n(intel_crtc);
6259
6260         intel_crtc->lowfreq_avail = false;
6261
6262         intel_set_pipe_timings(intel_crtc);
6263
6264         if (intel_crtc->config.has_pch_encoder) {
6265                 intel_cpu_transcoder_set_m_n(intel_crtc,
6266                                              &intel_crtc->config.fdi_m_n);
6267         }
6268
6269         haswell_set_pipeconf(crtc);
6270
6271         intel_set_pipe_csc(crtc);
6272
6273         /* Set up the display plane register */
6274         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6275         POSTING_READ(DSPCNTR(plane));
6276
6277         ret = intel_pipe_set_base(crtc, x, y, fb);
6278
6279         intel_update_watermarks(dev);
6280
6281         return ret;
6282 }
6283
6284 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6285                                     struct intel_crtc_config *pipe_config)
6286 {
6287         struct drm_device *dev = crtc->base.dev;
6288         struct drm_i915_private *dev_priv = dev->dev_private;
6289         enum intel_display_power_domain pfit_domain;
6290         uint32_t tmp;
6291
6292         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6293         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6294
6295         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6296         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6297                 enum pipe trans_edp_pipe;
6298                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6299                 default:
6300                         WARN(1, "unknown pipe linked to edp transcoder\n");
6301                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6302                 case TRANS_DDI_EDP_INPUT_A_ON:
6303                         trans_edp_pipe = PIPE_A;
6304                         break;
6305                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6306                         trans_edp_pipe = PIPE_B;
6307                         break;
6308                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6309                         trans_edp_pipe = PIPE_C;
6310                         break;
6311                 }
6312
6313                 if (trans_edp_pipe == crtc->pipe)
6314                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6315         }
6316
6317         if (!intel_display_power_enabled(dev,
6318                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6319                 return false;
6320
6321         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6322         if (!(tmp & PIPECONF_ENABLE))
6323                 return false;
6324
6325         /*
6326          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6327          * DDI E. So just check whether this pipe is wired to DDI E and whether
6328          * the PCH transcoder is on.
6329          */
6330         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6331         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6332             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6333                 pipe_config->has_pch_encoder = true;
6334
6335                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6336                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6337                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6338
6339                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6340         }
6341
6342         intel_get_pipe_timings(crtc, pipe_config);
6343
6344         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6345         if (intel_display_power_enabled(dev, pfit_domain))
6346                 ironlake_get_pfit_config(crtc, pipe_config);
6347
6348         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6349                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6350
6351         pipe_config->pixel_multiplier = 1;
6352
6353         return true;
6354 }
6355
6356 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6357                                int x, int y,
6358                                struct drm_framebuffer *fb)
6359 {
6360         struct drm_device *dev = crtc->dev;
6361         struct drm_i915_private *dev_priv = dev->dev_private;
6362         struct intel_encoder *encoder;
6363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6365         int pipe = intel_crtc->pipe;
6366         int ret;
6367
6368         drm_vblank_pre_modeset(dev, pipe);
6369
6370         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6371
6372         drm_vblank_post_modeset(dev, pipe);
6373
6374         if (ret != 0)
6375                 return ret;
6376
6377         for_each_encoder_on_crtc(dev, crtc, encoder) {
6378                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6379                         encoder->base.base.id,
6380                         drm_get_encoder_name(&encoder->base),
6381                         mode->base.id, mode->name);
6382                 encoder->mode_set(encoder);
6383         }
6384
6385         return 0;
6386 }
6387
6388 static bool intel_eld_uptodate(struct drm_connector *connector,
6389                                int reg_eldv, uint32_t bits_eldv,
6390                                int reg_elda, uint32_t bits_elda,
6391                                int reg_edid)
6392 {
6393         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6394         uint8_t *eld = connector->eld;
6395         uint32_t i;
6396
6397         i = I915_READ(reg_eldv);
6398         i &= bits_eldv;
6399
6400         if (!eld[0])
6401                 return !i;
6402
6403         if (!i)
6404                 return false;
6405
6406         i = I915_READ(reg_elda);
6407         i &= ~bits_elda;
6408         I915_WRITE(reg_elda, i);
6409
6410         for (i = 0; i < eld[2]; i++)
6411                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6412                         return false;
6413
6414         return true;
6415 }
6416
6417 static void g4x_write_eld(struct drm_connector *connector,
6418                           struct drm_crtc *crtc)
6419 {
6420         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6421         uint8_t *eld = connector->eld;
6422         uint32_t eldv;
6423         uint32_t len;
6424         uint32_t i;
6425
6426         i = I915_READ(G4X_AUD_VID_DID);
6427
6428         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6429                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6430         else
6431                 eldv = G4X_ELDV_DEVCTG;
6432
6433         if (intel_eld_uptodate(connector,
6434                                G4X_AUD_CNTL_ST, eldv,
6435                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6436                                G4X_HDMIW_HDMIEDID))
6437                 return;
6438
6439         i = I915_READ(G4X_AUD_CNTL_ST);
6440         i &= ~(eldv | G4X_ELD_ADDR);
6441         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6442         I915_WRITE(G4X_AUD_CNTL_ST, i);
6443
6444         if (!eld[0])
6445                 return;
6446
6447         len = min_t(uint8_t, eld[2], len);
6448         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6449         for (i = 0; i < len; i++)
6450                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6451
6452         i = I915_READ(G4X_AUD_CNTL_ST);
6453         i |= eldv;
6454         I915_WRITE(G4X_AUD_CNTL_ST, i);
6455 }
6456
6457 static void haswell_write_eld(struct drm_connector *connector,
6458                                      struct drm_crtc *crtc)
6459 {
6460         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6461         uint8_t *eld = connector->eld;
6462         struct drm_device *dev = crtc->dev;
6463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464         uint32_t eldv;
6465         uint32_t i;
6466         int len;
6467         int pipe = to_intel_crtc(crtc)->pipe;
6468         int tmp;
6469
6470         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6471         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6472         int aud_config = HSW_AUD_CFG(pipe);
6473         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6474
6475
6476         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6477
6478         /* Audio output enable */
6479         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6480         tmp = I915_READ(aud_cntrl_st2);
6481         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6482         I915_WRITE(aud_cntrl_st2, tmp);
6483
6484         /* Wait for 1 vertical blank */
6485         intel_wait_for_vblank(dev, pipe);
6486
6487         /* Set ELD valid state */
6488         tmp = I915_READ(aud_cntrl_st2);
6489         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6490         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6491         I915_WRITE(aud_cntrl_st2, tmp);
6492         tmp = I915_READ(aud_cntrl_st2);
6493         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6494
6495         /* Enable HDMI mode */
6496         tmp = I915_READ(aud_config);
6497         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6498         /* clear N_programing_enable and N_value_index */
6499         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6500         I915_WRITE(aud_config, tmp);
6501
6502         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6503
6504         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6505         intel_crtc->eld_vld = true;
6506
6507         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6508                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6509                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6510                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6511         } else
6512                 I915_WRITE(aud_config, 0);
6513
6514         if (intel_eld_uptodate(connector,
6515                                aud_cntrl_st2, eldv,
6516                                aud_cntl_st, IBX_ELD_ADDRESS,
6517                                hdmiw_hdmiedid))
6518                 return;
6519
6520         i = I915_READ(aud_cntrl_st2);
6521         i &= ~eldv;
6522         I915_WRITE(aud_cntrl_st2, i);
6523
6524         if (!eld[0])
6525                 return;
6526
6527         i = I915_READ(aud_cntl_st);
6528         i &= ~IBX_ELD_ADDRESS;
6529         I915_WRITE(aud_cntl_st, i);
6530         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6531         DRM_DEBUG_DRIVER("port num:%d\n", i);
6532
6533         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6534         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6535         for (i = 0; i < len; i++)
6536                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6537
6538         i = I915_READ(aud_cntrl_st2);
6539         i |= eldv;
6540         I915_WRITE(aud_cntrl_st2, i);
6541
6542 }
6543
6544 static void ironlake_write_eld(struct drm_connector *connector,
6545                                      struct drm_crtc *crtc)
6546 {
6547         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6548         uint8_t *eld = connector->eld;
6549         uint32_t eldv;
6550         uint32_t i;
6551         int len;
6552         int hdmiw_hdmiedid;
6553         int aud_config;
6554         int aud_cntl_st;
6555         int aud_cntrl_st2;
6556         int pipe = to_intel_crtc(crtc)->pipe;
6557
6558         if (HAS_PCH_IBX(connector->dev)) {
6559                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6560                 aud_config = IBX_AUD_CFG(pipe);
6561                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6562                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6563         } else {
6564                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6565                 aud_config = CPT_AUD_CFG(pipe);
6566                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6567                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6568         }
6569
6570         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6571
6572         i = I915_READ(aud_cntl_st);
6573         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6574         if (!i) {
6575                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6576                 /* operate blindly on all ports */
6577                 eldv = IBX_ELD_VALIDB;
6578                 eldv |= IBX_ELD_VALIDB << 4;
6579                 eldv |= IBX_ELD_VALIDB << 8;
6580         } else {
6581                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6582                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6583         }
6584
6585         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6586                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6587                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6588                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6589         } else
6590                 I915_WRITE(aud_config, 0);
6591
6592         if (intel_eld_uptodate(connector,
6593                                aud_cntrl_st2, eldv,
6594                                aud_cntl_st, IBX_ELD_ADDRESS,
6595                                hdmiw_hdmiedid))
6596                 return;
6597
6598         i = I915_READ(aud_cntrl_st2);
6599         i &= ~eldv;
6600         I915_WRITE(aud_cntrl_st2, i);
6601
6602         if (!eld[0])
6603                 return;
6604
6605         i = I915_READ(aud_cntl_st);
6606         i &= ~IBX_ELD_ADDRESS;
6607         I915_WRITE(aud_cntl_st, i);
6608
6609         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6610         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6611         for (i = 0; i < len; i++)
6612                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6613
6614         i = I915_READ(aud_cntrl_st2);
6615         i |= eldv;
6616         I915_WRITE(aud_cntrl_st2, i);
6617 }
6618
6619 void intel_write_eld(struct drm_encoder *encoder,
6620                      struct drm_display_mode *mode)
6621 {
6622         struct drm_crtc *crtc = encoder->crtc;
6623         struct drm_connector *connector;
6624         struct drm_device *dev = encoder->dev;
6625         struct drm_i915_private *dev_priv = dev->dev_private;
6626
6627         connector = drm_select_eld(encoder, mode);
6628         if (!connector)
6629                 return;
6630
6631         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6632                          connector->base.id,
6633                          drm_get_connector_name(connector),
6634                          connector->encoder->base.id,
6635                          drm_get_encoder_name(connector->encoder));
6636
6637         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6638
6639         if (dev_priv->display.write_eld)
6640                 dev_priv->display.write_eld(connector, crtc);
6641 }
6642
6643 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6644 void intel_crtc_load_lut(struct drm_crtc *crtc)
6645 {
6646         struct drm_device *dev = crtc->dev;
6647         struct drm_i915_private *dev_priv = dev->dev_private;
6648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649         enum pipe pipe = intel_crtc->pipe;
6650         int palreg = PALETTE(pipe);
6651         int i;
6652         bool reenable_ips = false;
6653
6654         /* The clocks have to be on to load the palette. */
6655         if (!crtc->enabled || !intel_crtc->active)
6656                 return;
6657
6658         if (!HAS_PCH_SPLIT(dev_priv->dev))
6659                 assert_pll_enabled(dev_priv, pipe);
6660
6661         /* use legacy palette for Ironlake */
6662         if (HAS_PCH_SPLIT(dev))
6663                 palreg = LGC_PALETTE(pipe);
6664
6665         /* Workaround : Do not read or write the pipe palette/gamma data while
6666          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6667          */
6668         if (intel_crtc->config.ips_enabled &&
6669             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6670              GAMMA_MODE_MODE_SPLIT)) {
6671                 hsw_disable_ips(intel_crtc);
6672                 reenable_ips = true;
6673         }
6674
6675         for (i = 0; i < 256; i++) {
6676                 I915_WRITE(palreg + 4 * i,
6677                            (intel_crtc->lut_r[i] << 16) |
6678                            (intel_crtc->lut_g[i] << 8) |
6679                            intel_crtc->lut_b[i]);
6680         }
6681
6682         if (reenable_ips)
6683                 hsw_enable_ips(intel_crtc);
6684 }
6685
6686 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6687 {
6688         struct drm_device *dev = crtc->dev;
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691         bool visible = base != 0;
6692         u32 cntl;
6693
6694         if (intel_crtc->cursor_visible == visible)
6695                 return;
6696
6697         cntl = I915_READ(_CURACNTR);
6698         if (visible) {
6699                 /* On these chipsets we can only modify the base whilst
6700                  * the cursor is disabled.
6701                  */
6702                 I915_WRITE(_CURABASE, base);
6703
6704                 cntl &= ~(CURSOR_FORMAT_MASK);
6705                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6706                 cntl |= CURSOR_ENABLE |
6707                         CURSOR_GAMMA_ENABLE |
6708                         CURSOR_FORMAT_ARGB;
6709         } else
6710                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6711         I915_WRITE(_CURACNTR, cntl);
6712
6713         intel_crtc->cursor_visible = visible;
6714 }
6715
6716 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6717 {
6718         struct drm_device *dev = crtc->dev;
6719         struct drm_i915_private *dev_priv = dev->dev_private;
6720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6721         int pipe = intel_crtc->pipe;
6722         bool visible = base != 0;
6723
6724         if (intel_crtc->cursor_visible != visible) {
6725                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6726                 if (base) {
6727                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6728                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6729                         cntl |= pipe << 28; /* Connect to correct pipe */
6730                 } else {
6731                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6732                         cntl |= CURSOR_MODE_DISABLE;
6733                 }
6734                 I915_WRITE(CURCNTR(pipe), cntl);
6735
6736                 intel_crtc->cursor_visible = visible;
6737         }
6738         /* and commit changes on next vblank */
6739         I915_WRITE(CURBASE(pipe), base);
6740 }
6741
6742 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6743 {
6744         struct drm_device *dev = crtc->dev;
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6747         int pipe = intel_crtc->pipe;
6748         bool visible = base != 0;
6749
6750         if (intel_crtc->cursor_visible != visible) {
6751                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6752                 if (base) {
6753                         cntl &= ~CURSOR_MODE;
6754                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6755                 } else {
6756                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6757                         cntl |= CURSOR_MODE_DISABLE;
6758                 }
6759                 if (IS_HASWELL(dev)) {
6760                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6761                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6762                 }
6763                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6764
6765                 intel_crtc->cursor_visible = visible;
6766         }
6767         /* and commit changes on next vblank */
6768         I915_WRITE(CURBASE_IVB(pipe), base);
6769 }
6770
6771 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6772 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6773                                      bool on)
6774 {
6775         struct drm_device *dev = crtc->dev;
6776         struct drm_i915_private *dev_priv = dev->dev_private;
6777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778         int pipe = intel_crtc->pipe;
6779         int x = intel_crtc->cursor_x;
6780         int y = intel_crtc->cursor_y;
6781         u32 base, pos;
6782         bool visible;
6783
6784         pos = 0;
6785
6786         if (on && crtc->enabled && crtc->fb) {
6787                 base = intel_crtc->cursor_addr;
6788                 if (x > (int) crtc->fb->width)
6789                         base = 0;
6790
6791                 if (y > (int) crtc->fb->height)
6792                         base = 0;
6793         } else
6794                 base = 0;
6795
6796         if (x < 0) {
6797                 if (x + intel_crtc->cursor_width < 0)
6798                         base = 0;
6799
6800                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6801                 x = -x;
6802         }
6803         pos |= x << CURSOR_X_SHIFT;
6804
6805         if (y < 0) {
6806                 if (y + intel_crtc->cursor_height < 0)
6807                         base = 0;
6808
6809                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6810                 y = -y;
6811         }
6812         pos |= y << CURSOR_Y_SHIFT;
6813
6814         visible = base != 0;
6815         if (!visible && !intel_crtc->cursor_visible)
6816                 return;
6817
6818         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6819                 I915_WRITE(CURPOS_IVB(pipe), pos);
6820                 ivb_update_cursor(crtc, base);
6821         } else {
6822                 I915_WRITE(CURPOS(pipe), pos);
6823                 if (IS_845G(dev) || IS_I865G(dev))
6824                         i845_update_cursor(crtc, base);
6825                 else
6826                         i9xx_update_cursor(crtc, base);
6827         }
6828 }
6829
6830 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6831                                  struct drm_file *file,
6832                                  uint32_t handle,
6833                                  uint32_t width, uint32_t height)
6834 {
6835         struct drm_device *dev = crtc->dev;
6836         struct drm_i915_private *dev_priv = dev->dev_private;
6837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838         struct drm_i915_gem_object *obj;
6839         uint32_t addr;
6840         int ret;
6841
6842         /* if we want to turn off the cursor ignore width and height */
6843         if (!handle) {
6844                 DRM_DEBUG_KMS("cursor off\n");
6845                 addr = 0;
6846                 obj = NULL;
6847                 mutex_lock(&dev->struct_mutex);
6848                 goto finish;
6849         }
6850
6851         /* Currently we only support 64x64 cursors */
6852         if (width != 64 || height != 64) {
6853                 DRM_ERROR("we currently only support 64x64 cursors\n");
6854                 return -EINVAL;
6855         }
6856
6857         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6858         if (&obj->base == NULL)
6859                 return -ENOENT;
6860
6861         if (obj->base.size < width * height * 4) {
6862                 DRM_ERROR("buffer is to small\n");
6863                 ret = -ENOMEM;
6864                 goto fail;
6865         }
6866
6867         /* we only need to pin inside GTT if cursor is non-phy */
6868         mutex_lock(&dev->struct_mutex);
6869         if (!dev_priv->info->cursor_needs_physical) {
6870                 unsigned alignment;
6871
6872                 if (obj->tiling_mode) {
6873                         DRM_ERROR("cursor cannot be tiled\n");
6874                         ret = -EINVAL;
6875                         goto fail_locked;
6876                 }
6877
6878                 /* Note that the w/a also requires 2 PTE of padding following
6879                  * the bo. We currently fill all unused PTE with the shadow
6880                  * page and so we should always have valid PTE following the
6881                  * cursor preventing the VT-d warning.
6882                  */
6883                 alignment = 0;
6884                 if (need_vtd_wa(dev))
6885                         alignment = 64*1024;
6886
6887                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6888                 if (ret) {
6889                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6890                         goto fail_locked;
6891                 }
6892
6893                 ret = i915_gem_object_put_fence(obj);
6894                 if (ret) {
6895                         DRM_ERROR("failed to release fence for cursor");
6896                         goto fail_unpin;
6897                 }
6898
6899                 addr = i915_gem_obj_ggtt_offset(obj);
6900         } else {
6901                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6902                 ret = i915_gem_attach_phys_object(dev, obj,
6903                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6904                                                   align);
6905                 if (ret) {
6906                         DRM_ERROR("failed to attach phys object\n");
6907                         goto fail_locked;
6908                 }
6909                 addr = obj->phys_obj->handle->busaddr;
6910         }
6911
6912         if (IS_GEN2(dev))
6913                 I915_WRITE(CURSIZE, (height << 12) | width);
6914
6915  finish:
6916         if (intel_crtc->cursor_bo) {
6917                 if (dev_priv->info->cursor_needs_physical) {
6918                         if (intel_crtc->cursor_bo != obj)
6919                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6920                 } else
6921                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6922                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6923         }
6924
6925         mutex_unlock(&dev->struct_mutex);
6926
6927         intel_crtc->cursor_addr = addr;
6928         intel_crtc->cursor_bo = obj;
6929         intel_crtc->cursor_width = width;
6930         intel_crtc->cursor_height = height;
6931
6932         if (intel_crtc->active)
6933                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6934
6935         return 0;
6936 fail_unpin:
6937         i915_gem_object_unpin_from_display_plane(obj);
6938 fail_locked:
6939         mutex_unlock(&dev->struct_mutex);
6940 fail:
6941         drm_gem_object_unreference_unlocked(&obj->base);
6942         return ret;
6943 }
6944
6945 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6946 {
6947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6948
6949         intel_crtc->cursor_x = x;
6950         intel_crtc->cursor_y = y;
6951
6952         if (intel_crtc->active)
6953                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6954
6955         return 0;
6956 }
6957
6958 /** Sets the color ramps on behalf of RandR */
6959 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6960                                  u16 blue, int regno)
6961 {
6962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6963
6964         intel_crtc->lut_r[regno] = red >> 8;
6965         intel_crtc->lut_g[regno] = green >> 8;
6966         intel_crtc->lut_b[regno] = blue >> 8;
6967 }
6968
6969 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6970                              u16 *blue, int regno)
6971 {
6972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6973
6974         *red = intel_crtc->lut_r[regno] << 8;
6975         *green = intel_crtc->lut_g[regno] << 8;
6976         *blue = intel_crtc->lut_b[regno] << 8;
6977 }
6978
6979 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6980                                  u16 *blue, uint32_t start, uint32_t size)
6981 {
6982         int end = (start + size > 256) ? 256 : start + size, i;
6983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6984
6985         for (i = start; i < end; i++) {
6986                 intel_crtc->lut_r[i] = red[i] >> 8;
6987                 intel_crtc->lut_g[i] = green[i] >> 8;
6988                 intel_crtc->lut_b[i] = blue[i] >> 8;
6989         }
6990
6991         intel_crtc_load_lut(crtc);
6992 }
6993
6994 /* VESA 640x480x72Hz mode to set on the pipe */
6995 static struct drm_display_mode load_detect_mode = {
6996         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6997                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6998 };
6999
7000 static struct drm_framebuffer *
7001 intel_framebuffer_create(struct drm_device *dev,
7002                          struct drm_mode_fb_cmd2 *mode_cmd,
7003                          struct drm_i915_gem_object *obj)
7004 {
7005         struct intel_framebuffer *intel_fb;
7006         int ret;
7007
7008         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7009         if (!intel_fb) {
7010                 drm_gem_object_unreference_unlocked(&obj->base);
7011                 return ERR_PTR(-ENOMEM);
7012         }
7013
7014         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7015         if (ret) {
7016                 drm_gem_object_unreference_unlocked(&obj->base);
7017                 kfree(intel_fb);
7018                 return ERR_PTR(ret);
7019         }
7020
7021         return &intel_fb->base;
7022 }
7023
7024 static u32
7025 intel_framebuffer_pitch_for_width(int width, int bpp)
7026 {
7027         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7028         return ALIGN(pitch, 64);
7029 }
7030
7031 static u32
7032 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7033 {
7034         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7035         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7036 }
7037
7038 static struct drm_framebuffer *
7039 intel_framebuffer_create_for_mode(struct drm_device *dev,
7040                                   struct drm_display_mode *mode,
7041                                   int depth, int bpp)
7042 {
7043         struct drm_i915_gem_object *obj;
7044         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7045
7046         obj = i915_gem_alloc_object(dev,
7047                                     intel_framebuffer_size_for_mode(mode, bpp));
7048         if (obj == NULL)
7049                 return ERR_PTR(-ENOMEM);
7050
7051         mode_cmd.width = mode->hdisplay;
7052         mode_cmd.height = mode->vdisplay;
7053         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7054                                                                 bpp);
7055         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7056
7057         return intel_framebuffer_create(dev, &mode_cmd, obj);
7058 }
7059
7060 static struct drm_framebuffer *
7061 mode_fits_in_fbdev(struct drm_device *dev,
7062                    struct drm_display_mode *mode)
7063 {
7064         struct drm_i915_private *dev_priv = dev->dev_private;
7065         struct drm_i915_gem_object *obj;
7066         struct drm_framebuffer *fb;
7067
7068         if (dev_priv->fbdev == NULL)
7069                 return NULL;
7070
7071         obj = dev_priv->fbdev->ifb.obj;
7072         if (obj == NULL)
7073                 return NULL;
7074
7075         fb = &dev_priv->fbdev->ifb.base;
7076         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7077                                                                fb->bits_per_pixel))
7078                 return NULL;
7079
7080         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7081                 return NULL;
7082
7083         return fb;
7084 }
7085
7086 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7087                                 struct drm_display_mode *mode,
7088                                 struct intel_load_detect_pipe *old)
7089 {
7090         struct intel_crtc *intel_crtc;
7091         struct intel_encoder *intel_encoder =
7092                 intel_attached_encoder(connector);
7093         struct drm_crtc *possible_crtc;
7094         struct drm_encoder *encoder = &intel_encoder->base;
7095         struct drm_crtc *crtc = NULL;
7096         struct drm_device *dev = encoder->dev;
7097         struct drm_framebuffer *fb;
7098         int i = -1;
7099
7100         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7101                       connector->base.id, drm_get_connector_name(connector),
7102                       encoder->base.id, drm_get_encoder_name(encoder));
7103
7104         /*
7105          * Algorithm gets a little messy:
7106          *
7107          *   - if the connector already has an assigned crtc, use it (but make
7108          *     sure it's on first)
7109          *
7110          *   - try to find the first unused crtc that can drive this connector,
7111          *     and use that if we find one
7112          */
7113
7114         /* See if we already have a CRTC for this connector */
7115         if (encoder->crtc) {
7116                 crtc = encoder->crtc;
7117
7118                 mutex_lock(&crtc->mutex);
7119
7120                 old->dpms_mode = connector->dpms;
7121                 old->load_detect_temp = false;
7122
7123                 /* Make sure the crtc and connector are running */
7124                 if (connector->dpms != DRM_MODE_DPMS_ON)
7125                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7126
7127                 return true;
7128         }
7129
7130         /* Find an unused one (if possible) */
7131         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7132                 i++;
7133                 if (!(encoder->possible_crtcs & (1 << i)))
7134                         continue;
7135                 if (!possible_crtc->enabled) {
7136                         crtc = possible_crtc;
7137                         break;
7138                 }
7139         }
7140
7141         /*
7142          * If we didn't find an unused CRTC, don't use any.
7143          */
7144         if (!crtc) {
7145                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7146                 return false;
7147         }
7148
7149         mutex_lock(&crtc->mutex);
7150         intel_encoder->new_crtc = to_intel_crtc(crtc);
7151         to_intel_connector(connector)->new_encoder = intel_encoder;
7152
7153         intel_crtc = to_intel_crtc(crtc);
7154         old->dpms_mode = connector->dpms;
7155         old->load_detect_temp = true;
7156         old->release_fb = NULL;
7157
7158         if (!mode)
7159                 mode = &load_detect_mode;
7160
7161         /* We need a framebuffer large enough to accommodate all accesses
7162          * that the plane may generate whilst we perform load detection.
7163          * We can not rely on the fbcon either being present (we get called
7164          * during its initialisation to detect all boot displays, or it may
7165          * not even exist) or that it is large enough to satisfy the
7166          * requested mode.
7167          */
7168         fb = mode_fits_in_fbdev(dev, mode);
7169         if (fb == NULL) {
7170                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7171                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7172                 old->release_fb = fb;
7173         } else
7174                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7175         if (IS_ERR(fb)) {
7176                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7177                 mutex_unlock(&crtc->mutex);
7178                 return false;
7179         }
7180
7181         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7182                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7183                 if (old->release_fb)
7184                         old->release_fb->funcs->destroy(old->release_fb);
7185                 mutex_unlock(&crtc->mutex);
7186                 return false;
7187         }
7188
7189         /* let the connector get through one full cycle before testing */
7190         intel_wait_for_vblank(dev, intel_crtc->pipe);
7191         return true;
7192 }
7193
7194 void intel_release_load_detect_pipe(struct drm_connector *connector,
7195                                     struct intel_load_detect_pipe *old)
7196 {
7197         struct intel_encoder *intel_encoder =
7198                 intel_attached_encoder(connector);
7199         struct drm_encoder *encoder = &intel_encoder->base;
7200         struct drm_crtc *crtc = encoder->crtc;
7201
7202         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7203                       connector->base.id, drm_get_connector_name(connector),
7204                       encoder->base.id, drm_get_encoder_name(encoder));
7205
7206         if (old->load_detect_temp) {
7207                 to_intel_connector(connector)->new_encoder = NULL;
7208                 intel_encoder->new_crtc = NULL;
7209                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7210
7211                 if (old->release_fb) {
7212                         drm_framebuffer_unregister_private(old->release_fb);
7213                         drm_framebuffer_unreference(old->release_fb);
7214                 }
7215
7216                 mutex_unlock(&crtc->mutex);
7217                 return;
7218         }
7219
7220         /* Switch crtc and encoder back off if necessary */
7221         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7222                 connector->funcs->dpms(connector, old->dpms_mode);
7223
7224         mutex_unlock(&crtc->mutex);
7225 }
7226
7227 /* Returns the clock of the currently programmed mode of the given pipe. */
7228 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7229                                 struct intel_crtc_config *pipe_config)
7230 {
7231         struct drm_device *dev = crtc->base.dev;
7232         struct drm_i915_private *dev_priv = dev->dev_private;
7233         int pipe = pipe_config->cpu_transcoder;
7234         u32 dpll = I915_READ(DPLL(pipe));
7235         u32 fp;
7236         intel_clock_t clock;
7237
7238         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7239                 fp = I915_READ(FP0(pipe));
7240         else
7241                 fp = I915_READ(FP1(pipe));
7242
7243         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7244         if (IS_PINEVIEW(dev)) {
7245                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7246                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7247         } else {
7248                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7249                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7250         }
7251
7252         if (!IS_GEN2(dev)) {
7253                 if (IS_PINEVIEW(dev))
7254                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7255                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7256                 else
7257                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7258                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7259
7260                 switch (dpll & DPLL_MODE_MASK) {
7261                 case DPLLB_MODE_DAC_SERIAL:
7262                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7263                                 5 : 10;
7264                         break;
7265                 case DPLLB_MODE_LVDS:
7266                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7267                                 7 : 14;
7268                         break;
7269                 default:
7270                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7271                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7272                         pipe_config->adjusted_mode.clock = 0;
7273                         return;
7274                 }
7275
7276                 if (IS_PINEVIEW(dev))
7277                         pineview_clock(96000, &clock);
7278                 else
7279                         i9xx_clock(96000, &clock);
7280         } else {
7281                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7282
7283                 if (is_lvds) {
7284                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7285                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7286                         clock.p2 = 14;
7287
7288                         if ((dpll & PLL_REF_INPUT_MASK) ==
7289                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7290                                 /* XXX: might not be 66MHz */
7291                                 i9xx_clock(66000, &clock);
7292                         } else
7293                                 i9xx_clock(48000, &clock);
7294                 } else {
7295                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7296                                 clock.p1 = 2;
7297                         else {
7298                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7299                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7300                         }
7301                         if (dpll & PLL_P2_DIVIDE_BY_4)
7302                                 clock.p2 = 4;
7303                         else
7304                                 clock.p2 = 2;
7305
7306                         i9xx_clock(48000, &clock);
7307                 }
7308         }
7309
7310         pipe_config->adjusted_mode.clock = clock.dot;
7311 }
7312
7313 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7314                                     struct intel_crtc_config *pipe_config)
7315 {
7316         struct drm_device *dev = crtc->base.dev;
7317         struct drm_i915_private *dev_priv = dev->dev_private;
7318         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7319         int link_freq, repeat;
7320         u64 clock;
7321         u32 link_m, link_n;
7322
7323         repeat = pipe_config->pixel_multiplier;
7324
7325         /*
7326          * The calculation for the data clock is:
7327          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7328          * But we want to avoid losing precison if possible, so:
7329          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7330          *
7331          * and the link clock is simpler:
7332          * link_clock = (m * link_clock * repeat) / n
7333          */
7334
7335         /*
7336          * We need to get the FDI or DP link clock here to derive
7337          * the M/N dividers.
7338          *
7339          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7340          * For DP, it's either 1.62GHz or 2.7GHz.
7341          * We do our calculations in 10*MHz since we don't need much precison.
7342          */
7343         if (pipe_config->has_pch_encoder)
7344                 link_freq = intel_fdi_link_freq(dev) * 10000;
7345         else
7346                 link_freq = pipe_config->port_clock;
7347
7348         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7349         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7350
7351         if (!link_m || !link_n)
7352                 return;
7353
7354         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7355         do_div(clock, link_n);
7356
7357         pipe_config->adjusted_mode.clock = clock;
7358 }
7359
7360 /** Returns the currently programmed mode of the given pipe. */
7361 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7362                                              struct drm_crtc *crtc)
7363 {
7364         struct drm_i915_private *dev_priv = dev->dev_private;
7365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7367         struct drm_display_mode *mode;
7368         struct intel_crtc_config pipe_config;
7369         int htot = I915_READ(HTOTAL(cpu_transcoder));
7370         int hsync = I915_READ(HSYNC(cpu_transcoder));
7371         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7372         int vsync = I915_READ(VSYNC(cpu_transcoder));
7373
7374         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7375         if (!mode)
7376                 return NULL;
7377
7378         /*
7379          * Construct a pipe_config sufficient for getting the clock info
7380          * back out of crtc_clock_get.
7381          *
7382          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7383          * to use a real value here instead.
7384          */
7385         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7386         pipe_config.pixel_multiplier = 1;
7387         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7388
7389         mode->clock = pipe_config.adjusted_mode.clock;
7390         mode->hdisplay = (htot & 0xffff) + 1;
7391         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7392         mode->hsync_start = (hsync & 0xffff) + 1;
7393         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7394         mode->vdisplay = (vtot & 0xffff) + 1;
7395         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7396         mode->vsync_start = (vsync & 0xffff) + 1;
7397         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7398
7399         drm_mode_set_name(mode);
7400
7401         return mode;
7402 }
7403
7404 static void intel_increase_pllclock(struct drm_crtc *crtc)
7405 {
7406         struct drm_device *dev = crtc->dev;
7407         drm_i915_private_t *dev_priv = dev->dev_private;
7408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7409         int pipe = intel_crtc->pipe;
7410         int dpll_reg = DPLL(pipe);
7411         int dpll;
7412
7413         if (HAS_PCH_SPLIT(dev))
7414                 return;
7415
7416         if (!dev_priv->lvds_downclock_avail)
7417                 return;
7418
7419         dpll = I915_READ(dpll_reg);
7420         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7421                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7422
7423                 assert_panel_unlocked(dev_priv, pipe);
7424
7425                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7426                 I915_WRITE(dpll_reg, dpll);
7427                 intel_wait_for_vblank(dev, pipe);
7428
7429                 dpll = I915_READ(dpll_reg);
7430                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7431                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7432         }
7433 }
7434
7435 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7436 {
7437         struct drm_device *dev = crtc->dev;
7438         drm_i915_private_t *dev_priv = dev->dev_private;
7439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7440
7441         if (HAS_PCH_SPLIT(dev))
7442                 return;
7443
7444         if (!dev_priv->lvds_downclock_avail)
7445                 return;
7446
7447         /*
7448          * Since this is called by a timer, we should never get here in
7449          * the manual case.
7450          */
7451         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7452                 int pipe = intel_crtc->pipe;
7453                 int dpll_reg = DPLL(pipe);
7454                 int dpll;
7455
7456                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7457
7458                 assert_panel_unlocked(dev_priv, pipe);
7459
7460                 dpll = I915_READ(dpll_reg);
7461                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7462                 I915_WRITE(dpll_reg, dpll);
7463                 intel_wait_for_vblank(dev, pipe);
7464                 dpll = I915_READ(dpll_reg);
7465                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7466                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7467         }
7468
7469 }
7470
7471 void intel_mark_busy(struct drm_device *dev)
7472 {
7473         struct drm_i915_private *dev_priv = dev->dev_private;
7474
7475         hsw_package_c8_gpu_busy(dev_priv);
7476         i915_update_gfx_val(dev_priv);
7477 }
7478
7479 void intel_mark_idle(struct drm_device *dev)
7480 {
7481         struct drm_i915_private *dev_priv = dev->dev_private;
7482         struct drm_crtc *crtc;
7483
7484         hsw_package_c8_gpu_idle(dev_priv);
7485
7486         if (!i915_powersave)
7487                 return;
7488
7489         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7490                 if (!crtc->fb)
7491                         continue;
7492
7493                 intel_decrease_pllclock(crtc);
7494         }
7495 }
7496
7497 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7498                         struct intel_ring_buffer *ring)
7499 {
7500         struct drm_device *dev = obj->base.dev;
7501         struct drm_crtc *crtc;
7502
7503         if (!i915_powersave)
7504                 return;
7505
7506         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7507                 if (!crtc->fb)
7508                         continue;
7509
7510                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7511                         continue;
7512
7513                 intel_increase_pllclock(crtc);
7514                 if (ring && intel_fbc_enabled(dev))
7515                         ring->fbc_dirty = true;
7516         }
7517 }
7518
7519 static void intel_crtc_destroy(struct drm_crtc *crtc)
7520 {
7521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7522         struct drm_device *dev = crtc->dev;
7523         struct intel_unpin_work *work;
7524         unsigned long flags;
7525
7526         spin_lock_irqsave(&dev->event_lock, flags);
7527         work = intel_crtc->unpin_work;
7528         intel_crtc->unpin_work = NULL;
7529         spin_unlock_irqrestore(&dev->event_lock, flags);
7530
7531         if (work) {
7532                 cancel_work_sync(&work->work);
7533                 kfree(work);
7534         }
7535
7536         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7537
7538         drm_crtc_cleanup(crtc);
7539
7540         kfree(intel_crtc);
7541 }
7542
7543 static void intel_unpin_work_fn(struct work_struct *__work)
7544 {
7545         struct intel_unpin_work *work =
7546                 container_of(__work, struct intel_unpin_work, work);
7547         struct drm_device *dev = work->crtc->dev;
7548
7549         mutex_lock(&dev->struct_mutex);
7550         intel_unpin_fb_obj(work->old_fb_obj);
7551         drm_gem_object_unreference(&work->pending_flip_obj->base);
7552         drm_gem_object_unreference(&work->old_fb_obj->base);
7553
7554         intel_update_fbc(dev);
7555         mutex_unlock(&dev->struct_mutex);
7556
7557         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7558         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7559
7560         kfree(work);
7561 }
7562
7563 static void do_intel_finish_page_flip(struct drm_device *dev,
7564                                       struct drm_crtc *crtc)
7565 {
7566         drm_i915_private_t *dev_priv = dev->dev_private;
7567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7568         struct intel_unpin_work *work;
7569         unsigned long flags;
7570
7571         /* Ignore early vblank irqs */
7572         if (intel_crtc == NULL)
7573                 return;
7574
7575         spin_lock_irqsave(&dev->event_lock, flags);
7576         work = intel_crtc->unpin_work;
7577
7578         /* Ensure we don't miss a work->pending update ... */
7579         smp_rmb();
7580
7581         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7582                 spin_unlock_irqrestore(&dev->event_lock, flags);
7583                 return;
7584         }
7585
7586         /* and that the unpin work is consistent wrt ->pending. */
7587         smp_rmb();
7588
7589         intel_crtc->unpin_work = NULL;
7590
7591         if (work->event)
7592                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7593
7594         drm_vblank_put(dev, intel_crtc->pipe);
7595
7596         spin_unlock_irqrestore(&dev->event_lock, flags);
7597
7598         wake_up_all(&dev_priv->pending_flip_queue);
7599
7600         queue_work(dev_priv->wq, &work->work);
7601
7602         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7603 }
7604
7605 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7606 {
7607         drm_i915_private_t *dev_priv = dev->dev_private;
7608         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7609
7610         do_intel_finish_page_flip(dev, crtc);
7611 }
7612
7613 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7614 {
7615         drm_i915_private_t *dev_priv = dev->dev_private;
7616         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7617
7618         do_intel_finish_page_flip(dev, crtc);
7619 }
7620
7621 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7622 {
7623         drm_i915_private_t *dev_priv = dev->dev_private;
7624         struct intel_crtc *intel_crtc =
7625                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7626         unsigned long flags;
7627
7628         /* NB: An MMIO update of the plane base pointer will also
7629          * generate a page-flip completion irq, i.e. every modeset
7630          * is also accompanied by a spurious intel_prepare_page_flip().
7631          */
7632         spin_lock_irqsave(&dev->event_lock, flags);
7633         if (intel_crtc->unpin_work)
7634                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7635         spin_unlock_irqrestore(&dev->event_lock, flags);
7636 }
7637
7638 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7639 {
7640         /* Ensure that the work item is consistent when activating it ... */
7641         smp_wmb();
7642         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7643         /* and that it is marked active as soon as the irq could fire. */
7644         smp_wmb();
7645 }
7646
7647 static int intel_gen2_queue_flip(struct drm_device *dev,
7648                                  struct drm_crtc *crtc,
7649                                  struct drm_framebuffer *fb,
7650                                  struct drm_i915_gem_object *obj,
7651                                  uint32_t flags)
7652 {
7653         struct drm_i915_private *dev_priv = dev->dev_private;
7654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7655         u32 flip_mask;
7656         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7657         int ret;
7658
7659         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7660         if (ret)
7661                 goto err;
7662
7663         ret = intel_ring_begin(ring, 6);
7664         if (ret)
7665                 goto err_unpin;
7666
7667         /* Can't queue multiple flips, so wait for the previous
7668          * one to finish before executing the next.
7669          */
7670         if (intel_crtc->plane)
7671                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7672         else
7673                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7674         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7675         intel_ring_emit(ring, MI_NOOP);
7676         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7677                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7678         intel_ring_emit(ring, fb->pitches[0]);
7679         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7680         intel_ring_emit(ring, 0); /* aux display base address, unused */
7681
7682         intel_mark_page_flip_active(intel_crtc);
7683         intel_ring_advance(ring);
7684         return 0;
7685
7686 err_unpin:
7687         intel_unpin_fb_obj(obj);
7688 err:
7689         return ret;
7690 }
7691
7692 static int intel_gen3_queue_flip(struct drm_device *dev,
7693                                  struct drm_crtc *crtc,
7694                                  struct drm_framebuffer *fb,
7695                                  struct drm_i915_gem_object *obj,
7696                                  uint32_t flags)
7697 {
7698         struct drm_i915_private *dev_priv = dev->dev_private;
7699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7700         u32 flip_mask;
7701         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7702         int ret;
7703
7704         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7705         if (ret)
7706                 goto err;
7707
7708         ret = intel_ring_begin(ring, 6);
7709         if (ret)
7710                 goto err_unpin;
7711
7712         if (intel_crtc->plane)
7713                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7714         else
7715                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7716         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7717         intel_ring_emit(ring, MI_NOOP);
7718         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7719                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7720         intel_ring_emit(ring, fb->pitches[0]);
7721         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7722         intel_ring_emit(ring, MI_NOOP);
7723
7724         intel_mark_page_flip_active(intel_crtc);
7725         intel_ring_advance(ring);
7726         return 0;
7727
7728 err_unpin:
7729         intel_unpin_fb_obj(obj);
7730 err:
7731         return ret;
7732 }
7733
7734 static int intel_gen4_queue_flip(struct drm_device *dev,
7735                                  struct drm_crtc *crtc,
7736                                  struct drm_framebuffer *fb,
7737                                  struct drm_i915_gem_object *obj,
7738                                  uint32_t flags)
7739 {
7740         struct drm_i915_private *dev_priv = dev->dev_private;
7741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7742         uint32_t pf, pipesrc;
7743         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7744         int ret;
7745
7746         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7747         if (ret)
7748                 goto err;
7749
7750         ret = intel_ring_begin(ring, 4);
7751         if (ret)
7752                 goto err_unpin;
7753
7754         /* i965+ uses the linear or tiled offsets from the
7755          * Display Registers (which do not change across a page-flip)
7756          * so we need only reprogram the base address.
7757          */
7758         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7759                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7760         intel_ring_emit(ring, fb->pitches[0]);
7761         intel_ring_emit(ring,
7762                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7763                         obj->tiling_mode);
7764
7765         /* XXX Enabling the panel-fitter across page-flip is so far
7766          * untested on non-native modes, so ignore it for now.
7767          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7768          */
7769         pf = 0;
7770         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7771         intel_ring_emit(ring, pf | pipesrc);
7772
7773         intel_mark_page_flip_active(intel_crtc);
7774         intel_ring_advance(ring);
7775         return 0;
7776
7777 err_unpin:
7778         intel_unpin_fb_obj(obj);
7779 err:
7780         return ret;
7781 }
7782
7783 static int intel_gen6_queue_flip(struct drm_device *dev,
7784                                  struct drm_crtc *crtc,
7785                                  struct drm_framebuffer *fb,
7786                                  struct drm_i915_gem_object *obj,
7787                                  uint32_t flags)
7788 {
7789         struct drm_i915_private *dev_priv = dev->dev_private;
7790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7791         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7792         uint32_t pf, pipesrc;
7793         int ret;
7794
7795         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7796         if (ret)
7797                 goto err;
7798
7799         ret = intel_ring_begin(ring, 4);
7800         if (ret)
7801                 goto err_unpin;
7802
7803         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7804                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7805         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7806         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7807
7808         /* Contrary to the suggestions in the documentation,
7809          * "Enable Panel Fitter" does not seem to be required when page
7810          * flipping with a non-native mode, and worse causes a normal
7811          * modeset to fail.
7812          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7813          */
7814         pf = 0;
7815         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7816         intel_ring_emit(ring, pf | pipesrc);
7817
7818         intel_mark_page_flip_active(intel_crtc);
7819         intel_ring_advance(ring);
7820         return 0;
7821
7822 err_unpin:
7823         intel_unpin_fb_obj(obj);
7824 err:
7825         return ret;
7826 }
7827
7828 static int intel_gen7_queue_flip(struct drm_device *dev,
7829                                  struct drm_crtc *crtc,
7830                                  struct drm_framebuffer *fb,
7831                                  struct drm_i915_gem_object *obj,
7832                                  uint32_t flags)
7833 {
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836         struct intel_ring_buffer *ring;
7837         uint32_t plane_bit = 0;
7838         int len, ret;
7839
7840         ring = obj->ring;
7841         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7842                 ring = &dev_priv->ring[BCS];
7843
7844         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7845         if (ret)
7846                 goto err;
7847
7848         switch(intel_crtc->plane) {
7849         case PLANE_A:
7850                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7851                 break;
7852         case PLANE_B:
7853                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7854                 break;
7855         case PLANE_C:
7856                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7857                 break;
7858         default:
7859                 WARN_ONCE(1, "unknown plane in flip command\n");
7860                 ret = -ENODEV;
7861                 goto err_unpin;
7862         }
7863
7864         len = 4;
7865         if (ring->id == RCS)
7866                 len += 6;
7867
7868         ret = intel_ring_begin(ring, len);
7869         if (ret)
7870                 goto err_unpin;
7871
7872         /* Unmask the flip-done completion message. Note that the bspec says that
7873          * we should do this for both the BCS and RCS, and that we must not unmask
7874          * more than one flip event at any time (or ensure that one flip message
7875          * can be sent by waiting for flip-done prior to queueing new flips).
7876          * Experimentation says that BCS works despite DERRMR masking all
7877          * flip-done completion events and that unmasking all planes at once
7878          * for the RCS also doesn't appear to drop events. Setting the DERRMR
7879          * to zero does lead to lockups within MI_DISPLAY_FLIP.
7880          */
7881         if (ring->id == RCS) {
7882                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7883                 intel_ring_emit(ring, DERRMR);
7884                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7885                                         DERRMR_PIPEB_PRI_FLIP_DONE |
7886                                         DERRMR_PIPEC_PRI_FLIP_DONE));
7887                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7888                 intel_ring_emit(ring, DERRMR);
7889                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7890         }
7891
7892         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7893         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7894         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7895         intel_ring_emit(ring, (MI_NOOP));
7896
7897         intel_mark_page_flip_active(intel_crtc);
7898         intel_ring_advance(ring);
7899         return 0;
7900
7901 err_unpin:
7902         intel_unpin_fb_obj(obj);
7903 err:
7904         return ret;
7905 }
7906
7907 static int intel_default_queue_flip(struct drm_device *dev,
7908                                     struct drm_crtc *crtc,
7909                                     struct drm_framebuffer *fb,
7910                                     struct drm_i915_gem_object *obj,
7911                                     uint32_t flags)
7912 {
7913         return -ENODEV;
7914 }
7915
7916 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7917                                 struct drm_framebuffer *fb,
7918                                 struct drm_pending_vblank_event *event,
7919                                 uint32_t page_flip_flags)
7920 {
7921         struct drm_device *dev = crtc->dev;
7922         struct drm_i915_private *dev_priv = dev->dev_private;
7923         struct drm_framebuffer *old_fb = crtc->fb;
7924         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7926         struct intel_unpin_work *work;
7927         unsigned long flags;
7928         int ret;
7929
7930         /* Can't change pixel format via MI display flips. */
7931         if (fb->pixel_format != crtc->fb->pixel_format)
7932                 return -EINVAL;
7933
7934         /*
7935          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7936          * Note that pitch changes could also affect these register.
7937          */
7938         if (INTEL_INFO(dev)->gen > 3 &&
7939             (fb->offsets[0] != crtc->fb->offsets[0] ||
7940              fb->pitches[0] != crtc->fb->pitches[0]))
7941                 return -EINVAL;
7942
7943         work = kzalloc(sizeof *work, GFP_KERNEL);
7944         if (work == NULL)
7945                 return -ENOMEM;
7946
7947         work->event = event;
7948         work->crtc = crtc;
7949         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7950         INIT_WORK(&work->work, intel_unpin_work_fn);
7951
7952         ret = drm_vblank_get(dev, intel_crtc->pipe);
7953         if (ret)
7954                 goto free_work;
7955
7956         /* We borrow the event spin lock for protecting unpin_work */
7957         spin_lock_irqsave(&dev->event_lock, flags);
7958         if (intel_crtc->unpin_work) {
7959                 spin_unlock_irqrestore(&dev->event_lock, flags);
7960                 kfree(work);
7961                 drm_vblank_put(dev, intel_crtc->pipe);
7962
7963                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7964                 return -EBUSY;
7965         }
7966         intel_crtc->unpin_work = work;
7967         spin_unlock_irqrestore(&dev->event_lock, flags);
7968
7969         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7970                 flush_workqueue(dev_priv->wq);
7971
7972         ret = i915_mutex_lock_interruptible(dev);
7973         if (ret)
7974                 goto cleanup;
7975
7976         /* Reference the objects for the scheduled work. */
7977         drm_gem_object_reference(&work->old_fb_obj->base);
7978         drm_gem_object_reference(&obj->base);
7979
7980         crtc->fb = fb;
7981
7982         work->pending_flip_obj = obj;
7983
7984         work->enable_stall_check = true;
7985
7986         atomic_inc(&intel_crtc->unpin_work_count);
7987         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7988
7989         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
7990         if (ret)
7991                 goto cleanup_pending;
7992
7993         intel_disable_fbc(dev);
7994         intel_mark_fb_busy(obj, NULL);
7995         mutex_unlock(&dev->struct_mutex);
7996
7997         trace_i915_flip_request(intel_crtc->plane, obj);
7998
7999         return 0;
8000
8001 cleanup_pending:
8002         atomic_dec(&intel_crtc->unpin_work_count);
8003         crtc->fb = old_fb;
8004         drm_gem_object_unreference(&work->old_fb_obj->base);
8005         drm_gem_object_unreference(&obj->base);
8006         mutex_unlock(&dev->struct_mutex);
8007
8008 cleanup:
8009         spin_lock_irqsave(&dev->event_lock, flags);
8010         intel_crtc->unpin_work = NULL;
8011         spin_unlock_irqrestore(&dev->event_lock, flags);
8012
8013         drm_vblank_put(dev, intel_crtc->pipe);
8014 free_work:
8015         kfree(work);
8016
8017         return ret;
8018 }
8019
8020 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8021         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8022         .load_lut = intel_crtc_load_lut,
8023 };
8024
8025 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8026                                   struct drm_crtc *crtc)
8027 {
8028         struct drm_device *dev;
8029         struct drm_crtc *tmp;
8030         int crtc_mask = 1;
8031
8032         WARN(!crtc, "checking null crtc?\n");
8033
8034         dev = crtc->dev;
8035
8036         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8037                 if (tmp == crtc)
8038                         break;
8039                 crtc_mask <<= 1;
8040         }
8041
8042         if (encoder->possible_crtcs & crtc_mask)
8043                 return true;
8044         return false;
8045 }
8046
8047 /**
8048  * intel_modeset_update_staged_output_state
8049  *
8050  * Updates the staged output configuration state, e.g. after we've read out the
8051  * current hw state.
8052  */
8053 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8054 {
8055         struct intel_encoder *encoder;
8056         struct intel_connector *connector;
8057
8058         list_for_each_entry(connector, &dev->mode_config.connector_list,
8059                             base.head) {
8060                 connector->new_encoder =
8061                         to_intel_encoder(connector->base.encoder);
8062         }
8063
8064         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8065                             base.head) {
8066                 encoder->new_crtc =
8067                         to_intel_crtc(encoder->base.crtc);
8068         }
8069 }
8070
8071 /**
8072  * intel_modeset_commit_output_state
8073  *
8074  * This function copies the stage display pipe configuration to the real one.
8075  */
8076 static void intel_modeset_commit_output_state(struct drm_device *dev)
8077 {
8078         struct intel_encoder *encoder;
8079         struct intel_connector *connector;
8080
8081         list_for_each_entry(connector, &dev->mode_config.connector_list,
8082                             base.head) {
8083                 connector->base.encoder = &connector->new_encoder->base;
8084         }
8085
8086         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8087                             base.head) {
8088                 encoder->base.crtc = &encoder->new_crtc->base;
8089         }
8090 }
8091
8092 static void
8093 connected_sink_compute_bpp(struct intel_connector * connector,
8094                            struct intel_crtc_config *pipe_config)
8095 {
8096         int bpp = pipe_config->pipe_bpp;
8097
8098         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8099                 connector->base.base.id,
8100                 drm_get_connector_name(&connector->base));
8101
8102         /* Don't use an invalid EDID bpc value */
8103         if (connector->base.display_info.bpc &&
8104             connector->base.display_info.bpc * 3 < bpp) {
8105                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8106                               bpp, connector->base.display_info.bpc*3);
8107                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8108         }
8109
8110         /* Clamp bpp to 8 on screens without EDID 1.4 */
8111         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8112                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8113                               bpp);
8114                 pipe_config->pipe_bpp = 24;
8115         }
8116 }
8117
8118 static int
8119 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8120                           struct drm_framebuffer *fb,
8121                           struct intel_crtc_config *pipe_config)
8122 {
8123         struct drm_device *dev = crtc->base.dev;
8124         struct intel_connector *connector;
8125         int bpp;
8126
8127         switch (fb->pixel_format) {
8128         case DRM_FORMAT_C8:
8129                 bpp = 8*3; /* since we go through a colormap */
8130                 break;
8131         case DRM_FORMAT_XRGB1555:
8132         case DRM_FORMAT_ARGB1555:
8133                 /* checked in intel_framebuffer_init already */
8134                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8135                         return -EINVAL;
8136         case DRM_FORMAT_RGB565:
8137                 bpp = 6*3; /* min is 18bpp */
8138                 break;
8139         case DRM_FORMAT_XBGR8888:
8140         case DRM_FORMAT_ABGR8888:
8141                 /* checked in intel_framebuffer_init already */
8142                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8143                         return -EINVAL;
8144         case DRM_FORMAT_XRGB8888:
8145         case DRM_FORMAT_ARGB8888:
8146                 bpp = 8*3;
8147                 break;
8148         case DRM_FORMAT_XRGB2101010:
8149         case DRM_FORMAT_ARGB2101010:
8150         case DRM_FORMAT_XBGR2101010:
8151         case DRM_FORMAT_ABGR2101010:
8152                 /* checked in intel_framebuffer_init already */
8153                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8154                         return -EINVAL;
8155                 bpp = 10*3;
8156                 break;
8157         /* TODO: gen4+ supports 16 bpc floating point, too. */
8158         default:
8159                 DRM_DEBUG_KMS("unsupported depth\n");
8160                 return -EINVAL;
8161         }
8162
8163         pipe_config->pipe_bpp = bpp;
8164
8165         /* Clamp display bpp to EDID value */
8166         list_for_each_entry(connector, &dev->mode_config.connector_list,
8167                             base.head) {
8168                 if (!connector->new_encoder ||
8169                     connector->new_encoder->new_crtc != crtc)
8170                         continue;
8171
8172                 connected_sink_compute_bpp(connector, pipe_config);
8173         }
8174
8175         return bpp;
8176 }
8177
8178 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8179                                    struct intel_crtc_config *pipe_config,
8180                                    const char *context)
8181 {
8182         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8183                       context, pipe_name(crtc->pipe));
8184
8185         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8186         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8187                       pipe_config->pipe_bpp, pipe_config->dither);
8188         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8189                       pipe_config->has_pch_encoder,
8190                       pipe_config->fdi_lanes,
8191                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8192                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8193                       pipe_config->fdi_m_n.tu);
8194         DRM_DEBUG_KMS("requested mode:\n");
8195         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8196         DRM_DEBUG_KMS("adjusted mode:\n");
8197         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8198         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8199                       pipe_config->gmch_pfit.control,
8200                       pipe_config->gmch_pfit.pgm_ratios,
8201                       pipe_config->gmch_pfit.lvds_border_bits);
8202         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8203                       pipe_config->pch_pfit.pos,
8204                       pipe_config->pch_pfit.size,
8205                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8206         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8207 }
8208
8209 static bool check_encoder_cloning(struct drm_crtc *crtc)
8210 {
8211         int num_encoders = 0;
8212         bool uncloneable_encoders = false;
8213         struct intel_encoder *encoder;
8214
8215         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8216                             base.head) {
8217                 if (&encoder->new_crtc->base != crtc)
8218                         continue;
8219
8220                 num_encoders++;
8221                 if (!encoder->cloneable)
8222                         uncloneable_encoders = true;
8223         }
8224
8225         return !(num_encoders > 1 && uncloneable_encoders);
8226 }
8227
8228 static struct intel_crtc_config *
8229 intel_modeset_pipe_config(struct drm_crtc *crtc,
8230                           struct drm_framebuffer *fb,
8231                           struct drm_display_mode *mode)
8232 {
8233         struct drm_device *dev = crtc->dev;
8234         struct intel_encoder *encoder;
8235         struct intel_crtc_config *pipe_config;
8236         int plane_bpp, ret = -EINVAL;
8237         bool retry = true;
8238
8239         if (!check_encoder_cloning(crtc)) {
8240                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8241                 return ERR_PTR(-EINVAL);
8242         }
8243
8244         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8245         if (!pipe_config)
8246                 return ERR_PTR(-ENOMEM);
8247
8248         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8249         drm_mode_copy(&pipe_config->requested_mode, mode);
8250         pipe_config->cpu_transcoder =
8251                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8252         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8253
8254         /*
8255          * Sanitize sync polarity flags based on requested ones. If neither
8256          * positive or negative polarity is requested, treat this as meaning
8257          * negative polarity.
8258          */
8259         if (!(pipe_config->adjusted_mode.flags &
8260               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8261                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8262
8263         if (!(pipe_config->adjusted_mode.flags &
8264               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8265                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8266
8267         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8268          * plane pixel format and any sink constraints into account. Returns the
8269          * source plane bpp so that dithering can be selected on mismatches
8270          * after encoders and crtc also have had their say. */
8271         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8272                                               fb, pipe_config);
8273         if (plane_bpp < 0)
8274                 goto fail;
8275
8276 encoder_retry:
8277         /* Ensure the port clock defaults are reset when retrying. */
8278         pipe_config->port_clock = 0;
8279         pipe_config->pixel_multiplier = 1;
8280
8281         /* Fill in default crtc timings, allow encoders to overwrite them. */
8282         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8283
8284         /* Pass our mode to the connectors and the CRTC to give them a chance to
8285          * adjust it according to limitations or connector properties, and also
8286          * a chance to reject the mode entirely.
8287          */
8288         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8289                             base.head) {
8290
8291                 if (&encoder->new_crtc->base != crtc)
8292                         continue;
8293
8294                 if (!(encoder->compute_config(encoder, pipe_config))) {
8295                         DRM_DEBUG_KMS("Encoder config failure\n");
8296                         goto fail;
8297                 }
8298         }
8299
8300         /* Set default port clock if not overwritten by the encoder. Needs to be
8301          * done afterwards in case the encoder adjusts the mode. */
8302         if (!pipe_config->port_clock)
8303                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8304
8305         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8306         if (ret < 0) {
8307                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8308                 goto fail;
8309         }
8310
8311         if (ret == RETRY) {
8312                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8313                         ret = -EINVAL;
8314                         goto fail;
8315                 }
8316
8317                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8318                 retry = false;
8319                 goto encoder_retry;
8320         }
8321
8322         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8323         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8324                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8325
8326         return pipe_config;
8327 fail:
8328         kfree(pipe_config);
8329         return ERR_PTR(ret);
8330 }
8331
8332 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8333  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8334 static void
8335 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8336                              unsigned *prepare_pipes, unsigned *disable_pipes)
8337 {
8338         struct intel_crtc *intel_crtc;
8339         struct drm_device *dev = crtc->dev;
8340         struct intel_encoder *encoder;
8341         struct intel_connector *connector;
8342         struct drm_crtc *tmp_crtc;
8343
8344         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8345
8346         /* Check which crtcs have changed outputs connected to them, these need
8347          * to be part of the prepare_pipes mask. We don't (yet) support global
8348          * modeset across multiple crtcs, so modeset_pipes will only have one
8349          * bit set at most. */
8350         list_for_each_entry(connector, &dev->mode_config.connector_list,
8351                             base.head) {
8352                 if (connector->base.encoder == &connector->new_encoder->base)
8353                         continue;
8354
8355                 if (connector->base.encoder) {
8356                         tmp_crtc = connector->base.encoder->crtc;
8357
8358                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8359                 }
8360
8361                 if (connector->new_encoder)
8362                         *prepare_pipes |=
8363                                 1 << connector->new_encoder->new_crtc->pipe;
8364         }
8365
8366         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8367                             base.head) {
8368                 if (encoder->base.crtc == &encoder->new_crtc->base)
8369                         continue;
8370
8371                 if (encoder->base.crtc) {
8372                         tmp_crtc = encoder->base.crtc;
8373
8374                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8375                 }
8376
8377                 if (encoder->new_crtc)
8378                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8379         }
8380
8381         /* Check for any pipes that will be fully disabled ... */
8382         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8383                             base.head) {
8384                 bool used = false;
8385
8386                 /* Don't try to disable disabled crtcs. */
8387                 if (!intel_crtc->base.enabled)
8388                         continue;
8389
8390                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8391                                     base.head) {
8392                         if (encoder->new_crtc == intel_crtc)
8393                                 used = true;
8394                 }
8395
8396                 if (!used)
8397                         *disable_pipes |= 1 << intel_crtc->pipe;
8398         }
8399
8400
8401         /* set_mode is also used to update properties on life display pipes. */
8402         intel_crtc = to_intel_crtc(crtc);
8403         if (crtc->enabled)
8404                 *prepare_pipes |= 1 << intel_crtc->pipe;
8405
8406         /*
8407          * For simplicity do a full modeset on any pipe where the output routing
8408          * changed. We could be more clever, but that would require us to be
8409          * more careful with calling the relevant encoder->mode_set functions.
8410          */
8411         if (*prepare_pipes)
8412                 *modeset_pipes = *prepare_pipes;
8413
8414         /* ... and mask these out. */
8415         *modeset_pipes &= ~(*disable_pipes);
8416         *prepare_pipes &= ~(*disable_pipes);
8417
8418         /*
8419          * HACK: We don't (yet) fully support global modesets. intel_set_config
8420          * obies this rule, but the modeset restore mode of
8421          * intel_modeset_setup_hw_state does not.
8422          */
8423         *modeset_pipes &= 1 << intel_crtc->pipe;
8424         *prepare_pipes &= 1 << intel_crtc->pipe;
8425
8426         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8427                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8428 }
8429
8430 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8431 {
8432         struct drm_encoder *encoder;
8433         struct drm_device *dev = crtc->dev;
8434
8435         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8436                 if (encoder->crtc == crtc)
8437                         return true;
8438
8439         return false;
8440 }
8441
8442 static void
8443 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8444 {
8445         struct intel_encoder *intel_encoder;
8446         struct intel_crtc *intel_crtc;
8447         struct drm_connector *connector;
8448
8449         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8450                             base.head) {
8451                 if (!intel_encoder->base.crtc)
8452                         continue;
8453
8454                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8455
8456                 if (prepare_pipes & (1 << intel_crtc->pipe))
8457                         intel_encoder->connectors_active = false;
8458         }
8459
8460         intel_modeset_commit_output_state(dev);
8461
8462         /* Update computed state. */
8463         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8464                             base.head) {
8465                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8466         }
8467
8468         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8469                 if (!connector->encoder || !connector->encoder->crtc)
8470                         continue;
8471
8472                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8473
8474                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8475                         struct drm_property *dpms_property =
8476                                 dev->mode_config.dpms_property;
8477
8478                         connector->dpms = DRM_MODE_DPMS_ON;
8479                         drm_object_property_set_value(&connector->base,
8480                                                          dpms_property,
8481                                                          DRM_MODE_DPMS_ON);
8482
8483                         intel_encoder = to_intel_encoder(connector->encoder);
8484                         intel_encoder->connectors_active = true;
8485                 }
8486         }
8487
8488 }
8489
8490 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8491                                     struct intel_crtc_config *new)
8492 {
8493         int clock1, clock2, diff;
8494
8495         clock1 = cur->adjusted_mode.clock;
8496         clock2 = new->adjusted_mode.clock;
8497
8498         if (clock1 == clock2)
8499                 return true;
8500
8501         if (!clock1 || !clock2)
8502                 return false;
8503
8504         diff = abs(clock1 - clock2);
8505
8506         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8507                 return true;
8508
8509         return false;
8510 }
8511
8512 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8513         list_for_each_entry((intel_crtc), \
8514                             &(dev)->mode_config.crtc_list, \
8515                             base.head) \
8516                 if (mask & (1 <<(intel_crtc)->pipe))
8517
8518 static bool
8519 intel_pipe_config_compare(struct drm_device *dev,
8520                           struct intel_crtc_config *current_config,
8521                           struct intel_crtc_config *pipe_config)
8522 {
8523 #define PIPE_CONF_CHECK_X(name) \
8524         if (current_config->name != pipe_config->name) { \
8525                 DRM_ERROR("mismatch in " #name " " \
8526                           "(expected 0x%08x, found 0x%08x)\n", \
8527                           current_config->name, \
8528                           pipe_config->name); \
8529                 return false; \
8530         }
8531
8532 #define PIPE_CONF_CHECK_I(name) \
8533         if (current_config->name != pipe_config->name) { \
8534                 DRM_ERROR("mismatch in " #name " " \
8535                           "(expected %i, found %i)\n", \
8536                           current_config->name, \
8537                           pipe_config->name); \
8538                 return false; \
8539         }
8540
8541 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8542         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8543                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8544                           "(expected %i, found %i)\n", \
8545                           current_config->name & (mask), \
8546                           pipe_config->name & (mask)); \
8547                 return false; \
8548         }
8549
8550 #define PIPE_CONF_QUIRK(quirk)  \
8551         ((current_config->quirks | pipe_config->quirks) & (quirk))
8552
8553         PIPE_CONF_CHECK_I(cpu_transcoder);
8554
8555         PIPE_CONF_CHECK_I(has_pch_encoder);
8556         PIPE_CONF_CHECK_I(fdi_lanes);
8557         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8558         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8559         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8560         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8561         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8562
8563         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8564         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8565         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8566         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8567         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8568         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8569
8570         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8571         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8572         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8573         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8574         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8575         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8576
8577         PIPE_CONF_CHECK_I(pixel_multiplier);
8578
8579         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8580                               DRM_MODE_FLAG_INTERLACE);
8581
8582         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8583                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8584                                       DRM_MODE_FLAG_PHSYNC);
8585                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8586                                       DRM_MODE_FLAG_NHSYNC);
8587                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8588                                       DRM_MODE_FLAG_PVSYNC);
8589                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8590                                       DRM_MODE_FLAG_NVSYNC);
8591         }
8592
8593         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8594         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8595
8596         PIPE_CONF_CHECK_I(gmch_pfit.control);
8597         /* pfit ratios are autocomputed by the hw on gen4+ */
8598         if (INTEL_INFO(dev)->gen < 4)
8599                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8600         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8601         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8602         if (current_config->pch_pfit.enabled) {
8603                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8604                 PIPE_CONF_CHECK_I(pch_pfit.size);
8605         }
8606
8607         PIPE_CONF_CHECK_I(ips_enabled);
8608
8609         PIPE_CONF_CHECK_I(shared_dpll);
8610         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8611         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8612         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8613         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8614
8615 #undef PIPE_CONF_CHECK_X
8616 #undef PIPE_CONF_CHECK_I
8617 #undef PIPE_CONF_CHECK_FLAGS
8618 #undef PIPE_CONF_QUIRK
8619
8620         if (!IS_HASWELL(dev)) {
8621                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8622                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8623                                   current_config->adjusted_mode.clock,
8624                                   pipe_config->adjusted_mode.clock);
8625                         return false;
8626                 }
8627         }
8628
8629         return true;
8630 }
8631
8632 static void
8633 check_connector_state(struct drm_device *dev)
8634 {
8635         struct intel_connector *connector;
8636
8637         list_for_each_entry(connector, &dev->mode_config.connector_list,
8638                             base.head) {
8639                 /* This also checks the encoder/connector hw state with the
8640                  * ->get_hw_state callbacks. */
8641                 intel_connector_check_state(connector);
8642
8643                 WARN(&connector->new_encoder->base != connector->base.encoder,
8644                      "connector's staged encoder doesn't match current encoder\n");
8645         }
8646 }
8647
8648 static void
8649 check_encoder_state(struct drm_device *dev)
8650 {
8651         struct intel_encoder *encoder;
8652         struct intel_connector *connector;
8653
8654         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8655                             base.head) {
8656                 bool enabled = false;
8657                 bool active = false;
8658                 enum pipe pipe, tracked_pipe;
8659
8660                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8661                               encoder->base.base.id,
8662                               drm_get_encoder_name(&encoder->base));
8663
8664                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8665                      "encoder's stage crtc doesn't match current crtc\n");
8666                 WARN(encoder->connectors_active && !encoder->base.crtc,
8667                      "encoder's active_connectors set, but no crtc\n");
8668
8669                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8670                                     base.head) {
8671                         if (connector->base.encoder != &encoder->base)
8672                                 continue;
8673                         enabled = true;
8674                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8675                                 active = true;
8676                 }
8677                 WARN(!!encoder->base.crtc != enabled,
8678                      "encoder's enabled state mismatch "
8679                      "(expected %i, found %i)\n",
8680                      !!encoder->base.crtc, enabled);
8681                 WARN(active && !encoder->base.crtc,
8682                      "active encoder with no crtc\n");
8683
8684                 WARN(encoder->connectors_active != active,
8685                      "encoder's computed active state doesn't match tracked active state "
8686                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8687
8688                 active = encoder->get_hw_state(encoder, &pipe);
8689                 WARN(active != encoder->connectors_active,
8690                      "encoder's hw state doesn't match sw tracking "
8691                      "(expected %i, found %i)\n",
8692                      encoder->connectors_active, active);
8693
8694                 if (!encoder->base.crtc)
8695                         continue;
8696
8697                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8698                 WARN(active && pipe != tracked_pipe,
8699                      "active encoder's pipe doesn't match"
8700                      "(expected %i, found %i)\n",
8701                      tracked_pipe, pipe);
8702
8703         }
8704 }
8705
8706 static void
8707 check_crtc_state(struct drm_device *dev)
8708 {
8709         drm_i915_private_t *dev_priv = dev->dev_private;
8710         struct intel_crtc *crtc;
8711         struct intel_encoder *encoder;
8712         struct intel_crtc_config pipe_config;
8713
8714         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8715                             base.head) {
8716                 bool enabled = false;
8717                 bool active = false;
8718
8719                 memset(&pipe_config, 0, sizeof(pipe_config));
8720
8721                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8722                               crtc->base.base.id);
8723
8724                 WARN(crtc->active && !crtc->base.enabled,
8725                      "active crtc, but not enabled in sw tracking\n");
8726
8727                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8728                                     base.head) {
8729                         if (encoder->base.crtc != &crtc->base)
8730                                 continue;
8731                         enabled = true;
8732                         if (encoder->connectors_active)
8733                                 active = true;
8734                 }
8735
8736                 WARN(active != crtc->active,
8737                      "crtc's computed active state doesn't match tracked active state "
8738                      "(expected %i, found %i)\n", active, crtc->active);
8739                 WARN(enabled != crtc->base.enabled,
8740                      "crtc's computed enabled state doesn't match tracked enabled state "
8741                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8742
8743                 active = dev_priv->display.get_pipe_config(crtc,
8744                                                            &pipe_config);
8745
8746                 /* hw state is inconsistent with the pipe A quirk */
8747                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8748                         active = crtc->active;
8749
8750                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8751                                     base.head) {
8752                         enum pipe pipe;
8753                         if (encoder->base.crtc != &crtc->base)
8754                                 continue;
8755                         if (encoder->get_config &&
8756                             encoder->get_hw_state(encoder, &pipe))
8757                                 encoder->get_config(encoder, &pipe_config);
8758                 }
8759
8760                 if (dev_priv->display.get_clock)
8761                         dev_priv->display.get_clock(crtc, &pipe_config);
8762
8763                 WARN(crtc->active != active,
8764                      "crtc active state doesn't match with hw state "
8765                      "(expected %i, found %i)\n", crtc->active, active);
8766
8767                 if (active &&
8768                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8769                         WARN(1, "pipe state doesn't match!\n");
8770                         intel_dump_pipe_config(crtc, &pipe_config,
8771                                                "[hw state]");
8772                         intel_dump_pipe_config(crtc, &crtc->config,
8773                                                "[sw state]");
8774                 }
8775         }
8776 }
8777
8778 static void
8779 check_shared_dpll_state(struct drm_device *dev)
8780 {
8781         drm_i915_private_t *dev_priv = dev->dev_private;
8782         struct intel_crtc *crtc;
8783         struct intel_dpll_hw_state dpll_hw_state;
8784         int i;
8785
8786         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8787                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8788                 int enabled_crtcs = 0, active_crtcs = 0;
8789                 bool active;
8790
8791                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8792
8793                 DRM_DEBUG_KMS("%s\n", pll->name);
8794
8795                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8796
8797                 WARN(pll->active > pll->refcount,
8798                      "more active pll users than references: %i vs %i\n",
8799                      pll->active, pll->refcount);
8800                 WARN(pll->active && !pll->on,
8801                      "pll in active use but not on in sw tracking\n");
8802                 WARN(pll->on && !pll->active,
8803                      "pll in on but not on in use in sw tracking\n");
8804                 WARN(pll->on != active,
8805                      "pll on state mismatch (expected %i, found %i)\n",
8806                      pll->on, active);
8807
8808                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8809                                     base.head) {
8810                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8811                                 enabled_crtcs++;
8812                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8813                                 active_crtcs++;
8814                 }
8815                 WARN(pll->active != active_crtcs,
8816                      "pll active crtcs mismatch (expected %i, found %i)\n",
8817                      pll->active, active_crtcs);
8818                 WARN(pll->refcount != enabled_crtcs,
8819                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8820                      pll->refcount, enabled_crtcs);
8821
8822                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8823                                        sizeof(dpll_hw_state)),
8824                      "pll hw state mismatch\n");
8825         }
8826 }
8827
8828 void
8829 intel_modeset_check_state(struct drm_device *dev)
8830 {
8831         check_connector_state(dev);
8832         check_encoder_state(dev);
8833         check_crtc_state(dev);
8834         check_shared_dpll_state(dev);
8835 }
8836
8837 static int __intel_set_mode(struct drm_crtc *crtc,
8838                             struct drm_display_mode *mode,
8839                             int x, int y, struct drm_framebuffer *fb)
8840 {
8841         struct drm_device *dev = crtc->dev;
8842         drm_i915_private_t *dev_priv = dev->dev_private;
8843         struct drm_display_mode *saved_mode, *saved_hwmode;
8844         struct intel_crtc_config *pipe_config = NULL;
8845         struct intel_crtc *intel_crtc;
8846         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8847         int ret = 0;
8848
8849         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8850         if (!saved_mode)
8851                 return -ENOMEM;
8852         saved_hwmode = saved_mode + 1;
8853
8854         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8855                                      &prepare_pipes, &disable_pipes);
8856
8857         *saved_hwmode = crtc->hwmode;
8858         *saved_mode = crtc->mode;
8859
8860         /* Hack: Because we don't (yet) support global modeset on multiple
8861          * crtcs, we don't keep track of the new mode for more than one crtc.
8862          * Hence simply check whether any bit is set in modeset_pipes in all the
8863          * pieces of code that are not yet converted to deal with mutliple crtcs
8864          * changing their mode at the same time. */
8865         if (modeset_pipes) {
8866                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8867                 if (IS_ERR(pipe_config)) {
8868                         ret = PTR_ERR(pipe_config);
8869                         pipe_config = NULL;
8870
8871                         goto out;
8872                 }
8873                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8874                                        "[modeset]");
8875         }
8876
8877         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8878                 intel_crtc_disable(&intel_crtc->base);
8879
8880         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8881                 if (intel_crtc->base.enabled)
8882                         dev_priv->display.crtc_disable(&intel_crtc->base);
8883         }
8884
8885         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8886          * to set it here already despite that we pass it down the callchain.
8887          */
8888         if (modeset_pipes) {
8889                 crtc->mode = *mode;
8890                 /* mode_set/enable/disable functions rely on a correct pipe
8891                  * config. */
8892                 to_intel_crtc(crtc)->config = *pipe_config;
8893         }
8894
8895         /* Only after disabling all output pipelines that will be changed can we
8896          * update the the output configuration. */
8897         intel_modeset_update_state(dev, prepare_pipes);
8898
8899         if (dev_priv->display.modeset_global_resources)
8900                 dev_priv->display.modeset_global_resources(dev);
8901
8902         /* Set up the DPLL and any encoders state that needs to adjust or depend
8903          * on the DPLL.
8904          */
8905         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8906                 ret = intel_crtc_mode_set(&intel_crtc->base,
8907                                           x, y, fb);
8908                 if (ret)
8909                         goto done;
8910         }
8911
8912         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8913         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8914                 dev_priv->display.crtc_enable(&intel_crtc->base);
8915
8916         if (modeset_pipes) {
8917                 /* Store real post-adjustment hardware mode. */
8918                 crtc->hwmode = pipe_config->adjusted_mode;
8919
8920                 /* Calculate and store various constants which
8921                  * are later needed by vblank and swap-completion
8922                  * timestamping. They are derived from true hwmode.
8923                  */
8924                 drm_calc_timestamping_constants(crtc);
8925         }
8926
8927         /* FIXME: add subpixel order */
8928 done:
8929         if (ret && crtc->enabled) {
8930                 crtc->hwmode = *saved_hwmode;
8931                 crtc->mode = *saved_mode;
8932         }
8933
8934 out:
8935         kfree(pipe_config);
8936         kfree(saved_mode);
8937         return ret;
8938 }
8939
8940 static int intel_set_mode(struct drm_crtc *crtc,
8941                           struct drm_display_mode *mode,
8942                           int x, int y, struct drm_framebuffer *fb)
8943 {
8944         int ret;
8945
8946         ret = __intel_set_mode(crtc, mode, x, y, fb);
8947
8948         if (ret == 0)
8949                 intel_modeset_check_state(crtc->dev);
8950
8951         return ret;
8952 }
8953
8954 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8955 {
8956         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8957 }
8958
8959 #undef for_each_intel_crtc_masked
8960
8961 static void intel_set_config_free(struct intel_set_config *config)
8962 {
8963         if (!config)
8964                 return;
8965
8966         kfree(config->save_connector_encoders);
8967         kfree(config->save_encoder_crtcs);
8968         kfree(config);
8969 }
8970
8971 static int intel_set_config_save_state(struct drm_device *dev,
8972                                        struct intel_set_config *config)
8973 {
8974         struct drm_encoder *encoder;
8975         struct drm_connector *connector;
8976         int count;
8977
8978         config->save_encoder_crtcs =
8979                 kcalloc(dev->mode_config.num_encoder,
8980                         sizeof(struct drm_crtc *), GFP_KERNEL);
8981         if (!config->save_encoder_crtcs)
8982                 return -ENOMEM;
8983
8984         config->save_connector_encoders =
8985                 kcalloc(dev->mode_config.num_connector,
8986                         sizeof(struct drm_encoder *), GFP_KERNEL);
8987         if (!config->save_connector_encoders)
8988                 return -ENOMEM;
8989
8990         /* Copy data. Note that driver private data is not affected.
8991          * Should anything bad happen only the expected state is
8992          * restored, not the drivers personal bookkeeping.
8993          */
8994         count = 0;
8995         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8996                 config->save_encoder_crtcs[count++] = encoder->crtc;
8997         }
8998
8999         count = 0;
9000         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9001                 config->save_connector_encoders[count++] = connector->encoder;
9002         }
9003
9004         return 0;
9005 }
9006
9007 static void intel_set_config_restore_state(struct drm_device *dev,
9008                                            struct intel_set_config *config)
9009 {
9010         struct intel_encoder *encoder;
9011         struct intel_connector *connector;
9012         int count;
9013
9014         count = 0;
9015         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9016                 encoder->new_crtc =
9017                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9018         }
9019
9020         count = 0;
9021         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9022                 connector->new_encoder =
9023                         to_intel_encoder(config->save_connector_encoders[count++]);
9024         }
9025 }
9026
9027 static bool
9028 is_crtc_connector_off(struct drm_mode_set *set)
9029 {
9030         int i;
9031
9032         if (set->num_connectors == 0)
9033                 return false;
9034
9035         if (WARN_ON(set->connectors == NULL))
9036                 return false;
9037
9038         for (i = 0; i < set->num_connectors; i++)
9039                 if (set->connectors[i]->encoder &&
9040                     set->connectors[i]->encoder->crtc == set->crtc &&
9041                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9042                         return true;
9043
9044         return false;
9045 }
9046
9047 static void
9048 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9049                                       struct intel_set_config *config)
9050 {
9051
9052         /* We should be able to check here if the fb has the same properties
9053          * and then just flip_or_move it */
9054         if (is_crtc_connector_off(set)) {
9055                 config->mode_changed = true;
9056         } else if (set->crtc->fb != set->fb) {
9057                 /* If we have no fb then treat it as a full mode set */
9058                 if (set->crtc->fb == NULL) {
9059                         struct intel_crtc *intel_crtc =
9060                                 to_intel_crtc(set->crtc);
9061
9062                         if (intel_crtc->active && i915_fastboot) {
9063                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9064                                 config->fb_changed = true;
9065                         } else {
9066                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9067                                 config->mode_changed = true;
9068                         }
9069                 } else if (set->fb == NULL) {
9070                         config->mode_changed = true;
9071                 } else if (set->fb->pixel_format !=
9072                            set->crtc->fb->pixel_format) {
9073                         config->mode_changed = true;
9074                 } else {
9075                         config->fb_changed = true;
9076                 }
9077         }
9078
9079         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9080                 config->fb_changed = true;
9081
9082         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9083                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9084                 drm_mode_debug_printmodeline(&set->crtc->mode);
9085                 drm_mode_debug_printmodeline(set->mode);
9086                 config->mode_changed = true;
9087         }
9088
9089         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9090                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9091 }
9092
9093 static int
9094 intel_modeset_stage_output_state(struct drm_device *dev,
9095                                  struct drm_mode_set *set,
9096                                  struct intel_set_config *config)
9097 {
9098         struct drm_crtc *new_crtc;
9099         struct intel_connector *connector;
9100         struct intel_encoder *encoder;
9101         int ro;
9102
9103         /* The upper layers ensure that we either disable a crtc or have a list
9104          * of connectors. For paranoia, double-check this. */
9105         WARN_ON(!set->fb && (set->num_connectors != 0));
9106         WARN_ON(set->fb && (set->num_connectors == 0));
9107
9108         list_for_each_entry(connector, &dev->mode_config.connector_list,
9109                             base.head) {
9110                 /* Otherwise traverse passed in connector list and get encoders
9111                  * for them. */
9112                 for (ro = 0; ro < set->num_connectors; ro++) {
9113                         if (set->connectors[ro] == &connector->base) {
9114                                 connector->new_encoder = connector->encoder;
9115                                 break;
9116                         }
9117                 }
9118
9119                 /* If we disable the crtc, disable all its connectors. Also, if
9120                  * the connector is on the changing crtc but not on the new
9121                  * connector list, disable it. */
9122                 if ((!set->fb || ro == set->num_connectors) &&
9123                     connector->base.encoder &&
9124                     connector->base.encoder->crtc == set->crtc) {
9125                         connector->new_encoder = NULL;
9126
9127                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9128                                 connector->base.base.id,
9129                                 drm_get_connector_name(&connector->base));
9130                 }
9131
9132
9133                 if (&connector->new_encoder->base != connector->base.encoder) {
9134                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9135                         config->mode_changed = true;
9136                 }
9137         }
9138         /* connector->new_encoder is now updated for all connectors. */
9139
9140         /* Update crtc of enabled connectors. */
9141         list_for_each_entry(connector, &dev->mode_config.connector_list,
9142                             base.head) {
9143                 if (!connector->new_encoder)
9144                         continue;
9145
9146                 new_crtc = connector->new_encoder->base.crtc;
9147
9148                 for (ro = 0; ro < set->num_connectors; ro++) {
9149                         if (set->connectors[ro] == &connector->base)
9150                                 new_crtc = set->crtc;
9151                 }
9152
9153                 /* Make sure the new CRTC will work with the encoder */
9154                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9155                                            new_crtc)) {
9156                         return -EINVAL;
9157                 }
9158                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9159
9160                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9161                         connector->base.base.id,
9162                         drm_get_connector_name(&connector->base),
9163                         new_crtc->base.id);
9164         }
9165
9166         /* Check for any encoders that needs to be disabled. */
9167         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9168                             base.head) {
9169                 list_for_each_entry(connector,
9170                                     &dev->mode_config.connector_list,
9171                                     base.head) {
9172                         if (connector->new_encoder == encoder) {
9173                                 WARN_ON(!connector->new_encoder->new_crtc);
9174
9175                                 goto next_encoder;
9176                         }
9177                 }
9178                 encoder->new_crtc = NULL;
9179 next_encoder:
9180                 /* Only now check for crtc changes so we don't miss encoders
9181                  * that will be disabled. */
9182                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9183                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9184                         config->mode_changed = true;
9185                 }
9186         }
9187         /* Now we've also updated encoder->new_crtc for all encoders. */
9188
9189         return 0;
9190 }
9191
9192 static int intel_crtc_set_config(struct drm_mode_set *set)
9193 {
9194         struct drm_device *dev;
9195         struct drm_mode_set save_set;
9196         struct intel_set_config *config;
9197         int ret;
9198
9199         BUG_ON(!set);
9200         BUG_ON(!set->crtc);
9201         BUG_ON(!set->crtc->helper_private);
9202
9203         /* Enforce sane interface api - has been abused by the fb helper. */
9204         BUG_ON(!set->mode && set->fb);
9205         BUG_ON(set->fb && set->num_connectors == 0);
9206
9207         if (set->fb) {
9208                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9209                                 set->crtc->base.id, set->fb->base.id,
9210                                 (int)set->num_connectors, set->x, set->y);
9211         } else {
9212                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9213         }
9214
9215         dev = set->crtc->dev;
9216
9217         ret = -ENOMEM;
9218         config = kzalloc(sizeof(*config), GFP_KERNEL);
9219         if (!config)
9220                 goto out_config;
9221
9222         ret = intel_set_config_save_state(dev, config);
9223         if (ret)
9224                 goto out_config;
9225
9226         save_set.crtc = set->crtc;
9227         save_set.mode = &set->crtc->mode;
9228         save_set.x = set->crtc->x;
9229         save_set.y = set->crtc->y;
9230         save_set.fb = set->crtc->fb;
9231
9232         /* Compute whether we need a full modeset, only an fb base update or no
9233          * change at all. In the future we might also check whether only the
9234          * mode changed, e.g. for LVDS where we only change the panel fitter in
9235          * such cases. */
9236         intel_set_config_compute_mode_changes(set, config);
9237
9238         ret = intel_modeset_stage_output_state(dev, set, config);
9239         if (ret)
9240                 goto fail;
9241
9242         if (config->mode_changed) {
9243                 ret = intel_set_mode(set->crtc, set->mode,
9244                                      set->x, set->y, set->fb);
9245         } else if (config->fb_changed) {
9246                 intel_crtc_wait_for_pending_flips(set->crtc);
9247
9248                 ret = intel_pipe_set_base(set->crtc,
9249                                           set->x, set->y, set->fb);
9250         }
9251
9252         if (ret) {
9253                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9254                               set->crtc->base.id, ret);
9255 fail:
9256                 intel_set_config_restore_state(dev, config);
9257
9258                 /* Try to restore the config */
9259                 if (config->mode_changed &&
9260                     intel_set_mode(save_set.crtc, save_set.mode,
9261                                    save_set.x, save_set.y, save_set.fb))
9262                         DRM_ERROR("failed to restore config after modeset failure\n");
9263         }
9264
9265 out_config:
9266         intel_set_config_free(config);
9267         return ret;
9268 }
9269
9270 static const struct drm_crtc_funcs intel_crtc_funcs = {
9271         .cursor_set = intel_crtc_cursor_set,
9272         .cursor_move = intel_crtc_cursor_move,
9273         .gamma_set = intel_crtc_gamma_set,
9274         .set_config = intel_crtc_set_config,
9275         .destroy = intel_crtc_destroy,
9276         .page_flip = intel_crtc_page_flip,
9277 };
9278
9279 static void intel_cpu_pll_init(struct drm_device *dev)
9280 {
9281         if (HAS_DDI(dev))
9282                 intel_ddi_pll_init(dev);
9283 }
9284
9285 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9286                                       struct intel_shared_dpll *pll,
9287                                       struct intel_dpll_hw_state *hw_state)
9288 {
9289         uint32_t val;
9290
9291         val = I915_READ(PCH_DPLL(pll->id));
9292         hw_state->dpll = val;
9293         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9294         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9295
9296         return val & DPLL_VCO_ENABLE;
9297 }
9298
9299 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9300                                   struct intel_shared_dpll *pll)
9301 {
9302         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9303         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9304 }
9305
9306 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9307                                 struct intel_shared_dpll *pll)
9308 {
9309         /* PCH refclock must be enabled first */
9310         assert_pch_refclk_enabled(dev_priv);
9311
9312         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9313
9314         /* Wait for the clocks to stabilize. */
9315         POSTING_READ(PCH_DPLL(pll->id));
9316         udelay(150);
9317
9318         /* The pixel multiplier can only be updated once the
9319          * DPLL is enabled and the clocks are stable.
9320          *
9321          * So write it again.
9322          */
9323         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9324         POSTING_READ(PCH_DPLL(pll->id));
9325         udelay(200);
9326 }
9327
9328 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9329                                  struct intel_shared_dpll *pll)
9330 {
9331         struct drm_device *dev = dev_priv->dev;
9332         struct intel_crtc *crtc;
9333
9334         /* Make sure no transcoder isn't still depending on us. */
9335         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9336                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9337                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9338         }
9339
9340         I915_WRITE(PCH_DPLL(pll->id), 0);
9341         POSTING_READ(PCH_DPLL(pll->id));
9342         udelay(200);
9343 }
9344
9345 static char *ibx_pch_dpll_names[] = {
9346         "PCH DPLL A",
9347         "PCH DPLL B",
9348 };
9349
9350 static void ibx_pch_dpll_init(struct drm_device *dev)
9351 {
9352         struct drm_i915_private *dev_priv = dev->dev_private;
9353         int i;
9354
9355         dev_priv->num_shared_dpll = 2;
9356
9357         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9358                 dev_priv->shared_dplls[i].id = i;
9359                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9360                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9361                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9362                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9363                 dev_priv->shared_dplls[i].get_hw_state =
9364                         ibx_pch_dpll_get_hw_state;
9365         }
9366 }
9367
9368 static void intel_shared_dpll_init(struct drm_device *dev)
9369 {
9370         struct drm_i915_private *dev_priv = dev->dev_private;
9371
9372         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9373                 ibx_pch_dpll_init(dev);
9374         else
9375                 dev_priv->num_shared_dpll = 0;
9376
9377         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9378         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9379                       dev_priv->num_shared_dpll);
9380 }
9381
9382 static void intel_crtc_init(struct drm_device *dev, int pipe)
9383 {
9384         drm_i915_private_t *dev_priv = dev->dev_private;
9385         struct intel_crtc *intel_crtc;
9386         int i;
9387
9388         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9389         if (intel_crtc == NULL)
9390                 return;
9391
9392         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9393
9394         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9395         for (i = 0; i < 256; i++) {
9396                 intel_crtc->lut_r[i] = i;
9397                 intel_crtc->lut_g[i] = i;
9398                 intel_crtc->lut_b[i] = i;
9399         }
9400
9401         /* Swap pipes & planes for FBC on pre-965 */
9402         intel_crtc->pipe = pipe;
9403         intel_crtc->plane = pipe;
9404         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9405                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9406                 intel_crtc->plane = !pipe;
9407         }
9408
9409         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9410                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9411         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9412         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9413
9414         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9415 }
9416
9417 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9418                                 struct drm_file *file)
9419 {
9420         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9421         struct drm_mode_object *drmmode_obj;
9422         struct intel_crtc *crtc;
9423
9424         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9425                 return -ENODEV;
9426
9427         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9428                         DRM_MODE_OBJECT_CRTC);
9429
9430         if (!drmmode_obj) {
9431                 DRM_ERROR("no such CRTC id\n");
9432                 return -EINVAL;
9433         }
9434
9435         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9436         pipe_from_crtc_id->pipe = crtc->pipe;
9437
9438         return 0;
9439 }
9440
9441 static int intel_encoder_clones(struct intel_encoder *encoder)
9442 {
9443         struct drm_device *dev = encoder->base.dev;
9444         struct intel_encoder *source_encoder;
9445         int index_mask = 0;
9446         int entry = 0;
9447
9448         list_for_each_entry(source_encoder,
9449                             &dev->mode_config.encoder_list, base.head) {
9450
9451                 if (encoder == source_encoder)
9452                         index_mask |= (1 << entry);
9453
9454                 /* Intel hw has only one MUX where enocoders could be cloned. */
9455                 if (encoder->cloneable && source_encoder->cloneable)
9456                         index_mask |= (1 << entry);
9457
9458                 entry++;
9459         }
9460
9461         return index_mask;
9462 }
9463
9464 static bool has_edp_a(struct drm_device *dev)
9465 {
9466         struct drm_i915_private *dev_priv = dev->dev_private;
9467
9468         if (!IS_MOBILE(dev))
9469                 return false;
9470
9471         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9472                 return false;
9473
9474         if (IS_GEN5(dev) &&
9475             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9476                 return false;
9477
9478         return true;
9479 }
9480
9481 static void intel_setup_outputs(struct drm_device *dev)
9482 {
9483         struct drm_i915_private *dev_priv = dev->dev_private;
9484         struct intel_encoder *encoder;
9485         bool dpd_is_edp = false;
9486
9487         intel_lvds_init(dev);
9488
9489         if (!IS_ULT(dev))
9490                 intel_crt_init(dev);
9491
9492         if (HAS_DDI(dev)) {
9493                 int found;
9494
9495                 /* Haswell uses DDI functions to detect digital outputs */
9496                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9497                 /* DDI A only supports eDP */
9498                 if (found)
9499                         intel_ddi_init(dev, PORT_A);
9500
9501                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9502                  * register */
9503                 found = I915_READ(SFUSE_STRAP);
9504
9505                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9506                         intel_ddi_init(dev, PORT_B);
9507                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9508                         intel_ddi_init(dev, PORT_C);
9509                 if (found & SFUSE_STRAP_DDID_DETECTED)
9510                         intel_ddi_init(dev, PORT_D);
9511         } else if (HAS_PCH_SPLIT(dev)) {
9512                 int found;
9513                 dpd_is_edp = intel_dpd_is_edp(dev);
9514
9515                 if (has_edp_a(dev))
9516                         intel_dp_init(dev, DP_A, PORT_A);
9517
9518                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9519                         /* PCH SDVOB multiplex with HDMIB */
9520                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9521                         if (!found)
9522                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9523                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9524                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9525                 }
9526
9527                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9528                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9529
9530                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9531                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9532
9533                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9534                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9535
9536                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9537                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9538         } else if (IS_VALLEYVIEW(dev)) {
9539                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9540                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9541                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9542                                         PORT_C);
9543                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9544                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9545                                               PORT_C);
9546                 }
9547
9548                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9549                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9550                                         PORT_B);
9551                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9552                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9553                 }
9554         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9555                 bool found = false;
9556
9557                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9558                         DRM_DEBUG_KMS("probing SDVOB\n");
9559                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9560                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9561                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9562                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9563                         }
9564
9565                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9566                                 intel_dp_init(dev, DP_B, PORT_B);
9567                 }
9568
9569                 /* Before G4X SDVOC doesn't have its own detect register */
9570
9571                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9572                         DRM_DEBUG_KMS("probing SDVOC\n");
9573                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9574                 }
9575
9576                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9577
9578                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9579                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9580                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9581                         }
9582                         if (SUPPORTS_INTEGRATED_DP(dev))
9583                                 intel_dp_init(dev, DP_C, PORT_C);
9584                 }
9585
9586                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9587                     (I915_READ(DP_D) & DP_DETECTED))
9588                         intel_dp_init(dev, DP_D, PORT_D);
9589         } else if (IS_GEN2(dev))
9590                 intel_dvo_init(dev);
9591
9592         if (SUPPORTS_TV(dev))
9593                 intel_tv_init(dev);
9594
9595         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9596                 encoder->base.possible_crtcs = encoder->crtc_mask;
9597                 encoder->base.possible_clones =
9598                         intel_encoder_clones(encoder);
9599         }
9600
9601         intel_init_pch_refclk(dev);
9602
9603         drm_helper_move_panel_connectors_to_head(dev);
9604 }
9605
9606 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9607 {
9608         drm_framebuffer_cleanup(&fb->base);
9609         drm_gem_object_unreference_unlocked(&fb->obj->base);
9610 }
9611
9612 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9613 {
9614         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9615
9616         intel_framebuffer_fini(intel_fb);
9617         kfree(intel_fb);
9618 }
9619
9620 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9621                                                 struct drm_file *file,
9622                                                 unsigned int *handle)
9623 {
9624         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9625         struct drm_i915_gem_object *obj = intel_fb->obj;
9626
9627         return drm_gem_handle_create(file, &obj->base, handle);
9628 }
9629
9630 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9631         .destroy = intel_user_framebuffer_destroy,
9632         .create_handle = intel_user_framebuffer_create_handle,
9633 };
9634
9635 int intel_framebuffer_init(struct drm_device *dev,
9636                            struct intel_framebuffer *intel_fb,
9637                            struct drm_mode_fb_cmd2 *mode_cmd,
9638                            struct drm_i915_gem_object *obj)
9639 {
9640         int pitch_limit;
9641         int ret;
9642
9643         if (obj->tiling_mode == I915_TILING_Y) {
9644                 DRM_DEBUG("hardware does not support tiling Y\n");
9645                 return -EINVAL;
9646         }
9647
9648         if (mode_cmd->pitches[0] & 63) {
9649                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9650                           mode_cmd->pitches[0]);
9651                 return -EINVAL;
9652         }
9653
9654         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9655                 pitch_limit = 32*1024;
9656         } else if (INTEL_INFO(dev)->gen >= 4) {
9657                 if (obj->tiling_mode)
9658                         pitch_limit = 16*1024;
9659                 else
9660                         pitch_limit = 32*1024;
9661         } else if (INTEL_INFO(dev)->gen >= 3) {
9662                 if (obj->tiling_mode)
9663                         pitch_limit = 8*1024;
9664                 else
9665                         pitch_limit = 16*1024;
9666         } else
9667                 /* XXX DSPC is limited to 4k tiled */
9668                 pitch_limit = 8*1024;
9669
9670         if (mode_cmd->pitches[0] > pitch_limit) {
9671                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9672                           obj->tiling_mode ? "tiled" : "linear",
9673                           mode_cmd->pitches[0], pitch_limit);
9674                 return -EINVAL;
9675         }
9676
9677         if (obj->tiling_mode != I915_TILING_NONE &&
9678             mode_cmd->pitches[0] != obj->stride) {
9679                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9680                           mode_cmd->pitches[0], obj->stride);
9681                 return -EINVAL;
9682         }
9683
9684         /* Reject formats not supported by any plane early. */
9685         switch (mode_cmd->pixel_format) {
9686         case DRM_FORMAT_C8:
9687         case DRM_FORMAT_RGB565:
9688         case DRM_FORMAT_XRGB8888:
9689         case DRM_FORMAT_ARGB8888:
9690                 break;
9691         case DRM_FORMAT_XRGB1555:
9692         case DRM_FORMAT_ARGB1555:
9693                 if (INTEL_INFO(dev)->gen > 3) {
9694                         DRM_DEBUG("unsupported pixel format: %s\n",
9695                                   drm_get_format_name(mode_cmd->pixel_format));
9696                         return -EINVAL;
9697                 }
9698                 break;
9699         case DRM_FORMAT_XBGR8888:
9700         case DRM_FORMAT_ABGR8888:
9701         case DRM_FORMAT_XRGB2101010:
9702         case DRM_FORMAT_ARGB2101010:
9703         case DRM_FORMAT_XBGR2101010:
9704         case DRM_FORMAT_ABGR2101010:
9705                 if (INTEL_INFO(dev)->gen < 4) {
9706                         DRM_DEBUG("unsupported pixel format: %s\n",
9707                                   drm_get_format_name(mode_cmd->pixel_format));
9708                         return -EINVAL;
9709                 }
9710                 break;
9711         case DRM_FORMAT_YUYV:
9712         case DRM_FORMAT_UYVY:
9713         case DRM_FORMAT_YVYU:
9714         case DRM_FORMAT_VYUY:
9715                 if (INTEL_INFO(dev)->gen < 5) {
9716                         DRM_DEBUG("unsupported pixel format: %s\n",
9717                                   drm_get_format_name(mode_cmd->pixel_format));
9718                         return -EINVAL;
9719                 }
9720                 break;
9721         default:
9722                 DRM_DEBUG("unsupported pixel format: %s\n",
9723                           drm_get_format_name(mode_cmd->pixel_format));
9724                 return -EINVAL;
9725         }
9726
9727         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9728         if (mode_cmd->offsets[0] != 0)
9729                 return -EINVAL;
9730
9731         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9732         intel_fb->obj = obj;
9733
9734         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9735         if (ret) {
9736                 DRM_ERROR("framebuffer init failed %d\n", ret);
9737                 return ret;
9738         }
9739
9740         return 0;
9741 }
9742
9743 static struct drm_framebuffer *
9744 intel_user_framebuffer_create(struct drm_device *dev,
9745                               struct drm_file *filp,
9746                               struct drm_mode_fb_cmd2 *mode_cmd)
9747 {
9748         struct drm_i915_gem_object *obj;
9749
9750         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9751                                                 mode_cmd->handles[0]));
9752         if (&obj->base == NULL)
9753                 return ERR_PTR(-ENOENT);
9754
9755         return intel_framebuffer_create(dev, mode_cmd, obj);
9756 }
9757
9758 static const struct drm_mode_config_funcs intel_mode_funcs = {
9759         .fb_create = intel_user_framebuffer_create,
9760         .output_poll_changed = intel_fb_output_poll_changed,
9761 };
9762
9763 /* Set up chip specific display functions */
9764 static void intel_init_display(struct drm_device *dev)
9765 {
9766         struct drm_i915_private *dev_priv = dev->dev_private;
9767
9768         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9769                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9770         else if (IS_VALLEYVIEW(dev))
9771                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9772         else if (IS_PINEVIEW(dev))
9773                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9774         else
9775                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9776
9777         if (HAS_DDI(dev)) {
9778                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9779                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9780                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9781                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9782                 dev_priv->display.off = haswell_crtc_off;
9783                 dev_priv->display.update_plane = ironlake_update_plane;
9784         } else if (HAS_PCH_SPLIT(dev)) {
9785                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9786                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9787                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9788                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9789                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9790                 dev_priv->display.off = ironlake_crtc_off;
9791                 dev_priv->display.update_plane = ironlake_update_plane;
9792         } else if (IS_VALLEYVIEW(dev)) {
9793                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9794                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9795                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9796                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9797                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9798                 dev_priv->display.off = i9xx_crtc_off;
9799                 dev_priv->display.update_plane = i9xx_update_plane;
9800         } else {
9801                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9802                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9803                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9804                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9805                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9806                 dev_priv->display.off = i9xx_crtc_off;
9807                 dev_priv->display.update_plane = i9xx_update_plane;
9808         }
9809
9810         /* Returns the core display clock speed */
9811         if (IS_VALLEYVIEW(dev))
9812                 dev_priv->display.get_display_clock_speed =
9813                         valleyview_get_display_clock_speed;
9814         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9815                 dev_priv->display.get_display_clock_speed =
9816                         i945_get_display_clock_speed;
9817         else if (IS_I915G(dev))
9818                 dev_priv->display.get_display_clock_speed =
9819                         i915_get_display_clock_speed;
9820         else if (IS_I945GM(dev) || IS_845G(dev))
9821                 dev_priv->display.get_display_clock_speed =
9822                         i9xx_misc_get_display_clock_speed;
9823         else if (IS_PINEVIEW(dev))
9824                 dev_priv->display.get_display_clock_speed =
9825                         pnv_get_display_clock_speed;
9826         else if (IS_I915GM(dev))
9827                 dev_priv->display.get_display_clock_speed =
9828                         i915gm_get_display_clock_speed;
9829         else if (IS_I865G(dev))
9830                 dev_priv->display.get_display_clock_speed =
9831                         i865_get_display_clock_speed;
9832         else if (IS_I85X(dev))
9833                 dev_priv->display.get_display_clock_speed =
9834                         i855_get_display_clock_speed;
9835         else /* 852, 830 */
9836                 dev_priv->display.get_display_clock_speed =
9837                         i830_get_display_clock_speed;
9838
9839         if (HAS_PCH_SPLIT(dev)) {
9840                 if (IS_GEN5(dev)) {
9841                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9842                         dev_priv->display.write_eld = ironlake_write_eld;
9843                 } else if (IS_GEN6(dev)) {
9844                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9845                         dev_priv->display.write_eld = ironlake_write_eld;
9846                 } else if (IS_IVYBRIDGE(dev)) {
9847                         /* FIXME: detect B0+ stepping and use auto training */
9848                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9849                         dev_priv->display.write_eld = ironlake_write_eld;
9850                         dev_priv->display.modeset_global_resources =
9851                                 ivb_modeset_global_resources;
9852                 } else if (IS_HASWELL(dev)) {
9853                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9854                         dev_priv->display.write_eld = haswell_write_eld;
9855                         dev_priv->display.modeset_global_resources =
9856                                 haswell_modeset_global_resources;
9857                 }
9858         } else if (IS_G4X(dev)) {
9859                 dev_priv->display.write_eld = g4x_write_eld;
9860         }
9861
9862         /* Default just returns -ENODEV to indicate unsupported */
9863         dev_priv->display.queue_flip = intel_default_queue_flip;
9864
9865         switch (INTEL_INFO(dev)->gen) {
9866         case 2:
9867                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9868                 break;
9869
9870         case 3:
9871                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9872                 break;
9873
9874         case 4:
9875         case 5:
9876                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9877                 break;
9878
9879         case 6:
9880                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9881                 break;
9882         case 7:
9883                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9884                 break;
9885         }
9886 }
9887
9888 /*
9889  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9890  * resume, or other times.  This quirk makes sure that's the case for
9891  * affected systems.
9892  */
9893 static void quirk_pipea_force(struct drm_device *dev)
9894 {
9895         struct drm_i915_private *dev_priv = dev->dev_private;
9896
9897         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9898         DRM_INFO("applying pipe a force quirk\n");
9899 }
9900
9901 /*
9902  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9903  */
9904 static void quirk_ssc_force_disable(struct drm_device *dev)
9905 {
9906         struct drm_i915_private *dev_priv = dev->dev_private;
9907         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9908         DRM_INFO("applying lvds SSC disable quirk\n");
9909 }
9910
9911 /*
9912  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9913  * brightness value
9914  */
9915 static void quirk_invert_brightness(struct drm_device *dev)
9916 {
9917         struct drm_i915_private *dev_priv = dev->dev_private;
9918         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9919         DRM_INFO("applying inverted panel brightness quirk\n");
9920 }
9921
9922 /*
9923  * Some machines (Dell XPS13) suffer broken backlight controls if
9924  * BLM_PCH_PWM_ENABLE is set.
9925  */
9926 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9927 {
9928         struct drm_i915_private *dev_priv = dev->dev_private;
9929         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9930         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9931 }
9932
9933 struct intel_quirk {
9934         int device;
9935         int subsystem_vendor;
9936         int subsystem_device;
9937         void (*hook)(struct drm_device *dev);
9938 };
9939
9940 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9941 struct intel_dmi_quirk {
9942         void (*hook)(struct drm_device *dev);
9943         const struct dmi_system_id (*dmi_id_list)[];
9944 };
9945
9946 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9947 {
9948         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9949         return 1;
9950 }
9951
9952 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9953         {
9954                 .dmi_id_list = &(const struct dmi_system_id[]) {
9955                         {
9956                                 .callback = intel_dmi_reverse_brightness,
9957                                 .ident = "NCR Corporation",
9958                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9959                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9960                                 },
9961                         },
9962                         { }  /* terminating entry */
9963                 },
9964                 .hook = quirk_invert_brightness,
9965         },
9966 };
9967
9968 static struct intel_quirk intel_quirks[] = {
9969         /* HP Mini needs pipe A force quirk (LP: #322104) */
9970         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9971
9972         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9973         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9974
9975         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9976         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9977
9978         /* 830/845 need to leave pipe A & dpll A up */
9979         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9980         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9981
9982         /* Lenovo U160 cannot use SSC on LVDS */
9983         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9984
9985         /* Sony Vaio Y cannot use SSC on LVDS */
9986         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9987
9988         /* Acer Aspire 5734Z must invert backlight brightness */
9989         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9990
9991         /* Acer/eMachines G725 */
9992         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9993
9994         /* Acer/eMachines e725 */
9995         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9996
9997         /* Acer/Packard Bell NCL20 */
9998         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9999
10000         /* Acer Aspire 4736Z */
10001         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10002
10003         /* Dell XPS13 HD Sandy Bridge */
10004         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10005         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10006         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10007 };
10008
10009 static void intel_init_quirks(struct drm_device *dev)
10010 {
10011         struct pci_dev *d = dev->pdev;
10012         int i;
10013
10014         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10015                 struct intel_quirk *q = &intel_quirks[i];
10016
10017                 if (d->device == q->device &&
10018                     (d->subsystem_vendor == q->subsystem_vendor ||
10019                      q->subsystem_vendor == PCI_ANY_ID) &&
10020                     (d->subsystem_device == q->subsystem_device ||
10021                      q->subsystem_device == PCI_ANY_ID))
10022                         q->hook(dev);
10023         }
10024         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10025                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10026                         intel_dmi_quirks[i].hook(dev);
10027         }
10028 }
10029
10030 /* Disable the VGA plane that we never use */
10031 static void i915_disable_vga(struct drm_device *dev)
10032 {
10033         struct drm_i915_private *dev_priv = dev->dev_private;
10034         u8 sr1;
10035         u32 vga_reg = i915_vgacntrl_reg(dev);
10036
10037         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10038         outb(SR01, VGA_SR_INDEX);
10039         sr1 = inb(VGA_SR_DATA);
10040         outb(sr1 | 1<<5, VGA_SR_DATA);
10041         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10042         udelay(300);
10043
10044         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10045         POSTING_READ(vga_reg);
10046 }
10047
10048 void intel_modeset_init_hw(struct drm_device *dev)
10049 {
10050         intel_init_power_well(dev);
10051
10052         intel_prepare_ddi(dev);
10053
10054         intel_init_clock_gating(dev);
10055
10056         mutex_lock(&dev->struct_mutex);
10057         intel_enable_gt_powersave(dev);
10058         mutex_unlock(&dev->struct_mutex);
10059 }
10060
10061 void intel_modeset_suspend_hw(struct drm_device *dev)
10062 {
10063         intel_suspend_hw(dev);
10064 }
10065
10066 void intel_modeset_init(struct drm_device *dev)
10067 {
10068         struct drm_i915_private *dev_priv = dev->dev_private;
10069         int i, j, ret;
10070
10071         drm_mode_config_init(dev);
10072
10073         dev->mode_config.min_width = 0;
10074         dev->mode_config.min_height = 0;
10075
10076         dev->mode_config.preferred_depth = 24;
10077         dev->mode_config.prefer_shadow = 1;
10078
10079         dev->mode_config.funcs = &intel_mode_funcs;
10080
10081         intel_init_quirks(dev);
10082
10083         intel_init_pm(dev);
10084
10085         if (INTEL_INFO(dev)->num_pipes == 0)
10086                 return;
10087
10088         intel_init_display(dev);
10089
10090         if (IS_GEN2(dev)) {
10091                 dev->mode_config.max_width = 2048;
10092                 dev->mode_config.max_height = 2048;
10093         } else if (IS_GEN3(dev)) {
10094                 dev->mode_config.max_width = 4096;
10095                 dev->mode_config.max_height = 4096;
10096         } else {
10097                 dev->mode_config.max_width = 8192;
10098                 dev->mode_config.max_height = 8192;
10099         }
10100         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10101
10102         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10103                       INTEL_INFO(dev)->num_pipes,
10104                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10105
10106         for_each_pipe(i) {
10107                 intel_crtc_init(dev, i);
10108                 for (j = 0; j < dev_priv->num_plane; j++) {
10109                         ret = intel_plane_init(dev, i, j);
10110                         if (ret)
10111                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10112                                               pipe_name(i), sprite_name(i, j), ret);
10113                 }
10114         }
10115
10116         intel_cpu_pll_init(dev);
10117         intel_shared_dpll_init(dev);
10118
10119         /* Just disable it once at startup */
10120         i915_disable_vga(dev);
10121         intel_setup_outputs(dev);
10122
10123         /* Just in case the BIOS is doing something questionable. */
10124         intel_disable_fbc(dev);
10125 }
10126
10127 static void
10128 intel_connector_break_all_links(struct intel_connector *connector)
10129 {
10130         connector->base.dpms = DRM_MODE_DPMS_OFF;
10131         connector->base.encoder = NULL;
10132         connector->encoder->connectors_active = false;
10133         connector->encoder->base.crtc = NULL;
10134 }
10135
10136 static void intel_enable_pipe_a(struct drm_device *dev)
10137 {
10138         struct intel_connector *connector;
10139         struct drm_connector *crt = NULL;
10140         struct intel_load_detect_pipe load_detect_temp;
10141
10142         /* We can't just switch on the pipe A, we need to set things up with a
10143          * proper mode and output configuration. As a gross hack, enable pipe A
10144          * by enabling the load detect pipe once. */
10145         list_for_each_entry(connector,
10146                             &dev->mode_config.connector_list,
10147                             base.head) {
10148                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10149                         crt = &connector->base;
10150                         break;
10151                 }
10152         }
10153
10154         if (!crt)
10155                 return;
10156
10157         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10158                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10159
10160
10161 }
10162
10163 static bool
10164 intel_check_plane_mapping(struct intel_crtc *crtc)
10165 {
10166         struct drm_device *dev = crtc->base.dev;
10167         struct drm_i915_private *dev_priv = dev->dev_private;
10168         u32 reg, val;
10169
10170         if (INTEL_INFO(dev)->num_pipes == 1)
10171                 return true;
10172
10173         reg = DSPCNTR(!crtc->plane);
10174         val = I915_READ(reg);
10175
10176         if ((val & DISPLAY_PLANE_ENABLE) &&
10177             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10178                 return false;
10179
10180         return true;
10181 }
10182
10183 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10184 {
10185         struct drm_device *dev = crtc->base.dev;
10186         struct drm_i915_private *dev_priv = dev->dev_private;
10187         u32 reg;
10188
10189         /* Clear any frame start delays used for debugging left by the BIOS */
10190         reg = PIPECONF(crtc->config.cpu_transcoder);
10191         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10192
10193         /* We need to sanitize the plane -> pipe mapping first because this will
10194          * disable the crtc (and hence change the state) if it is wrong. Note
10195          * that gen4+ has a fixed plane -> pipe mapping.  */
10196         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10197                 struct intel_connector *connector;
10198                 bool plane;
10199
10200                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10201                               crtc->base.base.id);
10202
10203                 /* Pipe has the wrong plane attached and the plane is active.
10204                  * Temporarily change the plane mapping and disable everything
10205                  * ...  */
10206                 plane = crtc->plane;
10207                 crtc->plane = !plane;
10208                 dev_priv->display.crtc_disable(&crtc->base);
10209                 crtc->plane = plane;
10210
10211                 /* ... and break all links. */
10212                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10213                                     base.head) {
10214                         if (connector->encoder->base.crtc != &crtc->base)
10215                                 continue;
10216
10217                         intel_connector_break_all_links(connector);
10218                 }
10219
10220                 WARN_ON(crtc->active);
10221                 crtc->base.enabled = false;
10222         }
10223
10224         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10225             crtc->pipe == PIPE_A && !crtc->active) {
10226                 /* BIOS forgot to enable pipe A, this mostly happens after
10227                  * resume. Force-enable the pipe to fix this, the update_dpms
10228                  * call below we restore the pipe to the right state, but leave
10229                  * the required bits on. */
10230                 intel_enable_pipe_a(dev);
10231         }
10232
10233         /* Adjust the state of the output pipe according to whether we
10234          * have active connectors/encoders. */
10235         intel_crtc_update_dpms(&crtc->base);
10236
10237         if (crtc->active != crtc->base.enabled) {
10238                 struct intel_encoder *encoder;
10239
10240                 /* This can happen either due to bugs in the get_hw_state
10241                  * functions or because the pipe is force-enabled due to the
10242                  * pipe A quirk. */
10243                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10244                               crtc->base.base.id,
10245                               crtc->base.enabled ? "enabled" : "disabled",
10246                               crtc->active ? "enabled" : "disabled");
10247
10248                 crtc->base.enabled = crtc->active;
10249
10250                 /* Because we only establish the connector -> encoder ->
10251                  * crtc links if something is active, this means the
10252                  * crtc is now deactivated. Break the links. connector
10253                  * -> encoder links are only establish when things are
10254                  *  actually up, hence no need to break them. */
10255                 WARN_ON(crtc->active);
10256
10257                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10258                         WARN_ON(encoder->connectors_active);
10259                         encoder->base.crtc = NULL;
10260                 }
10261         }
10262 }
10263
10264 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10265 {
10266         struct intel_connector *connector;
10267         struct drm_device *dev = encoder->base.dev;
10268
10269         /* We need to check both for a crtc link (meaning that the
10270          * encoder is active and trying to read from a pipe) and the
10271          * pipe itself being active. */
10272         bool has_active_crtc = encoder->base.crtc &&
10273                 to_intel_crtc(encoder->base.crtc)->active;
10274
10275         if (encoder->connectors_active && !has_active_crtc) {
10276                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10277                               encoder->base.base.id,
10278                               drm_get_encoder_name(&encoder->base));
10279
10280                 /* Connector is active, but has no active pipe. This is
10281                  * fallout from our resume register restoring. Disable
10282                  * the encoder manually again. */
10283                 if (encoder->base.crtc) {
10284                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10285                                       encoder->base.base.id,
10286                                       drm_get_encoder_name(&encoder->base));
10287                         encoder->disable(encoder);
10288                 }
10289
10290                 /* Inconsistent output/port/pipe state happens presumably due to
10291                  * a bug in one of the get_hw_state functions. Or someplace else
10292                  * in our code, like the register restore mess on resume. Clamp
10293                  * things to off as a safer default. */
10294                 list_for_each_entry(connector,
10295                                     &dev->mode_config.connector_list,
10296                                     base.head) {
10297                         if (connector->encoder != encoder)
10298                                 continue;
10299
10300                         intel_connector_break_all_links(connector);
10301                 }
10302         }
10303         /* Enabled encoders without active connectors will be fixed in
10304          * the crtc fixup. */
10305 }
10306
10307 void i915_redisable_vga(struct drm_device *dev)
10308 {
10309         struct drm_i915_private *dev_priv = dev->dev_private;
10310         u32 vga_reg = i915_vgacntrl_reg(dev);
10311
10312         /* This function can be called both from intel_modeset_setup_hw_state or
10313          * at a very early point in our resume sequence, where the power well
10314          * structures are not yet restored. Since this function is at a very
10315          * paranoid "someone might have enabled VGA while we were not looking"
10316          * level, just check if the power well is enabled instead of trying to
10317          * follow the "don't touch the power well if we don't need it" policy
10318          * the rest of the driver uses. */
10319         if (HAS_POWER_WELL(dev) &&
10320             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10321                 return;
10322
10323         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10324                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10325                 i915_disable_vga(dev);
10326         }
10327 }
10328
10329 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10330 {
10331         struct drm_i915_private *dev_priv = dev->dev_private;
10332         enum pipe pipe;
10333         struct intel_crtc *crtc;
10334         struct intel_encoder *encoder;
10335         struct intel_connector *connector;
10336         int i;
10337
10338         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10339                             base.head) {
10340                 memset(&crtc->config, 0, sizeof(crtc->config));
10341
10342                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10343                                                                  &crtc->config);
10344
10345                 crtc->base.enabled = crtc->active;
10346
10347                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10348                               crtc->base.base.id,
10349                               crtc->active ? "enabled" : "disabled");
10350         }
10351
10352         /* FIXME: Smash this into the new shared dpll infrastructure. */
10353         if (HAS_DDI(dev))
10354                 intel_ddi_setup_hw_pll_state(dev);
10355
10356         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10357                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10358
10359                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10360                 pll->active = 0;
10361                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10362                                     base.head) {
10363                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10364                                 pll->active++;
10365                 }
10366                 pll->refcount = pll->active;
10367
10368                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10369                               pll->name, pll->refcount, pll->on);
10370         }
10371
10372         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10373                             base.head) {
10374                 pipe = 0;
10375
10376                 if (encoder->get_hw_state(encoder, &pipe)) {
10377                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10378                         encoder->base.crtc = &crtc->base;
10379                         if (encoder->get_config)
10380                                 encoder->get_config(encoder, &crtc->config);
10381                 } else {
10382                         encoder->base.crtc = NULL;
10383                 }
10384
10385                 encoder->connectors_active = false;
10386                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10387                               encoder->base.base.id,
10388                               drm_get_encoder_name(&encoder->base),
10389                               encoder->base.crtc ? "enabled" : "disabled",
10390                               pipe);
10391         }
10392
10393         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10394                             base.head) {
10395                 if (!crtc->active)
10396                         continue;
10397                 if (dev_priv->display.get_clock)
10398                         dev_priv->display.get_clock(crtc,
10399                                                     &crtc->config);
10400         }
10401
10402         list_for_each_entry(connector, &dev->mode_config.connector_list,
10403                             base.head) {
10404                 if (connector->get_hw_state(connector)) {
10405                         connector->base.dpms = DRM_MODE_DPMS_ON;
10406                         connector->encoder->connectors_active = true;
10407                         connector->base.encoder = &connector->encoder->base;
10408                 } else {
10409                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10410                         connector->base.encoder = NULL;
10411                 }
10412                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10413                               connector->base.base.id,
10414                               drm_get_connector_name(&connector->base),
10415                               connector->base.encoder ? "enabled" : "disabled");
10416         }
10417 }
10418
10419 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10420  * and i915 state tracking structures. */
10421 void intel_modeset_setup_hw_state(struct drm_device *dev,
10422                                   bool force_restore)
10423 {
10424         struct drm_i915_private *dev_priv = dev->dev_private;
10425         enum pipe pipe;
10426         struct drm_plane *plane;
10427         struct intel_crtc *crtc;
10428         struct intel_encoder *encoder;
10429         int i;
10430
10431         intel_modeset_readout_hw_state(dev);
10432
10433         /*
10434          * Now that we have the config, copy it to each CRTC struct
10435          * Note that this could go away if we move to using crtc_config
10436          * checking everywhere.
10437          */
10438         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10439                             base.head) {
10440                 if (crtc->active && i915_fastboot) {
10441                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10442
10443                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10444                                       crtc->base.base.id);
10445                         drm_mode_debug_printmodeline(&crtc->base.mode);
10446                 }
10447         }
10448
10449         /* HW state is read out, now we need to sanitize this mess. */
10450         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10451                             base.head) {
10452                 intel_sanitize_encoder(encoder);
10453         }
10454
10455         for_each_pipe(pipe) {
10456                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10457                 intel_sanitize_crtc(crtc);
10458                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10459         }
10460
10461         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10462                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10463
10464                 if (!pll->on || pll->active)
10465                         continue;
10466
10467                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10468
10469                 pll->disable(dev_priv, pll);
10470                 pll->on = false;
10471         }
10472
10473         if (force_restore) {
10474                 /*
10475                  * We need to use raw interfaces for restoring state to avoid
10476                  * checking (bogus) intermediate states.
10477                  */
10478                 for_each_pipe(pipe) {
10479                         struct drm_crtc *crtc =
10480                                 dev_priv->pipe_to_crtc_mapping[pipe];
10481
10482                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10483                                          crtc->fb);
10484                 }
10485                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10486                         intel_plane_restore(plane);
10487
10488                 i915_redisable_vga(dev);
10489         } else {
10490                 intel_modeset_update_staged_output_state(dev);
10491         }
10492
10493         intel_modeset_check_state(dev);
10494
10495         drm_mode_config_reset(dev);
10496 }
10497
10498 void intel_modeset_gem_init(struct drm_device *dev)
10499 {
10500         intel_modeset_init_hw(dev);
10501
10502         intel_setup_overlay(dev);
10503
10504         intel_modeset_setup_hw_state(dev, false);
10505 }
10506
10507 void intel_modeset_cleanup(struct drm_device *dev)
10508 {
10509         struct drm_i915_private *dev_priv = dev->dev_private;
10510         struct drm_crtc *crtc;
10511
10512         /*
10513          * Interrupts and polling as the first thing to avoid creating havoc.
10514          * Too much stuff here (turning of rps, connectors, ...) would
10515          * experience fancy races otherwise.
10516          */
10517         drm_irq_uninstall(dev);
10518         cancel_work_sync(&dev_priv->hotplug_work);
10519         /*
10520          * Due to the hpd irq storm handling the hotplug work can re-arm the
10521          * poll handlers. Hence disable polling after hpd handling is shut down.
10522          */
10523         drm_kms_helper_poll_fini(dev);
10524
10525         mutex_lock(&dev->struct_mutex);
10526
10527         intel_unregister_dsm_handler();
10528
10529         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10530                 /* Skip inactive CRTCs */
10531                 if (!crtc->fb)
10532                         continue;
10533
10534                 intel_increase_pllclock(crtc);
10535         }
10536
10537         intel_disable_fbc(dev);
10538
10539         intel_disable_gt_powersave(dev);
10540
10541         ironlake_teardown_rc6(dev);
10542
10543         mutex_unlock(&dev->struct_mutex);
10544
10545         /* flush any delayed tasks or pending work */
10546         flush_scheduled_work();
10547
10548         /* destroy backlight, if any, before the connectors */
10549         intel_panel_destroy_backlight(dev);
10550
10551         drm_mode_config_cleanup(dev);
10552
10553         intel_cleanup_overlay(dev);
10554 }
10555
10556 /*
10557  * Return which encoder is currently attached for connector.
10558  */
10559 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10560 {
10561         return &intel_attached_encoder(connector)->base;
10562 }
10563
10564 void intel_connector_attach_encoder(struct intel_connector *connector,
10565                                     struct intel_encoder *encoder)
10566 {
10567         connector->encoder = encoder;
10568         drm_mode_connector_attach_encoder(&connector->base,
10569                                           &encoder->base);
10570 }
10571
10572 /*
10573  * set vga decode state - true == enable VGA decode
10574  */
10575 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10576 {
10577         struct drm_i915_private *dev_priv = dev->dev_private;
10578         u16 gmch_ctrl;
10579
10580         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10581         if (state)
10582                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10583         else
10584                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10585         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10586         return 0;
10587 }
10588
10589 struct intel_display_error_state {
10590
10591         u32 power_well_driver;
10592
10593         int num_transcoders;
10594
10595         struct intel_cursor_error_state {
10596                 u32 control;
10597                 u32 position;
10598                 u32 base;
10599                 u32 size;
10600         } cursor[I915_MAX_PIPES];
10601
10602         struct intel_pipe_error_state {
10603                 u32 source;
10604         } pipe[I915_MAX_PIPES];
10605
10606         struct intel_plane_error_state {
10607                 u32 control;
10608                 u32 stride;
10609                 u32 size;
10610                 u32 pos;
10611                 u32 addr;
10612                 u32 surface;
10613                 u32 tile_offset;
10614         } plane[I915_MAX_PIPES];
10615
10616         struct intel_transcoder_error_state {
10617                 enum transcoder cpu_transcoder;
10618
10619                 u32 conf;
10620
10621                 u32 htotal;
10622                 u32 hblank;
10623                 u32 hsync;
10624                 u32 vtotal;
10625                 u32 vblank;
10626                 u32 vsync;
10627         } transcoder[4];
10628 };
10629
10630 struct intel_display_error_state *
10631 intel_display_capture_error_state(struct drm_device *dev)
10632 {
10633         drm_i915_private_t *dev_priv = dev->dev_private;
10634         struct intel_display_error_state *error;
10635         int transcoders[] = {
10636                 TRANSCODER_A,
10637                 TRANSCODER_B,
10638                 TRANSCODER_C,
10639                 TRANSCODER_EDP,
10640         };
10641         int i;
10642
10643         if (INTEL_INFO(dev)->num_pipes == 0)
10644                 return NULL;
10645
10646         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10647         if (error == NULL)
10648                 return NULL;
10649
10650         if (HAS_POWER_WELL(dev))
10651                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10652
10653         for_each_pipe(i) {
10654                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10655                         error->cursor[i].control = I915_READ(CURCNTR(i));
10656                         error->cursor[i].position = I915_READ(CURPOS(i));
10657                         error->cursor[i].base = I915_READ(CURBASE(i));
10658                 } else {
10659                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10660                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10661                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10662                 }
10663
10664                 error->plane[i].control = I915_READ(DSPCNTR(i));
10665                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10666                 if (INTEL_INFO(dev)->gen <= 3) {
10667                         error->plane[i].size = I915_READ(DSPSIZE(i));
10668                         error->plane[i].pos = I915_READ(DSPPOS(i));
10669                 }
10670                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10671                         error->plane[i].addr = I915_READ(DSPADDR(i));
10672                 if (INTEL_INFO(dev)->gen >= 4) {
10673                         error->plane[i].surface = I915_READ(DSPSURF(i));
10674                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10675                 }
10676
10677                 error->pipe[i].source = I915_READ(PIPESRC(i));
10678         }
10679
10680         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10681         if (HAS_DDI(dev_priv->dev))
10682                 error->num_transcoders++; /* Account for eDP. */
10683
10684         for (i = 0; i < error->num_transcoders; i++) {
10685                 enum transcoder cpu_transcoder = transcoders[i];
10686
10687                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10688
10689                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10690                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10691                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10692                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10693                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10694                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10695                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10696         }
10697
10698         /* In the code above we read the registers without checking if the power
10699          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10700          * prevent the next I915_WRITE from detecting it and printing an error
10701          * message. */
10702         intel_uncore_clear_errors(dev);
10703
10704         return error;
10705 }
10706
10707 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10708
10709 void
10710 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10711                                 struct drm_device *dev,
10712                                 struct intel_display_error_state *error)
10713 {
10714         int i;
10715
10716         if (!error)
10717                 return;
10718
10719         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10720         if (HAS_POWER_WELL(dev))
10721                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10722                            error->power_well_driver);
10723         for_each_pipe(i) {
10724                 err_printf(m, "Pipe [%d]:\n", i);
10725                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10726
10727                 err_printf(m, "Plane [%d]:\n", i);
10728                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10729                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10730                 if (INTEL_INFO(dev)->gen <= 3) {
10731                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10732                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10733                 }
10734                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10735                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10736                 if (INTEL_INFO(dev)->gen >= 4) {
10737                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10738                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10739                 }
10740
10741                 err_printf(m, "Cursor [%d]:\n", i);
10742                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10743                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10744                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10745         }
10746
10747         for (i = 0; i < error->num_transcoders; i++) {
10748                 err_printf(m, "  CPU transcoder: %c\n",
10749                            transcoder_name(error->transcoder[i].cpu_transcoder));
10750                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10751                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10752                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10753                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10754                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10755                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10756                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10757         }
10758 }