drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 333         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 434         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 447         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 reg = PIPEDSL(pipe);
 807         u32 line1, line2;
 808         u32 line_mask;
 809
 810         if (IS_GEN2(dev))
 811                 line_mask = DSL_LINEMASK_GEN2;
 812         else
 813                 line_mask = DSL_LINEMASK_GEN3;
 814
 815         line1 = I915_READ(reg) & line_mask;
 816         mdelay(5);
 817         line2 = I915_READ(reg) & line_mask;
 818
 819         return line1 == line2;
 820 }
 821
 822 /*
 823  * intel_wait_for_pipe_off - wait for pipe to turn off
 824  * @dev: drm device
 825  * @pipe: pipe to wait for
 826  *
 827  * After disabling a pipe, we can't wait for vblank in the usual way,
 828  * spinning on the vblank interrupt status bit, since we won't actually
 829  * see an interrupt when the pipe is disabled.
 830  *
 831  * On Gen4 and above:
 832  *   wait for the pipe register state bit to turn off
 833  *
 834  * Otherwise:
 835  *   wait for the display line value to settle (it usually
 836  *   ends up stopping at the start of the next frame).
 837  *
 838  */
 839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 840 {
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 843                                                                       pipe);
 844
 845         if (INTEL_INFO(dev)->gen >= 4) {
 846                 int reg = PIPECONF(cpu_transcoder);
 847
 848                 /* Wait for the Pipe State to go off */
 849                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 850                              100))
 851                         WARN(1, "pipe_off wait timed out\n");
 852         } else {
 853                 /* Wait for the display line to settle */
 854                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 855                         WARN(1, "pipe_off wait timed out\n");
 856         }
 857 }
 858
 859 /*
 860  * ibx_digital_port_connected - is the specified port connected?
 861  * @dev_priv: i915 private structure
 862  * @port: the port to test
 863  *
 864  * Returns true if @port is connected, false otherwise.
 865  */
 866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 867                                 struct intel_digital_port *port)
 868 {
 869         u32 bit;
 870
 871         if (HAS_PCH_IBX(dev_priv->dev)) {
 872                 switch(port->port) {
 873                 case PORT_B:
 874                         bit = SDE_PORTB_HOTPLUG;
 875                         break;
 876                 case PORT_C:
 877                         bit = SDE_PORTC_HOTPLUG;
 878                         break;
 879                 case PORT_D:
 880                         bit = SDE_PORTD_HOTPLUG;
 881                         break;
 882                 default:
 883                         return true;
 884                 }
 885         } else {
 886                 switch(port->port) {
 887                 case PORT_B:
 888                         bit = SDE_PORTB_HOTPLUG_CPT;
 889                         break;
 890                 case PORT_C:
 891                         bit = SDE_PORTC_HOTPLUG_CPT;
 892                         break;
 893                 case PORT_D:
 894                         bit = SDE_PORTD_HOTPLUG_CPT;
 895                         break;
 896                 default:
 897                         return true;
 898                 }
 899         }
 900
 901         return I915_READ(SDEISR) & bit;
 902 }
 903
 904 static const char *state_string(bool enabled)
 905 {
 906         return enabled ? "on" : "off";
 907 }
 908
 909 /* Only for pre-ILK configs */
 910 void assert_pll(struct drm_i915_private *dev_priv,
 911                 enum pipe pipe, bool state)
 912 {
 913         int reg;
 914         u32 val;
 915         bool cur_state;
 916
 917         reg = DPLL(pipe);
 918         val = I915_READ(reg);
 919         cur_state = !!(val & DPLL_VCO_ENABLE);
 920         WARN(cur_state != state,
 921              "PLL state assertion failure (expected %s, current %s)\n",
 922              state_string(state), state_string(cur_state));
 923 }
 924
 925 /* XXX: the dsi pll is shared between MIPI DSI ports */
 926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 927 {
 928         u32 val;
 929         bool cur_state;
 930
 931         mutex_lock(&dev_priv->dpio_lock);
 932         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 933         mutex_unlock(&dev_priv->dpio_lock);
 934
 935         cur_state = val & DSI_PLL_VCO_EN;
 936         WARN(cur_state != state,
 937              "DSI PLL state assertion failure (expected %s, current %s)\n",
 938              state_string(state), state_string(cur_state));
 939 }
 940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 942
 943 struct intel_shared_dpll *
 944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 945 {
 946         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 947
 948         if (crtc->config.shared_dpll < 0)
 949                 return NULL;
 950
 951         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 952 }
 953
 954 /* For ILK+ */
 955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 956                         struct intel_shared_dpll *pll,
 957                         bool state)
 958 {
 959         bool cur_state;
 960         struct intel_dpll_hw_state hw_state;
 961
 962         if (HAS_PCH_LPT(dev_priv->dev)) {
 963                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 964                 return;
 965         }
 966
 967         if (WARN (!pll,
 968                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 969                 return;
 970
 971         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 972         WARN(cur_state != state,
 973              "%s assertion failure (expected %s, current %s)\n",
 974              pll->name, state_string(state), state_string(cur_state));
 975 }
 976
 977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 978                           enum pipe pipe, bool state)
 979 {
 980         int reg;
 981         u32 val;
 982         bool cur_state;
 983         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 984                                                                       pipe);
 985
 986         if (HAS_DDI(dev_priv->dev)) {
 987                 /* DDI does not have a specific FDI_TX register */
 988                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 989                 val = I915_READ(reg);
 990                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 991         } else {
 992                 reg = FDI_TX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_TX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI TX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004                           enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = FDI_RX_CTL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & FDI_RX_ENABLE);
1013         WARN(cur_state != state,
1014              "FDI RX state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         /* ILK FDI PLL is always enabled */
1027         if (dev_priv->info->gen == 5)
1028                 return;
1029
1030         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031         if (HAS_DDI(dev_priv->dev))
1032                 return;
1033
1034         reg = FDI_TX_CTL(pipe);
1035         val = I915_READ(reg);
1036         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = FDI_RX_CTL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049         WARN(cur_state != state,
1050              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055                                   enum pipe pipe)
1056 {
1057         int pp_reg, lvds_reg;
1058         u32 val;
1059         enum pipe panel_pipe = PIPE_A;
1060         bool locked = true;
1061
1062         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063                 pp_reg = PCH_PP_CONTROL;
1064                 lvds_reg = PCH_LVDS;
1065         } else {
1066                 pp_reg = PP_CONTROL;
1067                 lvds_reg = LVDS;
1068         }
1069
1070         val = I915_READ(pp_reg);
1071         if (!(val & PANEL_POWER_ON) ||
1072             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073                 locked = false;
1074
1075         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076                 panel_pipe = PIPE_B;
1077
1078         WARN(panel_pipe == pipe && locked,
1079              "panel assertion failure, pipe %c regs locked\n",
1080              pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         struct drm_device *dev = dev_priv->dev;
1087         bool cur_state;
1088
1089         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091         else if (IS_845G(dev) || IS_I865G(dev))
1092                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093         else
1094                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096         WARN(cur_state != state,
1097              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098              pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104                  enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         /* if we need the pipe A quirk it must be always on */
1113         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114                 state = true;
1115
1116         if (!intel_display_power_enabled(dev_priv->dev,
1117                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118                 cur_state = false;
1119         } else {
1120                 reg = PIPECONF(cpu_transcoder);
1121                 val = I915_READ(reg);
1122                 cur_state = !!(val & PIPECONF_ENABLE);
1123         }
1124
1125         WARN(cur_state != state,
1126              "pipe %c assertion failure (expected %s, current %s)\n",
1127              pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131                          enum plane plane, bool state)
1132 {
1133         int reg;
1134         u32 val;
1135         bool cur_state;
1136
1137         reg = DSPCNTR(plane);
1138         val = I915_READ(reg);
1139         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140         WARN(cur_state != state,
1141              "plane %c assertion failure (expected %s, current %s)\n",
1142              plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149                                    enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154         int cur_pipe;
1155
1156         /* Primary planes are fixed to pipes on gen4+ */
1157         if (INTEL_INFO(dev)->gen >= 4) {
1158                 reg = DSPCNTR(pipe);
1159                 val = I915_READ(reg);
1160                 WARN((val & DISPLAY_PLANE_ENABLE),
1161                      "plane %c assertion failure, should be disabled but not\n",
1162                      plane_name(pipe));
1163                 return;
1164         }
1165
1166         /* Need to check both planes against the pipe */
1167         for_each_pipe(i) {
1168                 reg = DSPCNTR(i);
1169                 val = I915_READ(reg);
1170                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171                         DISPPLANE_SEL_PIPE_SHIFT;
1172                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(i), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179                                     enum pipe pipe)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         int reg, i;
1183         u32 val;
1184
1185         if (IS_VALLEYVIEW(dev)) {
1186                 for (i = 0; i < dev_priv->num_plane; i++) {
1187                         reg = SPCNTR(pipe, i);
1188                         val = I915_READ(reg);
1189                         WARN((val & SP_ENABLE),
1190                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                              sprite_name(pipe, i), pipe_name(pipe));
1192                 }
1193         } else if (INTEL_INFO(dev)->gen >= 7) {
1194                 reg = SPRCTL(pipe);
1195                 val = I915_READ(reg);
1196                 WARN((val & SPRITE_ENABLE),
1197                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198                      plane_name(pipe), pipe_name(pipe));
1199         } else if (INTEL_INFO(dev)->gen >= 5) {
1200                 reg = DVSCNTR(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & DVS_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210         u32 val;
1211         bool enabled;
1212
1213         if (HAS_PCH_LPT(dev_priv->dev)) {
1214                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215                 return;
1216         }
1217
1218         val = I915_READ(PCH_DREF_CONTROL);
1219         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220                             DREF_SUPERSPREAD_SOURCE_MASK));
1221         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229         bool enabled;
1230
1231         reg = PCH_TRANSCONF(pipe);
1232         val = I915_READ(reg);
1233         enabled = !!(val & TRANS_ENABLE);
1234         WARN(enabled,
1235              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236              pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240                             enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242         if ((val & DP_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249                         return false;
1250         } else {
1251                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252                         return false;
1253         }
1254         return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258                               enum pipe pipe, u32 val)
1259 {
1260         if ((val & SDVO_ENABLE) == 0)
1261                 return false;
1262
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274                               enum pipe pipe, u32 val)
1275 {
1276         if ((val & LVDS_PORT_EN) == 0)
1277                 return false;
1278
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290                               enum pipe pipe, u32 val)
1291 {
1292         if ((val & ADPA_DAC_ENABLE) == 0)
1293                 return false;
1294         if (HAS_PCH_CPT(dev_priv->dev)) {
1295                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296                         return false;
1297         } else {
1298                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299                         return false;
1300         }
1301         return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305                                    enum pipe pipe, int reg, u32 port_sel)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313              && (val & DP_PIPEB_SELECT),
1314              "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318                                      enum pipe pipe, int reg)
1319 {
1320         u32 val = I915_READ(reg);
1321         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323              reg, pipe_name(pipe));
1324
1325         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326              && (val & SDVO_PIPE_B_SELECT),
1327              "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331                                       enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335
1336         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340         reg = PCH_ADPA;
1341         val = I915_READ(reg);
1342         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343              "PCH VGA enabled on transcoder %c, should be disabled\n",
1344              pipe_name(pipe));
1345
1346         reg = PCH_LVDS;
1347         val = I915_READ(reg);
1348         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         if (!IS_VALLEYVIEW(dev))
1362                 return;
1363
1364         /*
1365          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1367          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368          *   b. The other bits such as sfr settings / modesel may all be set
1369          *      to 0.
1370          *
1371          * This should only be done on init and resume from S3 with both
1372          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373          */
1374         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379         struct drm_device *dev = crtc->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int reg = DPLL(crtc->pipe);
1382         u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384         assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386         /* No really, not for ILK+ */
1387         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389         /* PLL is protected by panel, make sure we can write it */
1390         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391                 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150);
1396
1397         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401         POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403         /* We do this three times for luck */
1404         I915_WRITE(reg, dpll);
1405         POSTING_READ(reg);
1406         udelay(150); /* wait for warmup */
1407         I915_WRITE(reg, dpll);
1408         POSTING_READ(reg);
1409         udelay(150); /* wait for warmup */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int reg = DPLL(crtc->pipe);
1420         u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422         assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424         /* No really, not for ILK+ */
1425         BUG_ON(dev_priv->info->gen >= 5);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         if (IS_MOBILE(dev) && !IS_I830(dev))
1429                 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431         I915_WRITE(reg, dpll);
1432
1433         /* Wait for the clocks to stabilize. */
1434         POSTING_READ(reg);
1435         udelay(150);
1436
1437         if (INTEL_INFO(dev)->gen >= 4) {
1438                 I915_WRITE(DPLL_MD(crtc->pipe),
1439                            crtc->config.dpll_hw_state.dpll_md);
1440         } else {
1441                 /* The pixel multiplier can only be updated once the
1442                  * DPLL is enabled and the clocks are stable.
1443                  *
1444                  * So write it again.
1445                  */
1446                 I915_WRITE(reg, dpll);
1447         }
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, dpll);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, dpll);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * i9xx_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         /* Don't disable pipe A or pipe A PLLs if needed */
1473         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474                 return;
1475
1476         /* Make sure the pipe isn't still relying on us */
1477         assert_pipe_disabled(dev_priv, pipe);
1478
1479         I915_WRITE(DPLL(pipe), 0);
1480         POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485         u32 val = 0;
1486
1487         /* Make sure the pipe isn't still relying on us */
1488         assert_pipe_disabled(dev_priv, pipe);
1489
1490         /* Leave integrated clock source enabled */
1491         if (pipe == PIPE_B)
1492                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493         I915_WRITE(DPLL(pipe), val);
1494         POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499         u32 port_mask;
1500
1501         if (!port)
1502                 port_mask = DPLL_PORTB_READY_MASK;
1503         else
1504                 port_mask = DPLL_PORTC_READY_MASK;
1505
1506         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508                      'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512  * ironlake_enable_shared_dpll - enable PCH PLL
1513  * @dev_priv: i915 private structure
1514  * @pipe: pipe PLL to enable
1515  *
1516  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517  * drives the transcoder clock.
1518  */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524         /* PCH PLLs only available on ILK, SNB and IVB */
1525         BUG_ON(dev_priv->info->gen < 5);
1526         if (WARN_ON(pll == NULL))
1527                 return;
1528
1529         if (WARN_ON(pll->refcount == 0))
1530                 return;
1531
1532         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533                       pll->name, pll->active, pll->on,
1534                       crtc->base.base.id);
1535
1536         if (pll->active++) {
1537                 WARN_ON(!pll->on);
1538                 assert_shared_dpll_enabled(dev_priv, pll);
1539                 return;
1540         }
1541         WARN_ON(pll->on);
1542
1543         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544         pll->enable(dev_priv, pll);
1545         pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553         /* PCH only available on ILK+ */
1554         BUG_ON(dev_priv->info->gen < 5);
1555         if (WARN_ON(pll == NULL))
1556                return;
1557
1558         if (WARN_ON(pll->refcount == 0))
1559                 return;
1560
1561         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562                       pll->name, pll->active, pll->on,
1563                       crtc->base.base.id);
1564
1565         if (WARN_ON(pll->active == 0)) {
1566                 assert_shared_dpll_disabled(dev_priv, pll);
1567                 return;
1568         }
1569
1570         assert_shared_dpll_enabled(dev_priv, pll);
1571         WARN_ON(!pll->on);
1572         if (--pll->active)
1573                 return;
1574
1575         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576         pll->disable(dev_priv, pll);
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586         uint32_t reg, val, pipeconf_val;
1587
1588         /* PCH only available on ILK+ */
1589         BUG_ON(dev_priv->info->gen < 5);
1590
1591         /* Make sure PCH DPLL is enabled */
1592         assert_shared_dpll_enabled(dev_priv,
1593                                    intel_crtc_to_shared_dpll(intel_crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port, bool dsi)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_cursor_disabled(dev_priv, pipe);
1739         assert_sprites_disabled(dev_priv, pipe);
1740
1741         if (HAS_PCH_LPT(dev_priv->dev))
1742                 pch_transcoder = TRANSCODER_A;
1743         else
1744                 pch_transcoder = pipe;
1745
1746         /*
1747          * A pipe without a PLL won't actually be able to drive bits from
1748          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1749          * need the check.
1750          */
1751         if (!HAS_PCH_SPLIT(dev_priv->dev))
1752                 if (dsi)
1753                         assert_dsi_pll_enabled(dev_priv);
1754                 else
1755                         assert_pll_enabled(dev_priv, pipe);
1756         else {
1757                 if (pch_port) {
1758                         /* if driving the PCH, we need FDI enabled */
1759                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760                         assert_fdi_tx_pll_enabled(dev_priv,
1761                                                   (enum pipe) cpu_transcoder);
1762                 }
1763                 /* FIXME: assert CPU port conditions for SNB+ */
1764         }
1765
1766         reg = PIPECONF(cpu_transcoder);
1767         val = I915_READ(reg);
1768         if (val & PIPECONF_ENABLE)
1769                 return;
1770
1771         I915_WRITE(reg, val | PIPECONF_ENABLE);
1772         intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776  * intel_disable_pipe - disable a pipe, asserting requirements
1777  * @dev_priv: i915 private structure
1778  * @pipe: pipe to disable
1779  *
1780  * Disable @pipe, making sure that various hardware specific requirements
1781  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782  *
1783  * @pipe should be %PIPE_A or %PIPE_B.
1784  *
1785  * Will wait until the pipe has shut down before returning.
1786  */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788                                enum pipe pipe)
1789 {
1790         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791                                                                       pipe);
1792         int reg;
1793         u32 val;
1794
1795         /*
1796          * Make sure planes won't keep trying to pump pixels to us,
1797          * or we might hang the display.
1798          */
1799         assert_planes_disabled(dev_priv, pipe);
1800         assert_cursor_disabled(dev_priv, pipe);
1801         assert_sprites_disabled(dev_priv, pipe);
1802
1803         /* Don't disable pipe A or pipe A PLLs if needed */
1804         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805                 return;
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if ((val & PIPECONF_ENABLE) == 0)
1810                 return;
1811
1812         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817  * Plane regs are double buffered, going from enabled->disabled needs a
1818  * trigger in order to latch.  The display address reg provides this.
1819  */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane)
1822 {
1823         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825         I915_WRITE(reg, I915_READ(reg));
1826         POSTING_READ(reg);
1827 }
1828
1829 /**
1830  * intel_enable_primary_plane - enable the primary plane on a given pipe
1831  * @dev_priv: i915 private structure
1832  * @plane: plane to enable
1833  * @pipe: pipe being fed
1834  *
1835  * Enable @plane on @pipe, making sure that @pipe is running first.
1836  */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838                                        enum plane plane, enum pipe pipe)
1839 {
1840         struct intel_crtc *intel_crtc =
1841                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842         int reg;
1843         u32 val;
1844
1845         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846         assert_pipe_enabled(dev_priv, pipe);
1847
1848         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850         intel_crtc->primary_enabled = true;
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_primary_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_primary_plane - disable the primary plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871                                         enum plane plane, enum pipe pipe)
1872 {
1873         struct intel_crtc *intel_crtc =
1874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875         int reg;
1876         u32 val;
1877
1878         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880         intel_crtc->primary_enabled = false;
1881
1882         reg = DSPCNTR(plane);
1883         val = I915_READ(reg);
1884         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885                 return;
1886
1887         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888         intel_flush_primary_plane(dev_priv, plane);
1889         intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896                 return true;
1897 #endif
1898         return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903                            struct drm_i915_gem_object *obj,
1904                            struct intel_ring_buffer *pipelined)
1905 {
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 alignment;
1908         int ret;
1909
1910         switch (obj->tiling_mode) {
1911         case I915_TILING_NONE:
1912                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913                         alignment = 128 * 1024;
1914                 else if (INTEL_INFO(dev)->gen >= 4)
1915                         alignment = 4 * 1024;
1916                 else
1917                         alignment = 64 * 1024;
1918                 break;
1919         case I915_TILING_X:
1920                 /* pin() will align the object as required by fence */
1921                 alignment = 0;
1922                 break;
1923         case I915_TILING_Y:
1924                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1925                 return -EINVAL;
1926         default:
1927                 BUG();
1928         }
1929
1930         /* Note that the w/a also requires 64 PTE of padding following the
1931          * bo. We currently fill all unused PTE with the shadow page and so
1932          * we should always have valid PTE following the scanout preventing
1933          * the VT-d warning.
1934          */
1935         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936                 alignment = 256 * 1024;
1937
1938         dev_priv->mm.interruptible = false;
1939         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1940         if (ret)
1941                 goto err_interruptible;
1942
1943         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944          * fence, whereas 965+ only requires a fence if using
1945          * framebuffer compression.  For simplicity, we always install
1946          * a fence as the cost is not that onerous.
1947          */
1948         ret = i915_gem_object_get_fence(obj);
1949         if (ret)
1950                 goto err_unpin;
1951
1952         i915_gem_object_pin_fence(obj);
1953
1954         dev_priv->mm.interruptible = true;
1955         return 0;
1956
1957 err_unpin:
1958         i915_gem_object_unpin_from_display_plane(obj);
1959 err_interruptible:
1960         dev_priv->mm.interruptible = true;
1961         return ret;
1962 }
1963
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965 {
1966         i915_gem_object_unpin_fence(obj);
1967         i915_gem_object_unpin_from_display_plane(obj);
1968 }
1969
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971  * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973                                              unsigned int tiling_mode,
1974                                              unsigned int cpp,
1975                                              unsigned int pitch)
1976 {
1977         if (tiling_mode != I915_TILING_NONE) {
1978                 unsigned int tile_rows, tiles;
1979
1980                 tile_rows = *y / 8;
1981                 *y %= 8;
1982
1983                 tiles = *x / (512/cpp);
1984                 *x %= 512/cpp;
1985
1986                 return tile_rows * pitch * 8 + tiles * 4096;
1987         } else {
1988                 unsigned int offset;
1989
1990                 offset = *y * pitch + *x * cpp;
1991                 *y = 0;
1992                 *x = (offset & 4095) / cpp;
1993                 return offset & -4096;
1994         }
1995 }
1996
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998                              int x, int y)
1999 {
2000         struct drm_device *dev = crtc->dev;
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003         struct intel_framebuffer *intel_fb;
2004         struct drm_i915_gem_object *obj;
2005         int plane = intel_crtc->plane;
2006         unsigned long linear_offset;
2007         u32 dspcntr;
2008         u32 reg;
2009
2010         switch (plane) {
2011         case 0:
2012         case 1:
2013                 break;
2014         default:
2015                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2016                 return -EINVAL;
2017         }
2018
2019         intel_fb = to_intel_framebuffer(fb);
2020         obj = intel_fb->obj;
2021
2022         reg = DSPCNTR(plane);
2023         dspcntr = I915_READ(reg);
2024         /* Mask out pixel format bits in case we change it */
2025         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026         switch (fb->pixel_format) {
2027         case DRM_FORMAT_C8:
2028                 dspcntr |= DISPPLANE_8BPP;
2029                 break;
2030         case DRM_FORMAT_XRGB1555:
2031         case DRM_FORMAT_ARGB1555:
2032                 dspcntr |= DISPPLANE_BGRX555;
2033                 break;
2034         case DRM_FORMAT_RGB565:
2035                 dspcntr |= DISPPLANE_BGRX565;
2036                 break;
2037         case DRM_FORMAT_XRGB8888:
2038         case DRM_FORMAT_ARGB8888:
2039                 dspcntr |= DISPPLANE_BGRX888;
2040                 break;
2041         case DRM_FORMAT_XBGR8888:
2042         case DRM_FORMAT_ABGR8888:
2043                 dspcntr |= DISPPLANE_RGBX888;
2044                 break;
2045         case DRM_FORMAT_XRGB2101010:
2046         case DRM_FORMAT_ARGB2101010:
2047                 dspcntr |= DISPPLANE_BGRX101010;
2048                 break;
2049         case DRM_FORMAT_XBGR2101010:
2050         case DRM_FORMAT_ABGR2101010:
2051                 dspcntr |= DISPPLANE_RGBX101010;
2052                 break;
2053         default:
2054                 BUG();
2055         }
2056
2057         if (INTEL_INFO(dev)->gen >= 4) {
2058                 if (obj->tiling_mode != I915_TILING_NONE)
2059                         dspcntr |= DISPPLANE_TILED;
2060                 else
2061                         dspcntr &= ~DISPPLANE_TILED;
2062         }
2063
2064         if (IS_G4X(dev))
2065                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
2067         I915_WRITE(reg, dspcntr);
2068
2069         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2070
2071         if (INTEL_INFO(dev)->gen >= 4) {
2072                 intel_crtc->dspaddr_offset =
2073                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074                                                        fb->bits_per_pixel / 8,
2075                                                        fb->pitches[0]);
2076                 linear_offset -= intel_crtc->dspaddr_offset;
2077         } else {
2078                 intel_crtc->dspaddr_offset = linear_offset;
2079         }
2080
2081         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083                       fb->pitches[0]);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090         } else
2091                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2092         POSTING_READ(reg);
2093
2094         return 0;
2095 }
2096
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098                                  struct drm_framebuffer *fb, int x, int y)
2099 {
2100         struct drm_device *dev = crtc->dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103         struct intel_framebuffer *intel_fb;
2104         struct drm_i915_gem_object *obj;
2105         int plane = intel_crtc->plane;
2106         unsigned long linear_offset;
2107         u32 dspcntr;
2108         u32 reg;
2109
2110         switch (plane) {
2111         case 0:
2112         case 1:
2113         case 2:
2114                 break;
2115         default:
2116                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2117                 return -EINVAL;
2118         }
2119
2120         intel_fb = to_intel_framebuffer(fb);
2121         obj = intel_fb->obj;
2122
2123         reg = DSPCNTR(plane);
2124         dspcntr = I915_READ(reg);
2125         /* Mask out pixel format bits in case we change it */
2126         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127         switch (fb->pixel_format) {
2128         case DRM_FORMAT_C8:
2129                 dspcntr |= DISPPLANE_8BPP;
2130                 break;
2131         case DRM_FORMAT_RGB565:
2132                 dspcntr |= DISPPLANE_BGRX565;
2133                 break;
2134         case DRM_FORMAT_XRGB8888:
2135         case DRM_FORMAT_ARGB8888:
2136                 dspcntr |= DISPPLANE_BGRX888;
2137                 break;
2138         case DRM_FORMAT_XBGR8888:
2139         case DRM_FORMAT_ABGR8888:
2140                 dspcntr |= DISPPLANE_RGBX888;
2141                 break;
2142         case DRM_FORMAT_XRGB2101010:
2143         case DRM_FORMAT_ARGB2101010:
2144                 dspcntr |= DISPPLANE_BGRX101010;
2145                 break;
2146         case DRM_FORMAT_XBGR2101010:
2147         case DRM_FORMAT_ABGR2101010:
2148                 dspcntr |= DISPPLANE_RGBX101010;
2149                 break;
2150         default:
2151                 BUG();
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2160                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161         else
2162                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2163
2164         I915_WRITE(reg, dspcntr);
2165
2166         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167         intel_crtc->dspaddr_offset =
2168                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169                                                fb->bits_per_pixel / 8,
2170                                                fb->pitches[0]);
2171         linear_offset -= intel_crtc->dspaddr_offset;
2172
2173         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175                       fb->pitches[0]);
2176         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177         I915_MODIFY_DISPBASE(DSPSURF(plane),
2178                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2180                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181         } else {
2182                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184         }
2185         POSTING_READ(reg);
2186
2187         return 0;
2188 }
2189
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2191 static int
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193                            int x, int y, enum mode_set_atomic state)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198         if (dev_priv->display.disable_fbc)
2199                 dev_priv->display.disable_fbc(dev);
2200         intel_increase_pllclock(crtc);
2201
2202         return dev_priv->display.update_plane(crtc, fb, x, y);
2203 }
2204
2205 void intel_display_handle_reset(struct drm_device *dev)
2206 {
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_crtc *crtc;
2209
2210         /*
2211          * Flips in the rings have been nuked by the reset,
2212          * so complete all pending flips so that user space
2213          * will get its events and not get stuck.
2214          *
2215          * Also update the base address of all primary
2216          * planes to the the last fb to make sure we're
2217          * showing the correct fb after a reset.
2218          *
2219          * Need to make two loops over the crtcs so that we
2220          * don't try to grab a crtc mutex before the
2221          * pending_flip_queue really got woken up.
2222          */
2223
2224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226                 enum plane plane = intel_crtc->plane;
2227
2228                 intel_prepare_page_flip(dev, plane);
2229                 intel_finish_page_flip_plane(dev, plane);
2230         }
2231
2232         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235                 mutex_lock(&crtc->mutex);
2236                 if (intel_crtc->active)
2237                         dev_priv->display.update_plane(crtc, crtc->fb,
2238                                                        crtc->x, crtc->y);
2239                 mutex_unlock(&crtc->mutex);
2240         }
2241 }
2242
2243 static int
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2245 {
2246         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248         bool was_interruptible = dev_priv->mm.interruptible;
2249         int ret;
2250
2251         /* Big Hammer, we also need to ensure that any pending
2252          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253          * current scanout is retired before unpinning the old
2254          * framebuffer.
2255          *
2256          * This should only fail upon a hung GPU, in which case we
2257          * can safely continue.
2258          */
2259         dev_priv->mm.interruptible = false;
2260         ret = i915_gem_object_finish_gpu(obj);
2261         dev_priv->mm.interruptible = was_interruptible;
2262
2263         return ret;
2264 }
2265
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_master_private *master_priv;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272         if (!dev->primary->master)
2273                 return;
2274
2275         master_priv = dev->primary->master->driver_priv;
2276         if (!master_priv->sarea_priv)
2277                 return;
2278
2279         switch (intel_crtc->pipe) {
2280         case 0:
2281                 master_priv->sarea_priv->pipeA_x = x;
2282                 master_priv->sarea_priv->pipeA_y = y;
2283                 break;
2284         case 1:
2285                 master_priv->sarea_priv->pipeB_x = x;
2286                 master_priv->sarea_priv->pipeB_y = y;
2287                 break;
2288         default:
2289                 break;
2290         }
2291 }
2292
2293 static int
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295                     struct drm_framebuffer *fb)
2296 {
2297         struct drm_device *dev = crtc->dev;
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300         struct drm_framebuffer *old_fb;
2301         int ret;
2302
2303         /* no fb bound */
2304         if (!fb) {
2305                 DRM_ERROR("No FB bound\n");
2306                 return 0;
2307         }
2308
2309         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311                           plane_name(intel_crtc->plane),
2312                           INTEL_INFO(dev)->num_pipes);
2313                 return -EINVAL;
2314         }
2315
2316         mutex_lock(&dev->struct_mutex);
2317         ret = intel_pin_and_fence_fb_obj(dev,
2318                                          to_intel_framebuffer(fb)->obj,
2319                                          NULL);
2320         if (ret != 0) {
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("pin & fence failed\n");
2323                 return ret;
2324         }
2325
2326         /*
2327          * Update pipe size and adjust fitter if needed: the reason for this is
2328          * that in compute_mode_changes we check the native mode (not the pfit
2329          * mode) to see if we can flip rather than do a full mode set. In the
2330          * fastboot case, we'll flip, but if we don't update the pipesrc and
2331          * pfit state, we'll end up with a big fb scanned out into the wrong
2332          * sized surface.
2333          *
2334          * To fix this properly, we need to hoist the checks up into
2335          * compute_mode_changes (or above), check the actual pfit state and
2336          * whether the platform allows pfit disable with pipe active, and only
2337          * then update the pipesrc and pfit state, even on the flip path.
2338          */
2339         if (i915_fastboot) {
2340                 const struct drm_display_mode *adjusted_mode =
2341                         &intel_crtc->config.adjusted_mode;
2342
2343                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345                            (adjusted_mode->crtc_vdisplay - 1));
2346                 if (!intel_crtc->config.pch_pfit.enabled &&
2347                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352                 }
2353         }
2354
2355         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2356         if (ret) {
2357                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358                 mutex_unlock(&dev->struct_mutex);
2359                 DRM_ERROR("failed to update base address\n");
2360                 return ret;
2361         }
2362
2363         old_fb = crtc->fb;
2364         crtc->fb = fb;
2365         crtc->x = x;
2366         crtc->y = y;
2367
2368         if (old_fb) {
2369                 if (intel_crtc->active && old_fb != fb)
2370                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2371                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372         }
2373
2374         intel_update_fbc(dev);
2375         intel_edp_psr_update(dev);
2376         mutex_unlock(&dev->struct_mutex);
2377
2378         intel_crtc_update_sarea_pos(crtc, x, y);
2379
2380         return 0;
2381 }
2382
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384 {
2385         struct drm_device *dev = crtc->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388         int pipe = intel_crtc->pipe;
2389         u32 reg, temp;
2390
2391         /* enable normal train */
2392         reg = FDI_TX_CTL(pipe);
2393         temp = I915_READ(reg);
2394         if (IS_IVYBRIDGE(dev)) {
2395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         } else {
2398                 temp &= ~FDI_LINK_TRAIN_NONE;
2399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         }
2401         I915_WRITE(reg, temp);
2402
2403         reg = FDI_RX_CTL(pipe);
2404         temp = I915_READ(reg);
2405         if (HAS_PCH_CPT(dev)) {
2406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408         } else {
2409                 temp &= ~FDI_LINK_TRAIN_NONE;
2410                 temp |= FDI_LINK_TRAIN_NONE;
2411         }
2412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414         /* wait one idle pattern time */
2415         POSTING_READ(reg);
2416         udelay(1000);
2417
2418         /* IVB wants error correction enabled */
2419         if (IS_IVYBRIDGE(dev))
2420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421                            FDI_FE_ERRC_ENABLE);
2422 }
2423
2424 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2425 {
2426         return crtc->base.enabled && crtc->active &&
2427                 crtc->config.has_pch_encoder;
2428 }
2429
2430 static void ivb_modeset_global_resources(struct drm_device *dev)
2431 {
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *pipe_B_crtc =
2434                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435         struct intel_crtc *pipe_C_crtc =
2436                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437         uint32_t temp;
2438
2439         /*
2440          * When everything is off disable fdi C so that we could enable fdi B
2441          * with all lanes. Note that we don't care about enabled pipes without
2442          * an enabled pch encoder.
2443          */
2444         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445             !pipe_has_enabled_pch(pipe_C_crtc)) {
2446                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449                 temp = I915_READ(SOUTH_CHICKEN1);
2450                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452                 I915_WRITE(SOUTH_CHICKEN1, temp);
2453         }
2454 }
2455
2456 /* The FDI link training functions for ILK/Ibexpeak. */
2457 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458 {
2459         struct drm_device *dev = crtc->dev;
2460         struct drm_i915_private *dev_priv = dev->dev_private;
2461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462         int pipe = intel_crtc->pipe;
2463         int plane = intel_crtc->plane;
2464         u32 reg, temp, tries;
2465
2466         /* FDI needs bits from pipe & plane first */
2467         assert_pipe_enabled(dev_priv, pipe);
2468         assert_plane_enabled(dev_priv, plane);
2469
2470         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471            for train result */
2472         reg = FDI_RX_IMR(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_RX_SYMBOL_LOCK;
2475         temp &= ~FDI_RX_BIT_LOCK;
2476         I915_WRITE(reg, temp);
2477         I915_READ(reg);
2478         udelay(150);
2479
2480         /* enable CPU FDI TX and PCH FDI RX */
2481         reg = FDI_TX_CTL(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2485         temp &= ~FDI_LINK_TRAIN_NONE;
2486         temp |= FDI_LINK_TRAIN_PATTERN_1;
2487         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2488
2489         reg = FDI_RX_CTL(pipe);
2490         temp = I915_READ(reg);
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495         POSTING_READ(reg);
2496         udelay(150);
2497
2498         /* Ironlake workaround, enable clock pointer after FDI enable*/
2499         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501                    FDI_RX_PHASE_SYNC_POINTER_EN);
2502
2503         reg = FDI_RX_IIR(pipe);
2504         for (tries = 0; tries < 5; tries++) {
2505                 temp = I915_READ(reg);
2506                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508                 if ((temp & FDI_RX_BIT_LOCK)) {
2509                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2510                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2511                         break;
2512                 }
2513         }
2514         if (tries == 5)
2515                 DRM_ERROR("FDI train 1 fail!\n");
2516
2517         /* Train 2 */
2518         reg = FDI_TX_CTL(pipe);
2519         temp = I915_READ(reg);
2520         temp &= ~FDI_LINK_TRAIN_NONE;
2521         temp |= FDI_LINK_TRAIN_PATTERN_2;
2522         I915_WRITE(reg, temp);
2523
2524         reg = FDI_RX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~FDI_LINK_TRAIN_NONE;
2527         temp |= FDI_LINK_TRAIN_PATTERN_2;
2528         I915_WRITE(reg, temp);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         reg = FDI_RX_IIR(pipe);
2534         for (tries = 0; tries < 5; tries++) {
2535                 temp = I915_READ(reg);
2536                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538                 if (temp & FDI_RX_SYMBOL_LOCK) {
2539                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2540                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2541                         break;
2542                 }
2543         }
2544         if (tries == 5)
2545                 DRM_ERROR("FDI train 2 fail!\n");
2546
2547         DRM_DEBUG_KMS("FDI train done\n");
2548
2549 }
2550
2551 static const int snb_b_fdi_train_param[] = {
2552         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556 };
2557
2558 /* The FDI link training functions for SNB/Cougarpoint. */
2559 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560 {
2561         struct drm_device *dev = crtc->dev;
2562         struct drm_i915_private *dev_priv = dev->dev_private;
2563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564         int pipe = intel_crtc->pipe;
2565         u32 reg, temp, i, retry;
2566
2567         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568            for train result */
2569         reg = FDI_RX_IMR(pipe);
2570         temp = I915_READ(reg);
2571         temp &= ~FDI_RX_SYMBOL_LOCK;
2572         temp &= ~FDI_RX_BIT_LOCK;
2573         I915_WRITE(reg, temp);
2574
2575         POSTING_READ(reg);
2576         udelay(150);
2577
2578         /* enable CPU FDI TX and PCH FDI RX */
2579         reg = FDI_TX_CTL(pipe);
2580         temp = I915_READ(reg);
2581         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2583         temp &= ~FDI_LINK_TRAIN_NONE;
2584         temp |= FDI_LINK_TRAIN_PATTERN_1;
2585         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586         /* SNB-B */
2587         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2588         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2589
2590         I915_WRITE(FDI_RX_MISC(pipe),
2591                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601         }
2602         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_BIT_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 1 fail!\n");
2633
2634         /* Train 2 */
2635         reg = FDI_TX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         temp &= ~FDI_LINK_TRAIN_NONE;
2638         temp |= FDI_LINK_TRAIN_PATTERN_2;
2639         if (IS_GEN6(dev)) {
2640                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641                 /* SNB-B */
2642                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643         }
2644         I915_WRITE(reg, temp);
2645
2646         reg = FDI_RX_CTL(pipe);
2647         temp = I915_READ(reg);
2648         if (HAS_PCH_CPT(dev)) {
2649                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651         } else {
2652                 temp &= ~FDI_LINK_TRAIN_NONE;
2653                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654         }
2655         I915_WRITE(reg, temp);
2656
2657         POSTING_READ(reg);
2658         udelay(150);
2659
2660         for (i = 0; i < 4; i++) {
2661                 reg = FDI_TX_CTL(pipe);
2662                 temp = I915_READ(reg);
2663                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664                 temp |= snb_b_fdi_train_param[i];
2665                 I915_WRITE(reg, temp);
2666
2667                 POSTING_READ(reg);
2668                 udelay(500);
2669
2670                 for (retry = 0; retry < 5; retry++) {
2671                         reg = FDI_RX_IIR(pipe);
2672                         temp = I915_READ(reg);
2673                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674                         if (temp & FDI_RX_SYMBOL_LOCK) {
2675                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677                                 break;
2678                         }
2679                         udelay(50);
2680                 }
2681                 if (retry < 5)
2682                         break;
2683         }
2684         if (i == 4)
2685                 DRM_ERROR("FDI train 2 fail!\n");
2686
2687         DRM_DEBUG_KMS("FDI train done.\n");
2688 }
2689
2690 /* Manual link training for Ivy Bridge A0 parts */
2691 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692 {
2693         struct drm_device *dev = crtc->dev;
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696         int pipe = intel_crtc->pipe;
2697         u32 reg, temp, i, j;
2698
2699         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700            for train result */
2701         reg = FDI_RX_IMR(pipe);
2702         temp = I915_READ(reg);
2703         temp &= ~FDI_RX_SYMBOL_LOCK;
2704         temp &= ~FDI_RX_BIT_LOCK;
2705         I915_WRITE(reg, temp);
2706
2707         POSTING_READ(reg);
2708         udelay(150);
2709
2710         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711                       I915_READ(FDI_RX_IIR(pipe)));
2712
2713         /* Try each vswing and preemphasis setting twice before moving on */
2714         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715                 /* disable first in case we need to retry */
2716                 reg = FDI_TX_CTL(pipe);
2717                 temp = I915_READ(reg);
2718                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719                 temp &= ~FDI_TX_ENABLE;
2720                 I915_WRITE(reg, temp);
2721
2722                 reg = FDI_RX_CTL(pipe);
2723                 temp = I915_READ(reg);
2724                 temp &= ~FDI_LINK_TRAIN_AUTO;
2725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726                 temp &= ~FDI_RX_ENABLE;
2727                 I915_WRITE(reg, temp);
2728
2729                 /* enable CPU FDI TX and PCH FDI RX */
2730                 reg = FDI_TX_CTL(pipe);
2731                 temp = I915_READ(reg);
2732                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736                 temp |= snb_b_fdi_train_param[j/2];
2737                 temp |= FDI_COMPOSITE_SYNC;
2738                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
2740                 I915_WRITE(FDI_RX_MISC(pipe),
2741                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
2743                 reg = FDI_RX_CTL(pipe);
2744                 temp = I915_READ(reg);
2745                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746                 temp |= FDI_COMPOSITE_SYNC;
2747                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2748
2749                 POSTING_READ(reg);
2750                 udelay(1); /* should be 0.5us */
2751
2752                 for (i = 0; i < 4; i++) {
2753                         reg = FDI_RX_IIR(pipe);
2754                         temp = I915_READ(reg);
2755                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2756
2757                         if (temp & FDI_RX_BIT_LOCK ||
2758                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761                                               i);
2762                                 break;
2763                         }
2764                         udelay(1); /* should be 0.5us */
2765                 }
2766                 if (i == 4) {
2767                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2768                         continue;
2769                 }
2770
2771                 /* Train 2 */
2772                 reg = FDI_TX_CTL(pipe);
2773                 temp = I915_READ(reg);
2774                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776                 I915_WRITE(reg, temp);
2777
2778                 reg = FDI_RX_CTL(pipe);
2779                 temp = I915_READ(reg);
2780                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2782                 I915_WRITE(reg, temp);
2783
2784                 POSTING_READ(reg);
2785                 udelay(2); /* should be 1.5us */
2786
2787                 for (i = 0; i < 4; i++) {
2788                         reg = FDI_RX_IIR(pipe);
2789                         temp = I915_READ(reg);
2790                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2791
2792                         if (temp & FDI_RX_SYMBOL_LOCK ||
2793                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796                                               i);
2797                                 goto train_done;
2798                         }
2799                         udelay(2); /* should be 1.5us */
2800                 }
2801                 if (i == 4)
2802                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2803         }
2804
2805 train_done:
2806         DRM_DEBUG_KMS("FDI train done.\n");
2807 }
2808
2809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2810 {
2811         struct drm_device *dev = intel_crtc->base.dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         int pipe = intel_crtc->pipe;
2814         u32 reg, temp;
2815
2816
2817         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2818         reg = FDI_RX_CTL(pipe);
2819         temp = I915_READ(reg);
2820         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2822         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2823         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825         POSTING_READ(reg);
2826         udelay(200);
2827
2828         /* Switch from Rawclk to PCDclk */
2829         temp = I915_READ(reg);
2830         I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832         POSTING_READ(reg);
2833         udelay(200);
2834
2835         /* Enable CPU FDI TX PLL, always on for Ironlake */
2836         reg = FDI_TX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2840
2841                 POSTING_READ(reg);
2842                 udelay(100);
2843         }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848         struct drm_device *dev = intel_crtc->base.dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* Switch from PCDclk to Rawclk */
2854         reg = FDI_RX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858         /* Disable CPU FDI TX PLL */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870         /* Wait for the clocks to turn off. */
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880         int pipe = intel_crtc->pipe;
2881         u32 reg, temp;
2882
2883         /* disable CPU FDI tx and PCH FDI rx */
2884         reg = FDI_TX_CTL(pipe);
2885         temp = I915_READ(reg);
2886         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887         POSTING_READ(reg);
2888
2889         reg = FDI_RX_CTL(pipe);
2890         temp = I915_READ(reg);
2891         temp &= ~(0x7 << 16);
2892         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2893         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895         POSTING_READ(reg);
2896         udelay(100);
2897
2898         /* Ironlake workaround, disable clock pointer after downing FDI */
2899         if (HAS_PCH_IBX(dev)) {
2900                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2901         }
2902
2903         /* still set train pattern 1 */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_LINK_TRAIN_NONE;
2907         temp |= FDI_LINK_TRAIN_PATTERN_1;
2908         I915_WRITE(reg, temp);
2909
2910         reg = FDI_RX_CTL(pipe);
2911         temp = I915_READ(reg);
2912         if (HAS_PCH_CPT(dev)) {
2913                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915         } else {
2916                 temp &= ~FDI_LINK_TRAIN_NONE;
2917                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918         }
2919         /* BPC in FDI rx is consistent with that in PIPECONF */
2920         temp &= ~(0x07 << 16);
2921         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2922         I915_WRITE(reg, temp);
2923
2924         POSTING_READ(reg);
2925         udelay(100);
2926 }
2927
2928 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929 {
2930         struct drm_device *dev = crtc->dev;
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2933         unsigned long flags;
2934         bool pending;
2935
2936         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2938                 return false;
2939
2940         spin_lock_irqsave(&dev->event_lock, flags);
2941         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942         spin_unlock_irqrestore(&dev->event_lock, flags);
2943
2944         return pending;
2945 }
2946
2947 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2948 {
2949         struct drm_device *dev = crtc->dev;
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951
2952         if (crtc->fb == NULL)
2953                 return;
2954
2955         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2956
2957         wait_event(dev_priv->pending_flip_queue,
2958                    !intel_crtc_has_pending_flip(crtc));
2959
2960         mutex_lock(&dev->struct_mutex);
2961         intel_finish_fb(crtc->fb);
2962         mutex_unlock(&dev->struct_mutex);
2963 }
2964
2965 /* Program iCLKIP clock to the desired frequency */
2966 static void lpt_program_iclkip(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2971         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2972         u32 temp;
2973
2974         mutex_lock(&dev_priv->dpio_lock);
2975
2976         /* It is necessary to ungate the pixclk gate prior to programming
2977          * the divisors, and gate it back when it is done.
2978          */
2979         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2980
2981         /* Disable SSCCTL */
2982         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2983                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984                                 SBI_SSCCTL_DISABLE,
2985                         SBI_ICLK);
2986
2987         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2988         if (clock == 20000) {
2989                 auxdiv = 1;
2990                 divsel = 0x41;
2991                 phaseinc = 0x20;
2992         } else {
2993                 /* The iCLK virtual clock root frequency is in MHz,
2994                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2995                  * divisors, it is necessary to divide one by another, so we
2996                  * convert the virtual clock precision to KHz here for higher
2997                  * precision.
2998                  */
2999                 u32 iclk_virtual_root_freq = 172800 * 1000;
3000                 u32 iclk_pi_range = 64;
3001                 u32 desired_divisor, msb_divisor_value, pi_value;
3002
3003                 desired_divisor = (iclk_virtual_root_freq / clock);
3004                 msb_divisor_value = desired_divisor / iclk_pi_range;
3005                 pi_value = desired_divisor % iclk_pi_range;
3006
3007                 auxdiv = 0;
3008                 divsel = msb_divisor_value - 2;
3009                 phaseinc = pi_value;
3010         }
3011
3012         /* This should not happen with any sane values */
3013         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3017
3018         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3019                         clock,
3020                         auxdiv,
3021                         divsel,
3022                         phasedir,
3023                         phaseinc);
3024
3025         /* Program SSCDIVINTPHASE6 */
3026         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3027         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3033         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3034
3035         /* Program SSCAUXDIV */
3036         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3037         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3039         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3040
3041         /* Enable modulator and associated divider */
3042         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3043         temp &= ~SBI_SSCCTL_DISABLE;
3044         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3045
3046         /* Wait for initialization time */
3047         udelay(24);
3048
3049         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3050
3051         mutex_unlock(&dev_priv->dpio_lock);
3052 }
3053
3054 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055                                                 enum pipe pch_transcoder)
3056 {
3057         struct drm_device *dev = crtc->base.dev;
3058         struct drm_i915_private *dev_priv = dev->dev_private;
3059         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3060
3061         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062                    I915_READ(HTOTAL(cpu_transcoder)));
3063         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064                    I915_READ(HBLANK(cpu_transcoder)));
3065         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066                    I915_READ(HSYNC(cpu_transcoder)));
3067
3068         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069                    I915_READ(VTOTAL(cpu_transcoder)));
3070         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071                    I915_READ(VBLANK(cpu_transcoder)));
3072         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073                    I915_READ(VSYNC(cpu_transcoder)));
3074         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076 }
3077
3078 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3079 {
3080         struct drm_i915_private *dev_priv = dev->dev_private;
3081         uint32_t temp;
3082
3083         temp = I915_READ(SOUTH_CHICKEN1);
3084         if (temp & FDI_BC_BIFURCATION_SELECT)
3085                 return;
3086
3087         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3089
3090         temp |= FDI_BC_BIFURCATION_SELECT;
3091         DRM_DEBUG_KMS("enabling fdi C rx\n");
3092         I915_WRITE(SOUTH_CHICKEN1, temp);
3093         POSTING_READ(SOUTH_CHICKEN1);
3094 }
3095
3096 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3097 {
3098         struct drm_device *dev = intel_crtc->base.dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101         switch (intel_crtc->pipe) {
3102         case PIPE_A:
3103                 break;
3104         case PIPE_B:
3105                 if (intel_crtc->config.fdi_lanes > 2)
3106                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3107                 else
3108                         cpt_enable_fdi_bc_bifurcation(dev);
3109
3110                 break;
3111         case PIPE_C:
3112                 cpt_enable_fdi_bc_bifurcation(dev);
3113
3114                 break;
3115         default:
3116                 BUG();
3117         }
3118 }
3119
3120 /*
3121  * Enable PCH resources required for PCH ports:
3122  *   - PCH PLLs
3123  *   - FDI training & RX/TX
3124  *   - update transcoder timings
3125  *   - DP transcoding bits
3126  *   - transcoder
3127  */
3128 static void ironlake_pch_enable(struct drm_crtc *crtc)
3129 {
3130         struct drm_device *dev = crtc->dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133         int pipe = intel_crtc->pipe;
3134         u32 reg, temp;
3135
3136         assert_pch_transcoder_disabled(dev_priv, pipe);
3137
3138         if (IS_IVYBRIDGE(dev))
3139                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3140
3141         /* Write the TU size bits before fdi link training, so that error
3142          * detection works. */
3143         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
3146         /* For PCH output, training FDI link */
3147         dev_priv->display.fdi_link_train(crtc);
3148
3149         /* We need to program the right clock selection before writing the pixel
3150          * mutliplier into the DPLL. */
3151         if (HAS_PCH_CPT(dev)) {
3152                 u32 sel;
3153
3154                 temp = I915_READ(PCH_DPLL_SEL);
3155                 temp |= TRANS_DPLL_ENABLE(pipe);
3156                 sel = TRANS_DPLLB_SEL(pipe);
3157                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3158                         temp |= sel;
3159                 else
3160                         temp &= ~sel;
3161                 I915_WRITE(PCH_DPLL_SEL, temp);
3162         }
3163
3164         /* XXX: pch pll's can be enabled any time before we enable the PCH
3165          * transcoder, and we actually should do this to not upset any PCH
3166          * transcoder that already use the clock when we share it.
3167          *
3168          * Note that enable_shared_dpll tries to do the right thing, but
3169          * get_shared_dpll unconditionally resets the pll - we need that to have
3170          * the right LVDS enable sequence. */
3171         ironlake_enable_shared_dpll(intel_crtc);
3172
3173         /* set transcoder timing, panel must allow it */
3174         assert_panel_unlocked(dev_priv, pipe);
3175         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3176
3177         intel_fdi_normal_train(crtc);
3178
3179         /* For PCH DP, enable TRANS_DP_CTL */
3180         if (HAS_PCH_CPT(dev) &&
3181             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3183                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3184                 reg = TRANS_DP_CTL(pipe);
3185                 temp = I915_READ(reg);
3186                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3187                           TRANS_DP_SYNC_MASK |
3188                           TRANS_DP_BPC_MASK);
3189                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190                          TRANS_DP_ENH_FRAMING);
3191                 temp |= bpc << 9; /* same format but at 11:9 */
3192
3193                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3194                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3195                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3196                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3197
3198                 switch (intel_trans_dp_port_sel(crtc)) {
3199                 case PCH_DP_B:
3200                         temp |= TRANS_DP_PORT_SEL_B;
3201                         break;
3202                 case PCH_DP_C:
3203                         temp |= TRANS_DP_PORT_SEL_C;
3204                         break;
3205                 case PCH_DP_D:
3206                         temp |= TRANS_DP_PORT_SEL_D;
3207                         break;
3208                 default:
3209                         BUG();
3210                 }
3211
3212                 I915_WRITE(reg, temp);
3213         }
3214
3215         ironlake_enable_pch_transcoder(dev_priv, pipe);
3216 }
3217
3218 static void lpt_pch_enable(struct drm_crtc *crtc)
3219 {
3220         struct drm_device *dev = crtc->dev;
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3224
3225         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3226
3227         lpt_program_iclkip(crtc);
3228
3229         /* Set transcoder timing. */
3230         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3231
3232         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3233 }
3234
3235 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3236 {
3237         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3238
3239         if (pll == NULL)
3240                 return;
3241
3242         if (pll->refcount == 0) {
3243                 WARN(1, "bad %s refcount\n", pll->name);
3244                 return;
3245         }
3246
3247         if (--pll->refcount == 0) {
3248                 WARN_ON(pll->on);
3249                 WARN_ON(pll->active);
3250         }
3251
3252         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3253 }
3254
3255 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3256 {
3257         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259         enum intel_dpll_id i;
3260
3261         if (pll) {
3262                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263                               crtc->base.base.id, pll->name);
3264                 intel_put_shared_dpll(crtc);
3265         }
3266
3267         if (HAS_PCH_IBX(dev_priv->dev)) {
3268                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3269                 i = (enum intel_dpll_id) crtc->pipe;
3270                 pll = &dev_priv->shared_dplls[i];
3271
3272                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273                               crtc->base.base.id, pll->name);
3274
3275                 goto found;
3276         }
3277
3278         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279                 pll = &dev_priv->shared_dplls[i];
3280
3281                 /* Only want to check enabled timings first */
3282                 if (pll->refcount == 0)
3283                         continue;
3284
3285                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286                            sizeof(pll->hw_state)) == 0) {
3287                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3288                                       crtc->base.base.id,
3289                                       pll->name, pll->refcount, pll->active);
3290
3291                         goto found;
3292                 }
3293         }
3294
3295         /* Ok no matching timings, maybe there's a free one? */
3296         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297                 pll = &dev_priv->shared_dplls[i];
3298                 if (pll->refcount == 0) {
3299                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300                                       crtc->base.base.id, pll->name);
3301                         goto found;
3302                 }
3303         }
3304
3305         return NULL;
3306
3307 found:
3308         crtc->config.shared_dpll = i;
3309         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310                          pipe_name(crtc->pipe));
3311
3312         if (pll->active == 0) {
3313                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314                        sizeof(pll->hw_state));
3315
3316                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3317                 WARN_ON(pll->on);
3318                 assert_shared_dpll_disabled(dev_priv, pll);
3319
3320                 pll->mode_set(dev_priv, pll);
3321         }
3322         pll->refcount++;
3323
3324         return pll;
3325 }
3326
3327 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 if (wait_for(I915_READ(dslreg) != temp, 5))
3337                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3338         }
3339 }
3340
3341 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->base.dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         int pipe = crtc->pipe;
3346
3347         if (crtc->config.pch_pfit.enabled) {
3348                 /* Force use of hard-coded filter coefficients
3349                  * as some pre-programmed values are broken,
3350                  * e.g. x201.
3351                  */
3352                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354                                                  PF_PIPE_SEL_IVB(pipe));
3355                 else
3356                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3359         }
3360 }
3361
3362 static void intel_enable_planes(struct drm_crtc *crtc)
3363 {
3364         struct drm_device *dev = crtc->dev;
3365         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366         struct intel_plane *intel_plane;
3367
3368         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369                 if (intel_plane->pipe == pipe)
3370                         intel_plane_restore(&intel_plane->base);
3371 }
3372
3373 static void intel_disable_planes(struct drm_crtc *crtc)
3374 {
3375         struct drm_device *dev = crtc->dev;
3376         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377         struct intel_plane *intel_plane;
3378
3379         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380                 if (intel_plane->pipe == pipe)
3381                         intel_plane_disable(&intel_plane->base);
3382 }
3383
3384 void hsw_enable_ips(struct intel_crtc *crtc)
3385 {
3386         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3387
3388         if (!crtc->config.ips_enabled)
3389                 return;
3390
3391         /* We can only enable IPS after we enable a plane and wait for a vblank.
3392          * We guarantee that the plane is enabled by calling intel_enable_ips
3393          * only after intel_enable_plane. And intel_enable_plane already waits
3394          * for a vblank, so all we need to do here is to enable the IPS bit. */
3395         assert_plane_enabled(dev_priv, crtc->plane);
3396         if (IS_BROADWELL(crtc->base.dev)) {
3397                 mutex_lock(&dev_priv->rps.hw_lock);
3398                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3399                 mutex_unlock(&dev_priv->rps.hw_lock);
3400                 /* Quoting Art Runyan: "its not safe to expect any particular
3401                  * value in IPS_CTL bit 31 after enabling IPS through the
3402                  * mailbox." Therefore we need to defer waiting on the state
3403                  * change.
3404                  * TODO: need to fix this for state checker
3405                  */
3406         } else {
3407                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3408                 /* The bit only becomes 1 in the next vblank, so this wait here
3409                  * is essentially intel_wait_for_vblank. If we don't have this
3410                  * and don't wait for vblanks until the end of crtc_enable, then
3411                  * the HW state readout code will complain that the expected
3412                  * IPS_CTL value is not the one we read. */
3413                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3414                         DRM_ERROR("Timed out waiting for IPS enable\n");
3415         }
3416 }
3417
3418 void hsw_disable_ips(struct intel_crtc *crtc)
3419 {
3420         struct drm_device *dev = crtc->base.dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423         if (!crtc->config.ips_enabled)
3424                 return;
3425
3426         assert_plane_enabled(dev_priv, crtc->plane);
3427         if (IS_BROADWELL(crtc->base.dev)) {
3428                 mutex_lock(&dev_priv->rps.hw_lock);
3429                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3430                 mutex_unlock(&dev_priv->rps.hw_lock);
3431         } else
3432                 I915_WRITE(IPS_CTL, 0);
3433         POSTING_READ(IPS_CTL);
3434
3435         /* We need to wait for a vblank before we can disable the plane. */
3436         intel_wait_for_vblank(dev, crtc->pipe);
3437 }
3438
3439 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3440 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3441 {
3442         struct drm_device *dev = crtc->dev;
3443         struct drm_i915_private *dev_priv = dev->dev_private;
3444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445         enum pipe pipe = intel_crtc->pipe;
3446         int palreg = PALETTE(pipe);
3447         int i;
3448         bool reenable_ips = false;
3449
3450         /* The clocks have to be on to load the palette. */
3451         if (!crtc->enabled || !intel_crtc->active)
3452                 return;
3453
3454         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3455                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3456                         assert_dsi_pll_enabled(dev_priv);
3457                 else
3458                         assert_pll_enabled(dev_priv, pipe);
3459         }
3460
3461         /* use legacy palette for Ironlake */
3462         if (HAS_PCH_SPLIT(dev))
3463                 palreg = LGC_PALETTE(pipe);
3464
3465         /* Workaround : Do not read or write the pipe palette/gamma data while
3466          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3467          */
3468         if (intel_crtc->config.ips_enabled &&
3469             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3470              GAMMA_MODE_MODE_SPLIT)) {
3471                 hsw_disable_ips(intel_crtc);
3472                 reenable_ips = true;
3473         }
3474
3475         for (i = 0; i < 256; i++) {
3476                 I915_WRITE(palreg + 4 * i,
3477                            (intel_crtc->lut_r[i] << 16) |
3478                            (intel_crtc->lut_g[i] << 8) |
3479                            intel_crtc->lut_b[i]);
3480         }
3481
3482         if (reenable_ips)
3483                 hsw_enable_ips(intel_crtc);
3484 }
3485
3486 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3487 {
3488         struct drm_device *dev = crtc->dev;
3489         struct drm_i915_private *dev_priv = dev->dev_private;
3490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491         struct intel_encoder *encoder;
3492         int pipe = intel_crtc->pipe;
3493         int plane = intel_crtc->plane;
3494
3495         WARN_ON(!crtc->enabled);
3496
3497         if (intel_crtc->active)
3498                 return;
3499
3500         intel_crtc->active = true;
3501
3502         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3503         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3504
3505         for_each_encoder_on_crtc(dev, crtc, encoder)
3506                 if (encoder->pre_enable)
3507                         encoder->pre_enable(encoder);
3508
3509         if (intel_crtc->config.has_pch_encoder) {
3510                 /* Note: FDI PLL enabling _must_ be done before we enable the
3511                  * cpu pipes, hence this is separate from all the other fdi/pch
3512                  * enabling. */
3513                 ironlake_fdi_pll_enable(intel_crtc);
3514         } else {
3515                 assert_fdi_tx_disabled(dev_priv, pipe);
3516                 assert_fdi_rx_disabled(dev_priv, pipe);
3517         }
3518
3519         ironlake_pfit_enable(intel_crtc);
3520
3521         /*
3522          * On ILK+ LUT must be loaded before the pipe is running but with
3523          * clocks enabled
3524          */
3525         intel_crtc_load_lut(crtc);
3526
3527         intel_update_watermarks(crtc);
3528         intel_enable_pipe(dev_priv, pipe,
3529                           intel_crtc->config.has_pch_encoder, false);
3530         intel_enable_primary_plane(dev_priv, plane, pipe);
3531         intel_enable_planes(crtc);
3532         intel_crtc_update_cursor(crtc, true);
3533
3534         if (intel_crtc->config.has_pch_encoder)
3535                 ironlake_pch_enable(crtc);
3536
3537         mutex_lock(&dev->struct_mutex);
3538         intel_update_fbc(dev);
3539         mutex_unlock(&dev->struct_mutex);
3540
3541         for_each_encoder_on_crtc(dev, crtc, encoder)
3542                 encoder->enable(encoder);
3543
3544         if (HAS_PCH_CPT(dev))
3545                 cpt_verify_modeset(dev, intel_crtc->pipe);
3546
3547         /*
3548          * There seems to be a race in PCH platform hw (at least on some
3549          * outputs) where an enabled pipe still completes any pageflip right
3550          * away (as if the pipe is off) instead of waiting for vblank. As soon
3551          * as the first vblank happend, everything works as expected. Hence just
3552          * wait for one vblank before returning to avoid strange things
3553          * happening.
3554          */
3555         intel_wait_for_vblank(dev, intel_crtc->pipe);
3556 }
3557
3558 /* IPS only exists on ULT machines and is tied to pipe A. */
3559 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3560 {
3561         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3562 }
3563
3564 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3565 {
3566         struct drm_device *dev = crtc->dev;
3567         struct drm_i915_private *dev_priv = dev->dev_private;
3568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569         int pipe = intel_crtc->pipe;
3570         int plane = intel_crtc->plane;
3571
3572         intel_enable_primary_plane(dev_priv, plane, pipe);
3573         intel_enable_planes(crtc);
3574         intel_crtc_update_cursor(crtc, true);
3575
3576         hsw_enable_ips(intel_crtc);
3577
3578         mutex_lock(&dev->struct_mutex);
3579         intel_update_fbc(dev);
3580         mutex_unlock(&dev->struct_mutex);
3581 }
3582
3583 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3584 {
3585         struct drm_device *dev = crtc->dev;
3586         struct drm_i915_private *dev_priv = dev->dev_private;
3587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588         int pipe = intel_crtc->pipe;
3589         int plane = intel_crtc->plane;
3590
3591         intel_crtc_wait_for_pending_flips(crtc);
3592         drm_vblank_off(dev, pipe);
3593
3594         /* FBC must be disabled before disabling the plane on HSW. */
3595         if (dev_priv->fbc.plane == plane)
3596                 intel_disable_fbc(dev);
3597
3598         hsw_disable_ips(intel_crtc);
3599
3600         intel_crtc_update_cursor(crtc, false);
3601         intel_disable_planes(crtc);
3602         intel_disable_primary_plane(dev_priv, plane, pipe);
3603 }
3604
3605 /*
3606  * This implements the workaround described in the "notes" section of the mode
3607  * set sequence documentation. When going from no pipes or single pipe to
3608  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3609  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3610  */
3611 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3612 {
3613         struct drm_device *dev = crtc->base.dev;
3614         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3615
3616         /* We want to get the other_active_crtc only if there's only 1 other
3617          * active crtc. */
3618         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3619                 if (!crtc_it->active || crtc_it == crtc)
3620                         continue;
3621
3622                 if (other_active_crtc)
3623                         return;
3624
3625                 other_active_crtc = crtc_it;
3626         }
3627         if (!other_active_crtc)
3628                 return;
3629
3630         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3631         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3632 }
3633
3634 static void haswell_crtc_enable(struct drm_crtc *crtc)
3635 {
3636         struct drm_device *dev = crtc->dev;
3637         struct drm_i915_private *dev_priv = dev->dev_private;
3638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639         struct intel_encoder *encoder;
3640         int pipe = intel_crtc->pipe;
3641
3642         WARN_ON(!crtc->enabled);
3643
3644         if (intel_crtc->active)
3645                 return;
3646
3647         intel_crtc->active = true;
3648
3649         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3650         if (intel_crtc->config.has_pch_encoder)
3651                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3652
3653         if (intel_crtc->config.has_pch_encoder)
3654                 dev_priv->display.fdi_link_train(crtc);
3655
3656         for_each_encoder_on_crtc(dev, crtc, encoder)
3657                 if (encoder->pre_enable)
3658                         encoder->pre_enable(encoder);
3659
3660         intel_ddi_enable_pipe_clock(intel_crtc);
3661
3662         ironlake_pfit_enable(intel_crtc);
3663
3664         /*
3665          * On ILK+ LUT must be loaded before the pipe is running but with
3666          * clocks enabled
3667          */
3668         intel_crtc_load_lut(crtc);
3669
3670         intel_ddi_set_pipe_settings(crtc);
3671         intel_ddi_enable_transcoder_func(crtc);
3672
3673         intel_update_watermarks(crtc);
3674         intel_enable_pipe(dev_priv, pipe,
3675                           intel_crtc->config.has_pch_encoder, false);
3676
3677         if (intel_crtc->config.has_pch_encoder)
3678                 lpt_pch_enable(crtc);
3679
3680         for_each_encoder_on_crtc(dev, crtc, encoder) {
3681                 encoder->enable(encoder);
3682                 intel_opregion_notify_encoder(encoder, true);
3683         }
3684
3685         /* If we change the relative order between pipe/planes enabling, we need
3686          * to change the workaround. */
3687         haswell_mode_set_planes_workaround(intel_crtc);
3688         haswell_crtc_enable_planes(crtc);
3689
3690         /*
3691          * There seems to be a race in PCH platform hw (at least on some
3692          * outputs) where an enabled pipe still completes any pageflip right
3693          * away (as if the pipe is off) instead of waiting for vblank. As soon
3694          * as the first vblank happend, everything works as expected. Hence just
3695          * wait for one vblank before returning to avoid strange things
3696          * happening.
3697          */
3698         intel_wait_for_vblank(dev, intel_crtc->pipe);
3699 }
3700
3701 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3702 {
3703         struct drm_device *dev = crtc->base.dev;
3704         struct drm_i915_private *dev_priv = dev->dev_private;
3705         int pipe = crtc->pipe;
3706
3707         /* To avoid upsetting the power well on haswell only disable the pfit if
3708          * it's in use. The hw state code will make sure we get this right. */
3709         if (crtc->config.pch_pfit.enabled) {
3710                 I915_WRITE(PF_CTL(pipe), 0);
3711                 I915_WRITE(PF_WIN_POS(pipe), 0);
3712                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3713         }
3714 }
3715
3716 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         struct intel_encoder *encoder;
3722         int pipe = intel_crtc->pipe;
3723         int plane = intel_crtc->plane;
3724         u32 reg, temp;
3725
3726
3727         if (!intel_crtc->active)
3728                 return;
3729
3730         for_each_encoder_on_crtc(dev, crtc, encoder)
3731                 encoder->disable(encoder);
3732
3733         intel_crtc_wait_for_pending_flips(crtc);
3734         drm_vblank_off(dev, pipe);
3735
3736         if (dev_priv->fbc.plane == plane)
3737                 intel_disable_fbc(dev);
3738
3739         intel_crtc_update_cursor(crtc, false);
3740         intel_disable_planes(crtc);
3741         intel_disable_primary_plane(dev_priv, plane, pipe);
3742
3743         if (intel_crtc->config.has_pch_encoder)
3744                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3745
3746         intel_disable_pipe(dev_priv, pipe);
3747
3748         ironlake_pfit_disable(intel_crtc);
3749
3750         for_each_encoder_on_crtc(dev, crtc, encoder)
3751                 if (encoder->post_disable)
3752                         encoder->post_disable(encoder);
3753
3754         if (intel_crtc->config.has_pch_encoder) {
3755                 ironlake_fdi_disable(crtc);
3756
3757                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3758                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3759
3760                 if (HAS_PCH_CPT(dev)) {
3761                         /* disable TRANS_DP_CTL */
3762                         reg = TRANS_DP_CTL(pipe);
3763                         temp = I915_READ(reg);
3764                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3765                                   TRANS_DP_PORT_SEL_MASK);
3766                         temp |= TRANS_DP_PORT_SEL_NONE;
3767                         I915_WRITE(reg, temp);
3768
3769                         /* disable DPLL_SEL */
3770                         temp = I915_READ(PCH_DPLL_SEL);
3771                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3772                         I915_WRITE(PCH_DPLL_SEL, temp);
3773                 }
3774
3775                 /* disable PCH DPLL */
3776                 intel_disable_shared_dpll(intel_crtc);
3777
3778                 ironlake_fdi_pll_disable(intel_crtc);
3779         }
3780
3781         intel_crtc->active = false;
3782         intel_update_watermarks(crtc);
3783
3784         mutex_lock(&dev->struct_mutex);
3785         intel_update_fbc(dev);
3786         mutex_unlock(&dev->struct_mutex);
3787 }
3788
3789 static void haswell_crtc_disable(struct drm_crtc *crtc)
3790 {
3791         struct drm_device *dev = crtc->dev;
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3794         struct intel_encoder *encoder;
3795         int pipe = intel_crtc->pipe;
3796         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3797
3798         if (!intel_crtc->active)
3799                 return;
3800
3801         haswell_crtc_disable_planes(crtc);
3802
3803         for_each_encoder_on_crtc(dev, crtc, encoder) {
3804                 intel_opregion_notify_encoder(encoder, false);
3805                 encoder->disable(encoder);
3806         }
3807
3808         if (intel_crtc->config.has_pch_encoder)
3809                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3810         intel_disable_pipe(dev_priv, pipe);
3811
3812         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3813
3814         ironlake_pfit_disable(intel_crtc);
3815
3816         intel_ddi_disable_pipe_clock(intel_crtc);
3817
3818         for_each_encoder_on_crtc(dev, crtc, encoder)
3819                 if (encoder->post_disable)
3820                         encoder->post_disable(encoder);
3821
3822         if (intel_crtc->config.has_pch_encoder) {
3823                 lpt_disable_pch_transcoder(dev_priv);
3824                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3825                 intel_ddi_fdi_disable(crtc);
3826         }
3827
3828         intel_crtc->active = false;
3829         intel_update_watermarks(crtc);
3830
3831         mutex_lock(&dev->struct_mutex);
3832         intel_update_fbc(dev);
3833         mutex_unlock(&dev->struct_mutex);
3834 }
3835
3836 static void ironlake_crtc_off(struct drm_crtc *crtc)
3837 {
3838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839         intel_put_shared_dpll(intel_crtc);
3840 }
3841
3842 static void haswell_crtc_off(struct drm_crtc *crtc)
3843 {
3844         intel_ddi_put_crtc_pll(crtc);
3845 }
3846
3847 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3848 {
3849         if (!enable && intel_crtc->overlay) {
3850                 struct drm_device *dev = intel_crtc->base.dev;
3851                 struct drm_i915_private *dev_priv = dev->dev_private;
3852
3853                 mutex_lock(&dev->struct_mutex);
3854                 dev_priv->mm.interruptible = false;
3855                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3856                 dev_priv->mm.interruptible = true;
3857                 mutex_unlock(&dev->struct_mutex);
3858         }
3859
3860         /* Let userspace switch the overlay on again. In most cases userspace
3861          * has to recompute where to put it anyway.
3862          */
3863 }
3864
3865 /**
3866  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3867  * cursor plane briefly if not already running after enabling the display
3868  * plane.
3869  * This workaround avoids occasional blank screens when self refresh is
3870  * enabled.
3871  */
3872 static void
3873 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3874 {
3875         u32 cntl = I915_READ(CURCNTR(pipe));
3876
3877         if ((cntl & CURSOR_MODE) == 0) {
3878                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3879
3880                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3881                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3882                 intel_wait_for_vblank(dev_priv->dev, pipe);
3883                 I915_WRITE(CURCNTR(pipe), cntl);
3884                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3885                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3886         }
3887 }
3888
3889 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3890 {
3891         struct drm_device *dev = crtc->base.dev;
3892         struct drm_i915_private *dev_priv = dev->dev_private;
3893         struct intel_crtc_config *pipe_config = &crtc->config;
3894
3895         if (!crtc->config.gmch_pfit.control)
3896                 return;
3897
3898         /*
3899          * The panel fitter should only be adjusted whilst the pipe is disabled,
3900          * according to register description and PRM.
3901          */
3902         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3903         assert_pipe_disabled(dev_priv, crtc->pipe);
3904
3905         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3906         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3907
3908         /* Border color in case we don't scale up to the full screen. Black by
3909          * default, change to something else for debugging. */
3910         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3911 }
3912
3913 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3914 {
3915         struct drm_device *dev = crtc->dev;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918         struct intel_encoder *encoder;
3919         int pipe = intel_crtc->pipe;
3920         int plane = intel_crtc->plane;
3921         bool is_dsi;
3922
3923         WARN_ON(!crtc->enabled);
3924
3925         if (intel_crtc->active)
3926                 return;
3927
3928         intel_crtc->active = true;
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->pre_pll_enable)
3932                         encoder->pre_pll_enable(encoder);
3933
3934         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3935
3936         if (!is_dsi)
3937                 vlv_enable_pll(intel_crtc);
3938
3939         for_each_encoder_on_crtc(dev, crtc, encoder)
3940                 if (encoder->pre_enable)
3941                         encoder->pre_enable(encoder);
3942
3943         i9xx_pfit_enable(intel_crtc);
3944
3945         intel_crtc_load_lut(crtc);
3946
3947         intel_update_watermarks(crtc);
3948         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3949         intel_enable_primary_plane(dev_priv, plane, pipe);
3950         intel_enable_planes(crtc);
3951         intel_crtc_update_cursor(crtc, true);
3952
3953         intel_update_fbc(dev);
3954
3955         for_each_encoder_on_crtc(dev, crtc, encoder)
3956                 encoder->enable(encoder);
3957 }
3958
3959 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3960 {
3961         struct drm_device *dev = crtc->dev;
3962         struct drm_i915_private *dev_priv = dev->dev_private;
3963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964         struct intel_encoder *encoder;
3965         int pipe = intel_crtc->pipe;
3966         int plane = intel_crtc->plane;
3967
3968         WARN_ON(!crtc->enabled);
3969
3970         if (intel_crtc->active)
3971                 return;
3972
3973         intel_crtc->active = true;
3974
3975         for_each_encoder_on_crtc(dev, crtc, encoder)
3976                 if (encoder->pre_enable)
3977                         encoder->pre_enable(encoder);
3978
3979         i9xx_enable_pll(intel_crtc);
3980
3981         i9xx_pfit_enable(intel_crtc);
3982
3983         intel_crtc_load_lut(crtc);
3984
3985         intel_update_watermarks(crtc);
3986         intel_enable_pipe(dev_priv, pipe, false, false);
3987         intel_enable_primary_plane(dev_priv, plane, pipe);
3988         intel_enable_planes(crtc);
3989         /* The fixup needs to happen before cursor is enabled */
3990         if (IS_G4X(dev))
3991                 g4x_fixup_plane(dev_priv, pipe);
3992         intel_crtc_update_cursor(crtc, true);
3993
3994         /* Give the overlay scaler a chance to enable if it's on this pipe */
3995         intel_crtc_dpms_overlay(intel_crtc, true);
3996
3997         intel_update_fbc(dev);
3998
3999         for_each_encoder_on_crtc(dev, crtc, encoder)
4000                 encoder->enable(encoder);
4001 }
4002
4003 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4004 {
4005         struct drm_device *dev = crtc->base.dev;
4006         struct drm_i915_private *dev_priv = dev->dev_private;
4007
4008         if (!crtc->config.gmch_pfit.control)
4009                 return;
4010
4011         assert_pipe_disabled(dev_priv, crtc->pipe);
4012
4013         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4014                          I915_READ(PFIT_CONTROL));
4015         I915_WRITE(PFIT_CONTROL, 0);
4016 }
4017
4018 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4019 {
4020         struct drm_device *dev = crtc->dev;
4021         struct drm_i915_private *dev_priv = dev->dev_private;
4022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4023         struct intel_encoder *encoder;
4024         int pipe = intel_crtc->pipe;
4025         int plane = intel_crtc->plane;
4026
4027         if (!intel_crtc->active)
4028                 return;
4029
4030         for_each_encoder_on_crtc(dev, crtc, encoder)
4031                 encoder->disable(encoder);
4032
4033         /* Give the overlay scaler a chance to disable if it's on this pipe */
4034         intel_crtc_wait_for_pending_flips(crtc);
4035         drm_vblank_off(dev, pipe);
4036
4037         if (dev_priv->fbc.plane == plane)
4038                 intel_disable_fbc(dev);
4039
4040         intel_crtc_dpms_overlay(intel_crtc, false);
4041         intel_crtc_update_cursor(crtc, false);
4042         intel_disable_planes(crtc);
4043         intel_disable_primary_plane(dev_priv, plane, pipe);
4044
4045         intel_disable_pipe(dev_priv, pipe);
4046
4047         i9xx_pfit_disable(intel_crtc);
4048
4049         for_each_encoder_on_crtc(dev, crtc, encoder)
4050                 if (encoder->post_disable)
4051                         encoder->post_disable(encoder);
4052
4053         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4054                 vlv_disable_pll(dev_priv, pipe);
4055         else if (!IS_VALLEYVIEW(dev))
4056                 i9xx_disable_pll(dev_priv, pipe);
4057
4058         intel_crtc->active = false;
4059         intel_update_watermarks(crtc);
4060
4061         intel_update_fbc(dev);
4062 }
4063
4064 static void i9xx_crtc_off(struct drm_crtc *crtc)
4065 {
4066 }
4067
4068 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4069                                     bool enabled)
4070 {
4071         struct drm_device *dev = crtc->dev;
4072         struct drm_i915_master_private *master_priv;
4073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074         int pipe = intel_crtc->pipe;
4075
4076         if (!dev->primary->master)
4077                 return;
4078
4079         master_priv = dev->primary->master->driver_priv;
4080         if (!master_priv->sarea_priv)
4081                 return;
4082
4083         switch (pipe) {
4084         case 0:
4085                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4086                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4087                 break;
4088         case 1:
4089                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4090                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4091                 break;
4092         default:
4093                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4094                 break;
4095         }
4096 }
4097
4098 /**
4099  * Sets the power management mode of the pipe and plane.
4100  */
4101 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4102 {
4103         struct drm_device *dev = crtc->dev;
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105         struct intel_encoder *intel_encoder;
4106         bool enable = false;
4107
4108         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4109                 enable |= intel_encoder->connectors_active;
4110
4111         if (enable)
4112                 dev_priv->display.crtc_enable(crtc);
4113         else
4114                 dev_priv->display.crtc_disable(crtc);
4115
4116         intel_crtc_update_sarea(crtc, enable);
4117 }
4118
4119 static void intel_crtc_disable(struct drm_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         struct drm_connector *connector;
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125
4126         /* crtc should still be enabled when we disable it. */
4127         WARN_ON(!crtc->enabled);
4128
4129         dev_priv->display.crtc_disable(crtc);
4130         intel_crtc->eld_vld = false;
4131         intel_crtc_update_sarea(crtc, false);
4132         dev_priv->display.off(crtc);
4133
4134         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4135         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4136         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4137
4138         if (crtc->fb) {
4139                 mutex_lock(&dev->struct_mutex);
4140                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4141                 mutex_unlock(&dev->struct_mutex);
4142                 crtc->fb = NULL;
4143         }
4144
4145         /* Update computed state. */
4146         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4147                 if (!connector->encoder || !connector->encoder->crtc)
4148                         continue;
4149
4150                 if (connector->encoder->crtc != crtc)
4151                         continue;
4152
4153                 connector->dpms = DRM_MODE_DPMS_OFF;
4154                 to_intel_encoder(connector->encoder)->connectors_active = false;
4155         }
4156 }
4157
4158 void intel_encoder_destroy(struct drm_encoder *encoder)
4159 {
4160         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4161
4162         drm_encoder_cleanup(encoder);
4163         kfree(intel_encoder);
4164 }
4165
4166 /* Simple dpms helper for encoders with just one connector, no cloning and only
4167  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4168  * state of the entire output pipe. */
4169 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4170 {
4171         if (mode == DRM_MODE_DPMS_ON) {
4172                 encoder->connectors_active = true;
4173
4174                 intel_crtc_update_dpms(encoder->base.crtc);
4175         } else {
4176                 encoder->connectors_active = false;
4177
4178                 intel_crtc_update_dpms(encoder->base.crtc);
4179         }
4180 }
4181
4182 /* Cross check the actual hw state with our own modeset state tracking (and it's
4183  * internal consistency). */
4184 static void intel_connector_check_state(struct intel_connector *connector)
4185 {
4186         if (connector->get_hw_state(connector)) {
4187                 struct intel_encoder *encoder = connector->encoder;
4188                 struct drm_crtc *crtc;
4189                 bool encoder_enabled;
4190                 enum pipe pipe;
4191
4192                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4193                               connector->base.base.id,
4194                               drm_get_connector_name(&connector->base));
4195
4196                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4197                      "wrong connector dpms state\n");
4198                 WARN(connector->base.encoder != &encoder->base,
4199                      "active connector not linked to encoder\n");
4200                 WARN(!encoder->connectors_active,
4201                      "encoder->connectors_active not set\n");
4202
4203                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4204                 WARN(!encoder_enabled, "encoder not enabled\n");
4205                 if (WARN_ON(!encoder->base.crtc))
4206                         return;
4207
4208                 crtc = encoder->base.crtc;
4209
4210                 WARN(!crtc->enabled, "crtc not enabled\n");
4211                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4212                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4213                      "encoder active on the wrong pipe\n");
4214         }
4215 }
4216
4217 /* Even simpler default implementation, if there's really no special case to
4218  * consider. */
4219 void intel_connector_dpms(struct drm_connector *connector, int mode)
4220 {
4221         /* All the simple cases only support two dpms states. */
4222         if (mode != DRM_MODE_DPMS_ON)
4223                 mode = DRM_MODE_DPMS_OFF;
4224
4225         if (mode == connector->dpms)
4226                 return;
4227
4228         connector->dpms = mode;
4229
4230         /* Only need to change hw state when actually enabled */
4231         if (connector->encoder)
4232                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4233
4234         intel_modeset_check_state(connector->dev);
4235 }
4236
4237 /* Simple connector->get_hw_state implementation for encoders that support only
4238  * one connector and no cloning and hence the encoder state determines the state
4239  * of the connector. */
4240 bool intel_connector_get_hw_state(struct intel_connector *connector)
4241 {
4242         enum pipe pipe = 0;
4243         struct intel_encoder *encoder = connector->encoder;
4244
4245         return encoder->get_hw_state(encoder, &pipe);
4246 }
4247
4248 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4249                                      struct intel_crtc_config *pipe_config)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         struct intel_crtc *pipe_B_crtc =
4253                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4254
4255         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4256                       pipe_name(pipe), pipe_config->fdi_lanes);
4257         if (pipe_config->fdi_lanes > 4) {
4258                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4259                               pipe_name(pipe), pipe_config->fdi_lanes);
4260                 return false;
4261         }
4262
4263         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4264                 if (pipe_config->fdi_lanes > 2) {
4265                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4266                                       pipe_config->fdi_lanes);
4267                         return false;
4268                 } else {
4269                         return true;
4270                 }
4271         }
4272
4273         if (INTEL_INFO(dev)->num_pipes == 2)
4274                 return true;
4275
4276         /* Ivybridge 3 pipe is really complicated */
4277         switch (pipe) {
4278         case PIPE_A:
4279                 return true;
4280         case PIPE_B:
4281                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4282                     pipe_config->fdi_lanes > 2) {
4283                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4284                                       pipe_name(pipe), pipe_config->fdi_lanes);
4285                         return false;
4286                 }
4287                 return true;
4288         case PIPE_C:
4289                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4290                     pipe_B_crtc->config.fdi_lanes <= 2) {
4291                         if (pipe_config->fdi_lanes > 2) {
4292                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4293                                               pipe_name(pipe), pipe_config->fdi_lanes);
4294                                 return false;
4295                         }
4296                 } else {
4297                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4298                         return false;
4299                 }
4300                 return true;
4301         default:
4302                 BUG();
4303         }
4304 }
4305
4306 #define RETRY 1
4307 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4308                                        struct intel_crtc_config *pipe_config)
4309 {
4310         struct drm_device *dev = intel_crtc->base.dev;
4311         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4312         int lane, link_bw, fdi_dotclock;
4313         bool setup_ok, needs_recompute = false;
4314
4315 retry:
4316         /* FDI is a binary signal running at ~2.7GHz, encoding
4317          * each output octet as 10 bits. The actual frequency
4318          * is stored as a divider into a 100MHz clock, and the
4319          * mode pixel clock is stored in units of 1KHz.
4320          * Hence the bw of each lane in terms of the mode signal
4321          * is:
4322          */
4323         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4324
4325         fdi_dotclock = adjusted_mode->crtc_clock;
4326
4327         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4328                                            pipe_config->pipe_bpp);
4329
4330         pipe_config->fdi_lanes = lane;
4331
4332         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4333                                link_bw, &pipe_config->fdi_m_n);
4334
4335         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4336                                             intel_crtc->pipe, pipe_config);
4337         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4338                 pipe_config->pipe_bpp -= 2*3;
4339                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4340                               pipe_config->pipe_bpp);
4341                 needs_recompute = true;
4342                 pipe_config->bw_constrained = true;
4343
4344                 goto retry;
4345         }
4346
4347         if (needs_recompute)
4348                 return RETRY;
4349
4350         return setup_ok ? 0 : -EINVAL;
4351 }
4352
4353 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4354                                    struct intel_crtc_config *pipe_config)
4355 {
4356         pipe_config->ips_enabled = i915_enable_ips &&
4357                                    hsw_crtc_supports_ips(crtc) &&
4358                                    pipe_config->pipe_bpp <= 24;
4359 }
4360
4361 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4362                                      struct intel_crtc_config *pipe_config)
4363 {
4364         struct drm_device *dev = crtc->base.dev;
4365         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4366
4367         /* FIXME should check pixel clock limits on all platforms */
4368         if (INTEL_INFO(dev)->gen < 4) {
4369                 struct drm_i915_private *dev_priv = dev->dev_private;
4370                 int clock_limit =
4371                         dev_priv->display.get_display_clock_speed(dev);
4372
4373                 /*
4374                  * Enable pixel doubling when the dot clock
4375                  * is > 90% of the (display) core speed.
4376                  *
4377                  * GDG double wide on either pipe,
4378                  * otherwise pipe A only.
4379                  */
4380                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4381                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4382                         clock_limit *= 2;
4383                         pipe_config->double_wide = true;
4384                 }
4385
4386                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4387                         return -EINVAL;
4388         }
4389
4390         /*
4391          * Pipe horizontal size must be even in:
4392          * - DVO ganged mode
4393          * - LVDS dual channel mode
4394          * - Double wide pipe
4395          */
4396         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4397              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4398                 pipe_config->pipe_src_w &= ~1;
4399
4400         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4401          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4402          */
4403         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4404                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4405                 return -EINVAL;
4406
4407         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4408                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4409         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4410                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4411                  * for lvds. */
4412                 pipe_config->pipe_bpp = 8*3;
4413         }
4414
4415         if (HAS_IPS(dev))
4416                 hsw_compute_ips_config(crtc, pipe_config);
4417
4418         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4419          * clock survives for now. */
4420         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4421                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4422
4423         if (pipe_config->has_pch_encoder)
4424                 return ironlake_fdi_compute_config(crtc, pipe_config);
4425
4426         return 0;
4427 }
4428
4429 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4430 {
4431         return 400000; /* FIXME */
4432 }
4433
4434 static int i945_get_display_clock_speed(struct drm_device *dev)
4435 {
4436         return 400000;
4437 }
4438
4439 static int i915_get_display_clock_speed(struct drm_device *dev)
4440 {
4441         return 333000;
4442 }
4443
4444 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4445 {
4446         return 200000;
4447 }
4448
4449 static int pnv_get_display_clock_speed(struct drm_device *dev)
4450 {
4451         u16 gcfgc = 0;
4452
4453         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4454
4455         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4456         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4457                 return 267000;
4458         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4459                 return 333000;
4460         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4461                 return 444000;
4462         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4463                 return 200000;
4464         default:
4465                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4466         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4467                 return 133000;
4468         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4469                 return 167000;
4470         }
4471 }
4472
4473 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4474 {
4475         u16 gcfgc = 0;
4476
4477         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4478
4479         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4480                 return 133000;
4481         else {
4482                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4483                 case GC_DISPLAY_CLOCK_333_MHZ:
4484                         return 333000;
4485                 default:
4486                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4487                         return 190000;
4488                 }
4489         }
4490 }
4491
4492 static int i865_get_display_clock_speed(struct drm_device *dev)
4493 {
4494         return 266000;
4495 }
4496
4497 static int i855_get_display_clock_speed(struct drm_device *dev)
4498 {
4499         u16 hpllcc = 0;
4500         /* Assume that the hardware is in the high speed state.  This
4501          * should be the default.
4502          */
4503         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4504         case GC_CLOCK_133_200:
4505         case GC_CLOCK_100_200:
4506                 return 200000;
4507         case GC_CLOCK_166_250:
4508                 return 250000;
4509         case GC_CLOCK_100_133:
4510                 return 133000;
4511         }
4512
4513         /* Shouldn't happen */
4514         return 0;
4515 }
4516
4517 static int i830_get_display_clock_speed(struct drm_device *dev)
4518 {
4519         return 133000;
4520 }
4521
4522 static void
4523 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4524 {
4525         while (*num > DATA_LINK_M_N_MASK ||
4526                *den > DATA_LINK_M_N_MASK) {
4527                 *num >>= 1;
4528                 *den >>= 1;
4529         }
4530 }
4531
4532 static void compute_m_n(unsigned int m, unsigned int n,
4533                         uint32_t *ret_m, uint32_t *ret_n)
4534 {
4535         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4536         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4537         intel_reduce_m_n_ratio(ret_m, ret_n);
4538 }
4539
4540 void
4541 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4542                        int pixel_clock, int link_clock,
4543                        struct intel_link_m_n *m_n)
4544 {
4545         m_n->tu = 64;
4546
4547         compute_m_n(bits_per_pixel * pixel_clock,
4548                     link_clock * nlanes * 8,
4549                     &m_n->gmch_m, &m_n->gmch_n);
4550
4551         compute_m_n(pixel_clock, link_clock,
4552                     &m_n->link_m, &m_n->link_n);
4553 }
4554
4555 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4556 {
4557         if (i915_panel_use_ssc >= 0)
4558                 return i915_panel_use_ssc != 0;
4559         return dev_priv->vbt.lvds_use_ssc
4560                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4561 }
4562
4563 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4564 {
4565         struct drm_device *dev = crtc->dev;
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567         int refclk;
4568
4569         if (IS_VALLEYVIEW(dev)) {
4570                 refclk = 100000;
4571         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4572             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4573                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4574                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4575                               refclk / 1000);
4576         } else if (!IS_GEN2(dev)) {
4577                 refclk = 96000;
4578         } else {
4579                 refclk = 48000;
4580         }
4581
4582         return refclk;
4583 }
4584
4585 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4586 {
4587         return (1 << dpll->n) << 16 | dpll->m2;
4588 }
4589
4590 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4591 {
4592         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4593 }
4594
4595 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4596                                      intel_clock_t *reduced_clock)
4597 {
4598         struct drm_device *dev = crtc->base.dev;
4599         struct drm_i915_private *dev_priv = dev->dev_private;
4600         int pipe = crtc->pipe;
4601         u32 fp, fp2 = 0;
4602
4603         if (IS_PINEVIEW(dev)) {
4604                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4605                 if (reduced_clock)
4606                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4607         } else {
4608                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4609                 if (reduced_clock)
4610                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4611         }
4612
4613         I915_WRITE(FP0(pipe), fp);
4614         crtc->config.dpll_hw_state.fp0 = fp;
4615
4616         crtc->lowfreq_avail = false;
4617         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4618             reduced_clock && i915_powersave) {
4619                 I915_WRITE(FP1(pipe), fp2);
4620                 crtc->config.dpll_hw_state.fp1 = fp2;
4621                 crtc->lowfreq_avail = true;
4622         } else {
4623                 I915_WRITE(FP1(pipe), fp);
4624                 crtc->config.dpll_hw_state.fp1 = fp;
4625         }
4626 }
4627
4628 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4629                 pipe)
4630 {
4631         u32 reg_val;
4632
4633         /*
4634          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4635          * and set it to a reasonable value instead.
4636          */
4637         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4638         reg_val &= 0xffffff00;
4639         reg_val |= 0x00000030;
4640         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4641
4642         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4643         reg_val &= 0x8cffffff;
4644         reg_val = 0x8c000000;
4645         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4646
4647         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4648         reg_val &= 0xffffff00;
4649         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4650
4651         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4652         reg_val &= 0x00ffffff;
4653         reg_val |= 0xb0000000;
4654         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4655 }
4656
4657 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4658                                          struct intel_link_m_n *m_n)
4659 {
4660         struct drm_device *dev = crtc->base.dev;
4661         struct drm_i915_private *dev_priv = dev->dev_private;
4662         int pipe = crtc->pipe;
4663
4664         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4665         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4666         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4667         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4668 }
4669
4670 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4671                                          struct intel_link_m_n *m_n)
4672 {
4673         struct drm_device *dev = crtc->base.dev;
4674         struct drm_i915_private *dev_priv = dev->dev_private;
4675         int pipe = crtc->pipe;
4676         enum transcoder transcoder = crtc->config.cpu_transcoder;
4677
4678         if (INTEL_INFO(dev)->gen >= 5) {
4679                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4680                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4681                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4682                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4683         } else {
4684                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4685                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4686                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4687                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4688         }
4689 }
4690
4691 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4692 {
4693         if (crtc->config.has_pch_encoder)
4694                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4695         else
4696                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4697 }
4698
4699 static void vlv_update_pll(struct intel_crtc *crtc)
4700 {
4701         struct drm_device *dev = crtc->base.dev;
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         int pipe = crtc->pipe;
4704         u32 dpll, mdiv;
4705         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4706         u32 coreclk, reg_val, dpll_md;
4707
4708         mutex_lock(&dev_priv->dpio_lock);
4709
4710         bestn = crtc->config.dpll.n;
4711         bestm1 = crtc->config.dpll.m1;
4712         bestm2 = crtc->config.dpll.m2;
4713         bestp1 = crtc->config.dpll.p1;
4714         bestp2 = crtc->config.dpll.p2;
4715
4716         /* See eDP HDMI DPIO driver vbios notes doc */
4717
4718         /* PLL B needs special handling */
4719         if (pipe)
4720                 vlv_pllb_recal_opamp(dev_priv, pipe);
4721
4722         /* Set up Tx target for periodic Rcomp update */
4723         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4724
4725         /* Disable target IRef on PLL */
4726         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4727         reg_val &= 0x00ffffff;
4728         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4729
4730         /* Disable fast lock */
4731         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4732
4733         /* Set idtafcrecal before PLL is enabled */
4734         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4735         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4736         mdiv |= ((bestn << DPIO_N_SHIFT));
4737         mdiv |= (1 << DPIO_K_SHIFT);
4738
4739         /*
4740          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4741          * but we don't support that).
4742          * Note: don't use the DAC post divider as it seems unstable.
4743          */
4744         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4745         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4746
4747         mdiv |= DPIO_ENABLE_CALIBRATION;
4748         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4749
4750         /* Set HBR and RBR LPF coefficients */
4751         if (crtc->config.port_clock == 162000 ||
4752             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4753             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4754                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4755                                  0x009f0003);
4756         else
4757                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4758                                  0x00d0000f);
4759
4760         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4761             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4762                 /* Use SSC source */
4763                 if (!pipe)
4764                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4765                                          0x0df40000);
4766                 else
4767                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4768                                          0x0df70000);
4769         } else { /* HDMI or VGA */
4770                 /* Use bend source */
4771                 if (!pipe)
4772                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4773                                          0x0df70000);
4774                 else
4775                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4776                                          0x0df40000);
4777         }
4778
4779         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4780         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4781         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4782             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4783                 coreclk |= 0x01000000;
4784         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4785
4786         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4787
4788         /* Enable DPIO clock input */
4789         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4790                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4791         /* We should never disable this, set it here for state tracking */
4792         if (pipe == PIPE_B)
4793                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4794         dpll |= DPLL_VCO_ENABLE;
4795         crtc->config.dpll_hw_state.dpll = dpll;
4796
4797         dpll_md = (crtc->config.pixel_multiplier - 1)
4798                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4799         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4800
4801         if (crtc->config.has_dp_encoder)
4802                 intel_dp_set_m_n(crtc);
4803
4804         mutex_unlock(&dev_priv->dpio_lock);
4805 }
4806
4807 static void i9xx_update_pll(struct intel_crtc *crtc,
4808                             intel_clock_t *reduced_clock,
4809                             int num_connectors)
4810 {
4811         struct drm_device *dev = crtc->base.dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         u32 dpll;
4814         bool is_sdvo;
4815         struct dpll *clock = &crtc->config.dpll;
4816
4817         i9xx_update_pll_dividers(crtc, reduced_clock);
4818
4819         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4820                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4821
4822         dpll = DPLL_VGA_MODE_DIS;
4823
4824         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4825                 dpll |= DPLLB_MODE_LVDS;
4826         else
4827                 dpll |= DPLLB_MODE_DAC_SERIAL;
4828
4829         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4830                 dpll |= (crtc->config.pixel_multiplier - 1)
4831                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4832         }
4833
4834         if (is_sdvo)
4835                 dpll |= DPLL_SDVO_HIGH_SPEED;
4836
4837         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4838                 dpll |= DPLL_SDVO_HIGH_SPEED;
4839
4840         /* compute bitmask from p1 value */
4841         if (IS_PINEVIEW(dev))
4842                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4843         else {
4844                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4845                 if (IS_G4X(dev) && reduced_clock)
4846                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4847         }
4848         switch (clock->p2) {
4849         case 5:
4850                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4851                 break;
4852         case 7:
4853                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4854                 break;
4855         case 10:
4856                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4857                 break;
4858         case 14:
4859                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4860                 break;
4861         }
4862         if (INTEL_INFO(dev)->gen >= 4)
4863                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4864
4865         if (crtc->config.sdvo_tv_clock)
4866                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4867         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4868                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4869                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4870         else
4871                 dpll |= PLL_REF_INPUT_DREFCLK;
4872
4873         dpll |= DPLL_VCO_ENABLE;
4874         crtc->config.dpll_hw_state.dpll = dpll;
4875
4876         if (INTEL_INFO(dev)->gen >= 4) {
4877                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4878                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4879                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4880         }
4881
4882         if (crtc->config.has_dp_encoder)
4883                 intel_dp_set_m_n(crtc);
4884 }
4885
4886 static void i8xx_update_pll(struct intel_crtc *crtc,
4887                             intel_clock_t *reduced_clock,
4888                             int num_connectors)
4889 {
4890         struct drm_device *dev = crtc->base.dev;
4891         struct drm_i915_private *dev_priv = dev->dev_private;
4892         u32 dpll;
4893         struct dpll *clock = &crtc->config.dpll;
4894
4895         i9xx_update_pll_dividers(crtc, reduced_clock);
4896
4897         dpll = DPLL_VGA_MODE_DIS;
4898
4899         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4900                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4901         } else {
4902                 if (clock->p1 == 2)
4903                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4904                 else
4905                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4906                 if (clock->p2 == 4)
4907                         dpll |= PLL_P2_DIVIDE_BY_4;
4908         }
4909
4910         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4911                 dpll |= DPLL_DVO_2X_MODE;
4912
4913         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4914                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4915                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4916         else
4917                 dpll |= PLL_REF_INPUT_DREFCLK;
4918
4919         dpll |= DPLL_VCO_ENABLE;
4920         crtc->config.dpll_hw_state.dpll = dpll;
4921 }
4922
4923 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4924 {
4925         struct drm_device *dev = intel_crtc->base.dev;
4926         struct drm_i915_private *dev_priv = dev->dev_private;
4927         enum pipe pipe = intel_crtc->pipe;
4928         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4929         struct drm_display_mode *adjusted_mode =
4930                 &intel_crtc->config.adjusted_mode;
4931         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4932
4933         /* We need to be careful not to changed the adjusted mode, for otherwise
4934          * the hw state checker will get angry at the mismatch. */
4935         crtc_vtotal = adjusted_mode->crtc_vtotal;
4936         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4937
4938         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4939                 /* the chip adds 2 halflines automatically */
4940                 crtc_vtotal -= 1;
4941                 crtc_vblank_end -= 1;
4942                 vsyncshift = adjusted_mode->crtc_hsync_start
4943                              - adjusted_mode->crtc_htotal / 2;
4944         } else {
4945                 vsyncshift = 0;
4946         }
4947
4948         if (INTEL_INFO(dev)->gen > 3)
4949                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4950
4951         I915_WRITE(HTOTAL(cpu_transcoder),
4952                    (adjusted_mode->crtc_hdisplay - 1) |
4953                    ((adjusted_mode->crtc_htotal - 1) << 16));
4954         I915_WRITE(HBLANK(cpu_transcoder),
4955                    (adjusted_mode->crtc_hblank_start - 1) |
4956                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4957         I915_WRITE(HSYNC(cpu_transcoder),
4958                    (adjusted_mode->crtc_hsync_start - 1) |
4959                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4960
4961         I915_WRITE(VTOTAL(cpu_transcoder),
4962                    (adjusted_mode->crtc_vdisplay - 1) |
4963                    ((crtc_vtotal - 1) << 16));
4964         I915_WRITE(VBLANK(cpu_transcoder),
4965                    (adjusted_mode->crtc_vblank_start - 1) |
4966                    ((crtc_vblank_end - 1) << 16));
4967         I915_WRITE(VSYNC(cpu_transcoder),
4968                    (adjusted_mode->crtc_vsync_start - 1) |
4969                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4970
4971         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4972          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4973          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4974          * bits. */
4975         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4976             (pipe == PIPE_B || pipe == PIPE_C))
4977                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4978
4979         /* pipesrc controls the size that is scaled from, which should
4980          * always be the user's requested size.
4981          */
4982         I915_WRITE(PIPESRC(pipe),
4983                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4984                    (intel_crtc->config.pipe_src_h - 1));
4985 }
4986
4987 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4988                                    struct intel_crtc_config *pipe_config)
4989 {
4990         struct drm_device *dev = crtc->base.dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4993         uint32_t tmp;
4994
4995         tmp = I915_READ(HTOTAL(cpu_transcoder));
4996         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4997         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4998         tmp = I915_READ(HBLANK(cpu_transcoder));
4999         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5000         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5001         tmp = I915_READ(HSYNC(cpu_transcoder));
5002         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5003         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5004
5005         tmp = I915_READ(VTOTAL(cpu_transcoder));
5006         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5007         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5008         tmp = I915_READ(VBLANK(cpu_transcoder));
5009         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5010         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5011         tmp = I915_READ(VSYNC(cpu_transcoder));
5012         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5013         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5014
5015         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5016                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5017                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5018                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5019         }
5020
5021         tmp = I915_READ(PIPESRC(crtc->pipe));
5022         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5023         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5024
5025         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5026         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5027 }
5028
5029 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5030                                              struct intel_crtc_config *pipe_config)
5031 {
5032         struct drm_crtc *crtc = &intel_crtc->base;
5033
5034         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5035         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5036         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5037         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5038
5039         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5040         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5041         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5042         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5043
5044         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5045
5046         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5047         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5048 }
5049
5050 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5051 {
5052         struct drm_device *dev = intel_crtc->base.dev;
5053         struct drm_i915_private *dev_priv = dev->dev_private;
5054         uint32_t pipeconf;
5055
5056         pipeconf = 0;
5057
5058         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5059             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5060                 pipeconf |= PIPECONF_ENABLE;
5061
5062         if (intel_crtc->config.double_wide)
5063                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5064
5065         /* only g4x and later have fancy bpc/dither controls */
5066         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5067                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5068                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5069                         pipeconf |= PIPECONF_DITHER_EN |
5070                                     PIPECONF_DITHER_TYPE_SP;
5071
5072                 switch (intel_crtc->config.pipe_bpp) {
5073                 case 18:
5074                         pipeconf |= PIPECONF_6BPC;
5075                         break;
5076                 case 24:
5077                         pipeconf |= PIPECONF_8BPC;
5078                         break;
5079                 case 30:
5080                         pipeconf |= PIPECONF_10BPC;
5081                         break;
5082                 default:
5083                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5084                         BUG();
5085                 }
5086         }
5087
5088         if (HAS_PIPE_CXSR(dev)) {
5089                 if (intel_crtc->lowfreq_avail) {
5090                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5091                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5092                 } else {
5093                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5094                 }
5095         }
5096
5097         if (!IS_GEN2(dev) &&
5098             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5099                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5100         else
5101                 pipeconf |= PIPECONF_PROGRESSIVE;
5102
5103         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5104                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5105
5106         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5107         POSTING_READ(PIPECONF(intel_crtc->pipe));
5108 }
5109
5110 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5111                               int x, int y,
5112                               struct drm_framebuffer *fb)
5113 {
5114         struct drm_device *dev = crtc->dev;
5115         struct drm_i915_private *dev_priv = dev->dev_private;
5116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117         int pipe = intel_crtc->pipe;
5118         int plane = intel_crtc->plane;
5119         int refclk, num_connectors = 0;
5120         intel_clock_t clock, reduced_clock;
5121         u32 dspcntr;
5122         bool ok, has_reduced_clock = false;
5123         bool is_lvds = false, is_dsi = false;
5124         struct intel_encoder *encoder;
5125         const intel_limit_t *limit;
5126         int ret;
5127
5128         for_each_encoder_on_crtc(dev, crtc, encoder) {
5129                 switch (encoder->type) {
5130                 case INTEL_OUTPUT_LVDS:
5131                         is_lvds = true;
5132                         break;
5133                 case INTEL_OUTPUT_DSI:
5134                         is_dsi = true;
5135                         break;
5136                 }
5137
5138                 num_connectors++;
5139         }
5140
5141         if (is_dsi)
5142                 goto skip_dpll;
5143
5144         if (!intel_crtc->config.clock_set) {
5145                 refclk = i9xx_get_refclk(crtc, num_connectors);
5146
5147                 /*
5148                  * Returns a set of divisors for the desired target clock with
5149                  * the given refclk, or FALSE.  The returned values represent
5150                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5151                  * 2) / p1 / p2.
5152                  */
5153                 limit = intel_limit(crtc, refclk);
5154                 ok = dev_priv->display.find_dpll(limit, crtc,
5155                                                  intel_crtc->config.port_clock,
5156                                                  refclk, NULL, &clock);
5157                 if (!ok) {
5158                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5159                         return -EINVAL;
5160                 }
5161
5162                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5163                         /*
5164                          * Ensure we match the reduced clock's P to the target
5165                          * clock.  If the clocks don't match, we can't switch
5166                          * the display clock by using the FP0/FP1. In such case
5167                          * we will disable the LVDS downclock feature.
5168                          */
5169                         has_reduced_clock =
5170                                 dev_priv->display.find_dpll(limit, crtc,
5171                                                             dev_priv->lvds_downclock,
5172                                                             refclk, &clock,
5173                                                             &reduced_clock);
5174                 }
5175                 /* Compat-code for transition, will disappear. */
5176                 intel_crtc->config.dpll.n = clock.n;
5177                 intel_crtc->config.dpll.m1 = clock.m1;
5178                 intel_crtc->config.dpll.m2 = clock.m2;
5179                 intel_crtc->config.dpll.p1 = clock.p1;
5180                 intel_crtc->config.dpll.p2 = clock.p2;
5181         }
5182
5183         if (IS_GEN2(dev)) {
5184                 i8xx_update_pll(intel_crtc,
5185                                 has_reduced_clock ? &reduced_clock : NULL,
5186                                 num_connectors);
5187         } else if (IS_VALLEYVIEW(dev)) {
5188                 vlv_update_pll(intel_crtc);
5189         } else {
5190                 i9xx_update_pll(intel_crtc,
5191                                 has_reduced_clock ? &reduced_clock : NULL,
5192                                 num_connectors);
5193         }
5194
5195 skip_dpll:
5196         /* Set up the display plane register */
5197         dspcntr = DISPPLANE_GAMMA_ENABLE;
5198
5199         if (!IS_VALLEYVIEW(dev)) {
5200                 if (pipe == 0)
5201                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5202                 else
5203                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5204         }
5205
5206         intel_set_pipe_timings(intel_crtc);
5207
5208         /* pipesrc and dspsize control the size that is scaled from,
5209          * which should always be the user's requested size.
5210          */
5211         I915_WRITE(DSPSIZE(plane),
5212                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5213                    (intel_crtc->config.pipe_src_w - 1));
5214         I915_WRITE(DSPPOS(plane), 0);
5215
5216         i9xx_set_pipeconf(intel_crtc);
5217
5218         I915_WRITE(DSPCNTR(plane), dspcntr);
5219         POSTING_READ(DSPCNTR(plane));
5220
5221         ret = intel_pipe_set_base(crtc, x, y, fb);
5222
5223         return ret;
5224 }
5225
5226 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5227                                  struct intel_crtc_config *pipe_config)
5228 {
5229         struct drm_device *dev = crtc->base.dev;
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231         uint32_t tmp;
5232
5233         tmp = I915_READ(PFIT_CONTROL);
5234         if (!(tmp & PFIT_ENABLE))
5235                 return;
5236
5237         /* Check whether the pfit is attached to our pipe. */
5238         if (INTEL_INFO(dev)->gen < 4) {
5239                 if (crtc->pipe != PIPE_B)
5240                         return;
5241         } else {
5242                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5243                         return;
5244         }
5245
5246         pipe_config->gmch_pfit.control = tmp;
5247         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5248         if (INTEL_INFO(dev)->gen < 5)
5249                 pipe_config->gmch_pfit.lvds_border_bits =
5250                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5251 }
5252
5253 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5254                                struct intel_crtc_config *pipe_config)
5255 {
5256         struct drm_device *dev = crtc->base.dev;
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         int pipe = pipe_config->cpu_transcoder;
5259         intel_clock_t clock;
5260         u32 mdiv;
5261         int refclk = 100000;
5262
5263         mutex_lock(&dev_priv->dpio_lock);
5264         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5265         mutex_unlock(&dev_priv->dpio_lock);
5266
5267         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5268         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5269         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5270         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5271         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5272
5273         vlv_clock(refclk, &clock);
5274
5275         /* clock.dot is the fast clock */
5276         pipe_config->port_clock = clock.dot / 5;
5277 }
5278
5279 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5280                                  struct intel_crtc_config *pipe_config)
5281 {
5282         struct drm_device *dev = crtc->base.dev;
5283         struct drm_i915_private *dev_priv = dev->dev_private;
5284         uint32_t tmp;
5285
5286         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5287         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5288
5289         tmp = I915_READ(PIPECONF(crtc->pipe));
5290         if (!(tmp & PIPECONF_ENABLE))
5291                 return false;
5292
5293         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5294                 switch (tmp & PIPECONF_BPC_MASK) {
5295                 case PIPECONF_6BPC:
5296                         pipe_config->pipe_bpp = 18;
5297                         break;
5298                 case PIPECONF_8BPC:
5299                         pipe_config->pipe_bpp = 24;
5300                         break;
5301                 case PIPECONF_10BPC:
5302                         pipe_config->pipe_bpp = 30;
5303                         break;
5304                 default:
5305                         break;
5306                 }
5307         }
5308
5309         if (INTEL_INFO(dev)->gen < 4)
5310                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5311
5312         intel_get_pipe_timings(crtc, pipe_config);
5313
5314         i9xx_get_pfit_config(crtc, pipe_config);
5315
5316         if (INTEL_INFO(dev)->gen >= 4) {
5317                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5318                 pipe_config->pixel_multiplier =
5319                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5320                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5321                 pipe_config->dpll_hw_state.dpll_md = tmp;
5322         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5323                 tmp = I915_READ(DPLL(crtc->pipe));
5324                 pipe_config->pixel_multiplier =
5325                         ((tmp & SDVO_MULTIPLIER_MASK)
5326                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5327         } else {
5328                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5329                  * port and will be fixed up in the encoder->get_config
5330                  * function. */
5331                 pipe_config->pixel_multiplier = 1;
5332         }
5333         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5334         if (!IS_VALLEYVIEW(dev)) {
5335                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5336                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5337         } else {
5338                 /* Mask out read-only status bits. */
5339                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5340                                                      DPLL_PORTC_READY_MASK |
5341                                                      DPLL_PORTB_READY_MASK);
5342         }
5343
5344         if (IS_VALLEYVIEW(dev))
5345                 vlv_crtc_clock_get(crtc, pipe_config);
5346         else
5347                 i9xx_crtc_clock_get(crtc, pipe_config);
5348
5349         return true;
5350 }
5351
5352 static void ironlake_init_pch_refclk(struct drm_device *dev)
5353 {
5354         struct drm_i915_private *dev_priv = dev->dev_private;
5355         struct drm_mode_config *mode_config = &dev->mode_config;
5356         struct intel_encoder *encoder;
5357         u32 val, final;
5358         bool has_lvds = false;
5359         bool has_cpu_edp = false;
5360         bool has_panel = false;
5361         bool has_ck505 = false;
5362         bool can_ssc = false;
5363
5364         /* We need to take the global config into account */
5365         list_for_each_entry(encoder, &mode_config->encoder_list,
5366                             base.head) {
5367                 switch (encoder->type) {
5368                 case INTEL_OUTPUT_LVDS:
5369                         has_panel = true;
5370                         has_lvds = true;
5371                         break;
5372                 case INTEL_OUTPUT_EDP:
5373                         has_panel = true;
5374                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5375                                 has_cpu_edp = true;
5376                         break;
5377                 }
5378         }
5379
5380         if (HAS_PCH_IBX(dev)) {
5381                 has_ck505 = dev_priv->vbt.display_clock_mode;
5382                 can_ssc = has_ck505;
5383         } else {
5384                 has_ck505 = false;
5385                 can_ssc = true;
5386         }
5387
5388         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5389                       has_panel, has_lvds, has_ck505);
5390
5391         /* Ironlake: try to setup display ref clock before DPLL
5392          * enabling. This is only under driver's control after
5393          * PCH B stepping, previous chipset stepping should be
5394          * ignoring this setting.
5395          */
5396         val = I915_READ(PCH_DREF_CONTROL);
5397
5398         /* As we must carefully and slowly disable/enable each source in turn,
5399          * compute the final state we want first and check if we need to
5400          * make any changes at all.
5401          */
5402         final = val;
5403         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5404         if (has_ck505)
5405                 final |= DREF_NONSPREAD_CK505_ENABLE;
5406         else
5407                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5408
5409         final &= ~DREF_SSC_SOURCE_MASK;
5410         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5411         final &= ~DREF_SSC1_ENABLE;
5412
5413         if (has_panel) {
5414                 final |= DREF_SSC_SOURCE_ENABLE;
5415
5416                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5417                         final |= DREF_SSC1_ENABLE;
5418
5419                 if (has_cpu_edp) {
5420                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5421                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5422                         else
5423                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5424                 } else
5425                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5426         } else {
5427                 final |= DREF_SSC_SOURCE_DISABLE;
5428                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5429         }
5430
5431         if (final == val)
5432                 return;
5433
5434         /* Always enable nonspread source */
5435         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5436
5437         if (has_ck505)
5438                 val |= DREF_NONSPREAD_CK505_ENABLE;
5439         else
5440                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5441
5442         if (has_panel) {
5443                 val &= ~DREF_SSC_SOURCE_MASK;
5444                 val |= DREF_SSC_SOURCE_ENABLE;
5445
5446                 /* SSC must be turned on before enabling the CPU output  */
5447                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5448                         DRM_DEBUG_KMS("Using SSC on panel\n");
5449                         val |= DREF_SSC1_ENABLE;
5450                 } else
5451                         val &= ~DREF_SSC1_ENABLE;
5452
5453                 /* Get SSC going before enabling the outputs */
5454                 I915_WRITE(PCH_DREF_CONTROL, val);
5455                 POSTING_READ(PCH_DREF_CONTROL);
5456                 udelay(200);
5457
5458                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5459
5460                 /* Enable CPU source on CPU attached eDP */
5461                 if (has_cpu_edp) {
5462                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5463                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5464                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5465                         }
5466                         else
5467                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5468                 } else
5469                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5470
5471                 I915_WRITE(PCH_DREF_CONTROL, val);
5472                 POSTING_READ(PCH_DREF_CONTROL);
5473                 udelay(200);
5474         } else {
5475                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5476
5477                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5478
5479                 /* Turn off CPU output */
5480                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5481
5482                 I915_WRITE(PCH_DREF_CONTROL, val);
5483                 POSTING_READ(PCH_DREF_CONTROL);
5484                 udelay(200);
5485
5486                 /* Turn off the SSC source */
5487                 val &= ~DREF_SSC_SOURCE_MASK;
5488                 val |= DREF_SSC_SOURCE_DISABLE;
5489
5490                 /* Turn off SSC1 */
5491                 val &= ~DREF_SSC1_ENABLE;
5492
5493                 I915_WRITE(PCH_DREF_CONTROL, val);
5494                 POSTING_READ(PCH_DREF_CONTROL);
5495                 udelay(200);
5496         }
5497
5498         BUG_ON(val != final);
5499 }
5500
5501 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5502 {
5503         uint32_t tmp;
5504
5505         tmp = I915_READ(SOUTH_CHICKEN2);
5506         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5507         I915_WRITE(SOUTH_CHICKEN2, tmp);
5508
5509         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5510                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5511                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5512
5513         tmp = I915_READ(SOUTH_CHICKEN2);
5514         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5515         I915_WRITE(SOUTH_CHICKEN2, tmp);
5516
5517         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5518                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5519                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5520 }
5521
5522 /* WaMPhyProgramming:hsw */
5523 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5524 {
5525         uint32_t tmp;
5526
5527         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5528         tmp &= ~(0xFF << 24);
5529         tmp |= (0x12 << 24);
5530         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5531
5532         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5533         tmp |= (1 << 11);
5534         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5535
5536         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5537         tmp |= (1 << 11);
5538         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5539
5540         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5541         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5542         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5543
5544         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5545         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5546         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5547
5548         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5549         tmp &= ~(7 << 13);
5550         tmp |= (5 << 13);
5551         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5552
5553         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5554         tmp &= ~(7 << 13);
5555         tmp |= (5 << 13);
5556         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5557
5558         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5559         tmp &= ~0xFF;
5560         tmp |= 0x1C;
5561         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5562
5563         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5564         tmp &= ~0xFF;
5565         tmp |= 0x1C;
5566         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5567
5568         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5569         tmp &= ~(0xFF << 16);
5570         tmp |= (0x1C << 16);
5571         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5572
5573         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5574         tmp &= ~(0xFF << 16);
5575         tmp |= (0x1C << 16);
5576         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5577
5578         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5579         tmp |= (1 << 27);
5580         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5581
5582         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5583         tmp |= (1 << 27);
5584         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5585
5586         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5587         tmp &= ~(0xF << 28);
5588         tmp |= (4 << 28);
5589         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5590
5591         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5592         tmp &= ~(0xF << 28);
5593         tmp |= (4 << 28);
5594         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5595 }
5596
5597 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5598  * Programming" based on the parameters passed:
5599  * - Sequence to enable CLKOUT_DP
5600  * - Sequence to enable CLKOUT_DP without spread
5601  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5602  */
5603 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5604                                  bool with_fdi)
5605 {
5606         struct drm_i915_private *dev_priv = dev->dev_private;
5607         uint32_t reg, tmp;
5608
5609         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5610                 with_spread = true;
5611         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5612                  with_fdi, "LP PCH doesn't have FDI\n"))
5613                 with_fdi = false;
5614
5615         mutex_lock(&dev_priv->dpio_lock);
5616
5617         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5618         tmp &= ~SBI_SSCCTL_DISABLE;
5619         tmp |= SBI_SSCCTL_PATHALT;
5620         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5621
5622         udelay(24);
5623
5624         if (with_spread) {
5625                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5626                 tmp &= ~SBI_SSCCTL_PATHALT;
5627                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5628
5629                 if (with_fdi) {
5630                         lpt_reset_fdi_mphy(dev_priv);
5631                         lpt_program_fdi_mphy(dev_priv);
5632                 }
5633         }
5634
5635         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5636                SBI_GEN0 : SBI_DBUFF0;
5637         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5638         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5639         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5640
5641         mutex_unlock(&dev_priv->dpio_lock);
5642 }
5643
5644 /* Sequence to disable CLKOUT_DP */
5645 static void lpt_disable_clkout_dp(struct drm_device *dev)
5646 {
5647         struct drm_i915_private *dev_priv = dev->dev_private;
5648         uint32_t reg, tmp;
5649
5650         mutex_lock(&dev_priv->dpio_lock);
5651
5652         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5653                SBI_GEN0 : SBI_DBUFF0;
5654         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5655         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5656         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5657
5658         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5659         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5660                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5661                         tmp |= SBI_SSCCTL_PATHALT;
5662                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5663                         udelay(32);
5664                 }
5665                 tmp |= SBI_SSCCTL_DISABLE;
5666                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5667         }
5668
5669         mutex_unlock(&dev_priv->dpio_lock);
5670 }
5671
5672 static void lpt_init_pch_refclk(struct drm_device *dev)
5673 {
5674         struct drm_mode_config *mode_config = &dev->mode_config;
5675         struct intel_encoder *encoder;
5676         bool has_vga = false;
5677
5678         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5679                 switch (encoder->type) {
5680                 case INTEL_OUTPUT_ANALOG:
5681                         has_vga = true;
5682                         break;
5683                 }
5684         }
5685
5686         if (has_vga)
5687                 lpt_enable_clkout_dp(dev, true, true);
5688         else
5689                 lpt_disable_clkout_dp(dev);
5690 }
5691
5692 /*
5693  * Initialize reference clocks when the driver loads
5694  */
5695 void intel_init_pch_refclk(struct drm_device *dev)
5696 {
5697         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5698                 ironlake_init_pch_refclk(dev);
5699         else if (HAS_PCH_LPT(dev))
5700                 lpt_init_pch_refclk(dev);
5701 }
5702
5703 static int ironlake_get_refclk(struct drm_crtc *crtc)
5704 {
5705         struct drm_device *dev = crtc->dev;
5706         struct drm_i915_private *dev_priv = dev->dev_private;
5707         struct intel_encoder *encoder;
5708         int num_connectors = 0;
5709         bool is_lvds = false;
5710
5711         for_each_encoder_on_crtc(dev, crtc, encoder) {
5712                 switch (encoder->type) {
5713                 case INTEL_OUTPUT_LVDS:
5714                         is_lvds = true;
5715                         break;
5716                 }
5717                 num_connectors++;
5718         }
5719
5720         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5721                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5722                               dev_priv->vbt.lvds_ssc_freq);
5723                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5724         }
5725
5726         return 120000;
5727 }
5728
5729 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5730 {
5731         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733         int pipe = intel_crtc->pipe;
5734         uint32_t val;
5735
5736         val = 0;
5737
5738         switch (intel_crtc->config.pipe_bpp) {
5739         case 18:
5740                 val |= PIPECONF_6BPC;
5741                 break;
5742         case 24:
5743                 val |= PIPECONF_8BPC;
5744                 break;
5745         case 30:
5746                 val |= PIPECONF_10BPC;
5747                 break;
5748         case 36:
5749                 val |= PIPECONF_12BPC;
5750                 break;
5751         default:
5752                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5753                 BUG();
5754         }
5755
5756         if (intel_crtc->config.dither)
5757                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5758
5759         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5760                 val |= PIPECONF_INTERLACED_ILK;
5761         else
5762                 val |= PIPECONF_PROGRESSIVE;
5763
5764         if (intel_crtc->config.limited_color_range)
5765                 val |= PIPECONF_COLOR_RANGE_SELECT;
5766
5767         I915_WRITE(PIPECONF(pipe), val);
5768         POSTING_READ(PIPECONF(pipe));
5769 }
5770
5771 /*
5772  * Set up the pipe CSC unit.
5773  *
5774  * Currently only full range RGB to limited range RGB conversion
5775  * is supported, but eventually this should handle various
5776  * RGB<->YCbCr scenarios as well.
5777  */
5778 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5779 {
5780         struct drm_device *dev = crtc->dev;
5781         struct drm_i915_private *dev_priv = dev->dev_private;
5782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5783         int pipe = intel_crtc->pipe;
5784         uint16_t coeff = 0x7800; /* 1.0 */
5785
5786         /*
5787          * TODO: Check what kind of values actually come out of the pipe
5788          * with these coeff/postoff values and adjust to get the best
5789          * accuracy. Perhaps we even need to take the bpc value into
5790          * consideration.
5791          */
5792
5793         if (intel_crtc->config.limited_color_range)
5794                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5795
5796         /*
5797          * GY/GU and RY/RU should be the other way around according
5798          * to BSpec, but reality doesn't agree. Just set them up in
5799          * a way that results in the correct picture.
5800          */
5801         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5802         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5803
5804         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5805         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5806
5807         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5808         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5809
5810         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5811         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5812         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5813
5814         if (INTEL_INFO(dev)->gen > 6) {
5815                 uint16_t postoff = 0;
5816
5817                 if (intel_crtc->config.limited_color_range)
5818                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5819
5820                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5821                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5822                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5823
5824                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5825         } else {
5826                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5827
5828                 if (intel_crtc->config.limited_color_range)
5829                         mode |= CSC_BLACK_SCREEN_OFFSET;
5830
5831                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5832         }
5833 }
5834
5835 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5836 {
5837         struct drm_device *dev = crtc->dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5840         enum pipe pipe = intel_crtc->pipe;
5841         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5842         uint32_t val;
5843
5844         val = 0;
5845
5846         if (IS_HASWELL(dev) && intel_crtc->config.dither)
5847                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5848
5849         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5850                 val |= PIPECONF_INTERLACED_ILK;
5851         else
5852                 val |= PIPECONF_PROGRESSIVE;
5853
5854         I915_WRITE(PIPECONF(cpu_transcoder), val);
5855         POSTING_READ(PIPECONF(cpu_transcoder));
5856
5857         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5858         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5859
5860         if (IS_BROADWELL(dev)) {
5861                 val = 0;
5862
5863                 switch (intel_crtc->config.pipe_bpp) {
5864                 case 18:
5865                         val |= PIPEMISC_DITHER_6_BPC;
5866                         break;
5867                 case 24:
5868                         val |= PIPEMISC_DITHER_8_BPC;
5869                         break;
5870                 case 30:
5871                         val |= PIPEMISC_DITHER_10_BPC;
5872                         break;
5873                 case 36:
5874                         val |= PIPEMISC_DITHER_12_BPC;
5875                         break;
5876                 default:
5877                         /* Case prevented by pipe_config_set_bpp. */
5878                         BUG();
5879                 }
5880
5881                 if (intel_crtc->config.dither)
5882                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5883
5884                 I915_WRITE(PIPEMISC(pipe), val);
5885         }
5886 }
5887
5888 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5889                                     intel_clock_t *clock,
5890                                     bool *has_reduced_clock,
5891                                     intel_clock_t *reduced_clock)
5892 {
5893         struct drm_device *dev = crtc->dev;
5894         struct drm_i915_private *dev_priv = dev->dev_private;
5895         struct intel_encoder *intel_encoder;
5896         int refclk;
5897         const intel_limit_t *limit;
5898         bool ret, is_lvds = false;
5899
5900         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5901                 switch (intel_encoder->type) {
5902                 case INTEL_OUTPUT_LVDS:
5903                         is_lvds = true;
5904                         break;
5905                 }
5906         }
5907
5908         refclk = ironlake_get_refclk(crtc);
5909
5910         /*
5911          * Returns a set of divisors for the desired target clock with the given
5912          * refclk, or FALSE.  The returned values represent the clock equation:
5913          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5914          */
5915         limit = intel_limit(crtc, refclk);
5916         ret = dev_priv->display.find_dpll(limit, crtc,
5917                                           to_intel_crtc(crtc)->config.port_clock,
5918                                           refclk, NULL, clock);
5919         if (!ret)
5920                 return false;
5921
5922         if (is_lvds && dev_priv->lvds_downclock_avail) {
5923                 /*
5924                  * Ensure we match the reduced clock's P to the target clock.
5925                  * If the clocks don't match, we can't switch the display clock
5926                  * by using the FP0/FP1. In such case we will disable the LVDS
5927                  * downclock feature.
5928                 */
5929                 *has_reduced_clock =
5930                         dev_priv->display.find_dpll(limit, crtc,
5931                                                     dev_priv->lvds_downclock,
5932                                                     refclk, clock,
5933                                                     reduced_clock);
5934         }
5935
5936         return true;
5937 }
5938
5939 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5940 {
5941         /*
5942          * Account for spread spectrum to avoid
5943          * oversubscribing the link. Max center spread
5944          * is 2.5%; use 5% for safety's sake.
5945          */
5946         u32 bps = target_clock * bpp * 21 / 20;
5947         return bps / (link_bw * 8) + 1;
5948 }
5949
5950 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5951 {
5952         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5953 }
5954
5955 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5956                                       u32 *fp,
5957                                       intel_clock_t *reduced_clock, u32 *fp2)
5958 {
5959         struct drm_crtc *crtc = &intel_crtc->base;
5960         struct drm_device *dev = crtc->dev;
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962         struct intel_encoder *intel_encoder;
5963         uint32_t dpll;
5964         int factor, num_connectors = 0;
5965         bool is_lvds = false, is_sdvo = false;
5966
5967         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5968                 switch (intel_encoder->type) {
5969                 case INTEL_OUTPUT_LVDS:
5970                         is_lvds = true;
5971                         break;
5972                 case INTEL_OUTPUT_SDVO:
5973                 case INTEL_OUTPUT_HDMI:
5974                         is_sdvo = true;
5975                         break;
5976                 }
5977
5978                 num_connectors++;
5979         }
5980
5981         /* Enable autotuning of the PLL clock (if permissible) */
5982         factor = 21;
5983         if (is_lvds) {
5984                 if ((intel_panel_use_ssc(dev_priv) &&
5985                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5986                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5987                         factor = 25;
5988         } else if (intel_crtc->config.sdvo_tv_clock)
5989                 factor = 20;
5990
5991         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5992                 *fp |= FP_CB_TUNE;
5993
5994         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5995                 *fp2 |= FP_CB_TUNE;
5996
5997         dpll = 0;
5998
5999         if (is_lvds)
6000                 dpll |= DPLLB_MODE_LVDS;
6001         else
6002                 dpll |= DPLLB_MODE_DAC_SERIAL;
6003
6004         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6005                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6006
6007         if (is_sdvo)
6008                 dpll |= DPLL_SDVO_HIGH_SPEED;
6009         if (intel_crtc->config.has_dp_encoder)
6010                 dpll |= DPLL_SDVO_HIGH_SPEED;
6011
6012         /* compute bitmask from p1 value */
6013         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6014         /* also FPA1 */
6015         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6016
6017         switch (intel_crtc->config.dpll.p2) {
6018         case 5:
6019                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6020                 break;
6021         case 7:
6022                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6023                 break;
6024         case 10:
6025                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6026                 break;
6027         case 14:
6028                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6029                 break;
6030         }
6031
6032         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6033                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6034         else
6035                 dpll |= PLL_REF_INPUT_DREFCLK;
6036
6037         return dpll | DPLL_VCO_ENABLE;
6038 }
6039
6040 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6041                                   int x, int y,
6042                                   struct drm_framebuffer *fb)
6043 {
6044         struct drm_device *dev = crtc->dev;
6045         struct drm_i915_private *dev_priv = dev->dev_private;
6046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047         int pipe = intel_crtc->pipe;
6048         int plane = intel_crtc->plane;
6049         int num_connectors = 0;
6050         intel_clock_t clock, reduced_clock;
6051         u32 dpll = 0, fp = 0, fp2 = 0;
6052         bool ok, has_reduced_clock = false;
6053         bool is_lvds = false;
6054         struct intel_encoder *encoder;
6055         struct intel_shared_dpll *pll;
6056         int ret;
6057
6058         for_each_encoder_on_crtc(dev, crtc, encoder) {
6059                 switch (encoder->type) {
6060                 case INTEL_OUTPUT_LVDS:
6061                         is_lvds = true;
6062                         break;
6063                 }
6064
6065                 num_connectors++;
6066         }
6067
6068         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6069              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6070
6071         ok = ironlake_compute_clocks(crtc, &clock,
6072                                      &has_reduced_clock, &reduced_clock);
6073         if (!ok && !intel_crtc->config.clock_set) {
6074                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6075                 return -EINVAL;
6076         }
6077         /* Compat-code for transition, will disappear. */
6078         if (!intel_crtc->config.clock_set) {
6079                 intel_crtc->config.dpll.n = clock.n;
6080                 intel_crtc->config.dpll.m1 = clock.m1;
6081                 intel_crtc->config.dpll.m2 = clock.m2;
6082                 intel_crtc->config.dpll.p1 = clock.p1;
6083                 intel_crtc->config.dpll.p2 = clock.p2;
6084         }
6085
6086         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6087         if (intel_crtc->config.has_pch_encoder) {
6088                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6089                 if (has_reduced_clock)
6090                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6091
6092                 dpll = ironlake_compute_dpll(intel_crtc,
6093                                              &fp, &reduced_clock,
6094                                              has_reduced_clock ? &fp2 : NULL);
6095
6096                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6097                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6098                 if (has_reduced_clock)
6099                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6100                 else
6101                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6102
6103                 pll = intel_get_shared_dpll(intel_crtc);
6104                 if (pll == NULL) {
6105                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6106                                          pipe_name(pipe));
6107                         return -EINVAL;
6108                 }
6109         } else
6110                 intel_put_shared_dpll(intel_crtc);
6111
6112         if (intel_crtc->config.has_dp_encoder)
6113                 intel_dp_set_m_n(intel_crtc);
6114
6115         if (is_lvds && has_reduced_clock && i915_powersave)
6116                 intel_crtc->lowfreq_avail = true;
6117         else
6118                 intel_crtc->lowfreq_avail = false;
6119
6120         intel_set_pipe_timings(intel_crtc);
6121
6122         if (intel_crtc->config.has_pch_encoder) {
6123                 intel_cpu_transcoder_set_m_n(intel_crtc,
6124                                              &intel_crtc->config.fdi_m_n);
6125         }
6126
6127         ironlake_set_pipeconf(crtc);
6128
6129         /* Set up the display plane register */
6130         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6131         POSTING_READ(DSPCNTR(plane));
6132
6133         ret = intel_pipe_set_base(crtc, x, y, fb);
6134
6135         return ret;
6136 }
6137
6138 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6139                                          struct intel_link_m_n *m_n)
6140 {
6141         struct drm_device *dev = crtc->base.dev;
6142         struct drm_i915_private *dev_priv = dev->dev_private;
6143         enum pipe pipe = crtc->pipe;
6144
6145         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6146         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6147         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6148                 & ~TU_SIZE_MASK;
6149         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6150         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6151                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6152 }
6153
6154 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6155                                          enum transcoder transcoder,
6156                                          struct intel_link_m_n *m_n)
6157 {
6158         struct drm_device *dev = crtc->base.dev;
6159         struct drm_i915_private *dev_priv = dev->dev_private;
6160         enum pipe pipe = crtc->pipe;
6161
6162         if (INTEL_INFO(dev)->gen >= 5) {
6163                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6164                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6165                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6166                         & ~TU_SIZE_MASK;
6167                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6168                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6169                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6170         } else {
6171                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6172                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6173                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6174                         & ~TU_SIZE_MASK;
6175                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6176                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6177                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6178         }
6179 }
6180
6181 void intel_dp_get_m_n(struct intel_crtc *crtc,
6182                       struct intel_crtc_config *pipe_config)
6183 {
6184         if (crtc->config.has_pch_encoder)
6185                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6186         else
6187                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6188                                              &pipe_config->dp_m_n);
6189 }
6190
6191 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6192                                         struct intel_crtc_config *pipe_config)
6193 {
6194         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6195                                      &pipe_config->fdi_m_n);
6196 }
6197
6198 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6199                                      struct intel_crtc_config *pipe_config)
6200 {
6201         struct drm_device *dev = crtc->base.dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         uint32_t tmp;
6204
6205         tmp = I915_READ(PF_CTL(crtc->pipe));
6206
6207         if (tmp & PF_ENABLE) {
6208                 pipe_config->pch_pfit.enabled = true;
6209                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6210                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6211
6212                 /* We currently do not free assignements of panel fitters on
6213                  * ivb/hsw (since we don't use the higher upscaling modes which
6214                  * differentiates them) so just WARN about this case for now. */
6215                 if (IS_GEN7(dev)) {
6216                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6217                                 PF_PIPE_SEL_IVB(crtc->pipe));
6218                 }
6219         }
6220 }
6221
6222 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6223                                      struct intel_crtc_config *pipe_config)
6224 {
6225         struct drm_device *dev = crtc->base.dev;
6226         struct drm_i915_private *dev_priv = dev->dev_private;
6227         uint32_t tmp;
6228
6229         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6230         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6231
6232         tmp = I915_READ(PIPECONF(crtc->pipe));
6233         if (!(tmp & PIPECONF_ENABLE))
6234                 return false;
6235
6236         switch (tmp & PIPECONF_BPC_MASK) {
6237         case PIPECONF_6BPC:
6238                 pipe_config->pipe_bpp = 18;
6239                 break;
6240         case PIPECONF_8BPC:
6241                 pipe_config->pipe_bpp = 24;
6242                 break;
6243         case PIPECONF_10BPC:
6244                 pipe_config->pipe_bpp = 30;
6245                 break;
6246         case PIPECONF_12BPC:
6247                 pipe_config->pipe_bpp = 36;
6248                 break;
6249         default:
6250                 break;
6251         }
6252
6253         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6254                 struct intel_shared_dpll *pll;
6255
6256                 pipe_config->has_pch_encoder = true;
6257
6258                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6259                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6260                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6261
6262                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6263
6264                 if (HAS_PCH_IBX(dev_priv->dev)) {
6265                         pipe_config->shared_dpll =
6266                                 (enum intel_dpll_id) crtc->pipe;
6267                 } else {
6268                         tmp = I915_READ(PCH_DPLL_SEL);
6269                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6270                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6271                         else
6272                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6273                 }
6274
6275                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6276
6277                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6278                                            &pipe_config->dpll_hw_state));
6279
6280                 tmp = pipe_config->dpll_hw_state.dpll;
6281                 pipe_config->pixel_multiplier =
6282                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6283                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6284
6285                 ironlake_pch_clock_get(crtc, pipe_config);
6286         } else {
6287                 pipe_config->pixel_multiplier = 1;
6288         }
6289
6290         intel_get_pipe_timings(crtc, pipe_config);
6291
6292         ironlake_get_pfit_config(crtc, pipe_config);
6293
6294         return true;
6295 }
6296
6297 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6298 {
6299         struct drm_device *dev = dev_priv->dev;
6300         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6301         struct intel_crtc *crtc;
6302         unsigned long irqflags;
6303         uint32_t val;
6304
6305         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6306                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6307                      pipe_name(crtc->pipe));
6308
6309         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6310         WARN(plls->spll_refcount, "SPLL enabled\n");
6311         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6312         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6313         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6314         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6315              "CPU PWM1 enabled\n");
6316         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6317              "CPU PWM2 enabled\n");
6318         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6319              "PCH PWM1 enabled\n");
6320         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6321              "Utility pin enabled\n");
6322         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6323
6324         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6325         val = I915_READ(DEIMR);
6326         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6327              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6328         val = I915_READ(SDEIMR);
6329         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6330              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6331         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6332 }
6333
6334 /*
6335  * This function implements pieces of two sequences from BSpec:
6336  * - Sequence for display software to disable LCPLL
6337  * - Sequence for display software to allow package C8+
6338  * The steps implemented here are just the steps that actually touch the LCPLL
6339  * register. Callers should take care of disabling all the display engine
6340  * functions, doing the mode unset, fixing interrupts, etc.
6341  */
6342 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6343                               bool switch_to_fclk, bool allow_power_down)
6344 {
6345         uint32_t val;
6346
6347         assert_can_disable_lcpll(dev_priv);
6348
6349         val = I915_READ(LCPLL_CTL);
6350
6351         if (switch_to_fclk) {
6352                 val |= LCPLL_CD_SOURCE_FCLK;
6353                 I915_WRITE(LCPLL_CTL, val);
6354
6355                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6356                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6357                         DRM_ERROR("Switching to FCLK failed\n");
6358
6359                 val = I915_READ(LCPLL_CTL);
6360         }
6361
6362         val |= LCPLL_PLL_DISABLE;
6363         I915_WRITE(LCPLL_CTL, val);
6364         POSTING_READ(LCPLL_CTL);
6365
6366         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6367                 DRM_ERROR("LCPLL still locked\n");
6368
6369         val = I915_READ(D_COMP);
6370         val |= D_COMP_COMP_DISABLE;
6371         mutex_lock(&dev_priv->rps.hw_lock);
6372         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6373                 DRM_ERROR("Failed to disable D_COMP\n");
6374         mutex_unlock(&dev_priv->rps.hw_lock);
6375         POSTING_READ(D_COMP);
6376         ndelay(100);
6377
6378         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6379                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6380
6381         if (allow_power_down) {
6382                 val = I915_READ(LCPLL_CTL);
6383                 val |= LCPLL_POWER_DOWN_ALLOW;
6384                 I915_WRITE(LCPLL_CTL, val);
6385                 POSTING_READ(LCPLL_CTL);
6386         }
6387 }
6388
6389 /*
6390  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6391  * source.
6392  */
6393 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6394 {
6395         uint32_t val;
6396
6397         val = I915_READ(LCPLL_CTL);
6398
6399         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6400                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6401                 return;
6402
6403         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6404          * we'll hang the machine! */
6405         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6406
6407         if (val & LCPLL_POWER_DOWN_ALLOW) {
6408                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6409                 I915_WRITE(LCPLL_CTL, val);
6410                 POSTING_READ(LCPLL_CTL);
6411         }
6412
6413         val = I915_READ(D_COMP);
6414         val |= D_COMP_COMP_FORCE;
6415         val &= ~D_COMP_COMP_DISABLE;
6416         mutex_lock(&dev_priv->rps.hw_lock);
6417         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6418                 DRM_ERROR("Failed to enable D_COMP\n");
6419         mutex_unlock(&dev_priv->rps.hw_lock);
6420         POSTING_READ(D_COMP);
6421
6422         val = I915_READ(LCPLL_CTL);
6423         val &= ~LCPLL_PLL_DISABLE;
6424         I915_WRITE(LCPLL_CTL, val);
6425
6426         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6427                 DRM_ERROR("LCPLL not locked yet\n");
6428
6429         if (val & LCPLL_CD_SOURCE_FCLK) {
6430                 val = I915_READ(LCPLL_CTL);
6431                 val &= ~LCPLL_CD_SOURCE_FCLK;
6432                 I915_WRITE(LCPLL_CTL, val);
6433
6434                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6435                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6436                         DRM_ERROR("Switching back to LCPLL failed\n");
6437         }
6438
6439         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6440 }
6441
6442 void hsw_enable_pc8_work(struct work_struct *__work)
6443 {
6444         struct drm_i915_private *dev_priv =
6445                 container_of(to_delayed_work(__work), struct drm_i915_private,
6446                              pc8.enable_work);
6447         struct drm_device *dev = dev_priv->dev;
6448         uint32_t val;
6449
6450         if (dev_priv->pc8.enabled)
6451                 return;
6452
6453         DRM_DEBUG_KMS("Enabling package C8+\n");
6454
6455         dev_priv->pc8.enabled = true;
6456
6457         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6458                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6459                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6460                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6461         }
6462
6463         lpt_disable_clkout_dp(dev);
6464         hsw_pc8_disable_interrupts(dev);
6465         hsw_disable_lcpll(dev_priv, true, true);
6466 }
6467
6468 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6469 {
6470         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6471         WARN(dev_priv->pc8.disable_count < 1,
6472              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6473
6474         dev_priv->pc8.disable_count--;
6475         if (dev_priv->pc8.disable_count != 0)
6476                 return;
6477
6478         schedule_delayed_work(&dev_priv->pc8.enable_work,
6479                               msecs_to_jiffies(i915_pc8_timeout));
6480 }
6481
6482 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6483 {
6484         struct drm_device *dev = dev_priv->dev;
6485         uint32_t val;
6486
6487         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6488         WARN(dev_priv->pc8.disable_count < 0,
6489              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6490
6491         dev_priv->pc8.disable_count++;
6492         if (dev_priv->pc8.disable_count != 1)
6493                 return;
6494
6495         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6496         if (!dev_priv->pc8.enabled)
6497                 return;
6498
6499         DRM_DEBUG_KMS("Disabling package C8+\n");
6500
6501         hsw_restore_lcpll(dev_priv);
6502         hsw_pc8_restore_interrupts(dev);
6503         lpt_init_pch_refclk(dev);
6504
6505         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6506                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6507                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6508                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6509         }
6510
6511         intel_prepare_ddi(dev);
6512         i915_gem_init_swizzling(dev);
6513         mutex_lock(&dev_priv->rps.hw_lock);
6514         gen6_update_ring_freq(dev);
6515         mutex_unlock(&dev_priv->rps.hw_lock);
6516         dev_priv->pc8.enabled = false;
6517 }
6518
6519 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6520 {
6521         mutex_lock(&dev_priv->pc8.lock);
6522         __hsw_enable_package_c8(dev_priv);
6523         mutex_unlock(&dev_priv->pc8.lock);
6524 }
6525
6526 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6527 {
6528         mutex_lock(&dev_priv->pc8.lock);
6529         __hsw_disable_package_c8(dev_priv);
6530         mutex_unlock(&dev_priv->pc8.lock);
6531 }
6532
6533 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6534 {
6535         struct drm_device *dev = dev_priv->dev;
6536         struct intel_crtc *crtc;
6537         uint32_t val;
6538
6539         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6540                 if (crtc->base.enabled)
6541                         return false;
6542
6543         /* This case is still possible since we have the i915.disable_power_well
6544          * parameter and also the KVMr or something else might be requesting the
6545          * power well. */
6546         val = I915_READ(HSW_PWR_WELL_DRIVER);
6547         if (val != 0) {
6548                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6549                 return false;
6550         }
6551
6552         return true;
6553 }
6554
6555 /* Since we're called from modeset_global_resources there's no way to
6556  * symmetrically increase and decrease the refcount, so we use
6557  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6558  * or not.
6559  */
6560 static void hsw_update_package_c8(struct drm_device *dev)
6561 {
6562         struct drm_i915_private *dev_priv = dev->dev_private;
6563         bool allow;
6564
6565         if (!i915_enable_pc8)
6566                 return;
6567
6568         mutex_lock(&dev_priv->pc8.lock);
6569
6570         allow = hsw_can_enable_package_c8(dev_priv);
6571
6572         if (allow == dev_priv->pc8.requirements_met)
6573                 goto done;
6574
6575         dev_priv->pc8.requirements_met = allow;
6576
6577         if (allow)
6578                 __hsw_enable_package_c8(dev_priv);
6579         else
6580                 __hsw_disable_package_c8(dev_priv);
6581
6582 done:
6583         mutex_unlock(&dev_priv->pc8.lock);
6584 }
6585
6586 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6587 {
6588         if (!dev_priv->pc8.gpu_idle) {
6589                 dev_priv->pc8.gpu_idle = true;
6590                 hsw_enable_package_c8(dev_priv);
6591         }
6592 }
6593
6594 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6595 {
6596         if (dev_priv->pc8.gpu_idle) {
6597                 dev_priv->pc8.gpu_idle = false;
6598                 hsw_disable_package_c8(dev_priv);
6599         }
6600 }
6601
6602 #define for_each_power_domain(domain, mask)                             \
6603         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6604                 if ((1 << (domain)) & (mask))
6605
6606 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6607                                             enum pipe pipe, bool pfit_enabled)
6608 {
6609         unsigned long mask;
6610         enum transcoder transcoder;
6611
6612         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6613
6614         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6615         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6616         if (pfit_enabled)
6617                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6618
6619         return mask;
6620 }
6621
6622 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6623 {
6624         struct drm_i915_private *dev_priv = dev->dev_private;
6625
6626         if (dev_priv->power_domains.init_power_on == enable)
6627                 return;
6628
6629         if (enable)
6630                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6631         else
6632                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6633
6634         dev_priv->power_domains.init_power_on = enable;
6635 }
6636
6637 static void modeset_update_power_wells(struct drm_device *dev)
6638 {
6639         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6640         struct intel_crtc *crtc;
6641
6642         /*
6643          * First get all needed power domains, then put all unneeded, to avoid
6644          * any unnecessary toggling of the power wells.
6645          */
6646         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6647                 enum intel_display_power_domain domain;
6648
6649                 if (!crtc->base.enabled)
6650                         continue;
6651
6652                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6653                                                 crtc->pipe,
6654                                                 crtc->config.pch_pfit.enabled);
6655
6656                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6657                         intel_display_power_get(dev, domain);
6658         }
6659
6660         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6661                 enum intel_display_power_domain domain;
6662
6663                 for_each_power_domain(domain, crtc->enabled_power_domains)
6664                         intel_display_power_put(dev, domain);
6665
6666                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6667         }
6668
6669         intel_display_set_init_power(dev, false);
6670 }
6671
6672 static void haswell_modeset_global_resources(struct drm_device *dev)
6673 {
6674         modeset_update_power_wells(dev);
6675         hsw_update_package_c8(dev);
6676 }
6677
6678 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6679                                  int x, int y,
6680                                  struct drm_framebuffer *fb)
6681 {
6682         struct drm_device *dev = crtc->dev;
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685         int plane = intel_crtc->plane;
6686         int ret;
6687
6688         if (!intel_ddi_pll_mode_set(crtc))
6689                 return -EINVAL;
6690
6691         if (intel_crtc->config.has_dp_encoder)
6692                 intel_dp_set_m_n(intel_crtc);
6693
6694         intel_crtc->lowfreq_avail = false;
6695
6696         intel_set_pipe_timings(intel_crtc);
6697
6698         if (intel_crtc->config.has_pch_encoder) {
6699                 intel_cpu_transcoder_set_m_n(intel_crtc,
6700                                              &intel_crtc->config.fdi_m_n);
6701         }
6702
6703         haswell_set_pipeconf(crtc);
6704
6705         intel_set_pipe_csc(crtc);
6706
6707         /* Set up the display plane register */
6708         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6709         POSTING_READ(DSPCNTR(plane));
6710
6711         ret = intel_pipe_set_base(crtc, x, y, fb);
6712
6713         return ret;
6714 }
6715
6716 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6717                                     struct intel_crtc_config *pipe_config)
6718 {
6719         struct drm_device *dev = crtc->base.dev;
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         enum intel_display_power_domain pfit_domain;
6722         uint32_t tmp;
6723
6724         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6725         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6726
6727         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6728         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6729                 enum pipe trans_edp_pipe;
6730                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6731                 default:
6732                         WARN(1, "unknown pipe linked to edp transcoder\n");
6733                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6734                 case TRANS_DDI_EDP_INPUT_A_ON:
6735                         trans_edp_pipe = PIPE_A;
6736                         break;
6737                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6738                         trans_edp_pipe = PIPE_B;
6739                         break;
6740                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6741                         trans_edp_pipe = PIPE_C;
6742                         break;
6743                 }
6744
6745                 if (trans_edp_pipe == crtc->pipe)
6746                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6747         }
6748
6749         if (!intel_display_power_enabled(dev,
6750                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6751                 return false;
6752
6753         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6754         if (!(tmp & PIPECONF_ENABLE))
6755                 return false;
6756
6757         /*
6758          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6759          * DDI E. So just check whether this pipe is wired to DDI E and whether
6760          * the PCH transcoder is on.
6761          */
6762         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6763         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6764             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6765                 pipe_config->has_pch_encoder = true;
6766
6767                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6768                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6769                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6770
6771                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6772         }
6773
6774         intel_get_pipe_timings(crtc, pipe_config);
6775
6776         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6777         if (intel_display_power_enabled(dev, pfit_domain))
6778                 ironlake_get_pfit_config(crtc, pipe_config);
6779
6780         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6781                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6782
6783         pipe_config->pixel_multiplier = 1;
6784
6785         return true;
6786 }
6787
6788 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6789                                int x, int y,
6790                                struct drm_framebuffer *fb)
6791 {
6792         struct drm_device *dev = crtc->dev;
6793         struct drm_i915_private *dev_priv = dev->dev_private;
6794         struct intel_encoder *encoder;
6795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6796         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6797         int pipe = intel_crtc->pipe;
6798         int ret;
6799
6800         drm_vblank_pre_modeset(dev, pipe);
6801
6802         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6803
6804         drm_vblank_post_modeset(dev, pipe);
6805
6806         if (ret != 0)
6807                 return ret;
6808
6809         for_each_encoder_on_crtc(dev, crtc, encoder) {
6810                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6811                         encoder->base.base.id,
6812                         drm_get_encoder_name(&encoder->base),
6813                         mode->base.id, mode->name);
6814                 encoder->mode_set(encoder);
6815         }
6816
6817         return 0;
6818 }
6819
6820 static struct {
6821         int clock;
6822         u32 config;
6823 } hdmi_audio_clock[] = {
6824         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6825         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6826         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6827         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6828         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6829         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6830         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6831         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6832         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6833         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6834 };
6835
6836 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6837 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6838 {
6839         int i;
6840
6841         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6842                 if (mode->clock == hdmi_audio_clock[i].clock)
6843                         break;
6844         }
6845
6846         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6847                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6848                 i = 1;
6849         }
6850
6851         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6852                       hdmi_audio_clock[i].clock,
6853                       hdmi_audio_clock[i].config);
6854
6855         return hdmi_audio_clock[i].config;
6856 }
6857
6858 static bool intel_eld_uptodate(struct drm_connector *connector,
6859                                int reg_eldv, uint32_t bits_eldv,
6860                                int reg_elda, uint32_t bits_elda,
6861                                int reg_edid)
6862 {
6863         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6864         uint8_t *eld = connector->eld;
6865         uint32_t i;
6866
6867         i = I915_READ(reg_eldv);
6868         i &= bits_eldv;
6869
6870         if (!eld[0])
6871                 return !i;
6872
6873         if (!i)
6874                 return false;
6875
6876         i = I915_READ(reg_elda);
6877         i &= ~bits_elda;
6878         I915_WRITE(reg_elda, i);
6879
6880         for (i = 0; i < eld[2]; i++)
6881                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6882                         return false;
6883
6884         return true;
6885 }
6886
6887 static void g4x_write_eld(struct drm_connector *connector,
6888                           struct drm_crtc *crtc,
6889                           struct drm_display_mode *mode)
6890 {
6891         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6892         uint8_t *eld = connector->eld;
6893         uint32_t eldv;
6894         uint32_t len;
6895         uint32_t i;
6896
6897         i = I915_READ(G4X_AUD_VID_DID);
6898
6899         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6900                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6901         else
6902                 eldv = G4X_ELDV_DEVCTG;
6903
6904         if (intel_eld_uptodate(connector,
6905                                G4X_AUD_CNTL_ST, eldv,
6906                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6907                                G4X_HDMIW_HDMIEDID))
6908                 return;
6909
6910         i = I915_READ(G4X_AUD_CNTL_ST);
6911         i &= ~(eldv | G4X_ELD_ADDR);
6912         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6913         I915_WRITE(G4X_AUD_CNTL_ST, i);
6914
6915         if (!eld[0])
6916                 return;
6917
6918         len = min_t(uint8_t, eld[2], len);
6919         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6920         for (i = 0; i < len; i++)
6921                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6922
6923         i = I915_READ(G4X_AUD_CNTL_ST);
6924         i |= eldv;
6925         I915_WRITE(G4X_AUD_CNTL_ST, i);
6926 }
6927
6928 static void haswell_write_eld(struct drm_connector *connector,
6929                               struct drm_crtc *crtc,
6930                               struct drm_display_mode *mode)
6931 {
6932         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6933         uint8_t *eld = connector->eld;
6934         struct drm_device *dev = crtc->dev;
6935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6936         uint32_t eldv;
6937         uint32_t i;
6938         int len;
6939         int pipe = to_intel_crtc(crtc)->pipe;
6940         int tmp;
6941
6942         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6943         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6944         int aud_config = HSW_AUD_CFG(pipe);
6945         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6946
6947
6948         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6949
6950         /* Audio output enable */
6951         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6952         tmp = I915_READ(aud_cntrl_st2);
6953         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6954         I915_WRITE(aud_cntrl_st2, tmp);
6955
6956         /* Wait for 1 vertical blank */
6957         intel_wait_for_vblank(dev, pipe);
6958
6959         /* Set ELD valid state */
6960         tmp = I915_READ(aud_cntrl_st2);
6961         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6962         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6963         I915_WRITE(aud_cntrl_st2, tmp);
6964         tmp = I915_READ(aud_cntrl_st2);
6965         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6966
6967         /* Enable HDMI mode */
6968         tmp = I915_READ(aud_config);
6969         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6970         /* clear N_programing_enable and N_value_index */
6971         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6972         I915_WRITE(aud_config, tmp);
6973
6974         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6975
6976         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6977         intel_crtc->eld_vld = true;
6978
6979         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6980                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6981                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6982                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6983         } else {
6984                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6985         }
6986
6987         if (intel_eld_uptodate(connector,
6988                                aud_cntrl_st2, eldv,
6989                                aud_cntl_st, IBX_ELD_ADDRESS,
6990                                hdmiw_hdmiedid))
6991                 return;
6992
6993         i = I915_READ(aud_cntrl_st2);
6994         i &= ~eldv;
6995         I915_WRITE(aud_cntrl_st2, i);
6996
6997         if (!eld[0])
6998                 return;
6999
7000         i = I915_READ(aud_cntl_st);
7001         i &= ~IBX_ELD_ADDRESS;
7002         I915_WRITE(aud_cntl_st, i);
7003         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7004         DRM_DEBUG_DRIVER("port num:%d\n", i);
7005
7006         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7007         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7008         for (i = 0; i < len; i++)
7009                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7010
7011         i = I915_READ(aud_cntrl_st2);
7012         i |= eldv;
7013         I915_WRITE(aud_cntrl_st2, i);
7014
7015 }
7016
7017 static void ironlake_write_eld(struct drm_connector *connector,
7018                                struct drm_crtc *crtc,
7019                                struct drm_display_mode *mode)
7020 {
7021         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7022         uint8_t *eld = connector->eld;
7023         uint32_t eldv;
7024         uint32_t i;
7025         int len;
7026         int hdmiw_hdmiedid;
7027         int aud_config;
7028         int aud_cntl_st;
7029         int aud_cntrl_st2;
7030         int pipe = to_intel_crtc(crtc)->pipe;
7031
7032         if (HAS_PCH_IBX(connector->dev)) {
7033                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7034                 aud_config = IBX_AUD_CFG(pipe);
7035                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7036                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7037         } else if (IS_VALLEYVIEW(connector->dev)) {
7038                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7039                 aud_config = VLV_AUD_CFG(pipe);
7040                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7041                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7042         } else {
7043                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7044                 aud_config = CPT_AUD_CFG(pipe);
7045                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7046                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7047         }
7048
7049         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7050
7051         if (IS_VALLEYVIEW(connector->dev))  {
7052                 struct intel_encoder *intel_encoder;
7053                 struct intel_digital_port *intel_dig_port;
7054
7055                 intel_encoder = intel_attached_encoder(connector);
7056                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7057                 i = intel_dig_port->port;
7058         } else {
7059                 i = I915_READ(aud_cntl_st);
7060                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7061                 /* DIP_Port_Select, 0x1 = PortB */
7062         }
7063
7064         if (!i) {
7065                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7066                 /* operate blindly on all ports */
7067                 eldv = IBX_ELD_VALIDB;
7068                 eldv |= IBX_ELD_VALIDB << 4;
7069                 eldv |= IBX_ELD_VALIDB << 8;
7070         } else {
7071                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7072                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7073         }
7074
7075         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7076                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7077                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7078                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7079         } else {
7080                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7081         }
7082
7083         if (intel_eld_uptodate(connector,
7084                                aud_cntrl_st2, eldv,
7085                                aud_cntl_st, IBX_ELD_ADDRESS,
7086                                hdmiw_hdmiedid))
7087                 return;
7088
7089         i = I915_READ(aud_cntrl_st2);
7090         i &= ~eldv;
7091         I915_WRITE(aud_cntrl_st2, i);
7092
7093         if (!eld[0])
7094                 return;
7095
7096         i = I915_READ(aud_cntl_st);
7097         i &= ~IBX_ELD_ADDRESS;
7098         I915_WRITE(aud_cntl_st, i);
7099
7100         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7101         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7102         for (i = 0; i < len; i++)
7103                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7104
7105         i = I915_READ(aud_cntrl_st2);
7106         i |= eldv;
7107         I915_WRITE(aud_cntrl_st2, i);
7108 }
7109
7110 void intel_write_eld(struct drm_encoder *encoder,
7111                      struct drm_display_mode *mode)
7112 {
7113         struct drm_crtc *crtc = encoder->crtc;
7114         struct drm_connector *connector;
7115         struct drm_device *dev = encoder->dev;
7116         struct drm_i915_private *dev_priv = dev->dev_private;
7117
7118         connector = drm_select_eld(encoder, mode);
7119         if (!connector)
7120                 return;
7121
7122         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7123                          connector->base.id,
7124                          drm_get_connector_name(connector),
7125                          connector->encoder->base.id,
7126                          drm_get_encoder_name(connector->encoder));
7127
7128         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7129
7130         if (dev_priv->display.write_eld)
7131                 dev_priv->display.write_eld(connector, crtc, mode);
7132 }
7133
7134 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7135 {
7136         struct drm_device *dev = crtc->dev;
7137         struct drm_i915_private *dev_priv = dev->dev_private;
7138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7139         bool visible = base != 0;
7140         u32 cntl;
7141
7142         if (intel_crtc->cursor_visible == visible)
7143                 return;
7144
7145         cntl = I915_READ(_CURACNTR);
7146         if (visible) {
7147                 /* On these chipsets we can only modify the base whilst
7148                  * the cursor is disabled.
7149                  */
7150                 I915_WRITE(_CURABASE, base);
7151
7152                 cntl &= ~(CURSOR_FORMAT_MASK);
7153                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7154                 cntl |= CURSOR_ENABLE |
7155                         CURSOR_GAMMA_ENABLE |
7156                         CURSOR_FORMAT_ARGB;
7157         } else
7158                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7159         I915_WRITE(_CURACNTR, cntl);
7160
7161         intel_crtc->cursor_visible = visible;
7162 }
7163
7164 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7165 {
7166         struct drm_device *dev = crtc->dev;
7167         struct drm_i915_private *dev_priv = dev->dev_private;
7168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7169         int pipe = intel_crtc->pipe;
7170         bool visible = base != 0;
7171
7172         if (intel_crtc->cursor_visible != visible) {
7173                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7174                 if (base) {
7175                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7176                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7177                         cntl |= pipe << 28; /* Connect to correct pipe */
7178                 } else {
7179                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7180                         cntl |= CURSOR_MODE_DISABLE;
7181                 }
7182                 I915_WRITE(CURCNTR(pipe), cntl);
7183
7184                 intel_crtc->cursor_visible = visible;
7185         }
7186         /* and commit changes on next vblank */
7187         I915_WRITE(CURBASE(pipe), base);
7188 }
7189
7190 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7191 {
7192         struct drm_device *dev = crtc->dev;
7193         struct drm_i915_private *dev_priv = dev->dev_private;
7194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195         int pipe = intel_crtc->pipe;
7196         bool visible = base != 0;
7197
7198         if (intel_crtc->cursor_visible != visible) {
7199                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7200                 if (base) {
7201                         cntl &= ~CURSOR_MODE;
7202                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7203                 } else {
7204                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7205                         cntl |= CURSOR_MODE_DISABLE;
7206                 }
7207                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7208                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7209                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7210                 }
7211                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7212
7213                 intel_crtc->cursor_visible = visible;
7214         }
7215         /* and commit changes on next vblank */
7216         I915_WRITE(CURBASE_IVB(pipe), base);
7217 }
7218
7219 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7220 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7221                                      bool on)
7222 {
7223         struct drm_device *dev = crtc->dev;
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7226         int pipe = intel_crtc->pipe;
7227         int x = intel_crtc->cursor_x;
7228         int y = intel_crtc->cursor_y;
7229         u32 base = 0, pos = 0;
7230         bool visible;
7231
7232         if (on)
7233                 base = intel_crtc->cursor_addr;
7234
7235         if (x >= intel_crtc->config.pipe_src_w)
7236                 base = 0;
7237
7238         if (y >= intel_crtc->config.pipe_src_h)
7239                 base = 0;
7240
7241         if (x < 0) {
7242                 if (x + intel_crtc->cursor_width <= 0)
7243                         base = 0;
7244
7245                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7246                 x = -x;
7247         }
7248         pos |= x << CURSOR_X_SHIFT;
7249
7250         if (y < 0) {
7251                 if (y + intel_crtc->cursor_height <= 0)
7252                         base = 0;
7253
7254                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7255                 y = -y;
7256         }
7257         pos |= y << CURSOR_Y_SHIFT;
7258
7259         visible = base != 0;
7260         if (!visible && !intel_crtc->cursor_visible)
7261                 return;
7262
7263         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7264                 I915_WRITE(CURPOS_IVB(pipe), pos);
7265                 ivb_update_cursor(crtc, base);
7266         } else {
7267                 I915_WRITE(CURPOS(pipe), pos);
7268                 if (IS_845G(dev) || IS_I865G(dev))
7269                         i845_update_cursor(crtc, base);
7270                 else
7271                         i9xx_update_cursor(crtc, base);
7272         }
7273 }
7274
7275 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7276                                  struct drm_file *file,
7277                                  uint32_t handle,
7278                                  uint32_t width, uint32_t height)
7279 {
7280         struct drm_device *dev = crtc->dev;
7281         struct drm_i915_private *dev_priv = dev->dev_private;
7282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7283         struct drm_i915_gem_object *obj;
7284         uint32_t addr;
7285         int ret;
7286
7287         /* if we want to turn off the cursor ignore width and height */
7288         if (!handle) {
7289                 DRM_DEBUG_KMS("cursor off\n");
7290                 addr = 0;
7291                 obj = NULL;
7292                 mutex_lock(&dev->struct_mutex);
7293                 goto finish;
7294         }
7295
7296         /* Currently we only support 64x64 cursors */
7297         if (width != 64 || height != 64) {
7298                 DRM_ERROR("we currently only support 64x64 cursors\n");
7299                 return -EINVAL;
7300         }
7301
7302         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7303         if (&obj->base == NULL)
7304                 return -ENOENT;
7305
7306         if (obj->base.size < width * height * 4) {
7307                 DRM_ERROR("buffer is to small\n");
7308                 ret = -ENOMEM;
7309                 goto fail;
7310         }
7311
7312         /* we only need to pin inside GTT if cursor is non-phy */
7313         mutex_lock(&dev->struct_mutex);
7314         if (!dev_priv->info->cursor_needs_physical) {
7315                 unsigned alignment;
7316
7317                 if (obj->tiling_mode) {
7318                         DRM_ERROR("cursor cannot be tiled\n");
7319                         ret = -EINVAL;
7320                         goto fail_locked;
7321                 }
7322
7323                 /* Note that the w/a also requires 2 PTE of padding following
7324                  * the bo. We currently fill all unused PTE with the shadow
7325                  * page and so we should always have valid PTE following the
7326                  * cursor preventing the VT-d warning.
7327                  */
7328                 alignment = 0;
7329                 if (need_vtd_wa(dev))
7330                         alignment = 64*1024;
7331
7332                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7333                 if (ret) {
7334                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7335                         goto fail_locked;
7336                 }
7337
7338                 ret = i915_gem_object_put_fence(obj);
7339                 if (ret) {
7340                         DRM_ERROR("failed to release fence for cursor");
7341                         goto fail_unpin;
7342                 }
7343
7344                 addr = i915_gem_obj_ggtt_offset(obj);
7345         } else {
7346                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7347                 ret = i915_gem_attach_phys_object(dev, obj,
7348                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7349                                                   align);
7350                 if (ret) {
7351                         DRM_ERROR("failed to attach phys object\n");
7352                         goto fail_locked;
7353                 }
7354                 addr = obj->phys_obj->handle->busaddr;
7355         }
7356
7357         if (IS_GEN2(dev))
7358                 I915_WRITE(CURSIZE, (height << 12) | width);
7359
7360  finish:
7361         if (intel_crtc->cursor_bo) {
7362                 if (dev_priv->info->cursor_needs_physical) {
7363                         if (intel_crtc->cursor_bo != obj)
7364                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7365                 } else
7366                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7367                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7368         }
7369
7370         mutex_unlock(&dev->struct_mutex);
7371
7372         intel_crtc->cursor_addr = addr;
7373         intel_crtc->cursor_bo = obj;
7374         intel_crtc->cursor_width = width;
7375         intel_crtc->cursor_height = height;
7376
7377         if (intel_crtc->active)
7378                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7379
7380         return 0;
7381 fail_unpin:
7382         i915_gem_object_unpin_from_display_plane(obj);
7383 fail_locked:
7384         mutex_unlock(&dev->struct_mutex);
7385 fail:
7386         drm_gem_object_unreference_unlocked(&obj->base);
7387         return ret;
7388 }
7389
7390 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7391 {
7392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7393
7394         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7395         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7396
7397         if (intel_crtc->active)
7398                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7399
7400         return 0;
7401 }
7402
7403 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7404                                  u16 *blue, uint32_t start, uint32_t size)
7405 {
7406         int end = (start + size > 256) ? 256 : start + size, i;
7407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7408
7409         for (i = start; i < end; i++) {
7410                 intel_crtc->lut_r[i] = red[i] >> 8;
7411                 intel_crtc->lut_g[i] = green[i] >> 8;
7412                 intel_crtc->lut_b[i] = blue[i] >> 8;
7413         }
7414
7415         intel_crtc_load_lut(crtc);
7416 }
7417
7418 /* VESA 640x480x72Hz mode to set on the pipe */
7419 static struct drm_display_mode load_detect_mode = {
7420         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7421                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7422 };
7423
7424 static struct drm_framebuffer *
7425 intel_framebuffer_create(struct drm_device *dev,
7426                          struct drm_mode_fb_cmd2 *mode_cmd,
7427                          struct drm_i915_gem_object *obj)
7428 {
7429         struct intel_framebuffer *intel_fb;
7430         int ret;
7431
7432         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7433         if (!intel_fb) {
7434                 drm_gem_object_unreference_unlocked(&obj->base);
7435                 return ERR_PTR(-ENOMEM);
7436         }
7437
7438         ret = i915_mutex_lock_interruptible(dev);
7439         if (ret)
7440                 goto err;
7441
7442         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7443         mutex_unlock(&dev->struct_mutex);
7444         if (ret)
7445                 goto err;
7446
7447         return &intel_fb->base;
7448 err:
7449         drm_gem_object_unreference_unlocked(&obj->base);
7450         kfree(intel_fb);
7451
7452         return ERR_PTR(ret);
7453 }
7454
7455 static u32
7456 intel_framebuffer_pitch_for_width(int width, int bpp)
7457 {
7458         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7459         return ALIGN(pitch, 64);
7460 }
7461
7462 static u32
7463 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7464 {
7465         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7466         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7467 }
7468
7469 static struct drm_framebuffer *
7470 intel_framebuffer_create_for_mode(struct drm_device *dev,
7471                                   struct drm_display_mode *mode,
7472                                   int depth, int bpp)
7473 {
7474         struct drm_i915_gem_object *obj;
7475         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7476
7477         obj = i915_gem_alloc_object(dev,
7478                                     intel_framebuffer_size_for_mode(mode, bpp));
7479         if (obj == NULL)
7480                 return ERR_PTR(-ENOMEM);
7481
7482         mode_cmd.width = mode->hdisplay;
7483         mode_cmd.height = mode->vdisplay;
7484         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7485                                                                 bpp);
7486         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7487
7488         return intel_framebuffer_create(dev, &mode_cmd, obj);
7489 }
7490
7491 static struct drm_framebuffer *
7492 mode_fits_in_fbdev(struct drm_device *dev,
7493                    struct drm_display_mode *mode)
7494 {
7495 #ifdef CONFIG_DRM_I915_FBDEV
7496         struct drm_i915_private *dev_priv = dev->dev_private;
7497         struct drm_i915_gem_object *obj;
7498         struct drm_framebuffer *fb;
7499
7500         if (dev_priv->fbdev == NULL)
7501                 return NULL;
7502
7503         obj = dev_priv->fbdev->ifb.obj;
7504         if (obj == NULL)
7505                 return NULL;
7506
7507         fb = &dev_priv->fbdev->ifb.base;
7508         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7509                                                                fb->bits_per_pixel))
7510                 return NULL;
7511
7512         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7513                 return NULL;
7514
7515         return fb;
7516 #else
7517         return NULL;
7518 #endif
7519 }
7520
7521 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7522                                 struct drm_display_mode *mode,
7523                                 struct intel_load_detect_pipe *old)
7524 {
7525         struct intel_crtc *intel_crtc;
7526         struct intel_encoder *intel_encoder =
7527                 intel_attached_encoder(connector);
7528         struct drm_crtc *possible_crtc;
7529         struct drm_encoder *encoder = &intel_encoder->base;
7530         struct drm_crtc *crtc = NULL;
7531         struct drm_device *dev = encoder->dev;
7532         struct drm_framebuffer *fb;
7533         int i = -1;
7534
7535         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7536                       connector->base.id, drm_get_connector_name(connector),
7537                       encoder->base.id, drm_get_encoder_name(encoder));
7538
7539         /*
7540          * Algorithm gets a little messy:
7541          *
7542          *   - if the connector already has an assigned crtc, use it (but make
7543          *     sure it's on first)
7544          *
7545          *   - try to find the first unused crtc that can drive this connector,
7546          *     and use that if we find one
7547          */
7548
7549         /* See if we already have a CRTC for this connector */
7550         if (encoder->crtc) {
7551                 crtc = encoder->crtc;
7552
7553                 mutex_lock(&crtc->mutex);
7554
7555                 old->dpms_mode = connector->dpms;
7556                 old->load_detect_temp = false;
7557
7558                 /* Make sure the crtc and connector are running */
7559                 if (connector->dpms != DRM_MODE_DPMS_ON)
7560                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7561
7562                 return true;
7563         }
7564
7565         /* Find an unused one (if possible) */
7566         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7567                 i++;
7568                 if (!(encoder->possible_crtcs & (1 << i)))
7569                         continue;
7570                 if (!possible_crtc->enabled) {
7571                         crtc = possible_crtc;
7572                         break;
7573                 }
7574         }
7575
7576         /*
7577          * If we didn't find an unused CRTC, don't use any.
7578          */
7579         if (!crtc) {
7580                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7581                 return false;
7582         }
7583
7584         mutex_lock(&crtc->mutex);
7585         intel_encoder->new_crtc = to_intel_crtc(crtc);
7586         to_intel_connector(connector)->new_encoder = intel_encoder;
7587
7588         intel_crtc = to_intel_crtc(crtc);
7589         old->dpms_mode = connector->dpms;
7590         old->load_detect_temp = true;
7591         old->release_fb = NULL;
7592
7593         if (!mode)
7594                 mode = &load_detect_mode;
7595
7596         /* We need a framebuffer large enough to accommodate all accesses
7597          * that the plane may generate whilst we perform load detection.
7598          * We can not rely on the fbcon either being present (we get called
7599          * during its initialisation to detect all boot displays, or it may
7600          * not even exist) or that it is large enough to satisfy the
7601          * requested mode.
7602          */
7603         fb = mode_fits_in_fbdev(dev, mode);
7604         if (fb == NULL) {
7605                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7606                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7607                 old->release_fb = fb;
7608         } else
7609                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7610         if (IS_ERR(fb)) {
7611                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7612                 mutex_unlock(&crtc->mutex);
7613                 return false;
7614         }
7615
7616         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7617                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7618                 if (old->release_fb)
7619                         old->release_fb->funcs->destroy(old->release_fb);
7620                 mutex_unlock(&crtc->mutex);
7621                 return false;
7622         }
7623
7624         /* let the connector get through one full cycle before testing */
7625         intel_wait_for_vblank(dev, intel_crtc->pipe);
7626         return true;
7627 }
7628
7629 void intel_release_load_detect_pipe(struct drm_connector *connector,
7630                                     struct intel_load_detect_pipe *old)
7631 {
7632         struct intel_encoder *intel_encoder =
7633                 intel_attached_encoder(connector);
7634         struct drm_encoder *encoder = &intel_encoder->base;
7635         struct drm_crtc *crtc = encoder->crtc;
7636
7637         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7638                       connector->base.id, drm_get_connector_name(connector),
7639                       encoder->base.id, drm_get_encoder_name(encoder));
7640
7641         if (old->load_detect_temp) {
7642                 to_intel_connector(connector)->new_encoder = NULL;
7643                 intel_encoder->new_crtc = NULL;
7644                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7645
7646                 if (old->release_fb) {
7647                         drm_framebuffer_unregister_private(old->release_fb);
7648                         drm_framebuffer_unreference(old->release_fb);
7649                 }
7650
7651                 mutex_unlock(&crtc->mutex);
7652                 return;
7653         }
7654
7655         /* Switch crtc and encoder back off if necessary */
7656         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7657                 connector->funcs->dpms(connector, old->dpms_mode);
7658
7659         mutex_unlock(&crtc->mutex);
7660 }
7661
7662 static int i9xx_pll_refclk(struct drm_device *dev,
7663                            const struct intel_crtc_config *pipe_config)
7664 {
7665         struct drm_i915_private *dev_priv = dev->dev_private;
7666         u32 dpll = pipe_config->dpll_hw_state.dpll;
7667
7668         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7669                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7670         else if (HAS_PCH_SPLIT(dev))
7671                 return 120000;
7672         else if (!IS_GEN2(dev))
7673                 return 96000;
7674         else
7675                 return 48000;
7676 }
7677
7678 /* Returns the clock of the currently programmed mode of the given pipe. */
7679 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7680                                 struct intel_crtc_config *pipe_config)
7681 {
7682         struct drm_device *dev = crtc->base.dev;
7683         struct drm_i915_private *dev_priv = dev->dev_private;
7684         int pipe = pipe_config->cpu_transcoder;
7685         u32 dpll = pipe_config->dpll_hw_state.dpll;
7686         u32 fp;
7687         intel_clock_t clock;
7688         int refclk = i9xx_pll_refclk(dev, pipe_config);
7689
7690         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7691                 fp = pipe_config->dpll_hw_state.fp0;
7692         else
7693                 fp = pipe_config->dpll_hw_state.fp1;
7694
7695         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7696         if (IS_PINEVIEW(dev)) {
7697                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7698                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7699         } else {
7700                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7701                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7702         }
7703
7704         if (!IS_GEN2(dev)) {
7705                 if (IS_PINEVIEW(dev))
7706                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7707                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7708                 else
7709                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7710                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7711
7712                 switch (dpll & DPLL_MODE_MASK) {
7713                 case DPLLB_MODE_DAC_SERIAL:
7714                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7715                                 5 : 10;
7716                         break;
7717                 case DPLLB_MODE_LVDS:
7718                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7719                                 7 : 14;
7720                         break;
7721                 default:
7722                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7723                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7724                         return;
7725                 }
7726
7727                 if (IS_PINEVIEW(dev))
7728                         pineview_clock(refclk, &clock);
7729                 else
7730                         i9xx_clock(refclk, &clock);
7731         } else {
7732                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7733
7734                 if (is_lvds) {
7735                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7736                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7737                         clock.p2 = 14;
7738                 } else {
7739                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7740                                 clock.p1 = 2;
7741                         else {
7742                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7743                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7744                         }
7745                         if (dpll & PLL_P2_DIVIDE_BY_4)
7746                                 clock.p2 = 4;
7747                         else
7748                                 clock.p2 = 2;
7749                 }
7750
7751                 i9xx_clock(refclk, &clock);
7752         }
7753
7754         /*
7755          * This value includes pixel_multiplier. We will use
7756          * port_clock to compute adjusted_mode.crtc_clock in the
7757          * encoder's get_config() function.
7758          */
7759         pipe_config->port_clock = clock.dot;
7760 }
7761
7762 int intel_dotclock_calculate(int link_freq,
7763                              const struct intel_link_m_n *m_n)
7764 {
7765         /*
7766          * The calculation for the data clock is:
7767          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7768          * But we want to avoid losing precison if possible, so:
7769          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7770          *
7771          * and the link clock is simpler:
7772          * link_clock = (m * link_clock) / n
7773          */
7774
7775         if (!m_n->link_n)
7776                 return 0;
7777
7778         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7779 }
7780
7781 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7782                                    struct intel_crtc_config *pipe_config)
7783 {
7784         struct drm_device *dev = crtc->base.dev;
7785
7786         /* read out port_clock from the DPLL */
7787         i9xx_crtc_clock_get(crtc, pipe_config);
7788
7789         /*
7790          * This value does not include pixel_multiplier.
7791          * We will check that port_clock and adjusted_mode.crtc_clock
7792          * agree once we know their relationship in the encoder's
7793          * get_config() function.
7794          */
7795         pipe_config->adjusted_mode.crtc_clock =
7796                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7797                                          &pipe_config->fdi_m_n);
7798 }
7799
7800 /** Returns the currently programmed mode of the given pipe. */
7801 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7802                                              struct drm_crtc *crtc)
7803 {
7804         struct drm_i915_private *dev_priv = dev->dev_private;
7805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7806         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7807         struct drm_display_mode *mode;
7808         struct intel_crtc_config pipe_config;
7809         int htot = I915_READ(HTOTAL(cpu_transcoder));
7810         int hsync = I915_READ(HSYNC(cpu_transcoder));
7811         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7812         int vsync = I915_READ(VSYNC(cpu_transcoder));
7813         enum pipe pipe = intel_crtc->pipe;
7814
7815         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7816         if (!mode)
7817                 return NULL;
7818
7819         /*
7820          * Construct a pipe_config sufficient for getting the clock info
7821          * back out of crtc_clock_get.
7822          *
7823          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7824          * to use a real value here instead.
7825          */
7826         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7827         pipe_config.pixel_multiplier = 1;
7828         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7829         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7830         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7831         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7832
7833         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7834         mode->hdisplay = (htot & 0xffff) + 1;
7835         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7836         mode->hsync_start = (hsync & 0xffff) + 1;
7837         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7838         mode->vdisplay = (vtot & 0xffff) + 1;
7839         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7840         mode->vsync_start = (vsync & 0xffff) + 1;
7841         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7842
7843         drm_mode_set_name(mode);
7844
7845         return mode;
7846 }
7847
7848 static void intel_increase_pllclock(struct drm_crtc *crtc)
7849 {
7850         struct drm_device *dev = crtc->dev;
7851         drm_i915_private_t *dev_priv = dev->dev_private;
7852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7853         int pipe = intel_crtc->pipe;
7854         int dpll_reg = DPLL(pipe);
7855         int dpll;
7856
7857         if (HAS_PCH_SPLIT(dev))
7858                 return;
7859
7860         if (!dev_priv->lvds_downclock_avail)
7861                 return;
7862
7863         dpll = I915_READ(dpll_reg);
7864         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7865                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7866
7867                 assert_panel_unlocked(dev_priv, pipe);
7868
7869                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7870                 I915_WRITE(dpll_reg, dpll);
7871                 intel_wait_for_vblank(dev, pipe);
7872
7873                 dpll = I915_READ(dpll_reg);
7874                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7875                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7876         }
7877 }
7878
7879 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7880 {
7881         struct drm_device *dev = crtc->dev;
7882         drm_i915_private_t *dev_priv = dev->dev_private;
7883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7884
7885         if (HAS_PCH_SPLIT(dev))
7886                 return;
7887
7888         if (!dev_priv->lvds_downclock_avail)
7889                 return;
7890
7891         /*
7892          * Since this is called by a timer, we should never get here in
7893          * the manual case.
7894          */
7895         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7896                 int pipe = intel_crtc->pipe;
7897                 int dpll_reg = DPLL(pipe);
7898                 int dpll;
7899
7900                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7901
7902                 assert_panel_unlocked(dev_priv, pipe);
7903
7904                 dpll = I915_READ(dpll_reg);
7905                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7906                 I915_WRITE(dpll_reg, dpll);
7907                 intel_wait_for_vblank(dev, pipe);
7908                 dpll = I915_READ(dpll_reg);
7909                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7910                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7911         }
7912
7913 }
7914
7915 void intel_mark_busy(struct drm_device *dev)
7916 {
7917         struct drm_i915_private *dev_priv = dev->dev_private;
7918
7919         hsw_package_c8_gpu_busy(dev_priv);
7920         i915_update_gfx_val(dev_priv);
7921 }
7922
7923 void intel_mark_idle(struct drm_device *dev)
7924 {
7925         struct drm_i915_private *dev_priv = dev->dev_private;
7926         struct drm_crtc *crtc;
7927
7928         hsw_package_c8_gpu_idle(dev_priv);
7929
7930         if (!i915_powersave)
7931                 return;
7932
7933         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7934                 if (!crtc->fb)
7935                         continue;
7936
7937                 intel_decrease_pllclock(crtc);
7938         }
7939
7940         if (dev_priv->info->gen >= 6)
7941                 gen6_rps_idle(dev->dev_private);
7942 }
7943
7944 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7945                         struct intel_ring_buffer *ring)
7946 {
7947         struct drm_device *dev = obj->base.dev;
7948         struct drm_crtc *crtc;
7949
7950         if (!i915_powersave)
7951                 return;
7952
7953         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7954                 if (!crtc->fb)
7955                         continue;
7956
7957                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7958                         continue;
7959
7960                 intel_increase_pllclock(crtc);
7961                 if (ring && intel_fbc_enabled(dev))
7962                         ring->fbc_dirty = true;
7963         }
7964 }
7965
7966 static void intel_crtc_destroy(struct drm_crtc *crtc)
7967 {
7968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7969         struct drm_device *dev = crtc->dev;
7970         struct intel_unpin_work *work;
7971         unsigned long flags;
7972
7973         spin_lock_irqsave(&dev->event_lock, flags);
7974         work = intel_crtc->unpin_work;
7975         intel_crtc->unpin_work = NULL;
7976         spin_unlock_irqrestore(&dev->event_lock, flags);
7977
7978         if (work) {
7979                 cancel_work_sync(&work->work);
7980                 kfree(work);
7981         }
7982
7983         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7984
7985         drm_crtc_cleanup(crtc);
7986
7987         kfree(intel_crtc);
7988 }
7989
7990 static void intel_unpin_work_fn(struct work_struct *__work)
7991 {
7992         struct intel_unpin_work *work =
7993                 container_of(__work, struct intel_unpin_work, work);
7994         struct drm_device *dev = work->crtc->dev;
7995
7996         mutex_lock(&dev->struct_mutex);
7997         intel_unpin_fb_obj(work->old_fb_obj);
7998         drm_gem_object_unreference(&work->pending_flip_obj->base);
7999         drm_gem_object_unreference(&work->old_fb_obj->base);
8000
8001         intel_update_fbc(dev);
8002         mutex_unlock(&dev->struct_mutex);
8003
8004         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8005         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8006
8007         kfree(work);
8008 }
8009
8010 static void do_intel_finish_page_flip(struct drm_device *dev,
8011                                       struct drm_crtc *crtc)
8012 {
8013         drm_i915_private_t *dev_priv = dev->dev_private;
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         struct intel_unpin_work *work;
8016         unsigned long flags;
8017
8018         /* Ignore early vblank irqs */
8019         if (intel_crtc == NULL)
8020                 return;
8021
8022         spin_lock_irqsave(&dev->event_lock, flags);
8023         work = intel_crtc->unpin_work;
8024
8025         /* Ensure we don't miss a work->pending update ... */
8026         smp_rmb();
8027
8028         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8029                 spin_unlock_irqrestore(&dev->event_lock, flags);
8030                 return;
8031         }
8032
8033         /* and that the unpin work is consistent wrt ->pending. */
8034         smp_rmb();
8035
8036         intel_crtc->unpin_work = NULL;
8037
8038         if (work->event)
8039                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8040
8041         drm_vblank_put(dev, intel_crtc->pipe);
8042
8043         spin_unlock_irqrestore(&dev->event_lock, flags);
8044
8045         wake_up_all(&dev_priv->pending_flip_queue);
8046
8047         queue_work(dev_priv->wq, &work->work);
8048
8049         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8050 }
8051
8052 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8053 {
8054         drm_i915_private_t *dev_priv = dev->dev_private;
8055         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8056
8057         do_intel_finish_page_flip(dev, crtc);
8058 }
8059
8060 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8061 {
8062         drm_i915_private_t *dev_priv = dev->dev_private;
8063         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8064
8065         do_intel_finish_page_flip(dev, crtc);
8066 }
8067
8068 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8069 {
8070         drm_i915_private_t *dev_priv = dev->dev_private;
8071         struct intel_crtc *intel_crtc =
8072                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8073         unsigned long flags;
8074
8075         /* NB: An MMIO update of the plane base pointer will also
8076          * generate a page-flip completion irq, i.e. every modeset
8077          * is also accompanied by a spurious intel_prepare_page_flip().
8078          */
8079         spin_lock_irqsave(&dev->event_lock, flags);
8080         if (intel_crtc->unpin_work)
8081                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8082         spin_unlock_irqrestore(&dev->event_lock, flags);
8083 }
8084
8085 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8086 {
8087         /* Ensure that the work item is consistent when activating it ... */
8088         smp_wmb();
8089         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8090         /* and that it is marked active as soon as the irq could fire. */
8091         smp_wmb();
8092 }
8093
8094 static int intel_gen2_queue_flip(struct drm_device *dev,
8095                                  struct drm_crtc *crtc,
8096                                  struct drm_framebuffer *fb,
8097                                  struct drm_i915_gem_object *obj,
8098                                  uint32_t flags)
8099 {
8100         struct drm_i915_private *dev_priv = dev->dev_private;
8101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8102         u32 flip_mask;
8103         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8104         int ret;
8105
8106         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8107         if (ret)
8108                 goto err;
8109
8110         ret = intel_ring_begin(ring, 6);
8111         if (ret)
8112                 goto err_unpin;
8113
8114         /* Can't queue multiple flips, so wait for the previous
8115          * one to finish before executing the next.
8116          */
8117         if (intel_crtc->plane)
8118                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8119         else
8120                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8121         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8122         intel_ring_emit(ring, MI_NOOP);
8123         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8124                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8125         intel_ring_emit(ring, fb->pitches[0]);
8126         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8127         intel_ring_emit(ring, 0); /* aux display base address, unused */
8128
8129         intel_mark_page_flip_active(intel_crtc);
8130         __intel_ring_advance(ring);
8131         return 0;
8132
8133 err_unpin:
8134         intel_unpin_fb_obj(obj);
8135 err:
8136         return ret;
8137 }
8138
8139 static int intel_gen3_queue_flip(struct drm_device *dev,
8140                                  struct drm_crtc *crtc,
8141                                  struct drm_framebuffer *fb,
8142                                  struct drm_i915_gem_object *obj,
8143                                  uint32_t flags)
8144 {
8145         struct drm_i915_private *dev_priv = dev->dev_private;
8146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8147         u32 flip_mask;
8148         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8149         int ret;
8150
8151         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8152         if (ret)
8153                 goto err;
8154
8155         ret = intel_ring_begin(ring, 6);
8156         if (ret)
8157                 goto err_unpin;
8158
8159         if (intel_crtc->plane)
8160                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8161         else
8162                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8163         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8164         intel_ring_emit(ring, MI_NOOP);
8165         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8166                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8167         intel_ring_emit(ring, fb->pitches[0]);
8168         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8169         intel_ring_emit(ring, MI_NOOP);
8170
8171         intel_mark_page_flip_active(intel_crtc);
8172         __intel_ring_advance(ring);
8173         return 0;
8174
8175 err_unpin:
8176         intel_unpin_fb_obj(obj);
8177 err:
8178         return ret;
8179 }
8180
8181 static int intel_gen4_queue_flip(struct drm_device *dev,
8182                                  struct drm_crtc *crtc,
8183                                  struct drm_framebuffer *fb,
8184                                  struct drm_i915_gem_object *obj,
8185                                  uint32_t flags)
8186 {
8187         struct drm_i915_private *dev_priv = dev->dev_private;
8188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8189         uint32_t pf, pipesrc;
8190         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8191         int ret;
8192
8193         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8194         if (ret)
8195                 goto err;
8196
8197         ret = intel_ring_begin(ring, 4);
8198         if (ret)
8199                 goto err_unpin;
8200
8201         /* i965+ uses the linear or tiled offsets from the
8202          * Display Registers (which do not change across a page-flip)
8203          * so we need only reprogram the base address.
8204          */
8205         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8206                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8207         intel_ring_emit(ring, fb->pitches[0]);
8208         intel_ring_emit(ring,
8209                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8210                         obj->tiling_mode);
8211
8212         /* XXX Enabling the panel-fitter across page-flip is so far
8213          * untested on non-native modes, so ignore it for now.
8214          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8215          */
8216         pf = 0;
8217         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8218         intel_ring_emit(ring, pf | pipesrc);
8219
8220         intel_mark_page_flip_active(intel_crtc);
8221         __intel_ring_advance(ring);
8222         return 0;
8223
8224 err_unpin:
8225         intel_unpin_fb_obj(obj);
8226 err:
8227         return ret;
8228 }
8229
8230 static int intel_gen6_queue_flip(struct drm_device *dev,
8231                                  struct drm_crtc *crtc,
8232                                  struct drm_framebuffer *fb,
8233                                  struct drm_i915_gem_object *obj,
8234                                  uint32_t flags)
8235 {
8236         struct drm_i915_private *dev_priv = dev->dev_private;
8237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8238         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8239         uint32_t pf, pipesrc;
8240         int ret;
8241
8242         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8243         if (ret)
8244                 goto err;
8245
8246         ret = intel_ring_begin(ring, 4);
8247         if (ret)
8248                 goto err_unpin;
8249
8250         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8251                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8252         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8253         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8254
8255         /* Contrary to the suggestions in the documentation,
8256          * "Enable Panel Fitter" does not seem to be required when page
8257          * flipping with a non-native mode, and worse causes a normal
8258          * modeset to fail.
8259          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8260          */
8261         pf = 0;
8262         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8263         intel_ring_emit(ring, pf | pipesrc);
8264
8265         intel_mark_page_flip_active(intel_crtc);
8266         __intel_ring_advance(ring);
8267         return 0;
8268
8269 err_unpin:
8270         intel_unpin_fb_obj(obj);
8271 err:
8272         return ret;
8273 }
8274
8275 static int intel_gen7_queue_flip(struct drm_device *dev,
8276                                  struct drm_crtc *crtc,
8277                                  struct drm_framebuffer *fb,
8278                                  struct drm_i915_gem_object *obj,
8279                                  uint32_t flags)
8280 {
8281         struct drm_i915_private *dev_priv = dev->dev_private;
8282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8283         struct intel_ring_buffer *ring;
8284         uint32_t plane_bit = 0;
8285         int len, ret;
8286
8287         ring = obj->ring;
8288         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8289                 ring = &dev_priv->ring[BCS];
8290
8291         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8292         if (ret)
8293                 goto err;
8294
8295         switch(intel_crtc->plane) {
8296         case PLANE_A:
8297                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8298                 break;
8299         case PLANE_B:
8300                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8301                 break;
8302         case PLANE_C:
8303                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8304                 break;
8305         default:
8306                 WARN_ONCE(1, "unknown plane in flip command\n");
8307                 ret = -ENODEV;
8308                 goto err_unpin;
8309         }
8310
8311         len = 4;
8312         if (ring->id == RCS)
8313                 len += 6;
8314
8315         ret = intel_ring_begin(ring, len);
8316         if (ret)
8317                 goto err_unpin;
8318
8319         /* Unmask the flip-done completion message. Note that the bspec says that
8320          * we should do this for both the BCS and RCS, and that we must not unmask
8321          * more than one flip event at any time (or ensure that one flip message
8322          * can be sent by waiting for flip-done prior to queueing new flips).
8323          * Experimentation says that BCS works despite DERRMR masking all
8324          * flip-done completion events and that unmasking all planes at once
8325          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8326          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8327          */
8328         if (ring->id == RCS) {
8329                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8330                 intel_ring_emit(ring, DERRMR);
8331                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8332                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8333                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8334                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8335                 intel_ring_emit(ring, DERRMR);
8336                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8337         }
8338
8339         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8340         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8341         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8342         intel_ring_emit(ring, (MI_NOOP));
8343
8344         intel_mark_page_flip_active(intel_crtc);
8345         __intel_ring_advance(ring);
8346         return 0;
8347
8348 err_unpin:
8349         intel_unpin_fb_obj(obj);
8350 err:
8351         return ret;
8352 }
8353
8354 static int intel_default_queue_flip(struct drm_device *dev,
8355                                     struct drm_crtc *crtc,
8356                                     struct drm_framebuffer *fb,
8357                                     struct drm_i915_gem_object *obj,
8358                                     uint32_t flags)
8359 {
8360         return -ENODEV;
8361 }
8362
8363 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8364                                 struct drm_framebuffer *fb,
8365                                 struct drm_pending_vblank_event *event,
8366                                 uint32_t page_flip_flags)
8367 {
8368         struct drm_device *dev = crtc->dev;
8369         struct drm_i915_private *dev_priv = dev->dev_private;
8370         struct drm_framebuffer *old_fb = crtc->fb;
8371         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8373         struct intel_unpin_work *work;
8374         unsigned long flags;
8375         int ret;
8376
8377         /* Can't change pixel format via MI display flips. */
8378         if (fb->pixel_format != crtc->fb->pixel_format)
8379                 return -EINVAL;
8380
8381         /*
8382          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8383          * Note that pitch changes could also affect these register.
8384          */
8385         if (INTEL_INFO(dev)->gen > 3 &&
8386             (fb->offsets[0] != crtc->fb->offsets[0] ||
8387              fb->pitches[0] != crtc->fb->pitches[0]))
8388                 return -EINVAL;
8389
8390         work = kzalloc(sizeof(*work), GFP_KERNEL);
8391         if (work == NULL)
8392                 return -ENOMEM;
8393
8394         work->event = event;
8395         work->crtc = crtc;
8396         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8397         INIT_WORK(&work->work, intel_unpin_work_fn);
8398
8399         ret = drm_vblank_get(dev, intel_crtc->pipe);
8400         if (ret)
8401                 goto free_work;
8402
8403         /* We borrow the event spin lock for protecting unpin_work */
8404         spin_lock_irqsave(&dev->event_lock, flags);
8405         if (intel_crtc->unpin_work) {
8406                 spin_unlock_irqrestore(&dev->event_lock, flags);
8407                 kfree(work);
8408                 drm_vblank_put(dev, intel_crtc->pipe);
8409
8410                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8411                 return -EBUSY;
8412         }
8413         intel_crtc->unpin_work = work;
8414         spin_unlock_irqrestore(&dev->event_lock, flags);
8415
8416         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8417                 flush_workqueue(dev_priv->wq);
8418
8419         ret = i915_mutex_lock_interruptible(dev);
8420         if (ret)
8421                 goto cleanup;
8422
8423         /* Reference the objects for the scheduled work. */
8424         drm_gem_object_reference(&work->old_fb_obj->base);
8425         drm_gem_object_reference(&obj->base);
8426
8427         crtc->fb = fb;
8428
8429         work->pending_flip_obj = obj;
8430
8431         work->enable_stall_check = true;
8432
8433         atomic_inc(&intel_crtc->unpin_work_count);
8434         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8435
8436         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8437         if (ret)
8438                 goto cleanup_pending;
8439
8440         intel_disable_fbc(dev);
8441         intel_mark_fb_busy(obj, NULL);
8442         mutex_unlock(&dev->struct_mutex);
8443
8444         trace_i915_flip_request(intel_crtc->plane, obj);
8445
8446         return 0;
8447
8448 cleanup_pending:
8449         atomic_dec(&intel_crtc->unpin_work_count);
8450         crtc->fb = old_fb;
8451         drm_gem_object_unreference(&work->old_fb_obj->base);
8452         drm_gem_object_unreference(&obj->base);
8453         mutex_unlock(&dev->struct_mutex);
8454
8455 cleanup:
8456         spin_lock_irqsave(&dev->event_lock, flags);
8457         intel_crtc->unpin_work = NULL;
8458         spin_unlock_irqrestore(&dev->event_lock, flags);
8459
8460         drm_vblank_put(dev, intel_crtc->pipe);
8461 free_work:
8462         kfree(work);
8463
8464         return ret;
8465 }
8466
8467 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8468         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8469         .load_lut = intel_crtc_load_lut,
8470 };
8471
8472 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8473                                   struct drm_crtc *crtc)
8474 {
8475         struct drm_device *dev;
8476         struct drm_crtc *tmp;
8477         int crtc_mask = 1;
8478
8479         WARN(!crtc, "checking null crtc?\n");
8480
8481         dev = crtc->dev;
8482
8483         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8484                 if (tmp == crtc)
8485                         break;
8486                 crtc_mask <<= 1;
8487         }
8488
8489         if (encoder->possible_crtcs & crtc_mask)
8490                 return true;
8491         return false;
8492 }
8493
8494 /**
8495  * intel_modeset_update_staged_output_state
8496  *
8497  * Updates the staged output configuration state, e.g. after we've read out the
8498  * current hw state.
8499  */
8500 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8501 {
8502         struct intel_encoder *encoder;
8503         struct intel_connector *connector;
8504
8505         list_for_each_entry(connector, &dev->mode_config.connector_list,
8506                             base.head) {
8507                 connector->new_encoder =
8508                         to_intel_encoder(connector->base.encoder);
8509         }
8510
8511         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8512                             base.head) {
8513                 encoder->new_crtc =
8514                         to_intel_crtc(encoder->base.crtc);
8515         }
8516 }
8517
8518 /**
8519  * intel_modeset_commit_output_state
8520  *
8521  * This function copies the stage display pipe configuration to the real one.
8522  */
8523 static void intel_modeset_commit_output_state(struct drm_device *dev)
8524 {
8525         struct intel_encoder *encoder;
8526         struct intel_connector *connector;
8527
8528         list_for_each_entry(connector, &dev->mode_config.connector_list,
8529                             base.head) {
8530                 connector->base.encoder = &connector->new_encoder->base;
8531         }
8532
8533         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8534                             base.head) {
8535                 encoder->base.crtc = &encoder->new_crtc->base;
8536         }
8537 }
8538
8539 static void
8540 connected_sink_compute_bpp(struct intel_connector * connector,
8541                            struct intel_crtc_config *pipe_config)
8542 {
8543         int bpp = pipe_config->pipe_bpp;
8544
8545         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8546                 connector->base.base.id,
8547                 drm_get_connector_name(&connector->base));
8548
8549         /* Don't use an invalid EDID bpc value */
8550         if (connector->base.display_info.bpc &&
8551             connector->base.display_info.bpc * 3 < bpp) {
8552                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8553                               bpp, connector->base.display_info.bpc*3);
8554                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8555         }
8556
8557         /* Clamp bpp to 8 on screens without EDID 1.4 */
8558         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8559                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8560                               bpp);
8561                 pipe_config->pipe_bpp = 24;
8562         }
8563 }
8564
8565 static int
8566 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8567                           struct drm_framebuffer *fb,
8568                           struct intel_crtc_config *pipe_config)
8569 {
8570         struct drm_device *dev = crtc->base.dev;
8571         struct intel_connector *connector;
8572         int bpp;
8573
8574         switch (fb->pixel_format) {
8575         case DRM_FORMAT_C8:
8576                 bpp = 8*3; /* since we go through a colormap */
8577                 break;
8578         case DRM_FORMAT_XRGB1555:
8579         case DRM_FORMAT_ARGB1555:
8580                 /* checked in intel_framebuffer_init already */
8581                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8582                         return -EINVAL;
8583         case DRM_FORMAT_RGB565:
8584                 bpp = 6*3; /* min is 18bpp */
8585                 break;
8586         case DRM_FORMAT_XBGR8888:
8587         case DRM_FORMAT_ABGR8888:
8588                 /* checked in intel_framebuffer_init already */
8589                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8590                         return -EINVAL;
8591         case DRM_FORMAT_XRGB8888:
8592         case DRM_FORMAT_ARGB8888:
8593                 bpp = 8*3;
8594                 break;
8595         case DRM_FORMAT_XRGB2101010:
8596         case DRM_FORMAT_ARGB2101010:
8597         case DRM_FORMAT_XBGR2101010:
8598         case DRM_FORMAT_ABGR2101010:
8599                 /* checked in intel_framebuffer_init already */
8600                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8601                         return -EINVAL;
8602                 bpp = 10*3;
8603                 break;
8604         /* TODO: gen4+ supports 16 bpc floating point, too. */
8605         default:
8606                 DRM_DEBUG_KMS("unsupported depth\n");
8607                 return -EINVAL;
8608         }
8609
8610         pipe_config->pipe_bpp = bpp;
8611
8612         /* Clamp display bpp to EDID value */
8613         list_for_each_entry(connector, &dev->mode_config.connector_list,
8614                             base.head) {
8615                 if (!connector->new_encoder ||
8616                     connector->new_encoder->new_crtc != crtc)
8617                         continue;
8618
8619                 connected_sink_compute_bpp(connector, pipe_config);
8620         }
8621
8622         return bpp;
8623 }
8624
8625 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8626 {
8627         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8628                         "type: 0x%x flags: 0x%x\n",
8629                 mode->crtc_clock,
8630                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8631                 mode->crtc_hsync_end, mode->crtc_htotal,
8632                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8633                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8634 }
8635
8636 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8637                                    struct intel_crtc_config *pipe_config,
8638                                    const char *context)
8639 {
8640         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8641                       context, pipe_name(crtc->pipe));
8642
8643         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8644         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8645                       pipe_config->pipe_bpp, pipe_config->dither);
8646         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8647                       pipe_config->has_pch_encoder,
8648                       pipe_config->fdi_lanes,
8649                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8650                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8651                       pipe_config->fdi_m_n.tu);
8652         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8653                       pipe_config->has_dp_encoder,
8654                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8655                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8656                       pipe_config->dp_m_n.tu);
8657         DRM_DEBUG_KMS("requested mode:\n");
8658         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8659         DRM_DEBUG_KMS("adjusted mode:\n");
8660         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8661         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8662         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8663         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8664                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8665         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8666                       pipe_config->gmch_pfit.control,
8667                       pipe_config->gmch_pfit.pgm_ratios,
8668                       pipe_config->gmch_pfit.lvds_border_bits);
8669         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8670                       pipe_config->pch_pfit.pos,
8671                       pipe_config->pch_pfit.size,
8672                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8673         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8674         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8675 }
8676
8677 static bool check_encoder_cloning(struct drm_crtc *crtc)
8678 {
8679         int num_encoders = 0;
8680         bool uncloneable_encoders = false;
8681         struct intel_encoder *encoder;
8682
8683         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8684                             base.head) {
8685                 if (&encoder->new_crtc->base != crtc)
8686                         continue;
8687
8688                 num_encoders++;
8689                 if (!encoder->cloneable)
8690                         uncloneable_encoders = true;
8691         }
8692
8693         return !(num_encoders > 1 && uncloneable_encoders);
8694 }
8695
8696 static struct intel_crtc_config *
8697 intel_modeset_pipe_config(struct drm_crtc *crtc,
8698                           struct drm_framebuffer *fb,
8699                           struct drm_display_mode *mode)
8700 {
8701         struct drm_device *dev = crtc->dev;
8702         struct intel_encoder *encoder;
8703         struct intel_crtc_config *pipe_config;
8704         int plane_bpp, ret = -EINVAL;
8705         bool retry = true;
8706
8707         if (!check_encoder_cloning(crtc)) {
8708                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8709                 return ERR_PTR(-EINVAL);
8710         }
8711
8712         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8713         if (!pipe_config)
8714                 return ERR_PTR(-ENOMEM);
8715
8716         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8717         drm_mode_copy(&pipe_config->requested_mode, mode);
8718
8719         pipe_config->cpu_transcoder =
8720                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8721         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8722
8723         /*
8724          * Sanitize sync polarity flags based on requested ones. If neither
8725          * positive or negative polarity is requested, treat this as meaning
8726          * negative polarity.
8727          */
8728         if (!(pipe_config->adjusted_mode.flags &
8729               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8730                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8731
8732         if (!(pipe_config->adjusted_mode.flags &
8733               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8734                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8735
8736         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8737          * plane pixel format and any sink constraints into account. Returns the
8738          * source plane bpp so that dithering can be selected on mismatches
8739          * after encoders and crtc also have had their say. */
8740         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8741                                               fb, pipe_config);
8742         if (plane_bpp < 0)
8743                 goto fail;
8744
8745         /*
8746          * Determine the real pipe dimensions. Note that stereo modes can
8747          * increase the actual pipe size due to the frame doubling and
8748          * insertion of additional space for blanks between the frame. This
8749          * is stored in the crtc timings. We use the requested mode to do this
8750          * computation to clearly distinguish it from the adjusted mode, which
8751          * can be changed by the connectors in the below retry loop.
8752          */
8753         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8754         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8755         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8756
8757 encoder_retry:
8758         /* Ensure the port clock defaults are reset when retrying. */
8759         pipe_config->port_clock = 0;
8760         pipe_config->pixel_multiplier = 1;
8761
8762         /* Fill in default crtc timings, allow encoders to overwrite them. */
8763         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8764
8765         /* Pass our mode to the connectors and the CRTC to give them a chance to
8766          * adjust it according to limitations or connector properties, and also
8767          * a chance to reject the mode entirely.
8768          */
8769         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8770                             base.head) {
8771
8772                 if (&encoder->new_crtc->base != crtc)
8773                         continue;
8774
8775                 if (!(encoder->compute_config(encoder, pipe_config))) {
8776                         DRM_DEBUG_KMS("Encoder config failure\n");
8777                         goto fail;
8778                 }
8779         }
8780
8781         /* Set default port clock if not overwritten by the encoder. Needs to be
8782          * done afterwards in case the encoder adjusts the mode. */
8783         if (!pipe_config->port_clock)
8784                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8785                         * pipe_config->pixel_multiplier;
8786
8787         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8788         if (ret < 0) {
8789                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8790                 goto fail;
8791         }
8792
8793         if (ret == RETRY) {
8794                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8795                         ret = -EINVAL;
8796                         goto fail;
8797                 }
8798
8799                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8800                 retry = false;
8801                 goto encoder_retry;
8802         }
8803
8804         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8805         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8806                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8807
8808         return pipe_config;
8809 fail:
8810         kfree(pipe_config);
8811         return ERR_PTR(ret);
8812 }
8813
8814 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8815  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8816 static void
8817 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8818                              unsigned *prepare_pipes, unsigned *disable_pipes)
8819 {
8820         struct intel_crtc *intel_crtc;
8821         struct drm_device *dev = crtc->dev;
8822         struct intel_encoder *encoder;
8823         struct intel_connector *connector;
8824         struct drm_crtc *tmp_crtc;
8825
8826         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8827
8828         /* Check which crtcs have changed outputs connected to them, these need
8829          * to be part of the prepare_pipes mask. We don't (yet) support global
8830          * modeset across multiple crtcs, so modeset_pipes will only have one
8831          * bit set at most. */
8832         list_for_each_entry(connector, &dev->mode_config.connector_list,
8833                             base.head) {
8834                 if (connector->base.encoder == &connector->new_encoder->base)
8835                         continue;
8836
8837                 if (connector->base.encoder) {
8838                         tmp_crtc = connector->base.encoder->crtc;
8839
8840                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8841                 }
8842
8843                 if (connector->new_encoder)
8844                         *prepare_pipes |=
8845                                 1 << connector->new_encoder->new_crtc->pipe;
8846         }
8847
8848         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8849                             base.head) {
8850                 if (encoder->base.crtc == &encoder->new_crtc->base)
8851                         continue;
8852
8853                 if (encoder->base.crtc) {
8854                         tmp_crtc = encoder->base.crtc;
8855
8856                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8857                 }
8858
8859                 if (encoder->new_crtc)
8860                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8861         }
8862
8863         /* Check for any pipes that will be fully disabled ... */
8864         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8865                             base.head) {
8866                 bool used = false;
8867
8868                 /* Don't try to disable disabled crtcs. */
8869                 if (!intel_crtc->base.enabled)
8870                         continue;
8871
8872                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8873                                     base.head) {
8874                         if (encoder->new_crtc == intel_crtc)
8875                                 used = true;
8876                 }
8877
8878                 if (!used)
8879                         *disable_pipes |= 1 << intel_crtc->pipe;
8880         }
8881
8882
8883         /* set_mode is also used to update properties on life display pipes. */
8884         intel_crtc = to_intel_crtc(crtc);
8885         if (crtc->enabled)
8886                 *prepare_pipes |= 1 << intel_crtc->pipe;
8887
8888         /*
8889          * For simplicity do a full modeset on any pipe where the output routing
8890          * changed. We could be more clever, but that would require us to be
8891          * more careful with calling the relevant encoder->mode_set functions.
8892          */
8893         if (*prepare_pipes)
8894                 *modeset_pipes = *prepare_pipes;
8895
8896         /* ... and mask these out. */
8897         *modeset_pipes &= ~(*disable_pipes);
8898         *prepare_pipes &= ~(*disable_pipes);
8899
8900         /*
8901          * HACK: We don't (yet) fully support global modesets. intel_set_config
8902          * obies this rule, but the modeset restore mode of
8903          * intel_modeset_setup_hw_state does not.
8904          */
8905         *modeset_pipes &= 1 << intel_crtc->pipe;
8906         *prepare_pipes &= 1 << intel_crtc->pipe;
8907
8908         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8909                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8910 }
8911
8912 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8913 {
8914         struct drm_encoder *encoder;
8915         struct drm_device *dev = crtc->dev;
8916
8917         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8918                 if (encoder->crtc == crtc)
8919                         return true;
8920
8921         return false;
8922 }
8923
8924 static void
8925 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8926 {
8927         struct intel_encoder *intel_encoder;
8928         struct intel_crtc *intel_crtc;
8929         struct drm_connector *connector;
8930
8931         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8932                             base.head) {
8933                 if (!intel_encoder->base.crtc)
8934                         continue;
8935
8936                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8937
8938                 if (prepare_pipes & (1 << intel_crtc->pipe))
8939                         intel_encoder->connectors_active = false;
8940         }
8941
8942         intel_modeset_commit_output_state(dev);
8943
8944         /* Update computed state. */
8945         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8946                             base.head) {
8947                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8948         }
8949
8950         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8951                 if (!connector->encoder || !connector->encoder->crtc)
8952                         continue;
8953
8954                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8955
8956                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8957                         struct drm_property *dpms_property =
8958                                 dev->mode_config.dpms_property;
8959
8960                         connector->dpms = DRM_MODE_DPMS_ON;
8961                         drm_object_property_set_value(&connector->base,
8962                                                          dpms_property,
8963                                                          DRM_MODE_DPMS_ON);
8964
8965                         intel_encoder = to_intel_encoder(connector->encoder);
8966                         intel_encoder->connectors_active = true;
8967                 }
8968         }
8969
8970 }
8971
8972 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8973 {
8974         int diff;
8975
8976         if (clock1 == clock2)
8977                 return true;
8978
8979         if (!clock1 || !clock2)
8980                 return false;
8981
8982         diff = abs(clock1 - clock2);
8983
8984         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8985                 return true;
8986
8987         return false;
8988 }
8989
8990 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8991         list_for_each_entry((intel_crtc), \
8992                             &(dev)->mode_config.crtc_list, \
8993                             base.head) \
8994                 if (mask & (1 <<(intel_crtc)->pipe))
8995
8996 static bool
8997 intel_pipe_config_compare(struct drm_device *dev,
8998                           struct intel_crtc_config *current_config,
8999                           struct intel_crtc_config *pipe_config)
9000 {
9001 #define PIPE_CONF_CHECK_X(name) \
9002         if (current_config->name != pipe_config->name) { \
9003                 DRM_ERROR("mismatch in " #name " " \
9004                           "(expected 0x%08x, found 0x%08x)\n", \
9005                           current_config->name, \
9006                           pipe_config->name); \
9007                 return false; \
9008         }
9009
9010 #define PIPE_CONF_CHECK_I(name) \
9011         if (current_config->name != pipe_config->name) { \
9012                 DRM_ERROR("mismatch in " #name " " \
9013                           "(expected %i, found %i)\n", \
9014                           current_config->name, \
9015                           pipe_config->name); \
9016                 return false; \
9017         }
9018
9019 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9020         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9021                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9022                           "(expected %i, found %i)\n", \
9023                           current_config->name & (mask), \
9024                           pipe_config->name & (mask)); \
9025                 return false; \
9026         }
9027
9028 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9029         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9030                 DRM_ERROR("mismatch in " #name " " \
9031                           "(expected %i, found %i)\n", \
9032                           current_config->name, \
9033                           pipe_config->name); \
9034                 return false; \
9035         }
9036
9037 #define PIPE_CONF_QUIRK(quirk)  \
9038         ((current_config->quirks | pipe_config->quirks) & (quirk))
9039
9040         PIPE_CONF_CHECK_I(cpu_transcoder);
9041
9042         PIPE_CONF_CHECK_I(has_pch_encoder);
9043         PIPE_CONF_CHECK_I(fdi_lanes);
9044         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9045         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9046         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9047         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9048         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9049
9050         PIPE_CONF_CHECK_I(has_dp_encoder);
9051         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9052         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9053         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9054         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9055         PIPE_CONF_CHECK_I(dp_m_n.tu);
9056
9057         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9058         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9059         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9060         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9061         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9062         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9063
9064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9066         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9067         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9068         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9069         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9070
9071         PIPE_CONF_CHECK_I(pixel_multiplier);
9072
9073         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9074                               DRM_MODE_FLAG_INTERLACE);
9075
9076         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9077                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9078                                       DRM_MODE_FLAG_PHSYNC);
9079                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9080                                       DRM_MODE_FLAG_NHSYNC);
9081                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9082                                       DRM_MODE_FLAG_PVSYNC);
9083                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9084                                       DRM_MODE_FLAG_NVSYNC);
9085         }
9086
9087         PIPE_CONF_CHECK_I(pipe_src_w);
9088         PIPE_CONF_CHECK_I(pipe_src_h);
9089
9090         PIPE_CONF_CHECK_I(gmch_pfit.control);
9091         /* pfit ratios are autocomputed by the hw on gen4+ */
9092         if (INTEL_INFO(dev)->gen < 4)
9093                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9094         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9095         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9096         if (current_config->pch_pfit.enabled) {
9097                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9098                 PIPE_CONF_CHECK_I(pch_pfit.size);
9099         }
9100
9101         PIPE_CONF_CHECK_I(ips_enabled);
9102
9103         PIPE_CONF_CHECK_I(double_wide);
9104
9105         PIPE_CONF_CHECK_I(shared_dpll);
9106         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9107         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9108         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9109         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9110
9111         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9112                 PIPE_CONF_CHECK_I(pipe_bpp);
9113
9114         if (!IS_HASWELL(dev)) {
9115                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9116                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9117         }
9118
9119 #undef PIPE_CONF_CHECK_X
9120 #undef PIPE_CONF_CHECK_I
9121 #undef PIPE_CONF_CHECK_FLAGS
9122 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9123 #undef PIPE_CONF_QUIRK
9124
9125         return true;
9126 }
9127
9128 static void
9129 check_connector_state(struct drm_device *dev)
9130 {
9131         struct intel_connector *connector;
9132
9133         list_for_each_entry(connector, &dev->mode_config.connector_list,
9134                             base.head) {
9135                 /* This also checks the encoder/connector hw state with the
9136                  * ->get_hw_state callbacks. */
9137                 intel_connector_check_state(connector);
9138
9139                 WARN(&connector->new_encoder->base != connector->base.encoder,
9140                      "connector's staged encoder doesn't match current encoder\n");
9141         }
9142 }
9143
9144 static void
9145 check_encoder_state(struct drm_device *dev)
9146 {
9147         struct intel_encoder *encoder;
9148         struct intel_connector *connector;
9149
9150         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9151                             base.head) {
9152                 bool enabled = false;
9153                 bool active = false;
9154                 enum pipe pipe, tracked_pipe;
9155
9156                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9157                               encoder->base.base.id,
9158                               drm_get_encoder_name(&encoder->base));
9159
9160                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9161                      "encoder's stage crtc doesn't match current crtc\n");
9162                 WARN(encoder->connectors_active && !encoder->base.crtc,
9163                      "encoder's active_connectors set, but no crtc\n");
9164
9165                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9166                                     base.head) {
9167                         if (connector->base.encoder != &encoder->base)
9168                                 continue;
9169                         enabled = true;
9170                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9171                                 active = true;
9172                 }
9173                 WARN(!!encoder->base.crtc != enabled,
9174                      "encoder's enabled state mismatch "
9175                      "(expected %i, found %i)\n",
9176                      !!encoder->base.crtc, enabled);
9177                 WARN(active && !encoder->base.crtc,
9178                      "active encoder with no crtc\n");
9179
9180                 WARN(encoder->connectors_active != active,
9181                      "encoder's computed active state doesn't match tracked active state "
9182                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9183
9184                 active = encoder->get_hw_state(encoder, &pipe);
9185                 WARN(active != encoder->connectors_active,
9186                      "encoder's hw state doesn't match sw tracking "
9187                      "(expected %i, found %i)\n",
9188                      encoder->connectors_active, active);
9189
9190                 if (!encoder->base.crtc)
9191                         continue;
9192
9193                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9194                 WARN(active && pipe != tracked_pipe,
9195                      "active encoder's pipe doesn't match"
9196                      "(expected %i, found %i)\n",
9197                      tracked_pipe, pipe);
9198
9199         }
9200 }
9201
9202 static void
9203 check_crtc_state(struct drm_device *dev)
9204 {
9205         drm_i915_private_t *dev_priv = dev->dev_private;
9206         struct intel_crtc *crtc;
9207         struct intel_encoder *encoder;
9208         struct intel_crtc_config pipe_config;
9209
9210         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9211                             base.head) {
9212                 bool enabled = false;
9213                 bool active = false;
9214
9215                 memset(&pipe_config, 0, sizeof(pipe_config));
9216
9217                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9218                               crtc->base.base.id);
9219
9220                 WARN(crtc->active && !crtc->base.enabled,
9221                      "active crtc, but not enabled in sw tracking\n");
9222
9223                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9224                                     base.head) {
9225                         if (encoder->base.crtc != &crtc->base)
9226                                 continue;
9227                         enabled = true;
9228                         if (encoder->connectors_active)
9229                                 active = true;
9230                 }
9231
9232                 WARN(active != crtc->active,
9233                      "crtc's computed active state doesn't match tracked active state "
9234                      "(expected %i, found %i)\n", active, crtc->active);
9235                 WARN(enabled != crtc->base.enabled,
9236                      "crtc's computed enabled state doesn't match tracked enabled state "
9237                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9238
9239                 active = dev_priv->display.get_pipe_config(crtc,
9240                                                            &pipe_config);
9241
9242                 /* hw state is inconsistent with the pipe A quirk */
9243                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9244                         active = crtc->active;
9245
9246                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9247                                     base.head) {
9248                         enum pipe pipe;
9249                         if (encoder->base.crtc != &crtc->base)
9250                                 continue;
9251                         if (encoder->get_config &&
9252                             encoder->get_hw_state(encoder, &pipe))
9253                                 encoder->get_config(encoder, &pipe_config);
9254                 }
9255
9256                 WARN(crtc->active != active,
9257                      "crtc active state doesn't match with hw state "
9258                      "(expected %i, found %i)\n", crtc->active, active);
9259
9260                 if (active &&
9261                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9262                         WARN(1, "pipe state doesn't match!\n");
9263                         intel_dump_pipe_config(crtc, &pipe_config,
9264                                                "[hw state]");
9265                         intel_dump_pipe_config(crtc, &crtc->config,
9266                                                "[sw state]");
9267                 }
9268         }
9269 }
9270
9271 static void
9272 check_shared_dpll_state(struct drm_device *dev)
9273 {
9274         drm_i915_private_t *dev_priv = dev->dev_private;
9275         struct intel_crtc *crtc;
9276         struct intel_dpll_hw_state dpll_hw_state;
9277         int i;
9278
9279         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9280                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9281                 int enabled_crtcs = 0, active_crtcs = 0;
9282                 bool active;
9283
9284                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9285
9286                 DRM_DEBUG_KMS("%s\n", pll->name);
9287
9288                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9289
9290                 WARN(pll->active > pll->refcount,
9291                      "more active pll users than references: %i vs %i\n",
9292                      pll->active, pll->refcount);
9293                 WARN(pll->active && !pll->on,
9294                      "pll in active use but not on in sw tracking\n");
9295                 WARN(pll->on && !pll->active,
9296                      "pll in on but not on in use in sw tracking\n");
9297                 WARN(pll->on != active,
9298                      "pll on state mismatch (expected %i, found %i)\n",
9299                      pll->on, active);
9300
9301                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9302                                     base.head) {
9303                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9304                                 enabled_crtcs++;
9305                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9306                                 active_crtcs++;
9307                 }
9308                 WARN(pll->active != active_crtcs,
9309                      "pll active crtcs mismatch (expected %i, found %i)\n",
9310                      pll->active, active_crtcs);
9311                 WARN(pll->refcount != enabled_crtcs,
9312                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9313                      pll->refcount, enabled_crtcs);
9314
9315                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9316                                        sizeof(dpll_hw_state)),
9317                      "pll hw state mismatch\n");
9318         }
9319 }
9320
9321 void
9322 intel_modeset_check_state(struct drm_device *dev)
9323 {
9324         check_connector_state(dev);
9325         check_encoder_state(dev);
9326         check_crtc_state(dev);
9327         check_shared_dpll_state(dev);
9328 }
9329
9330 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9331                                      int dotclock)
9332 {
9333         /*
9334          * FDI already provided one idea for the dotclock.
9335          * Yell if the encoder disagrees.
9336          */
9337         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9338              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9339              pipe_config->adjusted_mode.crtc_clock, dotclock);
9340 }
9341
9342 static int __intel_set_mode(struct drm_crtc *crtc,
9343                             struct drm_display_mode *mode,
9344                             int x, int y, struct drm_framebuffer *fb)
9345 {
9346         struct drm_device *dev = crtc->dev;
9347         drm_i915_private_t *dev_priv = dev->dev_private;
9348         struct drm_display_mode *saved_mode, *saved_hwmode;
9349         struct intel_crtc_config *pipe_config = NULL;
9350         struct intel_crtc *intel_crtc;
9351         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9352         int ret = 0;
9353
9354         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9355         if (!saved_mode)
9356                 return -ENOMEM;
9357         saved_hwmode = saved_mode + 1;
9358
9359         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9360                                      &prepare_pipes, &disable_pipes);
9361
9362         *saved_hwmode = crtc->hwmode;
9363         *saved_mode = crtc->mode;
9364
9365         /* Hack: Because we don't (yet) support global modeset on multiple
9366          * crtcs, we don't keep track of the new mode for more than one crtc.
9367          * Hence simply check whether any bit is set in modeset_pipes in all the
9368          * pieces of code that are not yet converted to deal with mutliple crtcs
9369          * changing their mode at the same time. */
9370         if (modeset_pipes) {
9371                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9372                 if (IS_ERR(pipe_config)) {
9373                         ret = PTR_ERR(pipe_config);
9374                         pipe_config = NULL;
9375
9376                         goto out;
9377                 }
9378                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9379                                        "[modeset]");
9380         }
9381
9382         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9383                 intel_crtc_disable(&intel_crtc->base);
9384
9385         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9386                 if (intel_crtc->base.enabled)
9387                         dev_priv->display.crtc_disable(&intel_crtc->base);
9388         }
9389
9390         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9391          * to set it here already despite that we pass it down the callchain.
9392          */
9393         if (modeset_pipes) {
9394                 crtc->mode = *mode;
9395                 /* mode_set/enable/disable functions rely on a correct pipe
9396                  * config. */
9397                 to_intel_crtc(crtc)->config = *pipe_config;
9398         }
9399
9400         /* Only after disabling all output pipelines that will be changed can we
9401          * update the the output configuration. */
9402         intel_modeset_update_state(dev, prepare_pipes);
9403
9404         if (dev_priv->display.modeset_global_resources)
9405                 dev_priv->display.modeset_global_resources(dev);
9406
9407         /* Set up the DPLL and any encoders state that needs to adjust or depend
9408          * on the DPLL.
9409          */
9410         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9411                 ret = intel_crtc_mode_set(&intel_crtc->base,
9412                                           x, y, fb);
9413                 if (ret)
9414                         goto done;
9415         }
9416
9417         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9418         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9419                 dev_priv->display.crtc_enable(&intel_crtc->base);
9420
9421         if (modeset_pipes) {
9422                 /* Store real post-adjustment hardware mode. */
9423                 crtc->hwmode = pipe_config->adjusted_mode;
9424
9425                 /* Calculate and store various constants which
9426                  * are later needed by vblank and swap-completion
9427                  * timestamping. They are derived from true hwmode.
9428                  */
9429                 drm_calc_timestamping_constants(crtc);
9430         }
9431
9432         /* FIXME: add subpixel order */
9433 done:
9434         if (ret && crtc->enabled) {
9435                 crtc->hwmode = *saved_hwmode;
9436                 crtc->mode = *saved_mode;
9437         }
9438
9439 out:
9440         kfree(pipe_config);
9441         kfree(saved_mode);
9442         return ret;
9443 }
9444
9445 static int intel_set_mode(struct drm_crtc *crtc,
9446                           struct drm_display_mode *mode,
9447                           int x, int y, struct drm_framebuffer *fb)
9448 {
9449         int ret;
9450
9451         ret = __intel_set_mode(crtc, mode, x, y, fb);
9452
9453         if (ret == 0)
9454                 intel_modeset_check_state(crtc->dev);
9455
9456         return ret;
9457 }
9458
9459 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9460 {
9461         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9462 }
9463
9464 #undef for_each_intel_crtc_masked
9465
9466 static void intel_set_config_free(struct intel_set_config *config)
9467 {
9468         if (!config)
9469                 return;
9470
9471         kfree(config->save_connector_encoders);
9472         kfree(config->save_encoder_crtcs);
9473         kfree(config);
9474 }
9475
9476 static int intel_set_config_save_state(struct drm_device *dev,
9477                                        struct intel_set_config *config)
9478 {
9479         struct drm_encoder *encoder;
9480         struct drm_connector *connector;
9481         int count;
9482
9483         config->save_encoder_crtcs =
9484                 kcalloc(dev->mode_config.num_encoder,
9485                         sizeof(struct drm_crtc *), GFP_KERNEL);
9486         if (!config->save_encoder_crtcs)
9487                 return -ENOMEM;
9488
9489         config->save_connector_encoders =
9490                 kcalloc(dev->mode_config.num_connector,
9491                         sizeof(struct drm_encoder *), GFP_KERNEL);
9492         if (!config->save_connector_encoders)
9493                 return -ENOMEM;
9494
9495         /* Copy data. Note that driver private data is not affected.
9496          * Should anything bad happen only the expected state is
9497          * restored, not the drivers personal bookkeeping.
9498          */
9499         count = 0;
9500         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9501                 config->save_encoder_crtcs[count++] = encoder->crtc;
9502         }
9503
9504         count = 0;
9505         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9506                 config->save_connector_encoders[count++] = connector->encoder;
9507         }
9508
9509         return 0;
9510 }
9511
9512 static void intel_set_config_restore_state(struct drm_device *dev,
9513                                            struct intel_set_config *config)
9514 {
9515         struct intel_encoder *encoder;
9516         struct intel_connector *connector;
9517         int count;
9518
9519         count = 0;
9520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9521                 encoder->new_crtc =
9522                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9523         }
9524
9525         count = 0;
9526         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9527                 connector->new_encoder =
9528                         to_intel_encoder(config->save_connector_encoders[count++]);
9529         }
9530 }
9531
9532 static bool
9533 is_crtc_connector_off(struct drm_mode_set *set)
9534 {
9535         int i;
9536
9537         if (set->num_connectors == 0)
9538                 return false;
9539
9540         if (WARN_ON(set->connectors == NULL))
9541                 return false;
9542
9543         for (i = 0; i < set->num_connectors; i++)
9544                 if (set->connectors[i]->encoder &&
9545                     set->connectors[i]->encoder->crtc == set->crtc &&
9546                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9547                         return true;
9548
9549         return false;
9550 }
9551
9552 static void
9553 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9554                                       struct intel_set_config *config)
9555 {
9556
9557         /* We should be able to check here if the fb has the same properties
9558          * and then just flip_or_move it */
9559         if (is_crtc_connector_off(set)) {
9560                 config->mode_changed = true;
9561         } else if (set->crtc->fb != set->fb) {
9562                 /* If we have no fb then treat it as a full mode set */
9563                 if (set->crtc->fb == NULL) {
9564                         struct intel_crtc *intel_crtc =
9565                                 to_intel_crtc(set->crtc);
9566
9567                         if (intel_crtc->active && i915_fastboot) {
9568                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9569                                 config->fb_changed = true;
9570                         } else {
9571                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9572                                 config->mode_changed = true;
9573                         }
9574                 } else if (set->fb == NULL) {
9575                         config->mode_changed = true;
9576                 } else if (set->fb->pixel_format !=
9577                            set->crtc->fb->pixel_format) {
9578                         config->mode_changed = true;
9579                 } else {
9580                         config->fb_changed = true;
9581                 }
9582         }
9583
9584         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9585                 config->fb_changed = true;
9586
9587         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9588                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9589                 drm_mode_debug_printmodeline(&set->crtc->mode);
9590                 drm_mode_debug_printmodeline(set->mode);
9591                 config->mode_changed = true;
9592         }
9593
9594         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9595                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9596 }
9597
9598 static int
9599 intel_modeset_stage_output_state(struct drm_device *dev,
9600                                  struct drm_mode_set *set,
9601                                  struct intel_set_config *config)
9602 {
9603         struct drm_crtc *new_crtc;
9604         struct intel_connector *connector;
9605         struct intel_encoder *encoder;
9606         int ro;
9607
9608         /* The upper layers ensure that we either disable a crtc or have a list
9609          * of connectors. For paranoia, double-check this. */
9610         WARN_ON(!set->fb && (set->num_connectors != 0));
9611         WARN_ON(set->fb && (set->num_connectors == 0));
9612
9613         list_for_each_entry(connector, &dev->mode_config.connector_list,
9614                             base.head) {
9615                 /* Otherwise traverse passed in connector list and get encoders
9616                  * for them. */
9617                 for (ro = 0; ro < set->num_connectors; ro++) {
9618                         if (set->connectors[ro] == &connector->base) {
9619                                 connector->new_encoder = connector->encoder;
9620                                 break;
9621                         }
9622                 }
9623
9624                 /* If we disable the crtc, disable all its connectors. Also, if
9625                  * the connector is on the changing crtc but not on the new
9626                  * connector list, disable it. */
9627                 if ((!set->fb || ro == set->num_connectors) &&
9628                     connector->base.encoder &&
9629                     connector->base.encoder->crtc == set->crtc) {
9630                         connector->new_encoder = NULL;
9631
9632                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9633                                 connector->base.base.id,
9634                                 drm_get_connector_name(&connector->base));
9635                 }
9636
9637
9638                 if (&connector->new_encoder->base != connector->base.encoder) {
9639                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9640                         config->mode_changed = true;
9641                 }
9642         }
9643         /* connector->new_encoder is now updated for all connectors. */
9644
9645         /* Update crtc of enabled connectors. */
9646         list_for_each_entry(connector, &dev->mode_config.connector_list,
9647                             base.head) {
9648                 if (!connector->new_encoder)
9649                         continue;
9650
9651                 new_crtc = connector->new_encoder->base.crtc;
9652
9653                 for (ro = 0; ro < set->num_connectors; ro++) {
9654                         if (set->connectors[ro] == &connector->base)
9655                                 new_crtc = set->crtc;
9656                 }
9657
9658                 /* Make sure the new CRTC will work with the encoder */
9659                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9660                                            new_crtc)) {
9661                         return -EINVAL;
9662                 }
9663                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9664
9665                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9666                         connector->base.base.id,
9667                         drm_get_connector_name(&connector->base),
9668                         new_crtc->base.id);
9669         }
9670
9671         /* Check for any encoders that needs to be disabled. */
9672         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9673                             base.head) {
9674                 list_for_each_entry(connector,
9675                                     &dev->mode_config.connector_list,
9676                                     base.head) {
9677                         if (connector->new_encoder == encoder) {
9678                                 WARN_ON(!connector->new_encoder->new_crtc);
9679
9680                                 goto next_encoder;
9681                         }
9682                 }
9683                 encoder->new_crtc = NULL;
9684 next_encoder:
9685                 /* Only now check for crtc changes so we don't miss encoders
9686                  * that will be disabled. */
9687                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9688                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9689                         config->mode_changed = true;
9690                 }
9691         }
9692         /* Now we've also updated encoder->new_crtc for all encoders. */
9693
9694         return 0;
9695 }
9696
9697 static int intel_crtc_set_config(struct drm_mode_set *set)
9698 {
9699         struct drm_device *dev;
9700         struct drm_mode_set save_set;
9701         struct intel_set_config *config;
9702         int ret;
9703
9704         BUG_ON(!set);
9705         BUG_ON(!set->crtc);
9706         BUG_ON(!set->crtc->helper_private);
9707
9708         /* Enforce sane interface api - has been abused by the fb helper. */
9709         BUG_ON(!set->mode && set->fb);
9710         BUG_ON(set->fb && set->num_connectors == 0);
9711
9712         if (set->fb) {
9713                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9714                                 set->crtc->base.id, set->fb->base.id,
9715                                 (int)set->num_connectors, set->x, set->y);
9716         } else {
9717                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9718         }
9719
9720         dev = set->crtc->dev;
9721
9722         ret = -ENOMEM;
9723         config = kzalloc(sizeof(*config), GFP_KERNEL);
9724         if (!config)
9725                 goto out_config;
9726
9727         ret = intel_set_config_save_state(dev, config);
9728         if (ret)
9729                 goto out_config;
9730
9731         save_set.crtc = set->crtc;
9732         save_set.mode = &set->crtc->mode;
9733         save_set.x = set->crtc->x;
9734         save_set.y = set->crtc->y;
9735         save_set.fb = set->crtc->fb;
9736
9737         /* Compute whether we need a full modeset, only an fb base update or no
9738          * change at all. In the future we might also check whether only the
9739          * mode changed, e.g. for LVDS where we only change the panel fitter in
9740          * such cases. */
9741         intel_set_config_compute_mode_changes(set, config);
9742
9743         ret = intel_modeset_stage_output_state(dev, set, config);
9744         if (ret)
9745                 goto fail;
9746
9747         if (config->mode_changed) {
9748                 ret = intel_set_mode(set->crtc, set->mode,
9749                                      set->x, set->y, set->fb);
9750         } else if (config->fb_changed) {
9751                 intel_crtc_wait_for_pending_flips(set->crtc);
9752
9753                 ret = intel_pipe_set_base(set->crtc,
9754                                           set->x, set->y, set->fb);
9755         }
9756
9757         if (ret) {
9758                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9759                               set->crtc->base.id, ret);
9760 fail:
9761                 intel_set_config_restore_state(dev, config);
9762
9763                 /* Try to restore the config */
9764                 if (config->mode_changed &&
9765                     intel_set_mode(save_set.crtc, save_set.mode,
9766                                    save_set.x, save_set.y, save_set.fb))
9767                         DRM_ERROR("failed to restore config after modeset failure\n");
9768         }
9769
9770 out_config:
9771         intel_set_config_free(config);
9772         return ret;
9773 }
9774
9775 static const struct drm_crtc_funcs intel_crtc_funcs = {
9776         .cursor_set = intel_crtc_cursor_set,
9777         .cursor_move = intel_crtc_cursor_move,
9778         .gamma_set = intel_crtc_gamma_set,
9779         .set_config = intel_crtc_set_config,
9780         .destroy = intel_crtc_destroy,
9781         .page_flip = intel_crtc_page_flip,
9782 };
9783
9784 static void intel_cpu_pll_init(struct drm_device *dev)
9785 {
9786         if (HAS_DDI(dev))
9787                 intel_ddi_pll_init(dev);
9788 }
9789
9790 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9791                                       struct intel_shared_dpll *pll,
9792                                       struct intel_dpll_hw_state *hw_state)
9793 {
9794         uint32_t val;
9795
9796         val = I915_READ(PCH_DPLL(pll->id));
9797         hw_state->dpll = val;
9798         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9799         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9800
9801         return val & DPLL_VCO_ENABLE;
9802 }
9803
9804 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9805                                   struct intel_shared_dpll *pll)
9806 {
9807         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9808         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9809 }
9810
9811 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9812                                 struct intel_shared_dpll *pll)
9813 {
9814         /* PCH refclock must be enabled first */
9815         assert_pch_refclk_enabled(dev_priv);
9816
9817         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9818
9819         /* Wait for the clocks to stabilize. */
9820         POSTING_READ(PCH_DPLL(pll->id));
9821         udelay(150);
9822
9823         /* The pixel multiplier can only be updated once the
9824          * DPLL is enabled and the clocks are stable.
9825          *
9826          * So write it again.
9827          */
9828         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9829         POSTING_READ(PCH_DPLL(pll->id));
9830         udelay(200);
9831 }
9832
9833 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9834                                  struct intel_shared_dpll *pll)
9835 {
9836         struct drm_device *dev = dev_priv->dev;
9837         struct intel_crtc *crtc;
9838
9839         /* Make sure no transcoder isn't still depending on us. */
9840         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9841                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9842                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9843         }
9844
9845         I915_WRITE(PCH_DPLL(pll->id), 0);
9846         POSTING_READ(PCH_DPLL(pll->id));
9847         udelay(200);
9848 }
9849
9850 static char *ibx_pch_dpll_names[] = {
9851         "PCH DPLL A",
9852         "PCH DPLL B",
9853 };
9854
9855 static void ibx_pch_dpll_init(struct drm_device *dev)
9856 {
9857         struct drm_i915_private *dev_priv = dev->dev_private;
9858         int i;
9859
9860         dev_priv->num_shared_dpll = 2;
9861
9862         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9863                 dev_priv->shared_dplls[i].id = i;
9864                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9865                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9866                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9867                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9868                 dev_priv->shared_dplls[i].get_hw_state =
9869                         ibx_pch_dpll_get_hw_state;
9870         }
9871 }
9872
9873 static void intel_shared_dpll_init(struct drm_device *dev)
9874 {
9875         struct drm_i915_private *dev_priv = dev->dev_private;
9876
9877         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9878                 ibx_pch_dpll_init(dev);
9879         else
9880                 dev_priv->num_shared_dpll = 0;
9881
9882         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9883         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9884                       dev_priv->num_shared_dpll);
9885 }
9886
9887 static void intel_crtc_init(struct drm_device *dev, int pipe)
9888 {
9889         drm_i915_private_t *dev_priv = dev->dev_private;
9890         struct intel_crtc *intel_crtc;
9891         int i;
9892
9893         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9894         if (intel_crtc == NULL)
9895                 return;
9896
9897         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9898
9899         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9900         for (i = 0; i < 256; i++) {
9901                 intel_crtc->lut_r[i] = i;
9902                 intel_crtc->lut_g[i] = i;
9903                 intel_crtc->lut_b[i] = i;
9904         }
9905
9906         /* Swap pipes & planes for FBC on pre-965 */
9907         intel_crtc->pipe = pipe;
9908         intel_crtc->plane = pipe;
9909         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9910                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9911                 intel_crtc->plane = !pipe;
9912         }
9913
9914         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9915                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9916         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9917         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9918
9919         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9920 }
9921
9922 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
9923 {
9924         struct drm_encoder *encoder = connector->base.encoder;
9925
9926         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
9927
9928         if (!encoder)
9929                 return INVALID_PIPE;
9930
9931         return to_intel_crtc(encoder->crtc)->pipe;
9932 }
9933
9934 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9935                                 struct drm_file *file)
9936 {
9937         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9938         struct drm_mode_object *drmmode_obj;
9939         struct intel_crtc *crtc;
9940
9941         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9942                 return -ENODEV;
9943
9944         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9945                         DRM_MODE_OBJECT_CRTC);
9946
9947         if (!drmmode_obj) {
9948                 DRM_ERROR("no such CRTC id\n");
9949                 return -ENOENT;
9950         }
9951
9952         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9953         pipe_from_crtc_id->pipe = crtc->pipe;
9954
9955         return 0;
9956 }
9957
9958 static int intel_encoder_clones(struct intel_encoder *encoder)
9959 {
9960         struct drm_device *dev = encoder->base.dev;
9961         struct intel_encoder *source_encoder;
9962         int index_mask = 0;
9963         int entry = 0;
9964
9965         list_for_each_entry(source_encoder,
9966                             &dev->mode_config.encoder_list, base.head) {
9967
9968                 if (encoder == source_encoder)
9969                         index_mask |= (1 << entry);
9970
9971                 /* Intel hw has only one MUX where enocoders could be cloned. */
9972                 if (encoder->cloneable && source_encoder->cloneable)
9973                         index_mask |= (1 << entry);
9974
9975                 entry++;
9976         }
9977
9978         return index_mask;
9979 }
9980
9981 static bool has_edp_a(struct drm_device *dev)
9982 {
9983         struct drm_i915_private *dev_priv = dev->dev_private;
9984
9985         if (!IS_MOBILE(dev))
9986                 return false;
9987
9988         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9989                 return false;
9990
9991         if (IS_GEN5(dev) &&
9992             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9993                 return false;
9994
9995         return true;
9996 }
9997
9998 static void intel_setup_outputs(struct drm_device *dev)
9999 {
10000         struct drm_i915_private *dev_priv = dev->dev_private;
10001         struct intel_encoder *encoder;
10002         bool dpd_is_edp = false;
10003
10004         intel_lvds_init(dev);
10005
10006         if (!IS_ULT(dev))
10007                 intel_crt_init(dev);
10008
10009         if (HAS_DDI(dev)) {
10010                 int found;
10011
10012                 /* Haswell uses DDI functions to detect digital outputs */
10013                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10014                 /* DDI A only supports eDP */
10015                 if (found)
10016                         intel_ddi_init(dev, PORT_A);
10017
10018                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10019                  * register */
10020                 found = I915_READ(SFUSE_STRAP);
10021
10022                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10023                         intel_ddi_init(dev, PORT_B);
10024                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10025                         intel_ddi_init(dev, PORT_C);
10026                 if (found & SFUSE_STRAP_DDID_DETECTED)
10027                         intel_ddi_init(dev, PORT_D);
10028         } else if (HAS_PCH_SPLIT(dev)) {
10029                 int found;
10030                 dpd_is_edp = intel_dpd_is_edp(dev);
10031
10032                 if (has_edp_a(dev))
10033                         intel_dp_init(dev, DP_A, PORT_A);
10034
10035                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10036                         /* PCH SDVOB multiplex with HDMIB */
10037                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10038                         if (!found)
10039                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10040                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10041                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10042                 }
10043
10044                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10045                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10046
10047                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10048                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10049
10050                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10051                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10052
10053                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10054                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10055         } else if (IS_VALLEYVIEW(dev)) {
10056                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10057                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10058                                         PORT_B);
10059                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10060                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10061                 }
10062
10063                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10064                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10065                                         PORT_C);
10066                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10067                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10068                                               PORT_C);
10069                 }
10070
10071                 intel_dsi_init(dev);
10072         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10073                 bool found = false;
10074
10075                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10076                         DRM_DEBUG_KMS("probing SDVOB\n");
10077                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10078                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10079                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10080                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10081                         }
10082
10083                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10084                                 intel_dp_init(dev, DP_B, PORT_B);
10085                 }
10086
10087                 /* Before G4X SDVOC doesn't have its own detect register */
10088
10089                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10090                         DRM_DEBUG_KMS("probing SDVOC\n");
10091                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10092                 }
10093
10094                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10095
10096                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10097                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10098                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10099                         }
10100                         if (SUPPORTS_INTEGRATED_DP(dev))
10101                                 intel_dp_init(dev, DP_C, PORT_C);
10102                 }
10103
10104                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10105                     (I915_READ(DP_D) & DP_DETECTED))
10106                         intel_dp_init(dev, DP_D, PORT_D);
10107         } else if (IS_GEN2(dev))
10108                 intel_dvo_init(dev);
10109
10110         if (SUPPORTS_TV(dev))
10111                 intel_tv_init(dev);
10112
10113         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10114                 encoder->base.possible_crtcs = encoder->crtc_mask;
10115                 encoder->base.possible_clones =
10116                         intel_encoder_clones(encoder);
10117         }
10118
10119         intel_init_pch_refclk(dev);
10120
10121         drm_helper_move_panel_connectors_to_head(dev);
10122 }
10123
10124 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10125 {
10126         drm_framebuffer_cleanup(&fb->base);
10127         WARN_ON(!fb->obj->framebuffer_references--);
10128         drm_gem_object_unreference_unlocked(&fb->obj->base);
10129 }
10130
10131 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10132 {
10133         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10134
10135         intel_framebuffer_fini(intel_fb);
10136         kfree(intel_fb);
10137 }
10138
10139 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10140                                                 struct drm_file *file,
10141                                                 unsigned int *handle)
10142 {
10143         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10144         struct drm_i915_gem_object *obj = intel_fb->obj;
10145
10146         return drm_gem_handle_create(file, &obj->base, handle);
10147 }
10148
10149 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10150         .destroy = intel_user_framebuffer_destroy,
10151         .create_handle = intel_user_framebuffer_create_handle,
10152 };
10153
10154 int intel_framebuffer_init(struct drm_device *dev,
10155                            struct intel_framebuffer *intel_fb,
10156                            struct drm_mode_fb_cmd2 *mode_cmd,
10157                            struct drm_i915_gem_object *obj)
10158 {
10159         int aligned_height, tile_height;
10160         int pitch_limit;
10161         int ret;
10162
10163         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10164
10165         if (obj->tiling_mode == I915_TILING_Y) {
10166                 DRM_DEBUG("hardware does not support tiling Y\n");
10167                 return -EINVAL;
10168         }
10169
10170         if (mode_cmd->pitches[0] & 63) {
10171                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10172                           mode_cmd->pitches[0]);
10173                 return -EINVAL;
10174         }
10175
10176         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10177                 pitch_limit = 32*1024;
10178         } else if (INTEL_INFO(dev)->gen >= 4) {
10179                 if (obj->tiling_mode)
10180                         pitch_limit = 16*1024;
10181                 else
10182                         pitch_limit = 32*1024;
10183         } else if (INTEL_INFO(dev)->gen >= 3) {
10184                 if (obj->tiling_mode)
10185                         pitch_limit = 8*1024;
10186                 else
10187                         pitch_limit = 16*1024;
10188         } else
10189                 /* XXX DSPC is limited to 4k tiled */
10190                 pitch_limit = 8*1024;
10191
10192         if (mode_cmd->pitches[0] > pitch_limit) {
10193                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10194                           obj->tiling_mode ? "tiled" : "linear",
10195                           mode_cmd->pitches[0], pitch_limit);
10196                 return -EINVAL;
10197         }
10198
10199         if (obj->tiling_mode != I915_TILING_NONE &&
10200             mode_cmd->pitches[0] != obj->stride) {
10201                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10202                           mode_cmd->pitches[0], obj->stride);
10203                 return -EINVAL;
10204         }
10205
10206         /* Reject formats not supported by any plane early. */
10207         switch (mode_cmd->pixel_format) {
10208         case DRM_FORMAT_C8:
10209         case DRM_FORMAT_RGB565:
10210         case DRM_FORMAT_XRGB8888:
10211         case DRM_FORMAT_ARGB8888:
10212                 break;
10213         case DRM_FORMAT_XRGB1555:
10214         case DRM_FORMAT_ARGB1555:
10215                 if (INTEL_INFO(dev)->gen > 3) {
10216                         DRM_DEBUG("unsupported pixel format: %s\n",
10217                                   drm_get_format_name(mode_cmd->pixel_format));
10218                         return -EINVAL;
10219                 }
10220                 break;
10221         case DRM_FORMAT_XBGR8888:
10222         case DRM_FORMAT_ABGR8888:
10223         case DRM_FORMAT_XRGB2101010:
10224         case DRM_FORMAT_ARGB2101010:
10225         case DRM_FORMAT_XBGR2101010:
10226         case DRM_FORMAT_ABGR2101010:
10227                 if (INTEL_INFO(dev)->gen < 4) {
10228                         DRM_DEBUG("unsupported pixel format: %s\n",
10229                                   drm_get_format_name(mode_cmd->pixel_format));
10230                         return -EINVAL;
10231                 }
10232                 break;
10233         case DRM_FORMAT_YUYV:
10234         case DRM_FORMAT_UYVY:
10235         case DRM_FORMAT_YVYU:
10236         case DRM_FORMAT_VYUY:
10237                 if (INTEL_INFO(dev)->gen < 5) {
10238                         DRM_DEBUG("unsupported pixel format: %s\n",
10239                                   drm_get_format_name(mode_cmd->pixel_format));
10240                         return -EINVAL;
10241                 }
10242                 break;
10243         default:
10244                 DRM_DEBUG("unsupported pixel format: %s\n",
10245                           drm_get_format_name(mode_cmd->pixel_format));
10246                 return -EINVAL;
10247         }
10248
10249         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10250         if (mode_cmd->offsets[0] != 0)
10251                 return -EINVAL;
10252
10253         tile_height = IS_GEN2(dev) ? 16 : 8;
10254         aligned_height = ALIGN(mode_cmd->height,
10255                                obj->tiling_mode ? tile_height : 1);
10256         /* FIXME drm helper for size checks (especially planar formats)? */
10257         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10258                 return -EINVAL;
10259
10260         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10261         intel_fb->obj = obj;
10262         intel_fb->obj->framebuffer_references++;
10263
10264         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10265         if (ret) {
10266                 DRM_ERROR("framebuffer init failed %d\n", ret);
10267                 return ret;
10268         }
10269
10270         return 0;
10271 }
10272
10273 static struct drm_framebuffer *
10274 intel_user_framebuffer_create(struct drm_device *dev,
10275                               struct drm_file *filp,
10276                               struct drm_mode_fb_cmd2 *mode_cmd)
10277 {
10278         struct drm_i915_gem_object *obj;
10279
10280         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10281                                                 mode_cmd->handles[0]));
10282         if (&obj->base == NULL)
10283                 return ERR_PTR(-ENOENT);
10284
10285         return intel_framebuffer_create(dev, mode_cmd, obj);
10286 }
10287
10288 #ifndef CONFIG_DRM_I915_FBDEV
10289 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10290 {
10291 }
10292 #endif
10293
10294 static const struct drm_mode_config_funcs intel_mode_funcs = {
10295         .fb_create = intel_user_framebuffer_create,
10296         .output_poll_changed = intel_fbdev_output_poll_changed,
10297 };
10298
10299 /* Set up chip specific display functions */
10300 static void intel_init_display(struct drm_device *dev)
10301 {
10302         struct drm_i915_private *dev_priv = dev->dev_private;
10303
10304         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10305                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10306         else if (IS_VALLEYVIEW(dev))
10307                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10308         else if (IS_PINEVIEW(dev))
10309                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10310         else
10311                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10312
10313         if (HAS_DDI(dev)) {
10314                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10315                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10316                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10317                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10318                 dev_priv->display.off = haswell_crtc_off;
10319                 dev_priv->display.update_plane = ironlake_update_plane;
10320         } else if (HAS_PCH_SPLIT(dev)) {
10321                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10322                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10323                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10324                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10325                 dev_priv->display.off = ironlake_crtc_off;
10326                 dev_priv->display.update_plane = ironlake_update_plane;
10327         } else if (IS_VALLEYVIEW(dev)) {
10328                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10329                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10330                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10331                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10332                 dev_priv->display.off = i9xx_crtc_off;
10333                 dev_priv->display.update_plane = i9xx_update_plane;
10334         } else {
10335                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10336                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10337                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10338                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10339                 dev_priv->display.off = i9xx_crtc_off;
10340                 dev_priv->display.update_plane = i9xx_update_plane;
10341         }
10342
10343         /* Returns the core display clock speed */
10344         if (IS_VALLEYVIEW(dev))
10345                 dev_priv->display.get_display_clock_speed =
10346                         valleyview_get_display_clock_speed;
10347         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10348                 dev_priv->display.get_display_clock_speed =
10349                         i945_get_display_clock_speed;
10350         else if (IS_I915G(dev))
10351                 dev_priv->display.get_display_clock_speed =
10352                         i915_get_display_clock_speed;
10353         else if (IS_I945GM(dev) || IS_845G(dev))
10354                 dev_priv->display.get_display_clock_speed =
10355                         i9xx_misc_get_display_clock_speed;
10356         else if (IS_PINEVIEW(dev))
10357                 dev_priv->display.get_display_clock_speed =
10358                         pnv_get_display_clock_speed;
10359         else if (IS_I915GM(dev))
10360                 dev_priv->display.get_display_clock_speed =
10361                         i915gm_get_display_clock_speed;
10362         else if (IS_I865G(dev))
10363                 dev_priv->display.get_display_clock_speed =
10364                         i865_get_display_clock_speed;
10365         else if (IS_I85X(dev))
10366                 dev_priv->display.get_display_clock_speed =
10367                         i855_get_display_clock_speed;
10368         else /* 852, 830 */
10369                 dev_priv->display.get_display_clock_speed =
10370                         i830_get_display_clock_speed;
10371
10372         if (HAS_PCH_SPLIT(dev)) {
10373                 if (IS_GEN5(dev)) {
10374                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10375                         dev_priv->display.write_eld = ironlake_write_eld;
10376                 } else if (IS_GEN6(dev)) {
10377                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10378                         dev_priv->display.write_eld = ironlake_write_eld;
10379                 } else if (IS_IVYBRIDGE(dev)) {
10380                         /* FIXME: detect B0+ stepping and use auto training */
10381                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10382                         dev_priv->display.write_eld = ironlake_write_eld;
10383                         dev_priv->display.modeset_global_resources =
10384                                 ivb_modeset_global_resources;
10385                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10386                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10387                         dev_priv->display.write_eld = haswell_write_eld;
10388                         dev_priv->display.modeset_global_resources =
10389                                 haswell_modeset_global_resources;
10390                 }
10391         } else if (IS_G4X(dev)) {
10392                 dev_priv->display.write_eld = g4x_write_eld;
10393         } else if (IS_VALLEYVIEW(dev))
10394                 dev_priv->display.write_eld = ironlake_write_eld;
10395
10396         /* Default just returns -ENODEV to indicate unsupported */
10397         dev_priv->display.queue_flip = intel_default_queue_flip;
10398
10399         switch (INTEL_INFO(dev)->gen) {
10400         case 2:
10401                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10402                 break;
10403
10404         case 3:
10405                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10406                 break;
10407
10408         case 4:
10409         case 5:
10410                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10411                 break;
10412
10413         case 6:
10414                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10415                 break;
10416         case 7:
10417         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10418                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10419                 break;
10420         }
10421 }
10422
10423 /*
10424  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10425  * resume, or other times.  This quirk makes sure that's the case for
10426  * affected systems.
10427  */
10428 static void quirk_pipea_force(struct drm_device *dev)
10429 {
10430         struct drm_i915_private *dev_priv = dev->dev_private;
10431
10432         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10433         DRM_INFO("applying pipe a force quirk\n");
10434 }
10435
10436 /*
10437  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10438  */
10439 static void quirk_ssc_force_disable(struct drm_device *dev)
10440 {
10441         struct drm_i915_private *dev_priv = dev->dev_private;
10442         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10443         DRM_INFO("applying lvds SSC disable quirk\n");
10444 }
10445
10446 /*
10447  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10448  * brightness value
10449  */
10450 static void quirk_invert_brightness(struct drm_device *dev)
10451 {
10452         struct drm_i915_private *dev_priv = dev->dev_private;
10453         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10454         DRM_INFO("applying inverted panel brightness quirk\n");
10455 }
10456
10457 /*
10458  * Some machines (Dell XPS13) suffer broken backlight controls if
10459  * BLM_PCH_PWM_ENABLE is set.
10460  */
10461 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10462 {
10463         struct drm_i915_private *dev_priv = dev->dev_private;
10464         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10465         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10466 }
10467
10468 struct intel_quirk {
10469         int device;
10470         int subsystem_vendor;
10471         int subsystem_device;
10472         void (*hook)(struct drm_device *dev);
10473 };
10474
10475 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10476 struct intel_dmi_quirk {
10477         void (*hook)(struct drm_device *dev);
10478         const struct dmi_system_id (*dmi_id_list)[];
10479 };
10480
10481 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10482 {
10483         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10484         return 1;
10485 }
10486
10487 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10488         {
10489                 .dmi_id_list = &(const struct dmi_system_id[]) {
10490                         {
10491                                 .callback = intel_dmi_reverse_brightness,
10492                                 .ident = "NCR Corporation",
10493                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10494                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10495                                 },
10496                         },
10497                         { }  /* terminating entry */
10498                 },
10499                 .hook = quirk_invert_brightness,
10500         },
10501 };
10502
10503 static struct intel_quirk intel_quirks[] = {
10504         /* HP Mini needs pipe A force quirk (LP: #322104) */
10505         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10506
10507         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10508         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10509
10510         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10511         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10512
10513         /* 830 needs to leave pipe A & dpll A up */
10514         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10515
10516         /* Lenovo U160 cannot use SSC on LVDS */
10517         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10518
10519         /* Sony Vaio Y cannot use SSC on LVDS */
10520         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10521
10522         /*
10523          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10524          * seem to use inverted backlight PWM.
10525          */
10526         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10527
10528         /* Dell XPS13 HD Sandy Bridge */
10529         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10530         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10531         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10532 };
10533
10534 static void intel_init_quirks(struct drm_device *dev)
10535 {
10536         struct pci_dev *d = dev->pdev;
10537         int i;
10538
10539         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10540                 struct intel_quirk *q = &intel_quirks[i];
10541
10542                 if (d->device == q->device &&
10543                     (d->subsystem_vendor == q->subsystem_vendor ||
10544                      q->subsystem_vendor == PCI_ANY_ID) &&
10545                     (d->subsystem_device == q->subsystem_device ||
10546                      q->subsystem_device == PCI_ANY_ID))
10547                         q->hook(dev);
10548         }
10549         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10550                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10551                         intel_dmi_quirks[i].hook(dev);
10552         }
10553 }
10554
10555 /* Disable the VGA plane that we never use */
10556 static void i915_disable_vga(struct drm_device *dev)
10557 {
10558         struct drm_i915_private *dev_priv = dev->dev_private;
10559         u8 sr1;
10560         u32 vga_reg = i915_vgacntrl_reg(dev);
10561
10562         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10563         outb(SR01, VGA_SR_INDEX);
10564         sr1 = inb(VGA_SR_DATA);
10565         outb(sr1 | 1<<5, VGA_SR_DATA);
10566         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10567         udelay(300);
10568
10569         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10570         POSTING_READ(vga_reg);
10571 }
10572
10573 void intel_modeset_init_hw(struct drm_device *dev)
10574 {
10575         struct drm_i915_private *dev_priv = dev->dev_private;
10576
10577         intel_prepare_ddi(dev);
10578
10579         intel_init_clock_gating(dev);
10580
10581         /* Enable the CRI clock source so we can get at the display */
10582         if (IS_VALLEYVIEW(dev))
10583                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10584                            DPLL_INTEGRATED_CRI_CLK_VLV);
10585
10586         intel_init_dpio(dev);
10587
10588         mutex_lock(&dev->struct_mutex);
10589         intel_enable_gt_powersave(dev);
10590         mutex_unlock(&dev->struct_mutex);
10591 }
10592
10593 void intel_modeset_suspend_hw(struct drm_device *dev)
10594 {
10595         intel_suspend_hw(dev);
10596 }
10597
10598 void intel_modeset_init(struct drm_device *dev)
10599 {
10600         struct drm_i915_private *dev_priv = dev->dev_private;
10601         int i, j, ret;
10602
10603         drm_mode_config_init(dev);
10604
10605         dev->mode_config.min_width = 0;
10606         dev->mode_config.min_height = 0;
10607
10608         dev->mode_config.preferred_depth = 24;
10609         dev->mode_config.prefer_shadow = 1;
10610
10611         dev->mode_config.funcs = &intel_mode_funcs;
10612
10613         intel_init_quirks(dev);
10614
10615         intel_init_pm(dev);
10616
10617         if (INTEL_INFO(dev)->num_pipes == 0)
10618                 return;
10619
10620         intel_init_display(dev);
10621
10622         if (IS_GEN2(dev)) {
10623                 dev->mode_config.max_width = 2048;
10624                 dev->mode_config.max_height = 2048;
10625         } else if (IS_GEN3(dev)) {
10626                 dev->mode_config.max_width = 4096;
10627                 dev->mode_config.max_height = 4096;
10628         } else {
10629                 dev->mode_config.max_width = 8192;
10630                 dev->mode_config.max_height = 8192;
10631         }
10632         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10633
10634         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10635                       INTEL_INFO(dev)->num_pipes,
10636                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10637
10638         for_each_pipe(i) {
10639                 intel_crtc_init(dev, i);
10640                 for (j = 0; j < dev_priv->num_plane; j++) {
10641                         ret = intel_plane_init(dev, i, j);
10642                         if (ret)
10643                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10644                                               pipe_name(i), sprite_name(i, j), ret);
10645                 }
10646         }
10647
10648         intel_cpu_pll_init(dev);
10649         intel_shared_dpll_init(dev);
10650
10651         /* Just disable it once at startup */
10652         i915_disable_vga(dev);
10653         intel_setup_outputs(dev);
10654
10655         /* Just in case the BIOS is doing something questionable. */
10656         intel_disable_fbc(dev);
10657 }
10658
10659 static void
10660 intel_connector_break_all_links(struct intel_connector *connector)
10661 {
10662         connector->base.dpms = DRM_MODE_DPMS_OFF;
10663         connector->base.encoder = NULL;
10664         connector->encoder->connectors_active = false;
10665         connector->encoder->base.crtc = NULL;
10666 }
10667
10668 static void intel_enable_pipe_a(struct drm_device *dev)
10669 {
10670         struct intel_connector *connector;
10671         struct drm_connector *crt = NULL;
10672         struct intel_load_detect_pipe load_detect_temp;
10673
10674         /* We can't just switch on the pipe A, we need to set things up with a
10675          * proper mode and output configuration. As a gross hack, enable pipe A
10676          * by enabling the load detect pipe once. */
10677         list_for_each_entry(connector,
10678                             &dev->mode_config.connector_list,
10679                             base.head) {
10680                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10681                         crt = &connector->base;
10682                         break;
10683                 }
10684         }
10685
10686         if (!crt)
10687                 return;
10688
10689         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10690                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10691
10692
10693 }
10694
10695 static bool
10696 intel_check_plane_mapping(struct intel_crtc *crtc)
10697 {
10698         struct drm_device *dev = crtc->base.dev;
10699         struct drm_i915_private *dev_priv = dev->dev_private;
10700         u32 reg, val;
10701
10702         if (INTEL_INFO(dev)->num_pipes == 1)
10703                 return true;
10704
10705         reg = DSPCNTR(!crtc->plane);
10706         val = I915_READ(reg);
10707
10708         if ((val & DISPLAY_PLANE_ENABLE) &&
10709             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10710                 return false;
10711
10712         return true;
10713 }
10714
10715 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10716 {
10717         struct drm_device *dev = crtc->base.dev;
10718         struct drm_i915_private *dev_priv = dev->dev_private;
10719         u32 reg;
10720
10721         /* Clear any frame start delays used for debugging left by the BIOS */
10722         reg = PIPECONF(crtc->config.cpu_transcoder);
10723         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10724
10725         /* We need to sanitize the plane -> pipe mapping first because this will
10726          * disable the crtc (and hence change the state) if it is wrong. Note
10727          * that gen4+ has a fixed plane -> pipe mapping.  */
10728         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10729                 struct intel_connector *connector;
10730                 bool plane;
10731
10732                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10733                               crtc->base.base.id);
10734
10735                 /* Pipe has the wrong plane attached and the plane is active.
10736                  * Temporarily change the plane mapping and disable everything
10737                  * ...  */
10738                 plane = crtc->plane;
10739                 crtc->plane = !plane;
10740                 dev_priv->display.crtc_disable(&crtc->base);
10741                 crtc->plane = plane;
10742
10743                 /* ... and break all links. */
10744                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10745                                     base.head) {
10746                         if (connector->encoder->base.crtc != &crtc->base)
10747                                 continue;
10748
10749                         intel_connector_break_all_links(connector);
10750                 }
10751
10752                 WARN_ON(crtc->active);
10753                 crtc->base.enabled = false;
10754         }
10755
10756         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10757             crtc->pipe == PIPE_A && !crtc->active) {
10758                 /* BIOS forgot to enable pipe A, this mostly happens after
10759                  * resume. Force-enable the pipe to fix this, the update_dpms
10760                  * call below we restore the pipe to the right state, but leave
10761                  * the required bits on. */
10762                 intel_enable_pipe_a(dev);
10763         }
10764
10765         /* Adjust the state of the output pipe according to whether we
10766          * have active connectors/encoders. */
10767         intel_crtc_update_dpms(&crtc->base);
10768
10769         if (crtc->active != crtc->base.enabled) {
10770                 struct intel_encoder *encoder;
10771
10772                 /* This can happen either due to bugs in the get_hw_state
10773                  * functions or because the pipe is force-enabled due to the
10774                  * pipe A quirk. */
10775                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10776                               crtc->base.base.id,
10777                               crtc->base.enabled ? "enabled" : "disabled",
10778                               crtc->active ? "enabled" : "disabled");
10779
10780                 crtc->base.enabled = crtc->active;
10781
10782                 /* Because we only establish the connector -> encoder ->
10783                  * crtc links if something is active, this means the
10784                  * crtc is now deactivated. Break the links. connector
10785                  * -> encoder links are only establish when things are
10786                  *  actually up, hence no need to break them. */
10787                 WARN_ON(crtc->active);
10788
10789                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10790                         WARN_ON(encoder->connectors_active);
10791                         encoder->base.crtc = NULL;
10792                 }
10793         }
10794 }
10795
10796 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10797 {
10798         struct intel_connector *connector;
10799         struct drm_device *dev = encoder->base.dev;
10800
10801         /* We need to check both for a crtc link (meaning that the
10802          * encoder is active and trying to read from a pipe) and the
10803          * pipe itself being active. */
10804         bool has_active_crtc = encoder->base.crtc &&
10805                 to_intel_crtc(encoder->base.crtc)->active;
10806
10807         if (encoder->connectors_active && !has_active_crtc) {
10808                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10809                               encoder->base.base.id,
10810                               drm_get_encoder_name(&encoder->base));
10811
10812                 /* Connector is active, but has no active pipe. This is
10813                  * fallout from our resume register restoring. Disable
10814                  * the encoder manually again. */
10815                 if (encoder->base.crtc) {
10816                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10817                                       encoder->base.base.id,
10818                                       drm_get_encoder_name(&encoder->base));
10819                         encoder->disable(encoder);
10820                 }
10821
10822                 /* Inconsistent output/port/pipe state happens presumably due to
10823                  * a bug in one of the get_hw_state functions. Or someplace else
10824                  * in our code, like the register restore mess on resume. Clamp
10825                  * things to off as a safer default. */
10826                 list_for_each_entry(connector,
10827                                     &dev->mode_config.connector_list,
10828                                     base.head) {
10829                         if (connector->encoder != encoder)
10830                                 continue;
10831
10832                         intel_connector_break_all_links(connector);
10833                 }
10834         }
10835         /* Enabled encoders without active connectors will be fixed in
10836          * the crtc fixup. */
10837 }
10838
10839 void i915_redisable_vga(struct drm_device *dev)
10840 {
10841         struct drm_i915_private *dev_priv = dev->dev_private;
10842         u32 vga_reg = i915_vgacntrl_reg(dev);
10843
10844         /* This function can be called both from intel_modeset_setup_hw_state or
10845          * at a very early point in our resume sequence, where the power well
10846          * structures are not yet restored. Since this function is at a very
10847          * paranoid "someone might have enabled VGA while we were not looking"
10848          * level, just check if the power well is enabled instead of trying to
10849          * follow the "don't touch the power well if we don't need it" policy
10850          * the rest of the driver uses. */
10851         if (HAS_POWER_WELL(dev) &&
10852             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10853                 return;
10854
10855         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10856                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10857                 i915_disable_vga(dev);
10858         }
10859 }
10860
10861 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10862 {
10863         struct drm_i915_private *dev_priv = dev->dev_private;
10864         enum pipe pipe;
10865         struct intel_crtc *crtc;
10866         struct intel_encoder *encoder;
10867         struct intel_connector *connector;
10868         int i;
10869
10870         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10871                             base.head) {
10872                 memset(&crtc->config, 0, sizeof(crtc->config));
10873
10874                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10875                                                                  &crtc->config);
10876
10877                 crtc->base.enabled = crtc->active;
10878                 crtc->primary_enabled = crtc->active;
10879
10880                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10881                               crtc->base.base.id,
10882                               crtc->active ? "enabled" : "disabled");
10883         }
10884
10885         /* FIXME: Smash this into the new shared dpll infrastructure. */
10886         if (HAS_DDI(dev))
10887                 intel_ddi_setup_hw_pll_state(dev);
10888
10889         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10890                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10891
10892                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10893                 pll->active = 0;
10894                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10895                                     base.head) {
10896                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10897                                 pll->active++;
10898                 }
10899                 pll->refcount = pll->active;
10900
10901                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10902                               pll->name, pll->refcount, pll->on);
10903         }
10904
10905         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10906                             base.head) {
10907                 pipe = 0;
10908
10909                 if (encoder->get_hw_state(encoder, &pipe)) {
10910                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10911                         encoder->base.crtc = &crtc->base;
10912                         if (encoder->get_config)
10913                                 encoder->get_config(encoder, &crtc->config);
10914                 } else {
10915                         encoder->base.crtc = NULL;
10916                 }
10917
10918                 encoder->connectors_active = false;
10919                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10920                               encoder->base.base.id,
10921                               drm_get_encoder_name(&encoder->base),
10922                               encoder->base.crtc ? "enabled" : "disabled",
10923                               pipe_name(pipe));
10924         }
10925
10926         list_for_each_entry(connector, &dev->mode_config.connector_list,
10927                             base.head) {
10928                 if (connector->get_hw_state(connector)) {
10929                         connector->base.dpms = DRM_MODE_DPMS_ON;
10930                         connector->encoder->connectors_active = true;
10931                         connector->base.encoder = &connector->encoder->base;
10932                 } else {
10933                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10934                         connector->base.encoder = NULL;
10935                 }
10936                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10937                               connector->base.base.id,
10938                               drm_get_connector_name(&connector->base),
10939                               connector->base.encoder ? "enabled" : "disabled");
10940         }
10941 }
10942
10943 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10944  * and i915 state tracking structures. */
10945 void intel_modeset_setup_hw_state(struct drm_device *dev,
10946                                   bool force_restore)
10947 {
10948         struct drm_i915_private *dev_priv = dev->dev_private;
10949         enum pipe pipe;
10950         struct intel_crtc *crtc;
10951         struct intel_encoder *encoder;
10952         int i;
10953
10954         intel_modeset_readout_hw_state(dev);
10955
10956         /*
10957          * Now that we have the config, copy it to each CRTC struct
10958          * Note that this could go away if we move to using crtc_config
10959          * checking everywhere.
10960          */
10961         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10962                             base.head) {
10963                 if (crtc->active && i915_fastboot) {
10964                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10965
10966                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10967                                       crtc->base.base.id);
10968                         drm_mode_debug_printmodeline(&crtc->base.mode);
10969                 }
10970         }
10971
10972         /* HW state is read out, now we need to sanitize this mess. */
10973         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10974                             base.head) {
10975                 intel_sanitize_encoder(encoder);
10976         }
10977
10978         for_each_pipe(pipe) {
10979                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10980                 intel_sanitize_crtc(crtc);
10981                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10982         }
10983
10984         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10985                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10986
10987                 if (!pll->on || pll->active)
10988                         continue;
10989
10990                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10991
10992                 pll->disable(dev_priv, pll);
10993                 pll->on = false;
10994         }
10995
10996         if (IS_HASWELL(dev))
10997                 ilk_wm_get_hw_state(dev);
10998
10999         if (force_restore) {
11000                 i915_redisable_vga(dev);
11001
11002                 /*
11003                  * We need to use raw interfaces for restoring state to avoid
11004                  * checking (bogus) intermediate states.
11005                  */
11006                 for_each_pipe(pipe) {
11007                         struct drm_crtc *crtc =
11008                                 dev_priv->pipe_to_crtc_mapping[pipe];
11009
11010                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11011                                          crtc->fb);
11012                 }
11013         } else {
11014                 intel_modeset_update_staged_output_state(dev);
11015         }
11016
11017         intel_modeset_check_state(dev);
11018
11019         drm_mode_config_reset(dev);
11020 }
11021
11022 void intel_modeset_gem_init(struct drm_device *dev)
11023 {
11024         intel_modeset_init_hw(dev);
11025
11026         intel_setup_overlay(dev);
11027
11028         intel_modeset_setup_hw_state(dev, false);
11029 }
11030
11031 void intel_modeset_cleanup(struct drm_device *dev)
11032 {
11033         struct drm_i915_private *dev_priv = dev->dev_private;
11034         struct drm_crtc *crtc;
11035         struct drm_connector *connector;
11036
11037         /*
11038          * Interrupts and polling as the first thing to avoid creating havoc.
11039          * Too much stuff here (turning of rps, connectors, ...) would
11040          * experience fancy races otherwise.
11041          */
11042         drm_irq_uninstall(dev);
11043         cancel_work_sync(&dev_priv->hotplug_work);
11044         /*
11045          * Due to the hpd irq storm handling the hotplug work can re-arm the
11046          * poll handlers. Hence disable polling after hpd handling is shut down.
11047          */
11048         drm_kms_helper_poll_fini(dev);
11049
11050         mutex_lock(&dev->struct_mutex);
11051
11052         intel_unregister_dsm_handler();
11053
11054         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11055                 /* Skip inactive CRTCs */
11056                 if (!crtc->fb)
11057                         continue;
11058
11059                 intel_increase_pllclock(crtc);
11060         }
11061
11062         intel_disable_fbc(dev);
11063
11064         intel_disable_gt_powersave(dev);
11065
11066         ironlake_teardown_rc6(dev);
11067
11068         mutex_unlock(&dev->struct_mutex);
11069
11070         /* flush any delayed tasks or pending work */
11071         flush_scheduled_work();
11072
11073         /* destroy backlight, if any, before the connectors */
11074         intel_panel_destroy_backlight(dev);
11075
11076         /* destroy the sysfs files before encoders/connectors */
11077         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11078                 drm_sysfs_connector_remove(connector);
11079
11080         drm_mode_config_cleanup(dev);
11081
11082         intel_cleanup_overlay(dev);
11083 }
11084
11085 /*
11086  * Return which encoder is currently attached for connector.
11087  */
11088 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11089 {
11090         return &intel_attached_encoder(connector)->base;
11091 }
11092
11093 void intel_connector_attach_encoder(struct intel_connector *connector,
11094                                     struct intel_encoder *encoder)
11095 {
11096         connector->encoder = encoder;
11097         drm_mode_connector_attach_encoder(&connector->base,
11098                                           &encoder->base);
11099 }
11100
11101 /*
11102  * set vga decode state - true == enable VGA decode
11103  */
11104 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11105 {
11106         struct drm_i915_private *dev_priv = dev->dev_private;
11107         u16 gmch_ctrl;
11108
11109         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11110         if (state)
11111                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11112         else
11113                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11114         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11115         return 0;
11116 }
11117
11118 struct intel_display_error_state {
11119
11120         u32 power_well_driver;
11121
11122         int num_transcoders;
11123
11124         struct intel_cursor_error_state {
11125                 u32 control;
11126                 u32 position;
11127                 u32 base;
11128                 u32 size;
11129         } cursor[I915_MAX_PIPES];
11130
11131         struct intel_pipe_error_state {
11132                 u32 source;
11133         } pipe[I915_MAX_PIPES];
11134
11135         struct intel_plane_error_state {
11136                 u32 control;
11137                 u32 stride;
11138                 u32 size;
11139                 u32 pos;
11140                 u32 addr;
11141                 u32 surface;
11142                 u32 tile_offset;
11143         } plane[I915_MAX_PIPES];
11144
11145         struct intel_transcoder_error_state {
11146                 enum transcoder cpu_transcoder;
11147
11148                 u32 conf;
11149
11150                 u32 htotal;
11151                 u32 hblank;
11152                 u32 hsync;
11153                 u32 vtotal;
11154                 u32 vblank;
11155                 u32 vsync;
11156         } transcoder[4];
11157 };
11158
11159 struct intel_display_error_state *
11160 intel_display_capture_error_state(struct drm_device *dev)
11161 {
11162         drm_i915_private_t *dev_priv = dev->dev_private;
11163         struct intel_display_error_state *error;
11164         int transcoders[] = {
11165                 TRANSCODER_A,
11166                 TRANSCODER_B,
11167                 TRANSCODER_C,
11168                 TRANSCODER_EDP,
11169         };
11170         int i;
11171
11172         if (INTEL_INFO(dev)->num_pipes == 0)
11173                 return NULL;
11174
11175         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11176         if (error == NULL)
11177                 return NULL;
11178
11179         if (HAS_POWER_WELL(dev))
11180                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11181
11182         for_each_pipe(i) {
11183                 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11184                         continue;
11185
11186                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11187                         error->cursor[i].control = I915_READ(CURCNTR(i));
11188                         error->cursor[i].position = I915_READ(CURPOS(i));
11189                         error->cursor[i].base = I915_READ(CURBASE(i));
11190                 } else {
11191                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11192                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11193                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11194                 }
11195
11196                 error->plane[i].control = I915_READ(DSPCNTR(i));
11197                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11198                 if (INTEL_INFO(dev)->gen <= 3) {
11199                         error->plane[i].size = I915_READ(DSPSIZE(i));
11200                         error->plane[i].pos = I915_READ(DSPPOS(i));
11201                 }
11202                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11203                         error->plane[i].addr = I915_READ(DSPADDR(i));
11204                 if (INTEL_INFO(dev)->gen >= 4) {
11205                         error->plane[i].surface = I915_READ(DSPSURF(i));
11206                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11207                 }
11208
11209                 error->pipe[i].source = I915_READ(PIPESRC(i));
11210         }
11211
11212         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11213         if (HAS_DDI(dev_priv->dev))
11214                 error->num_transcoders++; /* Account for eDP. */
11215
11216         for (i = 0; i < error->num_transcoders; i++) {
11217                 enum transcoder cpu_transcoder = transcoders[i];
11218
11219                 if (!intel_display_power_enabled(dev,
11220                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11221                         continue;
11222
11223                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11224
11225                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11226                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11227                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11228                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11229                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11230                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11231                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11232         }
11233
11234         return error;
11235 }
11236
11237 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11238
11239 void
11240 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11241                                 struct drm_device *dev,
11242                                 struct intel_display_error_state *error)
11243 {
11244         int i;
11245
11246         if (!error)
11247                 return;
11248
11249         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11250         if (HAS_POWER_WELL(dev))
11251                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11252                            error->power_well_driver);
11253         for_each_pipe(i) {
11254                 err_printf(m, "Pipe [%d]:\n", i);
11255                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11256
11257                 err_printf(m, "Plane [%d]:\n", i);
11258                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11259                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11260                 if (INTEL_INFO(dev)->gen <= 3) {
11261                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11262                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11263                 }
11264                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11265                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11266                 if (INTEL_INFO(dev)->gen >= 4) {
11267                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11268                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11269                 }
11270
11271                 err_printf(m, "Cursor [%d]:\n", i);
11272                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11273                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11274                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11275         }
11276
11277         for (i = 0; i < error->num_transcoders; i++) {
11278                 err_printf(m, "CPU transcoder: %c\n",
11279                            transcoder_name(error->transcoder[i].cpu_transcoder));
11280                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11281                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11282                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11283                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11284                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11285                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11286                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11287         }
11288 }