drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 106 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return state->mode_changed || state->active_changed;
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 default:
1102                         return true;
1103                 }
1104         }
1105
1106         return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111         return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116                 enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121
1122         reg = DPLL(pipe);
1123         val = I915_READ(reg);
1124         cur_state = !!(val & DPLL_VCO_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "PLL state assertion failure (expected %s, current %s)\n",
1127              state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         mutex_lock(&dev_priv->sb_lock);
1137         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138         mutex_unlock(&dev_priv->sb_lock);
1139
1140         cur_state = val & DSI_PLL_VCO_EN;
1141         I915_STATE_WARN(cur_state != state,
1142              "DSI PLL state assertion failure (expected %s, current %s)\n",
1143              state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153         if (crtc->config->shared_dpll < 0)
1154                 return NULL;
1155
1156         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161                         struct intel_shared_dpll *pll,
1162                         bool state)
1163 {
1164         bool cur_state;
1165         struct intel_dpll_hw_state hw_state;
1166
1167         if (WARN (!pll,
1168                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1169                 return;
1170
1171         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172         I915_STATE_WARN(cur_state != state,
1173              "%s assertion failure (expected %s, current %s)\n",
1174              pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178                           enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184                                                                       pipe);
1185
1186         if (HAS_DDI(dev_priv->dev)) {
1187                 /* DDI does not have a specific FDI_TX register */
1188                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189                 val = I915_READ(reg);
1190                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191         } else {
1192                 reg = FDI_TX_CTL(pipe);
1193                 val = I915_READ(reg);
1194                 cur_state = !!(val & FDI_TX_ENABLE);
1195         }
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI TX state assertion failure (expected %s, current %s)\n",
1198              state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204                           enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209
1210         reg = FDI_RX_CTL(pipe);
1211         val = I915_READ(reg);
1212         cur_state = !!(val & FDI_RX_ENABLE);
1213         I915_STATE_WARN(cur_state != state,
1214              "FDI RX state assertion failure (expected %s, current %s)\n",
1215              state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221                                       enum pipe pipe)
1222 {
1223         int reg;
1224         u32 val;
1225
1226         /* ILK FDI PLL is always enabled */
1227         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228                 return;
1229
1230         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231         if (HAS_DDI(dev_priv->dev))
1232                 return;
1233
1234         reg = FDI_TX_CTL(pipe);
1235         val = I915_READ(reg);
1236         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240                        enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245
1246         reg = FDI_RX_CTL(pipe);
1247         val = I915_READ(reg);
1248         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255                            enum pipe pipe)
1256 {
1257         struct drm_device *dev = dev_priv->dev;
1258         int pp_reg;
1259         u32 val;
1260         enum pipe panel_pipe = PIPE_A;
1261         bool locked = true;
1262
1263         if (WARN_ON(HAS_DDI(dev)))
1264                 return;
1265
1266         if (HAS_PCH_SPLIT(dev)) {
1267                 u32 port_sel;
1268
1269                 pp_reg = PCH_PP_CONTROL;
1270                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274                         panel_pipe = PIPE_B;
1275                 /* XXX: else fix for eDP */
1276         } else if (IS_VALLEYVIEW(dev)) {
1277                 /* presumably write lock depends on pipe, not port select */
1278                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279                 panel_pipe = pipe;
1280         } else {
1281                 pp_reg = PP_CONTROL;
1282                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283                         panel_pipe = PIPE_B;
1284         }
1285
1286         val = I915_READ(pp_reg);
1287         if (!(val & PANEL_POWER_ON) ||
1288             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289                 locked = false;
1290
1291         I915_STATE_WARN(panel_pipe == pipe && locked,
1292              "panel assertion failure, pipe %c regs locked\n",
1293              pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297                           enum pipe pipe, bool state)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         bool cur_state;
1301
1302         if (IS_845G(dev) || IS_I865G(dev))
1303                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304         else
1305                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309              pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315                  enum pipe pipe, bool state)
1316 {
1317         int reg;
1318         u32 val;
1319         bool cur_state;
1320         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321                                                                       pipe);
1322
1323         /* if we need the pipe quirk it must be always on */
1324         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326                 state = true;
1327
1328         if (!intel_display_power_is_enabled(dev_priv,
1329                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330                 cur_state = false;
1331         } else {
1332                 reg = PIPECONF(cpu_transcoder);
1333                 val = I915_READ(reg);
1334                 cur_state = !!(val & PIPECONF_ENABLE);
1335         }
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343                          enum plane plane, bool state)
1344 {
1345         int reg;
1346         u32 val;
1347         bool cur_state;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352         I915_STATE_WARN(cur_state != state,
1353              "plane %c assertion failure (expected %s, current %s)\n",
1354              plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361                                    enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int reg, i;
1365         u32 val;
1366         int cur_pipe;
1367
1368         /* Primary planes are fixed to pipes on gen4+ */
1369         if (INTEL_INFO(dev)->gen >= 4) {
1370                 reg = DSPCNTR(pipe);
1371                 val = I915_READ(reg);
1372                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373                      "plane %c assertion failure, should be disabled but not\n",
1374                      plane_name(pipe));
1375                 return;
1376         }
1377
1378         /* Need to check both planes against the pipe */
1379         for_each_pipe(dev_priv, i) {
1380                 reg = DSPCNTR(i);
1381                 val = I915_READ(reg);
1382                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383                         DISPPLANE_SEL_PIPE_SHIFT;
1384                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386                      plane_name(i), pipe_name(pipe));
1387         }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391                                     enum pipe pipe)
1392 {
1393         struct drm_device *dev = dev_priv->dev;
1394         int reg, sprite;
1395         u32 val;
1396
1397         if (INTEL_INFO(dev)->gen >= 9) {
1398                 for_each_sprite(dev_priv, pipe, sprite) {
1399                         val = I915_READ(PLANE_CTL(pipe, sprite));
1400                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite, pipe_name(pipe));
1403                 }
1404         } else if (IS_VALLEYVIEW(dev)) {
1405                 for_each_sprite(dev_priv, pipe, sprite) {
1406                         reg = SPCNTR(pipe, sprite);
1407                         val = I915_READ(reg);
1408                         I915_STATE_WARN(val & SP_ENABLE,
1409                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite_name(pipe, sprite), pipe_name(pipe));
1411                 }
1412         } else if (INTEL_INFO(dev)->gen >= 7) {
1413                 reg = SPRCTL(pipe);
1414                 val = I915_READ(reg);
1415                 I915_STATE_WARN(val & SPRITE_ENABLE,
1416                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417                      plane_name(pipe), pipe_name(pipe));
1418         } else if (INTEL_INFO(dev)->gen >= 5) {
1419                 reg = DVSCNTR(pipe);
1420                 val = I915_READ(reg);
1421                 I915_STATE_WARN(val & DVS_ENABLE,
1422                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423                      plane_name(pipe), pipe_name(pipe));
1424         }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430                 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435         u32 val;
1436         bool enabled;
1437
1438         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440         val = I915_READ(PCH_DREF_CONTROL);
1441         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442                             DREF_SUPERSPREAD_SOURCE_MASK));
1443         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447                                            enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451         bool enabled;
1452
1453         reg = PCH_TRANSCONF(pipe);
1454         val = I915_READ(reg);
1455         enabled = !!(val & TRANS_ENABLE);
1456         I915_STATE_WARN(enabled,
1457              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458              pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462                             enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464         if ((val & DP_PORT_EN) == 0)
1465                 return false;
1466
1467         if (HAS_PCH_CPT(dev_priv->dev)) {
1468                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471                         return false;
1472         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483                               enum pipe pipe, u32 val)
1484 {
1485         if ((val & SDVO_ENABLE) == 0)
1486                 return false;
1487
1488         if (HAS_PCH_CPT(dev_priv->dev)) {
1489                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490                         return false;
1491         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493                         return false;
1494         } else {
1495                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496                         return false;
1497         }
1498         return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502                               enum pipe pipe, u32 val)
1503 {
1504         if ((val & LVDS_PORT_EN) == 0)
1505                 return false;
1506
1507         if (HAS_PCH_CPT(dev_priv->dev)) {
1508                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & ADPA_DAC_ENABLE) == 0)
1521                 return false;
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533                                    enum pipe pipe, int reg, u32 port_sel)
1534 {
1535         u32 val = I915_READ(reg);
1536         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538              reg, pipe_name(pipe));
1539
1540         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541              && (val & DP_PIPEB_SELECT),
1542              "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546                                      enum pipe pipe, int reg)
1547 {
1548         u32 val = I915_READ(reg);
1549         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551              reg, pipe_name(pipe));
1552
1553         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554              && (val & SDVO_PIPE_B_SELECT),
1555              "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559                                       enum pipe pipe)
1560 {
1561         int reg;
1562         u32 val;
1563
1564         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568         reg = PCH_ADPA;
1569         val = I915_READ(reg);
1570         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571              "PCH VGA enabled on transcoder %c, should be disabled\n",
1572              pipe_name(pipe));
1573
1574         reg = PCH_LVDS;
1575         val = I915_READ(reg);
1576         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578              pipe_name(pipe));
1579
1580         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         if (!IS_VALLEYVIEW(dev))
1590                 return;
1591
1592         /*
1593          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594          * CHV x1 PHY (DP/HDMI D)
1595          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596          */
1597         if (IS_CHERRYVIEW(dev)) {
1598                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600         } else {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602         }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606                            const struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_device *dev = crtc->base.dev;
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         int reg = DPLL(crtc->pipe);
1611         u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* No really, not for ILK+ */
1616         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618         /* PLL is protected by panel, make sure we can write it */
1619         if (IS_MOBILE(dev_priv->dev))
1620                 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622         I915_WRITE(reg, dpll);
1623         POSTING_READ(reg);
1624         udelay(150);
1625
1626         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630         POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632         /* We do this three times for luck */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645                            const struct intel_crtc_state *pipe_config)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         int pipe = crtc->pipe;
1650         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651         u32 tmp;
1652
1653         assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657         mutex_lock(&dev_priv->sb_lock);
1658
1659         /* Enable back the 10bit clock to display controller */
1660         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661         tmp |= DPIO_DCLKP_EN;
1662         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664         mutex_unlock(&dev_priv->sb_lock);
1665
1666         /*
1667          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668          */
1669         udelay(1);
1670
1671         /* Enable PLL */
1672         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674         /* Check PLL is locked */
1675         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678         /* not sure when this should be written */
1679         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680         POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685         struct intel_crtc *crtc;
1686         int count = 0;
1687
1688         for_each_intel_crtc(dev, crtc)
1689                 count += crtc->base.state->active &&
1690                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692         return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697         struct drm_device *dev = crtc->base.dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         int reg = DPLL(crtc->pipe);
1700         u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702         assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704         /* No really, not for ILK+ */
1705         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707         /* PLL is protected by panel, make sure we can write it */
1708         if (IS_MOBILE(dev) && !IS_I830(dev))
1709                 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711         /* Enable DVO 2x clock on both PLLs if necessary */
1712         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713                 /*
1714                  * It appears to be important that we don't enable this
1715                  * for the current pipe before otherwise configuring the
1716                  * PLL. No idea how this should be handled if multiple
1717                  * DVO outputs are enabled simultaneosly.
1718                  */
1719                 dpll |= DPLL_DVO_2X_MODE;
1720                 I915_WRITE(DPLL(!crtc->pipe),
1721                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722         }
1723
1724         /* Wait for the clocks to stabilize. */
1725         POSTING_READ(reg);
1726         udelay(150);
1727
1728         if (INTEL_INFO(dev)->gen >= 4) {
1729                 I915_WRITE(DPLL_MD(crtc->pipe),
1730                            crtc->config->dpll_hw_state.dpll_md);
1731         } else {
1732                 /* The pixel multiplier can only be updated once the
1733                  * DPLL is enabled and the clocks are stable.
1734                  *
1735                  * So write it again.
1736                  */
1737                 I915_WRITE(reg, dpll);
1738         }
1739
1740         /* We do this three times for luck */
1741         I915_WRITE(reg, dpll);
1742         POSTING_READ(reg);
1743         udelay(150); /* wait for warmup */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753  * i9xx_disable_pll - disable a PLL
1754  * @dev_priv: i915 private structure
1755  * @pipe: pipe PLL to disable
1756  *
1757  * Disable the PLL for @pipe, making sure the pipe is off first.
1758  *
1759  * Note!  This is for pre-ILK only.
1760  */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         enum pipe pipe = crtc->pipe;
1766
1767         /* Disable DVO 2x clock on both PLLs if necessary */
1768         if (IS_I830(dev) &&
1769             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770             !intel_num_dvo_pipes(dev)) {
1771                 I915_WRITE(DPLL(PIPE_B),
1772                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773                 I915_WRITE(DPLL(PIPE_A),
1774                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775         }
1776
1777         /* Don't disable pipe or pipe PLLs if needed */
1778         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780                 return;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786         POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791         u32 val;
1792
1793         /* Make sure the pipe isn't still relying on us */
1794         assert_pipe_disabled(dev_priv, pipe);
1795
1796         /*
1797          * Leave integrated clock source and reference clock enabled for pipe B.
1798          * The latter is needed for VGA hotplug / manual detection.
1799          */
1800         val = DPLL_VGA_MODE_DIS;
1801         if (pipe == PIPE_B)
1802                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803         I915_WRITE(DPLL(pipe), val);
1804         POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811         u32 val;
1812
1813         /* Make sure the pipe isn't still relying on us */
1814         assert_pipe_disabled(dev_priv, pipe);
1815
1816         /* Set PLL en = 0 */
1817         val = DPLL_SSC_REF_CLK_CHV |
1818                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819         if (pipe != PIPE_A)
1820                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821         I915_WRITE(DPLL(pipe), val);
1822         POSTING_READ(DPLL(pipe));
1823
1824         mutex_lock(&dev_priv->sb_lock);
1825
1826         /* Disable 10bit clock to display controller */
1827         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828         val &= ~DPIO_DCLKP_EN;
1829         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831         /* disable left/right clock distribution */
1832         if (pipe != PIPE_B) {
1833                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836         } else {
1837                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840         }
1841
1842         mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846                          struct intel_digital_port *dport,
1847                          unsigned int expected_mask)
1848 {
1849         u32 port_mask;
1850         int dpll_reg;
1851
1852         switch (dport->port) {
1853         case PORT_B:
1854                 port_mask = DPLL_PORTB_READY_MASK;
1855                 dpll_reg = DPLL(0);
1856                 break;
1857         case PORT_C:
1858                 port_mask = DPLL_PORTC_READY_MASK;
1859                 dpll_reg = DPLL(0);
1860                 expected_mask <<= 4;
1861                 break;
1862         case PORT_D:
1863                 port_mask = DPLL_PORTD_READY_MASK;
1864                 dpll_reg = DPIO_PHY_STATUS;
1865                 break;
1866         default:
1867                 BUG();
1868         }
1869
1870         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->base.dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881         if (WARN_ON(pll == NULL))
1882                 return;
1883
1884         WARN_ON(!pll->config.crtc_mask);
1885         if (pll->active == 0) {
1886                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887                 WARN_ON(pll->on);
1888                 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890                 pll->mode_set(dev_priv, pll);
1891         }
1892 }
1893
1894 /**
1895  * intel_enable_shared_dpll - enable PCH PLL
1896  * @dev_priv: i915 private structure
1897  * @pipe: pipe PLL to enable
1898  *
1899  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900  * drives the transcoder clock.
1901  */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904         struct drm_device *dev = crtc->base.dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908         if (WARN_ON(pll == NULL))
1909                 return;
1910
1911         if (WARN_ON(pll->config.crtc_mask == 0))
1912                 return;
1913
1914         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915                       pll->name, pll->active, pll->on,
1916                       crtc->base.base.id);
1917
1918         if (pll->active++) {
1919                 WARN_ON(!pll->on);
1920                 assert_shared_dpll_enabled(dev_priv, pll);
1921                 return;
1922         }
1923         WARN_ON(pll->on);
1924
1925         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928         pll->enable(dev_priv, pll);
1929         pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934         struct drm_device *dev = crtc->base.dev;
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938         /* PCH only available on ILK+ */
1939         BUG_ON(INTEL_INFO(dev)->gen < 5);
1940         if (pll == NULL)
1941                 return;
1942
1943         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1944                 return;
1945
1946         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947                       pll->name, pll->active, pll->on,
1948                       crtc->base.base.id);
1949
1950         if (WARN_ON(pll->active == 0)) {
1951                 assert_shared_dpll_disabled(dev_priv, pll);
1952                 return;
1953         }
1954
1955         assert_shared_dpll_enabled(dev_priv, pll);
1956         WARN_ON(!pll->on);
1957         if (--pll->active)
1958                 return;
1959
1960         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1961         pll->disable(dev_priv, pll);
1962         pll->on = false;
1963
1964         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1965 }
1966
1967 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1968                                            enum pipe pipe)
1969 {
1970         struct drm_device *dev = dev_priv->dev;
1971         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1973         uint32_t reg, val, pipeconf_val;
1974
1975         /* PCH only available on ILK+ */
1976         BUG_ON(!HAS_PCH_SPLIT(dev));
1977
1978         /* Make sure PCH DPLL is enabled */
1979         assert_shared_dpll_enabled(dev_priv,
1980                                    intel_crtc_to_shared_dpll(intel_crtc));
1981
1982         /* FDI must be feeding us bits for PCH ports */
1983         assert_fdi_tx_enabled(dev_priv, pipe);
1984         assert_fdi_rx_enabled(dev_priv, pipe);
1985
1986         if (HAS_PCH_CPT(dev)) {
1987                 /* Workaround: Set the timing override bit before enabling the
1988                  * pch transcoder. */
1989                 reg = TRANS_CHICKEN2(pipe);
1990                 val = I915_READ(reg);
1991                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992                 I915_WRITE(reg, val);
1993         }
1994
1995         reg = PCH_TRANSCONF(pipe);
1996         val = I915_READ(reg);
1997         pipeconf_val = I915_READ(PIPECONF(pipe));
1998
1999         if (HAS_PCH_IBX(dev_priv->dev)) {
2000                 /*
2001                  * Make the BPC in transcoder be consistent with
2002                  * that in pipeconf reg. For HDMI we must use 8bpc
2003                  * here for both 8bpc and 12bpc.
2004                  */
2005                 val &= ~PIPECONF_BPC_MASK;
2006                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2007                         val |= PIPECONF_8BPC;
2008                 else
2009                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2010         }
2011
2012         val &= ~TRANS_INTERLACE_MASK;
2013         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2014                 if (HAS_PCH_IBX(dev_priv->dev) &&
2015                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2016                         val |= TRANS_LEGACY_INTERLACED_ILK;
2017                 else
2018                         val |= TRANS_INTERLACED;
2019         else
2020                 val |= TRANS_PROGRESSIVE;
2021
2022         I915_WRITE(reg, val | TRANS_ENABLE);
2023         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2024                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2025 }
2026
2027 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2028                                       enum transcoder cpu_transcoder)
2029 {
2030         u32 val, pipeconf_val;
2031
2032         /* PCH only available on ILK+ */
2033         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2034
2035         /* FDI must be feeding us bits for PCH ports */
2036         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2037         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2038
2039         /* Workaround: set timing override bit. */
2040         val = I915_READ(_TRANSA_CHICKEN2);
2041         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2042         I915_WRITE(_TRANSA_CHICKEN2, val);
2043
2044         val = TRANS_ENABLE;
2045         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2046
2047         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2048             PIPECONF_INTERLACED_ILK)
2049                 val |= TRANS_INTERLACED;
2050         else
2051                 val |= TRANS_PROGRESSIVE;
2052
2053         I915_WRITE(LPT_TRANSCONF, val);
2054         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2055                 DRM_ERROR("Failed to enable PCH transcoder\n");
2056 }
2057
2058 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2059                                             enum pipe pipe)
2060 {
2061         struct drm_device *dev = dev_priv->dev;
2062         uint32_t reg, val;
2063
2064         /* FDI relies on the transcoder */
2065         assert_fdi_tx_disabled(dev_priv, pipe);
2066         assert_fdi_rx_disabled(dev_priv, pipe);
2067
2068         /* Ports must be off as well */
2069         assert_pch_ports_disabled(dev_priv, pipe);
2070
2071         reg = PCH_TRANSCONF(pipe);
2072         val = I915_READ(reg);
2073         val &= ~TRANS_ENABLE;
2074         I915_WRITE(reg, val);
2075         /* wait for PCH transcoder off, transcoder state */
2076         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2077                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2078
2079         if (!HAS_PCH_IBX(dev)) {
2080                 /* Workaround: Clear the timing override chicken bit again. */
2081                 reg = TRANS_CHICKEN2(pipe);
2082                 val = I915_READ(reg);
2083                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2084                 I915_WRITE(reg, val);
2085         }
2086 }
2087
2088 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2089 {
2090         u32 val;
2091
2092         val = I915_READ(LPT_TRANSCONF);
2093         val &= ~TRANS_ENABLE;
2094         I915_WRITE(LPT_TRANSCONF, val);
2095         /* wait for PCH transcoder off, transcoder state */
2096         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2097                 DRM_ERROR("Failed to disable PCH transcoder\n");
2098
2099         /* Workaround: clear timing override bit. */
2100         val = I915_READ(_TRANSA_CHICKEN2);
2101         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2102         I915_WRITE(_TRANSA_CHICKEN2, val);
2103 }
2104
2105 /**
2106  * intel_enable_pipe - enable a pipe, asserting requirements
2107  * @crtc: crtc responsible for the pipe
2108  *
2109  * Enable @crtc's pipe, making sure that various hardware specific requirements
2110  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2111  */
2112 static void intel_enable_pipe(struct intel_crtc *crtc)
2113 {
2114         struct drm_device *dev = crtc->base.dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         enum pipe pipe = crtc->pipe;
2117         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2118                                                                       pipe);
2119         enum pipe pch_transcoder;
2120         int reg;
2121         u32 val;
2122
2123         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2124
2125         assert_planes_disabled(dev_priv, pipe);
2126         assert_cursor_disabled(dev_priv, pipe);
2127         assert_sprites_disabled(dev_priv, pipe);
2128
2129         if (HAS_PCH_LPT(dev_priv->dev))
2130                 pch_transcoder = TRANSCODER_A;
2131         else
2132                 pch_transcoder = pipe;
2133
2134         /*
2135          * A pipe without a PLL won't actually be able to drive bits from
2136          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2137          * need the check.
2138          */
2139         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141                         assert_dsi_pll_enabled(dev_priv);
2142                 else
2143                         assert_pll_enabled(dev_priv, pipe);
2144         else {
2145                 if (crtc->config->has_pch_encoder) {
2146                         /* if driving the PCH, we need FDI enabled */
2147                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148                         assert_fdi_tx_pll_enabled(dev_priv,
2149                                                   (enum pipe) cpu_transcoder);
2150                 }
2151                 /* FIXME: assert CPU port conditions for SNB+ */
2152         }
2153
2154         reg = PIPECONF(cpu_transcoder);
2155         val = I915_READ(reg);
2156         if (val & PIPECONF_ENABLE) {
2157                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2159                 return;
2160         }
2161
2162         I915_WRITE(reg, val | PIPECONF_ENABLE);
2163         POSTING_READ(reg);
2164 }
2165
2166 /**
2167  * intel_disable_pipe - disable a pipe, asserting requirements
2168  * @crtc: crtc whose pipes is to be disabled
2169  *
2170  * Disable the pipe of @crtc, making sure that various hardware
2171  * specific requirements are met, if applicable, e.g. plane
2172  * disabled, panel fitter off, etc.
2173  *
2174  * Will wait until the pipe has shut down before returning.
2175  */
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2177 {
2178         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180         enum pipe pipe = crtc->pipe;
2181         int reg;
2182         u32 val;
2183
2184         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2185
2186         /*
2187          * Make sure planes won't keep trying to pump pixels to us,
2188          * or we might hang the display.
2189          */
2190         assert_planes_disabled(dev_priv, pipe);
2191         assert_cursor_disabled(dev_priv, pipe);
2192         assert_sprites_disabled(dev_priv, pipe);
2193
2194         reg = PIPECONF(cpu_transcoder);
2195         val = I915_READ(reg);
2196         if ((val & PIPECONF_ENABLE) == 0)
2197                 return;
2198
2199         /*
2200          * Double wide has implications for planes
2201          * so best keep it disabled when not needed.
2202          */
2203         if (crtc->config->double_wide)
2204                 val &= ~PIPECONF_DOUBLE_WIDE;
2205
2206         /* Don't disable pipe or pipe PLLs if needed */
2207         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2208             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2209                 val &= ~PIPECONF_ENABLE;
2210
2211         I915_WRITE(reg, val);
2212         if ((val & PIPECONF_ENABLE) == 0)
2213                 intel_wait_for_pipe_off(crtc);
2214 }
2215
2216 static bool need_vtd_wa(struct drm_device *dev)
2217 {
2218 #ifdef CONFIG_INTEL_IOMMU
2219         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2220                 return true;
2221 #endif
2222         return false;
2223 }
2224
2225 unsigned int
2226 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2227                   uint64_t fb_format_modifier)
2228 {
2229         unsigned int tile_height;
2230         uint32_t pixel_bytes;
2231
2232         switch (fb_format_modifier) {
2233         case DRM_FORMAT_MOD_NONE:
2234                 tile_height = 1;
2235                 break;
2236         case I915_FORMAT_MOD_X_TILED:
2237                 tile_height = IS_GEN2(dev) ? 16 : 8;
2238                 break;
2239         case I915_FORMAT_MOD_Y_TILED:
2240                 tile_height = 32;
2241                 break;
2242         case I915_FORMAT_MOD_Yf_TILED:
2243                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2244                 switch (pixel_bytes) {
2245                 default:
2246                 case 1:
2247                         tile_height = 64;
2248                         break;
2249                 case 2:
2250                 case 4:
2251                         tile_height = 32;
2252                         break;
2253                 case 8:
2254                         tile_height = 16;
2255                         break;
2256                 case 16:
2257                         WARN_ONCE(1,
2258                                   "128-bit pixels are not supported for display!");
2259                         tile_height = 16;
2260                         break;
2261                 }
2262                 break;
2263         default:
2264                 MISSING_CASE(fb_format_modifier);
2265                 tile_height = 1;
2266                 break;
2267         }
2268
2269         return tile_height;
2270 }
2271
2272 unsigned int
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274                       uint32_t pixel_format, uint64_t fb_format_modifier)
2275 {
2276         return ALIGN(height, intel_tile_height(dev, pixel_format,
2277                                                fb_format_modifier));
2278 }
2279
2280 static int
2281 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2282                         const struct drm_plane_state *plane_state)
2283 {
2284         struct intel_rotation_info *info = &view->rotation_info;
2285         unsigned int tile_height, tile_pitch;
2286
2287         *view = i915_ggtt_view_normal;
2288
2289         if (!plane_state)
2290                 return 0;
2291
2292         if (!intel_rotation_90_or_270(plane_state->rotation))
2293                 return 0;
2294
2295         *view = i915_ggtt_view_rotated;
2296
2297         info->height = fb->height;
2298         info->pixel_format = fb->pixel_format;
2299         info->pitch = fb->pitches[0];
2300         info->fb_modifier = fb->modifier[0];
2301
2302         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2303                                         fb->modifier[0]);
2304         tile_pitch = PAGE_SIZE / tile_height;
2305         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2306         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2307         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2308
2309         return 0;
2310 }
2311
2312 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2313 {
2314         if (INTEL_INFO(dev_priv)->gen >= 9)
2315                 return 256 * 1024;
2316         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317                  IS_VALLEYVIEW(dev_priv))
2318                 return 128 * 1024;
2319         else if (INTEL_INFO(dev_priv)->gen >= 4)
2320                 return 4 * 1024;
2321         else
2322                 return 0;
2323 }
2324
2325 int
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327                            struct drm_framebuffer *fb,
2328                            const struct drm_plane_state *plane_state,
2329                            struct intel_engine_cs *pipelined,
2330                            struct drm_i915_gem_request **pipelined_request)
2331 {
2332         struct drm_device *dev = fb->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2335         struct i915_ggtt_view view;
2336         u32 alignment;
2337         int ret;
2338
2339         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2340
2341         switch (fb->modifier[0]) {
2342         case DRM_FORMAT_MOD_NONE:
2343                 alignment = intel_linear_alignment(dev_priv);
2344                 break;
2345         case I915_FORMAT_MOD_X_TILED:
2346                 if (INTEL_INFO(dev)->gen >= 9)
2347                         alignment = 256 * 1024;
2348                 else {
2349                         /* pin() will align the object as required by fence */
2350                         alignment = 0;
2351                 }
2352                 break;
2353         case I915_FORMAT_MOD_Y_TILED:
2354         case I915_FORMAT_MOD_Yf_TILED:
2355                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356                           "Y tiling bo slipped through, driver bug!\n"))
2357                         return -EINVAL;
2358                 alignment = 1 * 1024 * 1024;
2359                 break;
2360         default:
2361                 MISSING_CASE(fb->modifier[0]);
2362                 return -EINVAL;
2363         }
2364
2365         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2366         if (ret)
2367                 return ret;
2368
2369         /* Note that the w/a also requires 64 PTE of padding following the
2370          * bo. We currently fill all unused PTE with the shadow page and so
2371          * we should always have valid PTE following the scanout preventing
2372          * the VT-d warning.
2373          */
2374         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2375                 alignment = 256 * 1024;
2376
2377         /*
2378          * Global gtt pte registers are special registers which actually forward
2379          * writes to a chunk of system memory. Which means that there is no risk
2380          * that the register values disappear as soon as we call
2381          * intel_runtime_pm_put(), so it is correct to wrap only the
2382          * pin/unpin/fence and not more.
2383          */
2384         intel_runtime_pm_get(dev_priv);
2385
2386         dev_priv->mm.interruptible = false;
2387         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2388                                                    pipelined_request, &view);
2389         if (ret)
2390                 goto err_interruptible;
2391
2392         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393          * fence, whereas 965+ only requires a fence if using
2394          * framebuffer compression.  For simplicity, we always install
2395          * a fence as the cost is not that onerous.
2396          */
2397         ret = i915_gem_object_get_fence(obj);
2398         if (ret)
2399                 goto err_unpin;
2400
2401         i915_gem_object_pin_fence(obj);
2402
2403         dev_priv->mm.interruptible = true;
2404         intel_runtime_pm_put(dev_priv);
2405         return 0;
2406
2407 err_unpin:
2408         i915_gem_object_unpin_from_display_plane(obj, &view);
2409 err_interruptible:
2410         dev_priv->mm.interruptible = true;
2411         intel_runtime_pm_put(dev_priv);
2412         return ret;
2413 }
2414
2415 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416                                const struct drm_plane_state *plane_state)
2417 {
2418         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2419         struct i915_ggtt_view view;
2420         int ret;
2421
2422         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2423
2424         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425         WARN_ONCE(ret, "Couldn't get view from plane state!");
2426
2427         i915_gem_object_unpin_fence(obj);
2428         i915_gem_object_unpin_from_display_plane(obj, &view);
2429 }
2430
2431 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432  * is assumed to be a power-of-two. */
2433 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2434                                              int *x, int *y,
2435                                              unsigned int tiling_mode,
2436                                              unsigned int cpp,
2437                                              unsigned int pitch)
2438 {
2439         if (tiling_mode != I915_TILING_NONE) {
2440                 unsigned int tile_rows, tiles;
2441
2442                 tile_rows = *y / 8;
2443                 *y %= 8;
2444
2445                 tiles = *x / (512/cpp);
2446                 *x %= 512/cpp;
2447
2448                 return tile_rows * pitch * 8 + tiles * 4096;
2449         } else {
2450                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2451                 unsigned int offset;
2452
2453                 offset = *y * pitch + *x * cpp;
2454                 *y = (offset & alignment) / pitch;
2455                 *x = ((offset & alignment) - *y * pitch) / cpp;
2456                 return offset & ~alignment;
2457         }
2458 }
2459
2460 static int i9xx_format_to_fourcc(int format)
2461 {
2462         switch (format) {
2463         case DISPPLANE_8BPP:
2464                 return DRM_FORMAT_C8;
2465         case DISPPLANE_BGRX555:
2466                 return DRM_FORMAT_XRGB1555;
2467         case DISPPLANE_BGRX565:
2468                 return DRM_FORMAT_RGB565;
2469         default:
2470         case DISPPLANE_BGRX888:
2471                 return DRM_FORMAT_XRGB8888;
2472         case DISPPLANE_RGBX888:
2473                 return DRM_FORMAT_XBGR8888;
2474         case DISPPLANE_BGRX101010:
2475                 return DRM_FORMAT_XRGB2101010;
2476         case DISPPLANE_RGBX101010:
2477                 return DRM_FORMAT_XBGR2101010;
2478         }
2479 }
2480
2481 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2482 {
2483         switch (format) {
2484         case PLANE_CTL_FORMAT_RGB_565:
2485                 return DRM_FORMAT_RGB565;
2486         default:
2487         case PLANE_CTL_FORMAT_XRGB_8888:
2488                 if (rgb_order) {
2489                         if (alpha)
2490                                 return DRM_FORMAT_ABGR8888;
2491                         else
2492                                 return DRM_FORMAT_XBGR8888;
2493                 } else {
2494                         if (alpha)
2495                                 return DRM_FORMAT_ARGB8888;
2496                         else
2497                                 return DRM_FORMAT_XRGB8888;
2498                 }
2499         case PLANE_CTL_FORMAT_XRGB_2101010:
2500                 if (rgb_order)
2501                         return DRM_FORMAT_XBGR2101010;
2502                 else
2503                         return DRM_FORMAT_XRGB2101010;
2504         }
2505 }
2506
2507 static bool
2508 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509                               struct intel_initial_plane_config *plane_config)
2510 {
2511         struct drm_device *dev = crtc->base.dev;
2512         struct drm_i915_gem_object *obj = NULL;
2513         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2514         struct drm_framebuffer *fb = &plane_config->fb->base;
2515         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2516         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2517                                     PAGE_SIZE);
2518
2519         size_aligned -= base_aligned;
2520
2521         if (plane_config->size == 0)
2522                 return false;
2523
2524         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2525                                                              base_aligned,
2526                                                              base_aligned,
2527                                                              size_aligned);
2528         if (!obj)
2529                 return false;
2530
2531         obj->tiling_mode = plane_config->tiling;
2532         if (obj->tiling_mode == I915_TILING_X)
2533                 obj->stride = fb->pitches[0];
2534
2535         mode_cmd.pixel_format = fb->pixel_format;
2536         mode_cmd.width = fb->width;
2537         mode_cmd.height = fb->height;
2538         mode_cmd.pitches[0] = fb->pitches[0];
2539         mode_cmd.modifier[0] = fb->modifier[0];
2540         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2541
2542         mutex_lock(&dev->struct_mutex);
2543         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2544                                    &mode_cmd, obj)) {
2545                 DRM_DEBUG_KMS("intel fb init failed\n");
2546                 goto out_unref_obj;
2547         }
2548         mutex_unlock(&dev->struct_mutex);
2549
2550         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2551         return true;
2552
2553 out_unref_obj:
2554         drm_gem_object_unreference(&obj->base);
2555         mutex_unlock(&dev->struct_mutex);
2556         return false;
2557 }
2558
2559 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2560 static void
2561 update_state_fb(struct drm_plane *plane)
2562 {
2563         if (plane->fb == plane->state->fb)
2564                 return;
2565
2566         if (plane->state->fb)
2567                 drm_framebuffer_unreference(plane->state->fb);
2568         plane->state->fb = plane->fb;
2569         if (plane->state->fb)
2570                 drm_framebuffer_reference(plane->state->fb);
2571 }
2572
2573 static void
2574 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2575                              struct intel_initial_plane_config *plane_config)
2576 {
2577         struct drm_device *dev = intel_crtc->base.dev;
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         struct drm_crtc *c;
2580         struct intel_crtc *i;
2581         struct drm_i915_gem_object *obj;
2582         struct drm_plane *primary = intel_crtc->base.primary;
2583         struct drm_plane_state *plane_state = primary->state;
2584         struct drm_framebuffer *fb;
2585
2586         if (!plane_config->fb)
2587                 return;
2588
2589         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2590                 fb = &plane_config->fb->base;
2591                 goto valid_fb;
2592         }
2593
2594         kfree(plane_config->fb);
2595
2596         /*
2597          * Failed to alloc the obj, check to see if we should share
2598          * an fb with another CRTC instead
2599          */
2600         for_each_crtc(dev, c) {
2601                 i = to_intel_crtc(c);
2602
2603                 if (c == &intel_crtc->base)
2604                         continue;
2605
2606                 if (!i->active)
2607                         continue;
2608
2609                 fb = c->primary->fb;
2610                 if (!fb)
2611                         continue;
2612
2613                 obj = intel_fb_obj(fb);
2614                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2615                         drm_framebuffer_reference(fb);
2616                         goto valid_fb;
2617                 }
2618         }
2619
2620         return;
2621
2622 valid_fb:
2623         plane_state->src_x = plane_state->src_y = 0;
2624         plane_state->src_w = fb->width << 16;
2625         plane_state->src_h = fb->height << 16;
2626
2627         plane_state->crtc_x = plane_state->src_y = 0;
2628         plane_state->crtc_w = fb->width;
2629         plane_state->crtc_h = fb->height;
2630
2631         obj = intel_fb_obj(fb);
2632         if (obj->tiling_mode != I915_TILING_NONE)
2633                 dev_priv->preserve_bios_swizzle = true;
2634
2635         drm_framebuffer_reference(fb);
2636         primary->fb = primary->state->fb = fb;
2637         primary->crtc = primary->state->crtc = &intel_crtc->base;
2638         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2639         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2640 }
2641
2642 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2643                                       struct drm_framebuffer *fb,
2644                                       int x, int y)
2645 {
2646         struct drm_device *dev = crtc->dev;
2647         struct drm_i915_private *dev_priv = dev->dev_private;
2648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2649         struct drm_plane *primary = crtc->primary;
2650         bool visible = to_intel_plane_state(primary->state)->visible;
2651         struct drm_i915_gem_object *obj;
2652         int plane = intel_crtc->plane;
2653         unsigned long linear_offset;
2654         u32 dspcntr;
2655         u32 reg = DSPCNTR(plane);
2656         int pixel_size;
2657
2658         if (!visible || !fb) {
2659                 I915_WRITE(reg, 0);
2660                 if (INTEL_INFO(dev)->gen >= 4)
2661                         I915_WRITE(DSPSURF(plane), 0);
2662                 else
2663                         I915_WRITE(DSPADDR(plane), 0);
2664                 POSTING_READ(reg);
2665                 return;
2666         }
2667
2668         obj = intel_fb_obj(fb);
2669         if (WARN_ON(obj == NULL))
2670                 return;
2671
2672         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2673
2674         dspcntr = DISPPLANE_GAMMA_ENABLE;
2675
2676         dspcntr |= DISPLAY_PLANE_ENABLE;
2677
2678         if (INTEL_INFO(dev)->gen < 4) {
2679                 if (intel_crtc->pipe == PIPE_B)
2680                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2681
2682                 /* pipesrc and dspsize control the size that is scaled from,
2683                  * which should always be the user's requested size.
2684                  */
2685                 I915_WRITE(DSPSIZE(plane),
2686                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2687                            (intel_crtc->config->pipe_src_w - 1));
2688                 I915_WRITE(DSPPOS(plane), 0);
2689         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2690                 I915_WRITE(PRIMSIZE(plane),
2691                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2692                            (intel_crtc->config->pipe_src_w - 1));
2693                 I915_WRITE(PRIMPOS(plane), 0);
2694                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2695         }
2696
2697         switch (fb->pixel_format) {
2698         case DRM_FORMAT_C8:
2699                 dspcntr |= DISPPLANE_8BPP;
2700                 break;
2701         case DRM_FORMAT_XRGB1555:
2702                 dspcntr |= DISPPLANE_BGRX555;
2703                 break;
2704         case DRM_FORMAT_RGB565:
2705                 dspcntr |= DISPPLANE_BGRX565;
2706                 break;
2707         case DRM_FORMAT_XRGB8888:
2708                 dspcntr |= DISPPLANE_BGRX888;
2709                 break;
2710         case DRM_FORMAT_XBGR8888:
2711                 dspcntr |= DISPPLANE_RGBX888;
2712                 break;
2713         case DRM_FORMAT_XRGB2101010:
2714                 dspcntr |= DISPPLANE_BGRX101010;
2715                 break;
2716         case DRM_FORMAT_XBGR2101010:
2717                 dspcntr |= DISPPLANE_RGBX101010;
2718                 break;
2719         default:
2720                 BUG();
2721         }
2722
2723         if (INTEL_INFO(dev)->gen >= 4 &&
2724             obj->tiling_mode != I915_TILING_NONE)
2725                 dspcntr |= DISPPLANE_TILED;
2726
2727         if (IS_G4X(dev))
2728                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2729
2730         linear_offset = y * fb->pitches[0] + x * pixel_size;
2731
2732         if (INTEL_INFO(dev)->gen >= 4) {
2733                 intel_crtc->dspaddr_offset =
2734                         intel_gen4_compute_page_offset(dev_priv,
2735                                                        &x, &y, obj->tiling_mode,
2736                                                        pixel_size,
2737                                                        fb->pitches[0]);
2738                 linear_offset -= intel_crtc->dspaddr_offset;
2739         } else {
2740                 intel_crtc->dspaddr_offset = linear_offset;
2741         }
2742
2743         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2744                 dspcntr |= DISPPLANE_ROTATE_180;
2745
2746                 x += (intel_crtc->config->pipe_src_w - 1);
2747                 y += (intel_crtc->config->pipe_src_h - 1);
2748
2749                 /* Finding the last pixel of the last line of the display
2750                 data and adding to linear_offset*/
2751                 linear_offset +=
2752                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2753                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2754         }
2755
2756         I915_WRITE(reg, dspcntr);
2757
2758         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2759         if (INTEL_INFO(dev)->gen >= 4) {
2760                 I915_WRITE(DSPSURF(plane),
2761                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2762                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2763                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2764         } else
2765                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2766         POSTING_READ(reg);
2767 }
2768
2769 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2770                                           struct drm_framebuffer *fb,
2771                                           int x, int y)
2772 {
2773         struct drm_device *dev = crtc->dev;
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776         struct drm_plane *primary = crtc->primary;
2777         bool visible = to_intel_plane_state(primary->state)->visible;
2778         struct drm_i915_gem_object *obj;
2779         int plane = intel_crtc->plane;
2780         unsigned long linear_offset;
2781         u32 dspcntr;
2782         u32 reg = DSPCNTR(plane);
2783         int pixel_size;
2784
2785         if (!visible || !fb) {
2786                 I915_WRITE(reg, 0);
2787                 I915_WRITE(DSPSURF(plane), 0);
2788                 POSTING_READ(reg);
2789                 return;
2790         }
2791
2792         obj = intel_fb_obj(fb);
2793         if (WARN_ON(obj == NULL))
2794                 return;
2795
2796         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2797
2798         dspcntr = DISPPLANE_GAMMA_ENABLE;
2799
2800         dspcntr |= DISPLAY_PLANE_ENABLE;
2801
2802         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2804
2805         switch (fb->pixel_format) {
2806         case DRM_FORMAT_C8:
2807                 dspcntr |= DISPPLANE_8BPP;
2808                 break;
2809         case DRM_FORMAT_RGB565:
2810                 dspcntr |= DISPPLANE_BGRX565;
2811                 break;
2812         case DRM_FORMAT_XRGB8888:
2813                 dspcntr |= DISPPLANE_BGRX888;
2814                 break;
2815         case DRM_FORMAT_XBGR8888:
2816                 dspcntr |= DISPPLANE_RGBX888;
2817                 break;
2818         case DRM_FORMAT_XRGB2101010:
2819                 dspcntr |= DISPPLANE_BGRX101010;
2820                 break;
2821         case DRM_FORMAT_XBGR2101010:
2822                 dspcntr |= DISPPLANE_RGBX101010;
2823                 break;
2824         default:
2825                 BUG();
2826         }
2827
2828         if (obj->tiling_mode != I915_TILING_NONE)
2829                 dspcntr |= DISPPLANE_TILED;
2830
2831         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2832                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2833
2834         linear_offset = y * fb->pitches[0] + x * pixel_size;
2835         intel_crtc->dspaddr_offset =
2836                 intel_gen4_compute_page_offset(dev_priv,
2837                                                &x, &y, obj->tiling_mode,
2838                                                pixel_size,
2839                                                fb->pitches[0]);
2840         linear_offset -= intel_crtc->dspaddr_offset;
2841         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2842                 dspcntr |= DISPPLANE_ROTATE_180;
2843
2844                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2845                         x += (intel_crtc->config->pipe_src_w - 1);
2846                         y += (intel_crtc->config->pipe_src_h - 1);
2847
2848                         /* Finding the last pixel of the last line of the display
2849                         data and adding to linear_offset*/
2850                         linear_offset +=
2851                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2852                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2853                 }
2854         }
2855
2856         I915_WRITE(reg, dspcntr);
2857
2858         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2859         I915_WRITE(DSPSURF(plane),
2860                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2861         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2862                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2863         } else {
2864                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2865                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2866         }
2867         POSTING_READ(reg);
2868 }
2869
2870 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2871                               uint32_t pixel_format)
2872 {
2873         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2874
2875         /*
2876          * The stride is either expressed as a multiple of 64 bytes
2877          * chunks for linear buffers or in number of tiles for tiled
2878          * buffers.
2879          */
2880         switch (fb_modifier) {
2881         case DRM_FORMAT_MOD_NONE:
2882                 return 64;
2883         case I915_FORMAT_MOD_X_TILED:
2884                 if (INTEL_INFO(dev)->gen == 2)
2885                         return 128;
2886                 return 512;
2887         case I915_FORMAT_MOD_Y_TILED:
2888                 /* No need to check for old gens and Y tiling since this is
2889                  * about the display engine and those will be blocked before
2890                  * we get here.
2891                  */
2892                 return 128;
2893         case I915_FORMAT_MOD_Yf_TILED:
2894                 if (bits_per_pixel == 8)
2895                         return 64;
2896                 else
2897                         return 128;
2898         default:
2899                 MISSING_CASE(fb_modifier);
2900                 return 64;
2901         }
2902 }
2903
2904 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2905                                      struct drm_i915_gem_object *obj)
2906 {
2907         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2908
2909         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2910                 view = &i915_ggtt_view_rotated;
2911
2912         return i915_gem_obj_ggtt_offset_view(obj, view);
2913 }
2914
2915 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2916 {
2917         struct drm_device *dev = intel_crtc->base.dev;
2918         struct drm_i915_private *dev_priv = dev->dev_private;
2919
2920         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2921         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2922         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2923         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2924                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2925 }
2926
2927 /*
2928  * This function detaches (aka. unbinds) unused scalers in hardware
2929  */
2930 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2931 {
2932         struct intel_crtc_scaler_state *scaler_state;
2933         int i;
2934
2935         scaler_state = &intel_crtc->config->scaler_state;
2936
2937         /* loop through and disable scalers that aren't in use */
2938         for (i = 0; i < intel_crtc->num_scalers; i++) {
2939                 if (!scaler_state->scalers[i].in_use)
2940                         skl_detach_scaler(intel_crtc, i);
2941         }
2942 }
2943
2944 u32 skl_plane_ctl_format(uint32_t pixel_format)
2945 {
2946         switch (pixel_format) {
2947         case DRM_FORMAT_C8:
2948                 return PLANE_CTL_FORMAT_INDEXED;
2949         case DRM_FORMAT_RGB565:
2950                 return PLANE_CTL_FORMAT_RGB_565;
2951         case DRM_FORMAT_XBGR8888:
2952                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2953         case DRM_FORMAT_XRGB8888:
2954                 return PLANE_CTL_FORMAT_XRGB_8888;
2955         /*
2956          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957          * to be already pre-multiplied. We need to add a knob (or a different
2958          * DRM_FORMAT) for user-space to configure that.
2959          */
2960         case DRM_FORMAT_ABGR8888:
2961                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2962                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2963         case DRM_FORMAT_ARGB8888:
2964                 return PLANE_CTL_FORMAT_XRGB_8888 |
2965                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966         case DRM_FORMAT_XRGB2101010:
2967                 return PLANE_CTL_FORMAT_XRGB_2101010;
2968         case DRM_FORMAT_XBGR2101010:
2969                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2970         case DRM_FORMAT_YUYV:
2971                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2972         case DRM_FORMAT_YVYU:
2973                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2974         case DRM_FORMAT_UYVY:
2975                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2976         case DRM_FORMAT_VYUY:
2977                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2978         default:
2979                 MISSING_CASE(pixel_format);
2980         }
2981
2982         return 0;
2983 }
2984
2985 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2986 {
2987         switch (fb_modifier) {
2988         case DRM_FORMAT_MOD_NONE:
2989                 break;
2990         case I915_FORMAT_MOD_X_TILED:
2991                 return PLANE_CTL_TILED_X;
2992         case I915_FORMAT_MOD_Y_TILED:
2993                 return PLANE_CTL_TILED_Y;
2994         case I915_FORMAT_MOD_Yf_TILED:
2995                 return PLANE_CTL_TILED_YF;
2996         default:
2997                 MISSING_CASE(fb_modifier);
2998         }
2999
3000         return 0;
3001 }
3002
3003 u32 skl_plane_ctl_rotation(unsigned int rotation)
3004 {
3005         switch (rotation) {
3006         case BIT(DRM_ROTATE_0):
3007                 break;
3008         /*
3009          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010          * while i915 HW rotation is clockwise, thats why this swapping.
3011          */
3012         case BIT(DRM_ROTATE_90):
3013                 return PLANE_CTL_ROTATE_270;
3014         case BIT(DRM_ROTATE_180):
3015                 return PLANE_CTL_ROTATE_180;
3016         case BIT(DRM_ROTATE_270):
3017                 return PLANE_CTL_ROTATE_90;
3018         default:
3019                 MISSING_CASE(rotation);
3020         }
3021
3022         return 0;
3023 }
3024
3025 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3026                                          struct drm_framebuffer *fb,
3027                                          int x, int y)
3028 {
3029         struct drm_device *dev = crtc->dev;
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032         struct drm_plane *plane = crtc->primary;
3033         bool visible = to_intel_plane_state(plane->state)->visible;
3034         struct drm_i915_gem_object *obj;
3035         int pipe = intel_crtc->pipe;
3036         u32 plane_ctl, stride_div, stride;
3037         u32 tile_height, plane_offset, plane_size;
3038         unsigned int rotation;
3039         int x_offset, y_offset;
3040         unsigned long surf_addr;
3041         struct intel_crtc_state *crtc_state = intel_crtc->config;
3042         struct intel_plane_state *plane_state;
3043         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3044         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3045         int scaler_id = -1;
3046
3047         plane_state = to_intel_plane_state(plane->state);
3048
3049         if (!visible || !fb) {
3050                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3051                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3052                 POSTING_READ(PLANE_CTL(pipe, 0));
3053                 return;
3054         }
3055
3056         plane_ctl = PLANE_CTL_ENABLE |
3057                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3058                     PLANE_CTL_PIPE_CSC_ENABLE;
3059
3060         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3061         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3062         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3063
3064         rotation = plane->state->rotation;
3065         plane_ctl |= skl_plane_ctl_rotation(rotation);
3066
3067         obj = intel_fb_obj(fb);
3068         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3069                                                fb->pixel_format);
3070         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3071
3072         /*
3073          * FIXME: intel_plane_state->src, dst aren't set when transitional
3074          * update_plane helpers are called from legacy paths.
3075          * Once full atomic crtc is available, below check can be avoided.
3076          */
3077         if (drm_rect_width(&plane_state->src)) {
3078                 scaler_id = plane_state->scaler_id;
3079                 src_x = plane_state->src.x1 >> 16;
3080                 src_y = plane_state->src.y1 >> 16;
3081                 src_w = drm_rect_width(&plane_state->src) >> 16;
3082                 src_h = drm_rect_height(&plane_state->src) >> 16;
3083                 dst_x = plane_state->dst.x1;
3084                 dst_y = plane_state->dst.y1;
3085                 dst_w = drm_rect_width(&plane_state->dst);
3086                 dst_h = drm_rect_height(&plane_state->dst);
3087
3088                 WARN_ON(x != src_x || y != src_y);
3089         } else {
3090                 src_w = intel_crtc->config->pipe_src_w;
3091                 src_h = intel_crtc->config->pipe_src_h;
3092         }
3093
3094         if (intel_rotation_90_or_270(rotation)) {
3095                 /* stride = Surface height in tiles */
3096                 tile_height = intel_tile_height(dev, fb->pixel_format,
3097                                                 fb->modifier[0]);
3098                 stride = DIV_ROUND_UP(fb->height, tile_height);
3099                 x_offset = stride * tile_height - y - src_h;
3100                 y_offset = x;
3101                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3102         } else {
3103                 stride = fb->pitches[0] / stride_div;
3104                 x_offset = x;
3105                 y_offset = y;
3106                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3107         }
3108         plane_offset = y_offset << 16 | x_offset;
3109
3110         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3111         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3112         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3113         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3114
3115         if (scaler_id >= 0) {
3116                 uint32_t ps_ctrl = 0;
3117
3118                 WARN_ON(!dst_w || !dst_h);
3119                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3120                         crtc_state->scaler_state.scalers[scaler_id].mode;
3121                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3122                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3123                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3124                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3125                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3126         } else {
3127                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3128         }
3129
3130         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3131
3132         POSTING_READ(PLANE_SURF(pipe, 0));
3133 }
3134
3135 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3136 static int
3137 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3138                            int x, int y, enum mode_set_atomic state)
3139 {
3140         struct drm_device *dev = crtc->dev;
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142
3143         if (dev_priv->fbc.disable_fbc)
3144                 dev_priv->fbc.disable_fbc(dev_priv);
3145
3146         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3147
3148         return 0;
3149 }
3150
3151 static void intel_complete_page_flips(struct drm_device *dev)
3152 {
3153         struct drm_crtc *crtc;
3154
3155         for_each_crtc(dev, crtc) {
3156                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157                 enum plane plane = intel_crtc->plane;
3158
3159                 intel_prepare_page_flip(dev, plane);
3160                 intel_finish_page_flip_plane(dev, plane);
3161         }
3162 }
3163
3164 static void intel_update_primary_planes(struct drm_device *dev)
3165 {
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct drm_crtc *crtc;
3168
3169         for_each_crtc(dev, crtc) {
3170                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171
3172                 drm_modeset_lock(&crtc->mutex, NULL);
3173                 /*
3174                  * FIXME: Once we have proper support for primary planes (and
3175                  * disabling them without disabling the entire crtc) allow again
3176                  * a NULL crtc->primary->fb.
3177                  */
3178                 if (intel_crtc->active && crtc->primary->fb)
3179                         dev_priv->display.update_primary_plane(crtc,
3180                                                                crtc->primary->fb,
3181                                                                crtc->x,
3182                                                                crtc->y);
3183                 drm_modeset_unlock(&crtc->mutex);
3184         }
3185 }
3186
3187 void intel_prepare_reset(struct drm_device *dev)
3188 {
3189         /* no reset support for gen2 */
3190         if (IS_GEN2(dev))
3191                 return;
3192
3193         /* reset doesn't touch the display */
3194         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3195                 return;
3196
3197         drm_modeset_lock_all(dev);
3198         /*
3199          * Disabling the crtcs gracefully seems nicer. Also the
3200          * g33 docs say we should at least disable all the planes.
3201          */
3202         intel_display_suspend(dev);
3203 }
3204
3205 void intel_finish_reset(struct drm_device *dev)
3206 {
3207         struct drm_i915_private *dev_priv = to_i915(dev);
3208
3209         /*
3210          * Flips in the rings will be nuked by the reset,
3211          * so complete all pending flips so that user space
3212          * will get its events and not get stuck.
3213          */
3214         intel_complete_page_flips(dev);
3215
3216         /* no reset support for gen2 */
3217         if (IS_GEN2(dev))
3218                 return;
3219
3220         /* reset doesn't touch the display */
3221         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3222                 /*
3223                  * Flips in the rings have been nuked by the reset,
3224                  * so update the base address of all primary
3225                  * planes to the the last fb to make sure we're
3226                  * showing the correct fb after a reset.
3227                  */
3228                 intel_update_primary_planes(dev);
3229                 return;
3230         }
3231
3232         /*
3233          * The display has been reset as well,
3234          * so need a full re-initialization.
3235          */
3236         intel_runtime_pm_disable_interrupts(dev_priv);
3237         intel_runtime_pm_enable_interrupts(dev_priv);
3238
3239         intel_modeset_init_hw(dev);
3240
3241         spin_lock_irq(&dev_priv->irq_lock);
3242         if (dev_priv->display.hpd_irq_setup)
3243                 dev_priv->display.hpd_irq_setup(dev);
3244         spin_unlock_irq(&dev_priv->irq_lock);
3245
3246         intel_display_resume(dev);
3247
3248         intel_hpd_init(dev_priv);
3249
3250         drm_modeset_unlock_all(dev);
3251 }
3252
3253 static void
3254 intel_finish_fb(struct drm_framebuffer *old_fb)
3255 {
3256         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3257         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3258         bool was_interruptible = dev_priv->mm.interruptible;
3259         int ret;
3260
3261         /* Big Hammer, we also need to ensure that any pending
3262          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3263          * current scanout is retired before unpinning the old
3264          * framebuffer. Note that we rely on userspace rendering
3265          * into the buffer attached to the pipe they are waiting
3266          * on. If not, userspace generates a GPU hang with IPEHR
3267          * point to the MI_WAIT_FOR_EVENT.
3268          *
3269          * This should only fail upon a hung GPU, in which case we
3270          * can safely continue.
3271          */
3272         dev_priv->mm.interruptible = false;
3273         ret = i915_gem_object_wait_rendering(obj, true);
3274         dev_priv->mm.interruptible = was_interruptible;
3275
3276         WARN_ON(ret);
3277 }
3278
3279 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3280 {
3281         struct drm_device *dev = crtc->dev;
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         bool pending;
3285
3286         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3287             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3288                 return false;
3289
3290         spin_lock_irq(&dev->event_lock);
3291         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3292         spin_unlock_irq(&dev->event_lock);
3293
3294         return pending;
3295 }
3296
3297 static void intel_update_pipe_size(struct intel_crtc *crtc)
3298 {
3299         struct drm_device *dev = crtc->base.dev;
3300         struct drm_i915_private *dev_priv = dev->dev_private;
3301         const struct drm_display_mode *adjusted_mode;
3302
3303         if (!i915.fastboot)
3304                 return;
3305
3306         /*
3307          * Update pipe size and adjust fitter if needed: the reason for this is
3308          * that in compute_mode_changes we check the native mode (not the pfit
3309          * mode) to see if we can flip rather than do a full mode set. In the
3310          * fastboot case, we'll flip, but if we don't update the pipesrc and
3311          * pfit state, we'll end up with a big fb scanned out into the wrong
3312          * sized surface.
3313          *
3314          * To fix this properly, we need to hoist the checks up into
3315          * compute_mode_changes (or above), check the actual pfit state and
3316          * whether the platform allows pfit disable with pipe active, and only
3317          * then update the pipesrc and pfit state, even on the flip path.
3318          */
3319
3320         adjusted_mode = &crtc->config->base.adjusted_mode;
3321
3322         I915_WRITE(PIPESRC(crtc->pipe),
3323                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3324                    (adjusted_mode->crtc_vdisplay - 1));
3325         if (!crtc->config->pch_pfit.enabled &&
3326             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3327              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3328                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3329                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3330                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3331         }
3332         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3333         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3334 }
3335
3336 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3337 {
3338         struct drm_device *dev = crtc->dev;
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341         int pipe = intel_crtc->pipe;
3342         u32 reg, temp;
3343
3344         /* enable normal train */
3345         reg = FDI_TX_CTL(pipe);
3346         temp = I915_READ(reg);
3347         if (IS_IVYBRIDGE(dev)) {
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3350         } else {
3351                 temp &= ~FDI_LINK_TRAIN_NONE;
3352                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3353         }
3354         I915_WRITE(reg, temp);
3355
3356         reg = FDI_RX_CTL(pipe);
3357         temp = I915_READ(reg);
3358         if (HAS_PCH_CPT(dev)) {
3359                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3361         } else {
3362                 temp &= ~FDI_LINK_TRAIN_NONE;
3363                 temp |= FDI_LINK_TRAIN_NONE;
3364         }
3365         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3366
3367         /* wait one idle pattern time */
3368         POSTING_READ(reg);
3369         udelay(1000);
3370
3371         /* IVB wants error correction enabled */
3372         if (IS_IVYBRIDGE(dev))
3373                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374                            FDI_FE_ERRC_ENABLE);
3375 }
3376
3377 /* The FDI link training functions for ILK/Ibexpeak. */
3378 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         int pipe = intel_crtc->pipe;
3384         u32 reg, temp, tries;
3385
3386         /* FDI needs bits from pipe first */
3387         assert_pipe_enabled(dev_priv, pipe);
3388
3389         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3390            for train result */
3391         reg = FDI_RX_IMR(pipe);
3392         temp = I915_READ(reg);
3393         temp &= ~FDI_RX_SYMBOL_LOCK;
3394         temp &= ~FDI_RX_BIT_LOCK;
3395         I915_WRITE(reg, temp);
3396         I915_READ(reg);
3397         udelay(150);
3398
3399         /* enable CPU FDI TX and PCH FDI RX */
3400         reg = FDI_TX_CTL(pipe);
3401         temp = I915_READ(reg);
3402         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3403         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_1;
3406         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3407
3408         reg = FDI_RX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_LINK_TRAIN_NONE;
3411         temp |= FDI_LINK_TRAIN_PATTERN_1;
3412         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3413
3414         POSTING_READ(reg);
3415         udelay(150);
3416
3417         /* Ironlake workaround, enable clock pointer after FDI enable*/
3418         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420                    FDI_RX_PHASE_SYNC_POINTER_EN);
3421
3422         reg = FDI_RX_IIR(pipe);
3423         for (tries = 0; tries < 5; tries++) {
3424                 temp = I915_READ(reg);
3425                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3426
3427                 if ((temp & FDI_RX_BIT_LOCK)) {
3428                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3429                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3430                         break;
3431                 }
3432         }
3433         if (tries == 5)
3434                 DRM_ERROR("FDI train 1 fail!\n");
3435
3436         /* Train 2 */
3437         reg = FDI_TX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         temp &= ~FDI_LINK_TRAIN_NONE;
3440         temp |= FDI_LINK_TRAIN_PATTERN_2;
3441         I915_WRITE(reg, temp);
3442
3443         reg = FDI_RX_CTL(pipe);
3444         temp = I915_READ(reg);
3445         temp &= ~FDI_LINK_TRAIN_NONE;
3446         temp |= FDI_LINK_TRAIN_PATTERN_2;
3447         I915_WRITE(reg, temp);
3448
3449         POSTING_READ(reg);
3450         udelay(150);
3451
3452         reg = FDI_RX_IIR(pipe);
3453         for (tries = 0; tries < 5; tries++) {
3454                 temp = I915_READ(reg);
3455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3456
3457                 if (temp & FDI_RX_SYMBOL_LOCK) {
3458                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3459                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3460                         break;
3461                 }
3462         }
3463         if (tries == 5)
3464                 DRM_ERROR("FDI train 2 fail!\n");
3465
3466         DRM_DEBUG_KMS("FDI train done\n");
3467
3468 }
3469
3470 static const int snb_b_fdi_train_param[] = {
3471         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3475 };
3476
3477 /* The FDI link training functions for SNB/Cougarpoint. */
3478 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3479 {
3480         struct drm_device *dev = crtc->dev;
3481         struct drm_i915_private *dev_priv = dev->dev_private;
3482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483         int pipe = intel_crtc->pipe;
3484         u32 reg, temp, i, retry;
3485
3486         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3487            for train result */
3488         reg = FDI_RX_IMR(pipe);
3489         temp = I915_READ(reg);
3490         temp &= ~FDI_RX_SYMBOL_LOCK;
3491         temp &= ~FDI_RX_BIT_LOCK;
3492         I915_WRITE(reg, temp);
3493
3494         POSTING_READ(reg);
3495         udelay(150);
3496
3497         /* enable CPU FDI TX and PCH FDI RX */
3498         reg = FDI_TX_CTL(pipe);
3499         temp = I915_READ(reg);
3500         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3501         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3502         temp &= ~FDI_LINK_TRAIN_NONE;
3503         temp |= FDI_LINK_TRAIN_PATTERN_1;
3504         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3505         /* SNB-B */
3506         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3507         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3508
3509         I915_WRITE(FDI_RX_MISC(pipe),
3510                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3511
3512         reg = FDI_RX_CTL(pipe);
3513         temp = I915_READ(reg);
3514         if (HAS_PCH_CPT(dev)) {
3515                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517         } else {
3518                 temp &= ~FDI_LINK_TRAIN_NONE;
3519                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520         }
3521         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3522
3523         POSTING_READ(reg);
3524         udelay(150);
3525
3526         for (i = 0; i < 4; i++) {
3527                 reg = FDI_TX_CTL(pipe);
3528                 temp = I915_READ(reg);
3529                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530                 temp |= snb_b_fdi_train_param[i];
3531                 I915_WRITE(reg, temp);
3532
3533                 POSTING_READ(reg);
3534                 udelay(500);
3535
3536                 for (retry = 0; retry < 5; retry++) {
3537                         reg = FDI_RX_IIR(pipe);
3538                         temp = I915_READ(reg);
3539                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540                         if (temp & FDI_RX_BIT_LOCK) {
3541                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3543                                 break;
3544                         }
3545                         udelay(50);
3546                 }
3547                 if (retry < 5)
3548                         break;
3549         }
3550         if (i == 4)
3551                 DRM_ERROR("FDI train 1 fail!\n");
3552
3553         /* Train 2 */
3554         reg = FDI_TX_CTL(pipe);
3555         temp = I915_READ(reg);
3556         temp &= ~FDI_LINK_TRAIN_NONE;
3557         temp |= FDI_LINK_TRAIN_PATTERN_2;
3558         if (IS_GEN6(dev)) {
3559                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560                 /* SNB-B */
3561                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3562         }
3563         I915_WRITE(reg, temp);
3564
3565         reg = FDI_RX_CTL(pipe);
3566         temp = I915_READ(reg);
3567         if (HAS_PCH_CPT(dev)) {
3568                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3570         } else {
3571                 temp &= ~FDI_LINK_TRAIN_NONE;
3572                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573         }
3574         I915_WRITE(reg, temp);
3575
3576         POSTING_READ(reg);
3577         udelay(150);
3578
3579         for (i = 0; i < 4; i++) {
3580                 reg = FDI_TX_CTL(pipe);
3581                 temp = I915_READ(reg);
3582                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583                 temp |= snb_b_fdi_train_param[i];
3584                 I915_WRITE(reg, temp);
3585
3586                 POSTING_READ(reg);
3587                 udelay(500);
3588
3589                 for (retry = 0; retry < 5; retry++) {
3590                         reg = FDI_RX_IIR(pipe);
3591                         temp = I915_READ(reg);
3592                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593                         if (temp & FDI_RX_SYMBOL_LOCK) {
3594                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3596                                 break;
3597                         }
3598                         udelay(50);
3599                 }
3600                 if (retry < 5)
3601                         break;
3602         }
3603         if (i == 4)
3604                 DRM_ERROR("FDI train 2 fail!\n");
3605
3606         DRM_DEBUG_KMS("FDI train done.\n");
3607 }
3608
3609 /* Manual link training for Ivy Bridge A0 parts */
3610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3611 {
3612         struct drm_device *dev = crtc->dev;
3613         struct drm_i915_private *dev_priv = dev->dev_private;
3614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615         int pipe = intel_crtc->pipe;
3616         u32 reg, temp, i, j;
3617
3618         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3619            for train result */
3620         reg = FDI_RX_IMR(pipe);
3621         temp = I915_READ(reg);
3622         temp &= ~FDI_RX_SYMBOL_LOCK;
3623         temp &= ~FDI_RX_BIT_LOCK;
3624         I915_WRITE(reg, temp);
3625
3626         POSTING_READ(reg);
3627         udelay(150);
3628
3629         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630                       I915_READ(FDI_RX_IIR(pipe)));
3631
3632         /* Try each vswing and preemphasis setting twice before moving on */
3633         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634                 /* disable first in case we need to retry */
3635                 reg = FDI_TX_CTL(pipe);
3636                 temp = I915_READ(reg);
3637                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638                 temp &= ~FDI_TX_ENABLE;
3639                 I915_WRITE(reg, temp);
3640
3641                 reg = FDI_RX_CTL(pipe);
3642                 temp = I915_READ(reg);
3643                 temp &= ~FDI_LINK_TRAIN_AUTO;
3644                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645                 temp &= ~FDI_RX_ENABLE;
3646                 I915_WRITE(reg, temp);
3647
3648                 /* enable CPU FDI TX and PCH FDI RX */
3649                 reg = FDI_TX_CTL(pipe);
3650                 temp = I915_READ(reg);
3651                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3652                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3653                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3654                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3655                 temp |= snb_b_fdi_train_param[j/2];
3656                 temp |= FDI_COMPOSITE_SYNC;
3657                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3658
3659                 I915_WRITE(FDI_RX_MISC(pipe),
3660                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3661
3662                 reg = FDI_RX_CTL(pipe);
3663                 temp = I915_READ(reg);
3664                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665                 temp |= FDI_COMPOSITE_SYNC;
3666                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3667
3668                 POSTING_READ(reg);
3669                 udelay(1); /* should be 0.5us */
3670
3671                 for (i = 0; i < 4; i++) {
3672                         reg = FDI_RX_IIR(pipe);
3673                         temp = I915_READ(reg);
3674                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3675
3676                         if (temp & FDI_RX_BIT_LOCK ||
3677                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3680                                               i);
3681                                 break;
3682                         }
3683                         udelay(1); /* should be 0.5us */
3684                 }
3685                 if (i == 4) {
3686                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3687                         continue;
3688                 }
3689
3690                 /* Train 2 */
3691                 reg = FDI_TX_CTL(pipe);
3692                 temp = I915_READ(reg);
3693                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695                 I915_WRITE(reg, temp);
3696
3697                 reg = FDI_RX_CTL(pipe);
3698                 temp = I915_READ(reg);
3699                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3701                 I915_WRITE(reg, temp);
3702
3703                 POSTING_READ(reg);
3704                 udelay(2); /* should be 1.5us */
3705
3706                 for (i = 0; i < 4; i++) {
3707                         reg = FDI_RX_IIR(pipe);
3708                         temp = I915_READ(reg);
3709                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3710
3711                         if (temp & FDI_RX_SYMBOL_LOCK ||
3712                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3715                                               i);
3716                                 goto train_done;
3717                         }
3718                         udelay(2); /* should be 1.5us */
3719                 }
3720                 if (i == 4)
3721                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3722         }
3723
3724 train_done:
3725         DRM_DEBUG_KMS("FDI train done.\n");
3726 }
3727
3728 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3729 {
3730         struct drm_device *dev = intel_crtc->base.dev;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732         int pipe = intel_crtc->pipe;
3733         u32 reg, temp;
3734
3735
3736         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3737         reg = FDI_RX_CTL(pipe);
3738         temp = I915_READ(reg);
3739         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3740         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3741         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3742         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3743
3744         POSTING_READ(reg);
3745         udelay(200);
3746
3747         /* Switch from Rawclk to PCDclk */
3748         temp = I915_READ(reg);
3749         I915_WRITE(reg, temp | FDI_PCDCLK);
3750
3751         POSTING_READ(reg);
3752         udelay(200);
3753
3754         /* Enable CPU FDI TX PLL, always on for Ironlake */
3755         reg = FDI_TX_CTL(pipe);
3756         temp = I915_READ(reg);
3757         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3759
3760                 POSTING_READ(reg);
3761                 udelay(100);
3762         }
3763 }
3764
3765 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3766 {
3767         struct drm_device *dev = intel_crtc->base.dev;
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769         int pipe = intel_crtc->pipe;
3770         u32 reg, temp;
3771
3772         /* Switch from PCDclk to Rawclk */
3773         reg = FDI_RX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3776
3777         /* Disable CPU FDI TX PLL */
3778         reg = FDI_TX_CTL(pipe);
3779         temp = I915_READ(reg);
3780         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3781
3782         POSTING_READ(reg);
3783         udelay(100);
3784
3785         reg = FDI_RX_CTL(pipe);
3786         temp = I915_READ(reg);
3787         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3788
3789         /* Wait for the clocks to turn off. */
3790         POSTING_READ(reg);
3791         udelay(100);
3792 }
3793
3794 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3795 {
3796         struct drm_device *dev = crtc->dev;
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799         int pipe = intel_crtc->pipe;
3800         u32 reg, temp;
3801
3802         /* disable CPU FDI tx and PCH FDI rx */
3803         reg = FDI_TX_CTL(pipe);
3804         temp = I915_READ(reg);
3805         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3806         POSTING_READ(reg);
3807
3808         reg = FDI_RX_CTL(pipe);
3809         temp = I915_READ(reg);
3810         temp &= ~(0x7 << 16);
3811         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3812         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3813
3814         POSTING_READ(reg);
3815         udelay(100);
3816
3817         /* Ironlake workaround, disable clock pointer after downing FDI */
3818         if (HAS_PCH_IBX(dev))
3819                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3820
3821         /* still set train pattern 1 */
3822         reg = FDI_TX_CTL(pipe);
3823         temp = I915_READ(reg);
3824         temp &= ~FDI_LINK_TRAIN_NONE;
3825         temp |= FDI_LINK_TRAIN_PATTERN_1;
3826         I915_WRITE(reg, temp);
3827
3828         reg = FDI_RX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         if (HAS_PCH_CPT(dev)) {
3831                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3833         } else {
3834                 temp &= ~FDI_LINK_TRAIN_NONE;
3835                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836         }
3837         /* BPC in FDI rx is consistent with that in PIPECONF */
3838         temp &= ~(0x07 << 16);
3839         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840         I915_WRITE(reg, temp);
3841
3842         POSTING_READ(reg);
3843         udelay(100);
3844 }
3845
3846 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3847 {
3848         struct intel_crtc *crtc;
3849
3850         /* Note that we don't need to be called with mode_config.lock here
3851          * as our list of CRTC objects is static for the lifetime of the
3852          * device and so cannot disappear as we iterate. Similarly, we can
3853          * happily treat the predicates as racy, atomic checks as userspace
3854          * cannot claim and pin a new fb without at least acquring the
3855          * struct_mutex and so serialising with us.
3856          */
3857         for_each_intel_crtc(dev, crtc) {
3858                 if (atomic_read(&crtc->unpin_work_count) == 0)
3859                         continue;
3860
3861                 if (crtc->unpin_work)
3862                         intel_wait_for_vblank(dev, crtc->pipe);
3863
3864                 return true;
3865         }
3866
3867         return false;
3868 }
3869
3870 static void page_flip_completed(struct intel_crtc *intel_crtc)
3871 {
3872         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873         struct intel_unpin_work *work = intel_crtc->unpin_work;
3874
3875         /* ensure that the unpin work is consistent wrt ->pending. */
3876         smp_rmb();
3877         intel_crtc->unpin_work = NULL;
3878
3879         if (work->event)
3880                 drm_send_vblank_event(intel_crtc->base.dev,
3881                                       intel_crtc->pipe,
3882                                       work->event);
3883
3884         drm_crtc_vblank_put(&intel_crtc->base);
3885
3886         wake_up_all(&dev_priv->pending_flip_queue);
3887         queue_work(dev_priv->wq, &work->work);
3888
3889         trace_i915_flip_complete(intel_crtc->plane,
3890                                  work->pending_flip_obj);
3891 }
3892
3893 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3894 {
3895         struct drm_device *dev = crtc->dev;
3896         struct drm_i915_private *dev_priv = dev->dev_private;
3897
3898         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3899         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3900                                        !intel_crtc_has_pending_flip(crtc),
3901                                        60*HZ) == 0)) {
3902                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3903
3904                 spin_lock_irq(&dev->event_lock);
3905                 if (intel_crtc->unpin_work) {
3906                         WARN_ONCE(1, "Removing stuck page flip\n");
3907                         page_flip_completed(intel_crtc);
3908                 }
3909                 spin_unlock_irq(&dev->event_lock);
3910         }
3911
3912         if (crtc->primary->fb) {
3913                 mutex_lock(&dev->struct_mutex);
3914                 intel_finish_fb(crtc->primary->fb);
3915                 mutex_unlock(&dev->struct_mutex);
3916         }
3917 }
3918
3919 /* Program iCLKIP clock to the desired frequency */
3920 static void lpt_program_iclkip(struct drm_crtc *crtc)
3921 {
3922         struct drm_device *dev = crtc->dev;
3923         struct drm_i915_private *dev_priv = dev->dev_private;
3924         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3925         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3926         u32 temp;
3927
3928         mutex_lock(&dev_priv->sb_lock);
3929
3930         /* It is necessary to ungate the pixclk gate prior to programming
3931          * the divisors, and gate it back when it is done.
3932          */
3933         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3934
3935         /* Disable SSCCTL */
3936         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3937                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3938                                 SBI_SSCCTL_DISABLE,
3939                         SBI_ICLK);
3940
3941         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3942         if (clock == 20000) {
3943                 auxdiv = 1;
3944                 divsel = 0x41;
3945                 phaseinc = 0x20;
3946         } else {
3947                 /* The iCLK virtual clock root frequency is in MHz,
3948                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3949                  * divisors, it is necessary to divide one by another, so we
3950                  * convert the virtual clock precision to KHz here for higher
3951                  * precision.
3952                  */
3953                 u32 iclk_virtual_root_freq = 172800 * 1000;
3954                 u32 iclk_pi_range = 64;
3955                 u32 desired_divisor, msb_divisor_value, pi_value;
3956
3957                 desired_divisor = (iclk_virtual_root_freq / clock);
3958                 msb_divisor_value = desired_divisor / iclk_pi_range;
3959                 pi_value = desired_divisor % iclk_pi_range;
3960
3961                 auxdiv = 0;
3962                 divsel = msb_divisor_value - 2;
3963                 phaseinc = pi_value;
3964         }
3965
3966         /* This should not happen with any sane values */
3967         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3968                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3969         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3970                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3971
3972         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3973                         clock,
3974                         auxdiv,
3975                         divsel,
3976                         phasedir,
3977                         phaseinc);
3978
3979         /* Program SSCDIVINTPHASE6 */
3980         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3981         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3982         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3983         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3984         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3985         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3986         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3987         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3988
3989         /* Program SSCAUXDIV */
3990         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3991         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3992         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3993         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3994
3995         /* Enable modulator and associated divider */
3996         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3997         temp &= ~SBI_SSCCTL_DISABLE;
3998         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3999
4000         /* Wait for initialization time */
4001         udelay(24);
4002
4003         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4004
4005         mutex_unlock(&dev_priv->sb_lock);
4006 }
4007
4008 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4009                                                 enum pipe pch_transcoder)
4010 {
4011         struct drm_device *dev = crtc->base.dev;
4012         struct drm_i915_private *dev_priv = dev->dev_private;
4013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4014
4015         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4016                    I915_READ(HTOTAL(cpu_transcoder)));
4017         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4018                    I915_READ(HBLANK(cpu_transcoder)));
4019         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4020                    I915_READ(HSYNC(cpu_transcoder)));
4021
4022         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4023                    I915_READ(VTOTAL(cpu_transcoder)));
4024         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4025                    I915_READ(VBLANK(cpu_transcoder)));
4026         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4027                    I915_READ(VSYNC(cpu_transcoder)));
4028         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4029                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4030 }
4031
4032 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4033 {
4034         struct drm_i915_private *dev_priv = dev->dev_private;
4035         uint32_t temp;
4036
4037         temp = I915_READ(SOUTH_CHICKEN1);
4038         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4039                 return;
4040
4041         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4042         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4043
4044         temp &= ~FDI_BC_BIFURCATION_SELECT;
4045         if (enable)
4046                 temp |= FDI_BC_BIFURCATION_SELECT;
4047
4048         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4049         I915_WRITE(SOUTH_CHICKEN1, temp);
4050         POSTING_READ(SOUTH_CHICKEN1);
4051 }
4052
4053 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4054 {
4055         struct drm_device *dev = intel_crtc->base.dev;
4056
4057         switch (intel_crtc->pipe) {
4058         case PIPE_A:
4059                 break;
4060         case PIPE_B:
4061                 if (intel_crtc->config->fdi_lanes > 2)
4062                         cpt_set_fdi_bc_bifurcation(dev, false);
4063                 else
4064                         cpt_set_fdi_bc_bifurcation(dev, true);
4065
4066                 break;
4067         case PIPE_C:
4068                 cpt_set_fdi_bc_bifurcation(dev, true);
4069
4070                 break;
4071         default:
4072                 BUG();
4073         }
4074 }
4075
4076 /*
4077  * Enable PCH resources required for PCH ports:
4078  *   - PCH PLLs
4079  *   - FDI training & RX/TX
4080  *   - update transcoder timings
4081  *   - DP transcoding bits
4082  *   - transcoder
4083  */
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4085 {
4086         struct drm_device *dev = crtc->dev;
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089         int pipe = intel_crtc->pipe;
4090         u32 reg, temp;
4091
4092         assert_pch_transcoder_disabled(dev_priv, pipe);
4093
4094         if (IS_IVYBRIDGE(dev))
4095                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4096
4097         /* Write the TU size bits before fdi link training, so that error
4098          * detection works. */
4099         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4101
4102         /* For PCH output, training FDI link */
4103         dev_priv->display.fdi_link_train(crtc);
4104
4105         /* We need to program the right clock selection before writing the pixel
4106          * mutliplier into the DPLL. */
4107         if (HAS_PCH_CPT(dev)) {
4108                 u32 sel;
4109
4110                 temp = I915_READ(PCH_DPLL_SEL);
4111                 temp |= TRANS_DPLL_ENABLE(pipe);
4112                 sel = TRANS_DPLLB_SEL(pipe);
4113                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4114                         temp |= sel;
4115                 else
4116                         temp &= ~sel;
4117                 I915_WRITE(PCH_DPLL_SEL, temp);
4118         }
4119
4120         /* XXX: pch pll's can be enabled any time before we enable the PCH
4121          * transcoder, and we actually should do this to not upset any PCH
4122          * transcoder that already use the clock when we share it.
4123          *
4124          * Note that enable_shared_dpll tries to do the right thing, but
4125          * get_shared_dpll unconditionally resets the pll - we need that to have
4126          * the right LVDS enable sequence. */
4127         intel_enable_shared_dpll(intel_crtc);
4128
4129         /* set transcoder timing, panel must allow it */
4130         assert_panel_unlocked(dev_priv, pipe);
4131         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4132
4133         intel_fdi_normal_train(crtc);
4134
4135         /* For PCH DP, enable TRANS_DP_CTL */
4136         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4137                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4138                 reg = TRANS_DP_CTL(pipe);
4139                 temp = I915_READ(reg);
4140                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4141                           TRANS_DP_SYNC_MASK |
4142                           TRANS_DP_BPC_MASK);
4143                 temp |= TRANS_DP_OUTPUT_ENABLE;
4144                 temp |= bpc << 9; /* same format but at 11:9 */
4145
4146                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4147                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4148                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4149                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4150
4151                 switch (intel_trans_dp_port_sel(crtc)) {
4152                 case PCH_DP_B:
4153                         temp |= TRANS_DP_PORT_SEL_B;
4154                         break;
4155                 case PCH_DP_C:
4156                         temp |= TRANS_DP_PORT_SEL_C;
4157                         break;
4158                 case PCH_DP_D:
4159                         temp |= TRANS_DP_PORT_SEL_D;
4160                         break;
4161                 default:
4162                         BUG();
4163                 }
4164
4165                 I915_WRITE(reg, temp);
4166         }
4167
4168         ironlake_enable_pch_transcoder(dev_priv, pipe);
4169 }
4170
4171 static void lpt_pch_enable(struct drm_crtc *crtc)
4172 {
4173         struct drm_device *dev = crtc->dev;
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4177
4178         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4179
4180         lpt_program_iclkip(crtc);
4181
4182         /* Set transcoder timing. */
4183         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4184
4185         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4186 }
4187
4188 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4189                                                 struct intel_crtc_state *crtc_state)
4190 {
4191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4192         struct intel_shared_dpll *pll;
4193         struct intel_shared_dpll_config *shared_dpll;
4194         enum intel_dpll_id i;
4195
4196         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4197
4198         if (HAS_PCH_IBX(dev_priv->dev)) {
4199                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4200                 i = (enum intel_dpll_id) crtc->pipe;
4201                 pll = &dev_priv->shared_dplls[i];
4202
4203                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4204                               crtc->base.base.id, pll->name);
4205
4206                 WARN_ON(shared_dpll[i].crtc_mask);
4207
4208                 goto found;
4209         }
4210
4211         if (IS_BROXTON(dev_priv->dev)) {
4212                 /* PLL is attached to port in bxt */
4213                 struct intel_encoder *encoder;
4214                 struct intel_digital_port *intel_dig_port;
4215
4216                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4217                 if (WARN_ON(!encoder))
4218                         return NULL;
4219
4220                 intel_dig_port = enc_to_dig_port(&encoder->base);
4221                 /* 1:1 mapping between ports and PLLs */
4222                 i = (enum intel_dpll_id)intel_dig_port->port;
4223                 pll = &dev_priv->shared_dplls[i];
4224                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4225                         crtc->base.base.id, pll->name);
4226                 WARN_ON(shared_dpll[i].crtc_mask);
4227
4228                 goto found;
4229         }
4230
4231         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4232                 pll = &dev_priv->shared_dplls[i];
4233
4234                 /* Only want to check enabled timings first */
4235                 if (shared_dpll[i].crtc_mask == 0)
4236                         continue;
4237
4238                 if (memcmp(&crtc_state->dpll_hw_state,
4239                            &shared_dpll[i].hw_state,
4240                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4241                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4242                                       crtc->base.base.id, pll->name,
4243                                       shared_dpll[i].crtc_mask,
4244                                       pll->active);
4245                         goto found;
4246                 }
4247         }
4248
4249         /* Ok no matching timings, maybe there's a free one? */
4250         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4251                 pll = &dev_priv->shared_dplls[i];
4252                 if (shared_dpll[i].crtc_mask == 0) {
4253                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4254                                       crtc->base.base.id, pll->name);
4255                         goto found;
4256                 }
4257         }
4258
4259         return NULL;
4260
4261 found:
4262         if (shared_dpll[i].crtc_mask == 0)
4263                 shared_dpll[i].hw_state =
4264                         crtc_state->dpll_hw_state;
4265
4266         crtc_state->shared_dpll = i;
4267         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4268                          pipe_name(crtc->pipe));
4269
4270         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4271
4272         return pll;
4273 }
4274
4275 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4276 {
4277         struct drm_i915_private *dev_priv = to_i915(state->dev);
4278         struct intel_shared_dpll_config *shared_dpll;
4279         struct intel_shared_dpll *pll;
4280         enum intel_dpll_id i;
4281
4282         if (!to_intel_atomic_state(state)->dpll_set)
4283                 return;
4284
4285         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4286         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4287                 pll = &dev_priv->shared_dplls[i];
4288                 pll->config = shared_dpll[i];
4289         }
4290 }
4291
4292 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4293 {
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295         int dslreg = PIPEDSL(pipe);
4296         u32 temp;
4297
4298         temp = I915_READ(dslreg);
4299         udelay(500);
4300         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4301                 if (wait_for(I915_READ(dslreg) != temp, 5))
4302                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4303         }
4304 }
4305
4306 static int
4307 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4308                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4309                   int src_w, int src_h, int dst_w, int dst_h)
4310 {
4311         struct intel_crtc_scaler_state *scaler_state =
4312                 &crtc_state->scaler_state;
4313         struct intel_crtc *intel_crtc =
4314                 to_intel_crtc(crtc_state->base.crtc);
4315         int need_scaling;
4316
4317         need_scaling = intel_rotation_90_or_270(rotation) ?
4318                 (src_h != dst_w || src_w != dst_h):
4319                 (src_w != dst_w || src_h != dst_h);
4320
4321         /*
4322          * if plane is being disabled or scaler is no more required or force detach
4323          *  - free scaler binded to this plane/crtc
4324          *  - in order to do this, update crtc->scaler_usage
4325          *
4326          * Here scaler state in crtc_state is set free so that
4327          * scaler can be assigned to other user. Actual register
4328          * update to free the scaler is done in plane/panel-fit programming.
4329          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4330          */
4331         if (force_detach || !need_scaling) {
4332                 if (*scaler_id >= 0) {
4333                         scaler_state->scaler_users &= ~(1 << scaler_user);
4334                         scaler_state->scalers[*scaler_id].in_use = 0;
4335
4336                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4337                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4338                                 intel_crtc->pipe, scaler_user, *scaler_id,
4339                                 scaler_state->scaler_users);
4340                         *scaler_id = -1;
4341                 }
4342                 return 0;
4343         }
4344
4345         /* range checks */
4346         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4347                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4348
4349                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4350                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4351                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4352                         "size is out of scaler range\n",
4353                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4354                 return -EINVAL;
4355         }
4356
4357         /* mark this plane as a scaler user in crtc_state */
4358         scaler_state->scaler_users |= (1 << scaler_user);
4359         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4360                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4361                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4362                 scaler_state->scaler_users);
4363
4364         return 0;
4365 }
4366
4367 /**
4368  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4369  *
4370  * @state: crtc's scaler state
4371  *
4372  * Return
4373  *     0 - scaler_usage updated successfully
4374  *    error - requested scaling cannot be supported or other error condition
4375  */
4376 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4377 {
4378         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4379         struct drm_display_mode *adjusted_mode =
4380                 &state->base.adjusted_mode;
4381
4382         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4383                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4384
4385         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4386                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4387                 state->pipe_src_w, state->pipe_src_h,
4388                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4389 }
4390
4391 /**
4392  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4393  *
4394  * @state: crtc's scaler state
4395  * @plane_state: atomic plane state to update
4396  *
4397  * Return
4398  *     0 - scaler_usage updated successfully
4399  *    error - requested scaling cannot be supported or other error condition
4400  */
4401 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4402                                    struct intel_plane_state *plane_state)
4403 {
4404
4405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4406         struct intel_plane *intel_plane =
4407                 to_intel_plane(plane_state->base.plane);
4408         struct drm_framebuffer *fb = plane_state->base.fb;
4409         int ret;
4410
4411         bool force_detach = !fb || !plane_state->visible;
4412
4413         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4414                       intel_plane->base.base.id, intel_crtc->pipe,
4415                       drm_plane_index(&intel_plane->base));
4416
4417         ret = skl_update_scaler(crtc_state, force_detach,
4418                                 drm_plane_index(&intel_plane->base),
4419                                 &plane_state->scaler_id,
4420                                 plane_state->base.rotation,
4421                                 drm_rect_width(&plane_state->src) >> 16,
4422                                 drm_rect_height(&plane_state->src) >> 16,
4423                                 drm_rect_width(&plane_state->dst),
4424                                 drm_rect_height(&plane_state->dst));
4425
4426         if (ret || plane_state->scaler_id < 0)
4427                 return ret;
4428
4429         /* check colorkey */
4430         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4431                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4432                               intel_plane->base.base.id);
4433                 return -EINVAL;
4434         }
4435
4436         /* Check src format */
4437         switch (fb->pixel_format) {
4438         case DRM_FORMAT_RGB565:
4439         case DRM_FORMAT_XBGR8888:
4440         case DRM_FORMAT_XRGB8888:
4441         case DRM_FORMAT_ABGR8888:
4442         case DRM_FORMAT_ARGB8888:
4443         case DRM_FORMAT_XRGB2101010:
4444         case DRM_FORMAT_XBGR2101010:
4445         case DRM_FORMAT_YUYV:
4446         case DRM_FORMAT_YVYU:
4447         case DRM_FORMAT_UYVY:
4448         case DRM_FORMAT_VYUY:
4449                 break;
4450         default:
4451                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4452                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4453                 return -EINVAL;
4454         }
4455
4456         return 0;
4457 }
4458
4459 static void skylake_scaler_disable(struct intel_crtc *crtc)
4460 {
4461         int i;
4462
4463         for (i = 0; i < crtc->num_scalers; i++)
4464                 skl_detach_scaler(crtc, i);
4465 }
4466
4467 static void skylake_pfit_enable(struct intel_crtc *crtc)
4468 {
4469         struct drm_device *dev = crtc->base.dev;
4470         struct drm_i915_private *dev_priv = dev->dev_private;
4471         int pipe = crtc->pipe;
4472         struct intel_crtc_scaler_state *scaler_state =
4473                 &crtc->config->scaler_state;
4474
4475         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4476
4477         if (crtc->config->pch_pfit.enabled) {
4478                 int id;
4479
4480                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4481                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4482                         return;
4483                 }
4484
4485                 id = scaler_state->scaler_id;
4486                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4487                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4488                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4489                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4490
4491                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4492         }
4493 }
4494
4495 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4496 {
4497         struct drm_device *dev = crtc->base.dev;
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         int pipe = crtc->pipe;
4500
4501         if (crtc->config->pch_pfit.enabled) {
4502                 /* Force use of hard-coded filter coefficients
4503                  * as some pre-programmed values are broken,
4504                  * e.g. x201.
4505                  */
4506                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4507                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4508                                                  PF_PIPE_SEL_IVB(pipe));
4509                 else
4510                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4511                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4512                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4513         }
4514 }
4515
4516 void hsw_enable_ips(struct intel_crtc *crtc)
4517 {
4518         struct drm_device *dev = crtc->base.dev;
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520
4521         if (!crtc->config->ips_enabled)
4522                 return;
4523
4524         /* We can only enable IPS after we enable a plane and wait for a vblank */
4525         intel_wait_for_vblank(dev, crtc->pipe);
4526
4527         assert_plane_enabled(dev_priv, crtc->plane);
4528         if (IS_BROADWELL(dev)) {
4529                 mutex_lock(&dev_priv->rps.hw_lock);
4530                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4531                 mutex_unlock(&dev_priv->rps.hw_lock);
4532                 /* Quoting Art Runyan: "its not safe to expect any particular
4533                  * value in IPS_CTL bit 31 after enabling IPS through the
4534                  * mailbox." Moreover, the mailbox may return a bogus state,
4535                  * so we need to just enable it and continue on.
4536                  */
4537         } else {
4538                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4539                 /* The bit only becomes 1 in the next vblank, so this wait here
4540                  * is essentially intel_wait_for_vblank. If we don't have this
4541                  * and don't wait for vblanks until the end of crtc_enable, then
4542                  * the HW state readout code will complain that the expected
4543                  * IPS_CTL value is not the one we read. */
4544                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4545                         DRM_ERROR("Timed out waiting for IPS enable\n");
4546         }
4547 }
4548
4549 void hsw_disable_ips(struct intel_crtc *crtc)
4550 {
4551         struct drm_device *dev = crtc->base.dev;
4552         struct drm_i915_private *dev_priv = dev->dev_private;
4553
4554         if (!crtc->config->ips_enabled)
4555                 return;
4556
4557         assert_plane_enabled(dev_priv, crtc->plane);
4558         if (IS_BROADWELL(dev)) {
4559                 mutex_lock(&dev_priv->rps.hw_lock);
4560                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4561                 mutex_unlock(&dev_priv->rps.hw_lock);
4562                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4563                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4564                         DRM_ERROR("Timed out waiting for IPS disable\n");
4565         } else {
4566                 I915_WRITE(IPS_CTL, 0);
4567                 POSTING_READ(IPS_CTL);
4568         }
4569
4570         /* We need to wait for a vblank before we can disable the plane. */
4571         intel_wait_for_vblank(dev, crtc->pipe);
4572 }
4573
4574 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4575 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4576 {
4577         struct drm_device *dev = crtc->dev;
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580         enum pipe pipe = intel_crtc->pipe;
4581         int palreg = PALETTE(pipe);
4582         int i;
4583         bool reenable_ips = false;
4584
4585         /* The clocks have to be on to load the palette. */
4586         if (!crtc->state->active)
4587                 return;
4588
4589         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4590                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4591                         assert_dsi_pll_enabled(dev_priv);
4592                 else
4593                         assert_pll_enabled(dev_priv, pipe);
4594         }
4595
4596         /* use legacy palette for Ironlake */
4597         if (!HAS_GMCH_DISPLAY(dev))
4598                 palreg = LGC_PALETTE(pipe);
4599
4600         /* Workaround : Do not read or write the pipe palette/gamma data while
4601          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4602          */
4603         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4604             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4605              GAMMA_MODE_MODE_SPLIT)) {
4606                 hsw_disable_ips(intel_crtc);
4607                 reenable_ips = true;
4608         }
4609
4610         for (i = 0; i < 256; i++) {
4611                 I915_WRITE(palreg + 4 * i,
4612                            (intel_crtc->lut_r[i] << 16) |
4613                            (intel_crtc->lut_g[i] << 8) |
4614                            intel_crtc->lut_b[i]);
4615         }
4616
4617         if (reenable_ips)
4618                 hsw_enable_ips(intel_crtc);
4619 }
4620
4621 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4622 {
4623         if (intel_crtc->overlay) {
4624                 struct drm_device *dev = intel_crtc->base.dev;
4625                 struct drm_i915_private *dev_priv = dev->dev_private;
4626
4627                 mutex_lock(&dev->struct_mutex);
4628                 dev_priv->mm.interruptible = false;
4629                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4630                 dev_priv->mm.interruptible = true;
4631                 mutex_unlock(&dev->struct_mutex);
4632         }
4633
4634         /* Let userspace switch the overlay on again. In most cases userspace
4635          * has to recompute where to put it anyway.
4636          */
4637 }
4638
4639 /**
4640  * intel_post_enable_primary - Perform operations after enabling primary plane
4641  * @crtc: the CRTC whose primary plane was just enabled
4642  *
4643  * Performs potentially sleeping operations that must be done after the primary
4644  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4645  * called due to an explicit primary plane update, or due to an implicit
4646  * re-enable that is caused when a sprite plane is updated to no longer
4647  * completely hide the primary plane.
4648  */
4649 static void
4650 intel_post_enable_primary(struct drm_crtc *crtc)
4651 {
4652         struct drm_device *dev = crtc->dev;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4655         int pipe = intel_crtc->pipe;
4656
4657         /*
4658          * BDW signals flip done immediately if the plane
4659          * is disabled, even if the plane enable is already
4660          * armed to occur at the next vblank :(
4661          */
4662         if (IS_BROADWELL(dev))
4663                 intel_wait_for_vblank(dev, pipe);
4664
4665         /*
4666          * FIXME IPS should be fine as long as one plane is
4667          * enabled, but in practice it seems to have problems
4668          * when going from primary only to sprite only and vice
4669          * versa.
4670          */
4671         hsw_enable_ips(intel_crtc);
4672
4673         /*
4674          * Gen2 reports pipe underruns whenever all planes are disabled.
4675          * So don't enable underrun reporting before at least some planes
4676          * are enabled.
4677          * FIXME: Need to fix the logic to work when we turn off all planes
4678          * but leave the pipe running.
4679          */
4680         if (IS_GEN2(dev))
4681                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4682
4683         /* Underruns don't raise interrupts, so check manually. */
4684         if (HAS_GMCH_DISPLAY(dev))
4685                 i9xx_check_fifo_underruns(dev_priv);
4686 }
4687
4688 /**
4689  * intel_pre_disable_primary - Perform operations before disabling primary plane
4690  * @crtc: the CRTC whose primary plane is to be disabled
4691  *
4692  * Performs potentially sleeping operations that must be done before the
4693  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4694  * be called due to an explicit primary plane update, or due to an implicit
4695  * disable that is caused when a sprite plane completely hides the primary
4696  * plane.
4697  */
4698 static void
4699 intel_pre_disable_primary(struct drm_crtc *crtc)
4700 {
4701         struct drm_device *dev = crtc->dev;
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704         int pipe = intel_crtc->pipe;
4705
4706         /*
4707          * Gen2 reports pipe underruns whenever all planes are disabled.
4708          * So diasble underrun reporting before all the planes get disabled.
4709          * FIXME: Need to fix the logic to work when we turn off all planes
4710          * but leave the pipe running.
4711          */
4712         if (IS_GEN2(dev))
4713                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4714
4715         /*
4716          * Vblank time updates from the shadow to live plane control register
4717          * are blocked if the memory self-refresh mode is active at that
4718          * moment. So to make sure the plane gets truly disabled, disable
4719          * first the self-refresh mode. The self-refresh enable bit in turn
4720          * will be checked/applied by the HW only at the next frame start
4721          * event which is after the vblank start event, so we need to have a
4722          * wait-for-vblank between disabling the plane and the pipe.
4723          */
4724         if (HAS_GMCH_DISPLAY(dev)) {
4725                 intel_set_memory_cxsr(dev_priv, false);
4726                 dev_priv->wm.vlv.cxsr = false;
4727                 intel_wait_for_vblank(dev, pipe);
4728         }
4729
4730         /*
4731          * FIXME IPS should be fine as long as one plane is
4732          * enabled, but in practice it seems to have problems
4733          * when going from primary only to sprite only and vice
4734          * versa.
4735          */
4736         hsw_disable_ips(intel_crtc);
4737 }
4738
4739 static void intel_post_plane_update(struct intel_crtc *crtc)
4740 {
4741         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742         struct drm_device *dev = crtc->base.dev;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         struct drm_plane *plane;
4745
4746         if (atomic->wait_vblank)
4747                 intel_wait_for_vblank(dev, crtc->pipe);
4748
4749         intel_frontbuffer_flip(dev, atomic->fb_bits);
4750
4751         if (atomic->disable_cxsr)
4752                 crtc->wm.cxsr_allowed = true;
4753
4754         if (crtc->atomic.update_wm_post)
4755                 intel_update_watermarks(&crtc->base);
4756
4757         if (atomic->update_fbc)
4758                 intel_fbc_update(dev_priv);
4759
4760         if (atomic->post_enable_primary)
4761                 intel_post_enable_primary(&crtc->base);
4762
4763         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4764                 intel_update_sprite_watermarks(plane, &crtc->base,
4765                                                0, 0, 0, false, false);
4766
4767         memset(atomic, 0, sizeof(*atomic));
4768 }
4769
4770 static void intel_pre_plane_update(struct intel_crtc *crtc)
4771 {
4772         struct drm_device *dev = crtc->base.dev;
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775         struct drm_plane *p;
4776
4777         /* Track fb's for any planes being disabled */
4778         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4779                 struct intel_plane *plane = to_intel_plane(p);
4780
4781                 mutex_lock(&dev->struct_mutex);
4782                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4783                                   plane->frontbuffer_bit);
4784                 mutex_unlock(&dev->struct_mutex);
4785         }
4786
4787         if (atomic->wait_for_flips)
4788                 intel_crtc_wait_for_pending_flips(&crtc->base);
4789
4790         if (atomic->disable_fbc)
4791                 intel_fbc_disable_crtc(crtc);
4792
4793         if (crtc->atomic.disable_ips)
4794                 hsw_disable_ips(crtc);
4795
4796         if (atomic->pre_disable_primary)
4797                 intel_pre_disable_primary(&crtc->base);
4798
4799         if (atomic->disable_cxsr) {
4800                 crtc->wm.cxsr_allowed = false;
4801                 intel_set_memory_cxsr(dev_priv, false);
4802         }
4803 }
4804
4805 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4806 {
4807         struct drm_device *dev = crtc->dev;
4808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809         struct drm_plane *p;
4810         int pipe = intel_crtc->pipe;
4811
4812         intel_crtc_dpms_overlay_disable(intel_crtc);
4813
4814         drm_for_each_plane_mask(p, dev, plane_mask)
4815                 to_intel_plane(p)->disable_plane(p, crtc);
4816
4817         /*
4818          * FIXME: Once we grow proper nuclear flip support out of this we need
4819          * to compute the mask of flip planes precisely. For the time being
4820          * consider this a flip to a NULL plane.
4821          */
4822         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4823 }
4824
4825 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4826 {
4827         struct drm_device *dev = crtc->dev;
4828         struct drm_i915_private *dev_priv = dev->dev_private;
4829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830         struct intel_encoder *encoder;
4831         int pipe = intel_crtc->pipe;
4832
4833         if (WARN_ON(intel_crtc->active))
4834                 return;
4835
4836         if (intel_crtc->config->has_pch_encoder)
4837                 intel_prepare_shared_dpll(intel_crtc);
4838
4839         if (intel_crtc->config->has_dp_encoder)
4840                 intel_dp_set_m_n(intel_crtc, M1_N1);
4841
4842         intel_set_pipe_timings(intel_crtc);
4843
4844         if (intel_crtc->config->has_pch_encoder) {
4845                 intel_cpu_transcoder_set_m_n(intel_crtc,
4846                                      &intel_crtc->config->fdi_m_n, NULL);
4847         }
4848
4849         ironlake_set_pipeconf(crtc);
4850
4851         intel_crtc->active = true;
4852
4853         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4854         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4855
4856         for_each_encoder_on_crtc(dev, crtc, encoder)
4857                 if (encoder->pre_enable)
4858                         encoder->pre_enable(encoder);
4859
4860         if (intel_crtc->config->has_pch_encoder) {
4861                 /* Note: FDI PLL enabling _must_ be done before we enable the
4862                  * cpu pipes, hence this is separate from all the other fdi/pch
4863                  * enabling. */
4864                 ironlake_fdi_pll_enable(intel_crtc);
4865         } else {
4866                 assert_fdi_tx_disabled(dev_priv, pipe);
4867                 assert_fdi_rx_disabled(dev_priv, pipe);
4868         }
4869
4870         ironlake_pfit_enable(intel_crtc);
4871
4872         /*
4873          * On ILK+ LUT must be loaded before the pipe is running but with
4874          * clocks enabled
4875          */
4876         intel_crtc_load_lut(crtc);
4877
4878         intel_update_watermarks(crtc);
4879         intel_enable_pipe(intel_crtc);
4880
4881         if (intel_crtc->config->has_pch_encoder)
4882                 ironlake_pch_enable(crtc);
4883
4884         assert_vblank_disabled(crtc);
4885         drm_crtc_vblank_on(crtc);
4886
4887         for_each_encoder_on_crtc(dev, crtc, encoder)
4888                 encoder->enable(encoder);
4889
4890         if (HAS_PCH_CPT(dev))
4891                 cpt_verify_modeset(dev, intel_crtc->pipe);
4892 }
4893
4894 /* IPS only exists on ULT machines and is tied to pipe A. */
4895 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4896 {
4897         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4898 }
4899
4900 static void haswell_crtc_enable(struct drm_crtc *crtc)
4901 {
4902         struct drm_device *dev = crtc->dev;
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905         struct intel_encoder *encoder;
4906         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4907         struct intel_crtc_state *pipe_config =
4908                 to_intel_crtc_state(crtc->state);
4909
4910         if (WARN_ON(intel_crtc->active))
4911                 return;
4912
4913         if (intel_crtc_to_shared_dpll(intel_crtc))
4914                 intel_enable_shared_dpll(intel_crtc);
4915
4916         if (intel_crtc->config->has_dp_encoder)
4917                 intel_dp_set_m_n(intel_crtc, M1_N1);
4918
4919         intel_set_pipe_timings(intel_crtc);
4920
4921         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4922                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4923                            intel_crtc->config->pixel_multiplier - 1);
4924         }
4925
4926         if (intel_crtc->config->has_pch_encoder) {
4927                 intel_cpu_transcoder_set_m_n(intel_crtc,
4928                                      &intel_crtc->config->fdi_m_n, NULL);
4929         }
4930
4931         haswell_set_pipeconf(crtc);
4932
4933         intel_set_pipe_csc(crtc);
4934
4935         intel_crtc->active = true;
4936
4937         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4938         for_each_encoder_on_crtc(dev, crtc, encoder)
4939                 if (encoder->pre_enable)
4940                         encoder->pre_enable(encoder);
4941
4942         if (intel_crtc->config->has_pch_encoder) {
4943                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4944                                                       true);
4945                 dev_priv->display.fdi_link_train(crtc);
4946         }
4947
4948         intel_ddi_enable_pipe_clock(intel_crtc);
4949
4950         if (INTEL_INFO(dev)->gen == 9)
4951                 skylake_pfit_enable(intel_crtc);
4952         else if (INTEL_INFO(dev)->gen < 9)
4953                 ironlake_pfit_enable(intel_crtc);
4954         else
4955                 MISSING_CASE(INTEL_INFO(dev)->gen);
4956
4957         /*
4958          * On ILK+ LUT must be loaded before the pipe is running but with
4959          * clocks enabled
4960          */
4961         intel_crtc_load_lut(crtc);
4962
4963         intel_ddi_set_pipe_settings(crtc);
4964         intel_ddi_enable_transcoder_func(crtc);
4965
4966         intel_update_watermarks(crtc);
4967         intel_enable_pipe(intel_crtc);
4968
4969         if (intel_crtc->config->has_pch_encoder)
4970                 lpt_pch_enable(crtc);
4971
4972         if (intel_crtc->config->dp_encoder_is_mst)
4973                 intel_ddi_set_vc_payload_alloc(crtc, true);
4974
4975         assert_vblank_disabled(crtc);
4976         drm_crtc_vblank_on(crtc);
4977
4978         for_each_encoder_on_crtc(dev, crtc, encoder) {
4979                 encoder->enable(encoder);
4980                 intel_opregion_notify_encoder(encoder, true);
4981         }
4982
4983         /* If we change the relative order between pipe/planes enabling, we need
4984          * to change the workaround. */
4985         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4986         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4987                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4989         }
4990 }
4991
4992 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4993 {
4994         struct drm_device *dev = crtc->base.dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         int pipe = crtc->pipe;
4997
4998         /* To avoid upsetting the power well on haswell only disable the pfit if
4999          * it's in use. The hw state code will make sure we get this right. */
5000         if (crtc->config->pch_pfit.enabled) {
5001                 I915_WRITE(PF_CTL(pipe), 0);
5002                 I915_WRITE(PF_WIN_POS(pipe), 0);
5003                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5004         }
5005 }
5006
5007 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012         struct intel_encoder *encoder;
5013         int pipe = intel_crtc->pipe;
5014         u32 reg, temp;
5015
5016         for_each_encoder_on_crtc(dev, crtc, encoder)
5017                 encoder->disable(encoder);
5018
5019         drm_crtc_vblank_off(crtc);
5020         assert_vblank_disabled(crtc);
5021
5022         if (intel_crtc->config->has_pch_encoder)
5023                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5024
5025         intel_disable_pipe(intel_crtc);
5026
5027         ironlake_pfit_disable(intel_crtc);
5028
5029         if (intel_crtc->config->has_pch_encoder)
5030                 ironlake_fdi_disable(crtc);
5031
5032         for_each_encoder_on_crtc(dev, crtc, encoder)
5033                 if (encoder->post_disable)
5034                         encoder->post_disable(encoder);
5035
5036         if (intel_crtc->config->has_pch_encoder) {
5037                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5038
5039                 if (HAS_PCH_CPT(dev)) {
5040                         /* disable TRANS_DP_CTL */
5041                         reg = TRANS_DP_CTL(pipe);
5042                         temp = I915_READ(reg);
5043                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5044                                   TRANS_DP_PORT_SEL_MASK);
5045                         temp |= TRANS_DP_PORT_SEL_NONE;
5046                         I915_WRITE(reg, temp);
5047
5048                         /* disable DPLL_SEL */
5049                         temp = I915_READ(PCH_DPLL_SEL);
5050                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5051                         I915_WRITE(PCH_DPLL_SEL, temp);
5052                 }
5053
5054                 ironlake_fdi_pll_disable(intel_crtc);
5055         }
5056
5057         intel_crtc->active = false;
5058         intel_update_watermarks(crtc);
5059 }
5060
5061 static void haswell_crtc_disable(struct drm_crtc *crtc)
5062 {
5063         struct drm_device *dev = crtc->dev;
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066         struct intel_encoder *encoder;
5067         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5068
5069         for_each_encoder_on_crtc(dev, crtc, encoder) {
5070                 intel_opregion_notify_encoder(encoder, false);
5071                 encoder->disable(encoder);
5072         }
5073
5074         drm_crtc_vblank_off(crtc);
5075         assert_vblank_disabled(crtc);
5076
5077         if (intel_crtc->config->has_pch_encoder)
5078                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5079                                                       false);
5080         intel_disable_pipe(intel_crtc);
5081
5082         if (intel_crtc->config->dp_encoder_is_mst)
5083                 intel_ddi_set_vc_payload_alloc(crtc, false);
5084
5085         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5086
5087         if (INTEL_INFO(dev)->gen == 9)
5088                 skylake_scaler_disable(intel_crtc);
5089         else if (INTEL_INFO(dev)->gen < 9)
5090                 ironlake_pfit_disable(intel_crtc);
5091         else
5092                 MISSING_CASE(INTEL_INFO(dev)->gen);
5093
5094         intel_ddi_disable_pipe_clock(intel_crtc);
5095
5096         if (intel_crtc->config->has_pch_encoder) {
5097                 lpt_disable_pch_transcoder(dev_priv);
5098                 intel_ddi_fdi_disable(crtc);
5099         }
5100
5101         for_each_encoder_on_crtc(dev, crtc, encoder)
5102                 if (encoder->post_disable)
5103                         encoder->post_disable(encoder);
5104
5105         intel_crtc->active = false;
5106         intel_update_watermarks(crtc);
5107 }
5108
5109 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5110 {
5111         struct drm_device *dev = crtc->base.dev;
5112         struct drm_i915_private *dev_priv = dev->dev_private;
5113         struct intel_crtc_state *pipe_config = crtc->config;
5114
5115         if (!pipe_config->gmch_pfit.control)
5116                 return;
5117
5118         /*
5119          * The panel fitter should only be adjusted whilst the pipe is disabled,
5120          * according to register description and PRM.
5121          */
5122         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5123         assert_pipe_disabled(dev_priv, crtc->pipe);
5124
5125         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5126         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5127
5128         /* Border color in case we don't scale up to the full screen. Black by
5129          * default, change to something else for debugging. */
5130         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5131 }
5132
5133 static enum intel_display_power_domain port_to_power_domain(enum port port)
5134 {
5135         switch (port) {
5136         case PORT_A:
5137                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5138         case PORT_B:
5139                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5140         case PORT_C:
5141                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5142         case PORT_D:
5143                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5144         default:
5145                 WARN_ON_ONCE(1);
5146                 return POWER_DOMAIN_PORT_OTHER;
5147         }
5148 }
5149
5150 #define for_each_power_domain(domain, mask)                             \
5151         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5152                 if ((1 << (domain)) & (mask))
5153
5154 enum intel_display_power_domain
5155 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5156 {
5157         struct drm_device *dev = intel_encoder->base.dev;
5158         struct intel_digital_port *intel_dig_port;
5159
5160         switch (intel_encoder->type) {
5161         case INTEL_OUTPUT_UNKNOWN:
5162                 /* Only DDI platforms should ever use this output type */
5163                 WARN_ON_ONCE(!HAS_DDI(dev));
5164         case INTEL_OUTPUT_DISPLAYPORT:
5165         case INTEL_OUTPUT_HDMI:
5166         case INTEL_OUTPUT_EDP:
5167                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5168                 return port_to_power_domain(intel_dig_port->port);
5169         case INTEL_OUTPUT_DP_MST:
5170                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5171                 return port_to_power_domain(intel_dig_port->port);
5172         case INTEL_OUTPUT_ANALOG:
5173                 return POWER_DOMAIN_PORT_CRT;
5174         case INTEL_OUTPUT_DSI:
5175                 return POWER_DOMAIN_PORT_DSI;
5176         default:
5177                 return POWER_DOMAIN_PORT_OTHER;
5178         }
5179 }
5180
5181 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5182 {
5183         struct drm_device *dev = crtc->dev;
5184         struct intel_encoder *intel_encoder;
5185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186         enum pipe pipe = intel_crtc->pipe;
5187         unsigned long mask;
5188         enum transcoder transcoder;
5189
5190         if (!crtc->state->active)
5191                 return 0;
5192
5193         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5194
5195         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5196         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5197         if (intel_crtc->config->pch_pfit.enabled ||
5198             intel_crtc->config->pch_pfit.force_thru)
5199                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5200
5201         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5202                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5203
5204         return mask;
5205 }
5206
5207 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5208 {
5209         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211         enum intel_display_power_domain domain;
5212         unsigned long domains, new_domains, old_domains;
5213
5214         old_domains = intel_crtc->enabled_power_domains;
5215         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5216
5217         domains = new_domains & ~old_domains;
5218
5219         for_each_power_domain(domain, domains)
5220                 intel_display_power_get(dev_priv, domain);
5221
5222         return old_domains & ~new_domains;
5223 }
5224
5225 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5226                                       unsigned long domains)
5227 {
5228         enum intel_display_power_domain domain;
5229
5230         for_each_power_domain(domain, domains)
5231                 intel_display_power_put(dev_priv, domain);
5232 }
5233
5234 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5235 {
5236         struct drm_device *dev = state->dev;
5237         struct drm_i915_private *dev_priv = dev->dev_private;
5238         unsigned long put_domains[I915_MAX_PIPES] = {};
5239         struct drm_crtc_state *crtc_state;
5240         struct drm_crtc *crtc;
5241         int i;
5242
5243         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5244                 if (needs_modeset(crtc->state))
5245                         put_domains[to_intel_crtc(crtc)->pipe] =
5246                                 modeset_get_crtc_power_domains(crtc);
5247         }
5248
5249         if (dev_priv->display.modeset_commit_cdclk) {
5250                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5251
5252                 if (cdclk != dev_priv->cdclk_freq &&
5253                     !WARN_ON(!state->allow_modeset))
5254                         dev_priv->display.modeset_commit_cdclk(state);
5255         }
5256
5257         for (i = 0; i < I915_MAX_PIPES; i++)
5258                 if (put_domains[i])
5259                         modeset_put_power_domains(dev_priv, put_domains[i]);
5260 }
5261
5262 static void intel_update_max_cdclk(struct drm_device *dev)
5263 {
5264         struct drm_i915_private *dev_priv = dev->dev_private;
5265
5266         if (IS_SKYLAKE(dev)) {
5267                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5268
5269                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5270                         dev_priv->max_cdclk_freq = 675000;
5271                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5272                         dev_priv->max_cdclk_freq = 540000;
5273                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5274                         dev_priv->max_cdclk_freq = 450000;
5275                 else
5276                         dev_priv->max_cdclk_freq = 337500;
5277         } else if (IS_BROADWELL(dev))  {
5278                 /*
5279                  * FIXME with extra cooling we can allow
5280                  * 540 MHz for ULX and 675 Mhz for ULT.
5281                  * How can we know if extra cooling is
5282                  * available? PCI ID, VTB, something else?
5283                  */
5284                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5285                         dev_priv->max_cdclk_freq = 450000;
5286                 else if (IS_BDW_ULX(dev))
5287                         dev_priv->max_cdclk_freq = 450000;
5288                 else if (IS_BDW_ULT(dev))
5289                         dev_priv->max_cdclk_freq = 540000;
5290                 else
5291                         dev_priv->max_cdclk_freq = 675000;
5292         } else if (IS_CHERRYVIEW(dev)) {
5293                 dev_priv->max_cdclk_freq = 320000;
5294         } else if (IS_VALLEYVIEW(dev)) {
5295                 dev_priv->max_cdclk_freq = 400000;
5296         } else {
5297                 /* otherwise assume cdclk is fixed */
5298                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5299         }
5300
5301         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302                          dev_priv->max_cdclk_freq);
5303 }
5304
5305 static void intel_update_cdclk(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311                          dev_priv->cdclk_freq);
5312
5313         /*
5314          * Program the gmbus_freq based on the cdclk frequency.
5315          * BSpec erroneously claims we should aim for 4MHz, but
5316          * in fact 1MHz is the correct frequency.
5317          */
5318         if (IS_VALLEYVIEW(dev)) {
5319                 /*
5320                  * Program the gmbus_freq based on the cdclk frequency.
5321                  * BSpec erroneously claims we should aim for 4MHz, but
5322                  * in fact 1MHz is the correct frequency.
5323                  */
5324                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5325         }
5326
5327         if (dev_priv->max_cdclk_freq == 0)
5328                 intel_update_max_cdclk(dev);
5329 }
5330
5331 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5332 {
5333         struct drm_i915_private *dev_priv = dev->dev_private;
5334         uint32_t divider;
5335         uint32_t ratio;
5336         uint32_t current_freq;
5337         int ret;
5338
5339         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340         switch (frequency) {
5341         case 144000:
5342                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343                 ratio = BXT_DE_PLL_RATIO(60);
5344                 break;
5345         case 288000:
5346                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347                 ratio = BXT_DE_PLL_RATIO(60);
5348                 break;
5349         case 384000:
5350                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351                 ratio = BXT_DE_PLL_RATIO(60);
5352                 break;
5353         case 576000:
5354                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355                 ratio = BXT_DE_PLL_RATIO(60);
5356                 break;
5357         case 624000:
5358                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359                 ratio = BXT_DE_PLL_RATIO(65);
5360                 break;
5361         case 19200:
5362                 /*
5363                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5364                  * to suppress GCC warning.
5365                  */
5366                 ratio = 0;
5367                 divider = 0;
5368                 break;
5369         default:
5370                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5371
5372                 return;
5373         }
5374
5375         mutex_lock(&dev_priv->rps.hw_lock);
5376         /* Inform power controller of upcoming frequency change */
5377         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5378                                       0x80000000);
5379         mutex_unlock(&dev_priv->rps.hw_lock);
5380
5381         if (ret) {
5382                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5383                           ret, frequency);
5384                 return;
5385         }
5386
5387         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389         current_freq = current_freq * 500 + 1000;
5390
5391         /*
5392          * DE PLL has to be disabled when
5393          * - setting to 19.2MHz (bypass, PLL isn't used)
5394          * - before setting to 624MHz (PLL needs toggling)
5395          * - before setting to any frequency from 624MHz (PLL needs toggling)
5396          */
5397         if (frequency == 19200 || frequency == 624000 ||
5398             current_freq == 624000) {
5399                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5400                 /* Timeout 200us */
5401                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5402                              1))
5403                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5404         }
5405
5406         if (frequency != 19200) {
5407                 uint32_t val;
5408
5409                 val = I915_READ(BXT_DE_PLL_CTL);
5410                 val &= ~BXT_DE_PLL_RATIO_MASK;
5411                 val |= ratio;
5412                 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415                 /* Timeout 200us */
5416                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5418
5419                 val = I915_READ(CDCLK_CTL);
5420                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5421                 val |= divider;
5422                 /*
5423                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5424                  * enable otherwise.
5425                  */
5426                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427                 if (frequency >= 500000)
5428                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429
5430                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432                 val |= (frequency - 1000) / 500;
5433                 I915_WRITE(CDCLK_CTL, val);
5434         }
5435
5436         mutex_lock(&dev_priv->rps.hw_lock);
5437         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438                                       DIV_ROUND_UP(frequency, 25000));
5439         mutex_unlock(&dev_priv->rps.hw_lock);
5440
5441         if (ret) {
5442                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5443                           ret, frequency);
5444                 return;
5445         }
5446
5447         intel_update_cdclk(dev);
5448 }
5449
5450 void broxton_init_cdclk(struct drm_device *dev)
5451 {
5452         struct drm_i915_private *dev_priv = dev->dev_private;
5453         uint32_t val;
5454
5455         /*
5456          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457          * or else the reset will hang because there is no PCH to respond.
5458          * Move the handshake programming to initialization sequence.
5459          * Previously was left up to BIOS.
5460          */
5461         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5464
5465         /* Enable PG1 for cdclk */
5466         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5467
5468         /* check if cd clock is enabled */
5469         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470                 DRM_DEBUG_KMS("Display already initialized\n");
5471                 return;
5472         }
5473
5474         /*
5475          * FIXME:
5476          * - The initial CDCLK needs to be read from VBT.
5477          *   Need to make this change after VBT has changes for BXT.
5478          * - check if setting the max (or any) cdclk freq is really necessary
5479          *   here, it belongs to modeset time
5480          */
5481         broxton_set_cdclk(dev, 624000);
5482
5483         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5484         POSTING_READ(DBUF_CTL);
5485
5486         udelay(10);
5487
5488         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489                 DRM_ERROR("DBuf power enable timeout!\n");
5490 }
5491
5492 void broxton_uninit_cdclk(struct drm_device *dev)
5493 {
5494         struct drm_i915_private *dev_priv = dev->dev_private;
5495
5496         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5497         POSTING_READ(DBUF_CTL);
5498
5499         udelay(10);
5500
5501         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502                 DRM_ERROR("DBuf power disable timeout!\n");
5503
5504         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505         broxton_set_cdclk(dev, 19200);
5506
5507         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5508 }
5509
5510 static const struct skl_cdclk_entry {
5511         unsigned int freq;
5512         unsigned int vco;
5513 } skl_cdclk_frequencies[] = {
5514         { .freq = 308570, .vco = 8640 },
5515         { .freq = 337500, .vco = 8100 },
5516         { .freq = 432000, .vco = 8640 },
5517         { .freq = 450000, .vco = 8100 },
5518         { .freq = 540000, .vco = 8100 },
5519         { .freq = 617140, .vco = 8640 },
5520         { .freq = 675000, .vco = 8100 },
5521 };
5522
5523 static unsigned int skl_cdclk_decimal(unsigned int freq)
5524 {
5525         return (freq - 1000) / 500;
5526 }
5527
5528 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5529 {
5530         unsigned int i;
5531
5532         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5534
5535                 if (e->freq == freq)
5536                         return e->vco;
5537         }
5538
5539         return 8100;
5540 }
5541
5542 static void
5543 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5544 {
5545         unsigned int min_freq;
5546         u32 val;
5547
5548         /* select the minimum CDCLK before enabling DPLL 0 */
5549         val = I915_READ(CDCLK_CTL);
5550         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551         val |= CDCLK_FREQ_337_308;
5552
5553         if (required_vco == 8640)
5554                 min_freq = 308570;
5555         else
5556                 min_freq = 337500;
5557
5558         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5559
5560         I915_WRITE(CDCLK_CTL, val);
5561         POSTING_READ(CDCLK_CTL);
5562
5563         /*
5564          * We always enable DPLL0 with the lowest link rate possible, but still
5565          * taking into account the VCO required to operate the eDP panel at the
5566          * desired frequency. The usual DP link rates operate with a VCO of
5567          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568          * The modeset code is responsible for the selection of the exact link
5569          * rate later on, with the constraint of choosing a frequency that
5570          * works with required_vco.
5571          */
5572         val = I915_READ(DPLL_CTRL1);
5573
5574         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577         if (required_vco == 8640)
5578                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5579                                             SKL_DPLL0);
5580         else
5581                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5582                                             SKL_DPLL0);
5583
5584         I915_WRITE(DPLL_CTRL1, val);
5585         POSTING_READ(DPLL_CTRL1);
5586
5587         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5588
5589         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590                 DRM_ERROR("DPLL0 not locked\n");
5591 }
5592
5593 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5594 {
5595         int ret;
5596         u32 val;
5597
5598         /* inform PCU we want to change CDCLK */
5599         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600         mutex_lock(&dev_priv->rps.hw_lock);
5601         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602         mutex_unlock(&dev_priv->rps.hw_lock);
5603
5604         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5605 }
5606
5607 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5608 {
5609         unsigned int i;
5610
5611         for (i = 0; i < 15; i++) {
5612                 if (skl_cdclk_pcu_ready(dev_priv))
5613                         return true;
5614                 udelay(10);
5615         }
5616
5617         return false;
5618 }
5619
5620 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5621 {
5622         struct drm_device *dev = dev_priv->dev;
5623         u32 freq_select, pcu_ack;
5624
5625         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5626
5627         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5629                 return;
5630         }
5631
5632         /* set CDCLK_CTL */
5633         switch(freq) {
5634         case 450000:
5635         case 432000:
5636                 freq_select = CDCLK_FREQ_450_432;
5637                 pcu_ack = 1;
5638                 break;
5639         case 540000:
5640                 freq_select = CDCLK_FREQ_540;
5641                 pcu_ack = 2;
5642                 break;
5643         case 308570:
5644         case 337500:
5645         default:
5646                 freq_select = CDCLK_FREQ_337_308;
5647                 pcu_ack = 0;
5648                 break;
5649         case 617140:
5650         case 675000:
5651                 freq_select = CDCLK_FREQ_675_617;
5652                 pcu_ack = 3;
5653                 break;
5654         }
5655
5656         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657         POSTING_READ(CDCLK_CTL);
5658
5659         /* inform PCU of the change */
5660         mutex_lock(&dev_priv->rps.hw_lock);
5661         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662         mutex_unlock(&dev_priv->rps.hw_lock);
5663
5664         intel_update_cdclk(dev);
5665 }
5666
5667 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5668 {
5669         /* disable DBUF power */
5670         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671         POSTING_READ(DBUF_CTL);
5672
5673         udelay(10);
5674
5675         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676                 DRM_ERROR("DBuf power disable timeout\n");
5677
5678         /* disable DPLL0 */
5679         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681                 DRM_ERROR("Couldn't disable DPLL0\n");
5682
5683         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5684 }
5685
5686 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5687 {
5688         u32 val;
5689         unsigned int required_vco;
5690
5691         /* enable PCH reset handshake */
5692         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5693         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5694
5695         /* enable PG1 and Misc I/O */
5696         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5697
5698         /* DPLL0 already enabed !? */
5699         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5700                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5701                 return;
5702         }
5703
5704         /* enable DPLL0 */
5705         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5706         skl_dpll0_enable(dev_priv, required_vco);
5707
5708         /* set CDCLK to the frequency the BIOS chose */
5709         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5710
5711         /* enable DBUF power */
5712         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5713         POSTING_READ(DBUF_CTL);
5714
5715         udelay(10);
5716
5717         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5718                 DRM_ERROR("DBuf power enable timeout\n");
5719 }
5720
5721 /* returns HPLL frequency in kHz */
5722 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5723 {
5724         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5725
5726         /* Obtain SKU information */
5727         mutex_lock(&dev_priv->sb_lock);
5728         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5729                 CCK_FUSE_HPLL_FREQ_MASK;
5730         mutex_unlock(&dev_priv->sb_lock);
5731
5732         return vco_freq[hpll_freq] * 1000;
5733 }
5734
5735 /* Adjust CDclk dividers to allow high res or save power if possible */
5736 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5737 {
5738         struct drm_i915_private *dev_priv = dev->dev_private;
5739         u32 val, cmd;
5740
5741         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5742                                         != dev_priv->cdclk_freq);
5743
5744         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5745                 cmd = 2;
5746         else if (cdclk == 266667)
5747                 cmd = 1;
5748         else
5749                 cmd = 0;
5750
5751         mutex_lock(&dev_priv->rps.hw_lock);
5752         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5753         val &= ~DSPFREQGUAR_MASK;
5754         val |= (cmd << DSPFREQGUAR_SHIFT);
5755         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5756         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5757                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5758                      50)) {
5759                 DRM_ERROR("timed out waiting for CDclk change\n");
5760         }
5761         mutex_unlock(&dev_priv->rps.hw_lock);
5762
5763         mutex_lock(&dev_priv->sb_lock);
5764
5765         if (cdclk == 400000) {
5766                 u32 divider;
5767
5768                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5769
5770                 /* adjust cdclk divider */
5771                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5772                 val &= ~DISPLAY_FREQUENCY_VALUES;
5773                 val |= divider;
5774                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5775
5776                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5777                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5778                              50))
5779                         DRM_ERROR("timed out waiting for CDclk change\n");
5780         }
5781
5782         /* adjust self-refresh exit latency value */
5783         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5784         val &= ~0x7f;
5785
5786         /*
5787          * For high bandwidth configs, we set a higher latency in the bunit
5788          * so that the core display fetch happens in time to avoid underruns.
5789          */
5790         if (cdclk == 400000)
5791                 val |= 4500 / 250; /* 4.5 usec */
5792         else
5793                 val |= 3000 / 250; /* 3.0 usec */
5794         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5795
5796         mutex_unlock(&dev_priv->sb_lock);
5797
5798         intel_update_cdclk(dev);
5799 }
5800
5801 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5802 {
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         u32 val, cmd;
5805
5806         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807                                                 != dev_priv->cdclk_freq);
5808
5809         switch (cdclk) {
5810         case 333333:
5811         case 320000:
5812         case 266667:
5813         case 200000:
5814                 break;
5815         default:
5816                 MISSING_CASE(cdclk);
5817                 return;
5818         }
5819
5820         /*
5821          * Specs are full of misinformation, but testing on actual
5822          * hardware has shown that we just need to write the desired
5823          * CCK divider into the Punit register.
5824          */
5825         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5826
5827         mutex_lock(&dev_priv->rps.hw_lock);
5828         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5829         val &= ~DSPFREQGUAR_MASK_CHV;
5830         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5831         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5832         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5833                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5834                      50)) {
5835                 DRM_ERROR("timed out waiting for CDclk change\n");
5836         }
5837         mutex_unlock(&dev_priv->rps.hw_lock);
5838
5839         intel_update_cdclk(dev);
5840 }
5841
5842 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5843                                  int max_pixclk)
5844 {
5845         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5846         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5847
5848         /*
5849          * Really only a few cases to deal with, as only 4 CDclks are supported:
5850          *   200MHz
5851          *   267MHz
5852          *   320/333MHz (depends on HPLL freq)
5853          *   400MHz (VLV only)
5854          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5855          * of the lower bin and adjust if needed.
5856          *
5857          * We seem to get an unstable or solid color picture at 200MHz.
5858          * Not sure what's wrong. For now use 200MHz only when all pipes
5859          * are off.
5860          */
5861         if (!IS_CHERRYVIEW(dev_priv) &&
5862             max_pixclk > freq_320*limit/100)
5863                 return 400000;
5864         else if (max_pixclk > 266667*limit/100)
5865                 return freq_320;
5866         else if (max_pixclk > 0)
5867                 return 266667;
5868         else
5869                 return 200000;
5870 }
5871
5872 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5873                               int max_pixclk)
5874 {
5875         /*
5876          * FIXME:
5877          * - remove the guardband, it's not needed on BXT
5878          * - set 19.2MHz bypass frequency if there are no active pipes
5879          */
5880         if (max_pixclk > 576000*9/10)
5881                 return 624000;
5882         else if (max_pixclk > 384000*9/10)
5883                 return 576000;
5884         else if (max_pixclk > 288000*9/10)
5885                 return 384000;
5886         else if (max_pixclk > 144000*9/10)
5887                 return 288000;
5888         else
5889                 return 144000;
5890 }
5891
5892 /* Compute the max pixel clock for new configuration. Uses atomic state if
5893  * that's non-NULL, look at current state otherwise. */
5894 static int intel_mode_max_pixclk(struct drm_device *dev,
5895                                  struct drm_atomic_state *state)
5896 {
5897         struct intel_crtc *intel_crtc;
5898         struct intel_crtc_state *crtc_state;
5899         int max_pixclk = 0;
5900
5901         for_each_intel_crtc(dev, intel_crtc) {
5902                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5903                 if (IS_ERR(crtc_state))
5904                         return PTR_ERR(crtc_state);
5905
5906                 if (!crtc_state->base.enable)
5907                         continue;
5908
5909                 max_pixclk = max(max_pixclk,
5910                                  crtc_state->base.adjusted_mode.crtc_clock);
5911         }
5912
5913         return max_pixclk;
5914 }
5915
5916 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5917 {
5918         struct drm_device *dev = state->dev;
5919         struct drm_i915_private *dev_priv = dev->dev_private;
5920         int max_pixclk = intel_mode_max_pixclk(dev, state);
5921
5922         if (max_pixclk < 0)
5923                 return max_pixclk;
5924
5925         to_intel_atomic_state(state)->cdclk =
5926                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5927
5928         return 0;
5929 }
5930
5931 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5932 {
5933         struct drm_device *dev = state->dev;
5934         struct drm_i915_private *dev_priv = dev->dev_private;
5935         int max_pixclk = intel_mode_max_pixclk(dev, state);
5936
5937         if (max_pixclk < 0)
5938                 return max_pixclk;
5939
5940         to_intel_atomic_state(state)->cdclk =
5941                 broxton_calc_cdclk(dev_priv, max_pixclk);
5942
5943         return 0;
5944 }
5945
5946 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5947 {
5948         unsigned int credits, default_credits;
5949
5950         if (IS_CHERRYVIEW(dev_priv))
5951                 default_credits = PFI_CREDIT(12);
5952         else
5953                 default_credits = PFI_CREDIT(8);
5954
5955         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5956                 /* CHV suggested value is 31 or 63 */
5957                 if (IS_CHERRYVIEW(dev_priv))
5958                         credits = PFI_CREDIT_63;
5959                 else
5960                         credits = PFI_CREDIT(15);
5961         } else {
5962                 credits = default_credits;
5963         }
5964
5965         /*
5966          * WA - write default credits before re-programming
5967          * FIXME: should we also set the resend bit here?
5968          */
5969         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5970                    default_credits);
5971
5972         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5973                    credits | PFI_CREDIT_RESEND);
5974
5975         /*
5976          * FIXME is this guaranteed to clear
5977          * immediately or should we poll for it?
5978          */
5979         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5980 }
5981
5982 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5983 {
5984         struct drm_device *dev = old_state->dev;
5985         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987
5988         /*
5989          * FIXME: We can end up here with all power domains off, yet
5990          * with a CDCLK frequency other than the minimum. To account
5991          * for this take the PIPE-A power domain, which covers the HW
5992          * blocks needed for the following programming. This can be
5993          * removed once it's guaranteed that we get here either with
5994          * the minimum CDCLK set, or the required power domains
5995          * enabled.
5996          */
5997         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5998
5999         if (IS_CHERRYVIEW(dev))
6000                 cherryview_set_cdclk(dev, req_cdclk);
6001         else
6002                 valleyview_set_cdclk(dev, req_cdclk);
6003
6004         vlv_program_pfi_credits(dev_priv);
6005
6006         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6007 }
6008
6009 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6010 {
6011         struct drm_device *dev = crtc->dev;
6012         struct drm_i915_private *dev_priv = to_i915(dev);
6013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014         struct intel_encoder *encoder;
6015         int pipe = intel_crtc->pipe;
6016         bool is_dsi;
6017
6018         if (WARN_ON(intel_crtc->active))
6019                 return;
6020
6021         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6022
6023         if (!is_dsi) {
6024                 if (IS_CHERRYVIEW(dev))
6025                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6026                 else
6027                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6028         }
6029
6030         if (intel_crtc->config->has_dp_encoder)
6031                 intel_dp_set_m_n(intel_crtc, M1_N1);
6032
6033         intel_set_pipe_timings(intel_crtc);
6034
6035         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6036                 struct drm_i915_private *dev_priv = dev->dev_private;
6037
6038                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6039                 I915_WRITE(CHV_CANVAS(pipe), 0);
6040         }
6041
6042         i9xx_set_pipeconf(intel_crtc);
6043
6044         intel_crtc->active = true;
6045
6046         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6047
6048         for_each_encoder_on_crtc(dev, crtc, encoder)
6049                 if (encoder->pre_pll_enable)
6050                         encoder->pre_pll_enable(encoder);
6051
6052         if (!is_dsi) {
6053                 if (IS_CHERRYVIEW(dev))
6054                         chv_enable_pll(intel_crtc, intel_crtc->config);
6055                 else
6056                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6057         }
6058
6059         for_each_encoder_on_crtc(dev, crtc, encoder)
6060                 if (encoder->pre_enable)
6061                         encoder->pre_enable(encoder);
6062
6063         i9xx_pfit_enable(intel_crtc);
6064
6065         intel_crtc_load_lut(crtc);
6066
6067         intel_enable_pipe(intel_crtc);
6068
6069         assert_vblank_disabled(crtc);
6070         drm_crtc_vblank_on(crtc);
6071
6072         for_each_encoder_on_crtc(dev, crtc, encoder)
6073                 encoder->enable(encoder);
6074 }
6075
6076 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6077 {
6078         struct drm_device *dev = crtc->base.dev;
6079         struct drm_i915_private *dev_priv = dev->dev_private;
6080
6081         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6082         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6083 }
6084
6085 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6086 {
6087         struct drm_device *dev = crtc->dev;
6088         struct drm_i915_private *dev_priv = to_i915(dev);
6089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090         struct intel_encoder *encoder;
6091         int pipe = intel_crtc->pipe;
6092
6093         if (WARN_ON(intel_crtc->active))
6094                 return;
6095
6096         i9xx_set_pll_dividers(intel_crtc);
6097
6098         if (intel_crtc->config->has_dp_encoder)
6099                 intel_dp_set_m_n(intel_crtc, M1_N1);
6100
6101         intel_set_pipe_timings(intel_crtc);
6102
6103         i9xx_set_pipeconf(intel_crtc);
6104
6105         intel_crtc->active = true;
6106
6107         if (!IS_GEN2(dev))
6108                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6109
6110         for_each_encoder_on_crtc(dev, crtc, encoder)
6111                 if (encoder->pre_enable)
6112                         encoder->pre_enable(encoder);
6113
6114         i9xx_enable_pll(intel_crtc);
6115
6116         i9xx_pfit_enable(intel_crtc);
6117
6118         intel_crtc_load_lut(crtc);
6119
6120         intel_update_watermarks(crtc);
6121         intel_enable_pipe(intel_crtc);
6122
6123         assert_vblank_disabled(crtc);
6124         drm_crtc_vblank_on(crtc);
6125
6126         for_each_encoder_on_crtc(dev, crtc, encoder)
6127                 encoder->enable(encoder);
6128 }
6129
6130 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6131 {
6132         struct drm_device *dev = crtc->base.dev;
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134
6135         if (!crtc->config->gmch_pfit.control)
6136                 return;
6137
6138         assert_pipe_disabled(dev_priv, crtc->pipe);
6139
6140         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6141                          I915_READ(PFIT_CONTROL));
6142         I915_WRITE(PFIT_CONTROL, 0);
6143 }
6144
6145 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6146 {
6147         struct drm_device *dev = crtc->dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150         struct intel_encoder *encoder;
6151         int pipe = intel_crtc->pipe;
6152
6153         /*
6154          * On gen2 planes are double buffered but the pipe isn't, so we must
6155          * wait for planes to fully turn off before disabling the pipe.
6156          * We also need to wait on all gmch platforms because of the
6157          * self-refresh mode constraint explained above.
6158          */
6159         intel_wait_for_vblank(dev, pipe);
6160
6161         for_each_encoder_on_crtc(dev, crtc, encoder)
6162                 encoder->disable(encoder);
6163
6164         drm_crtc_vblank_off(crtc);
6165         assert_vblank_disabled(crtc);
6166
6167         intel_disable_pipe(intel_crtc);
6168
6169         i9xx_pfit_disable(intel_crtc);
6170
6171         for_each_encoder_on_crtc(dev, crtc, encoder)
6172                 if (encoder->post_disable)
6173                         encoder->post_disable(encoder);
6174
6175         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6176                 if (IS_CHERRYVIEW(dev))
6177                         chv_disable_pll(dev_priv, pipe);
6178                 else if (IS_VALLEYVIEW(dev))
6179                         vlv_disable_pll(dev_priv, pipe);
6180                 else
6181                         i9xx_disable_pll(intel_crtc);
6182         }
6183
6184         if (!IS_GEN2(dev))
6185                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6186
6187         intel_crtc->active = false;
6188         intel_update_watermarks(crtc);
6189 }
6190
6191 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6192 {
6193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6195         enum intel_display_power_domain domain;
6196         unsigned long domains;
6197
6198         if (!intel_crtc->active)
6199                 return;
6200
6201         if (to_intel_plane_state(crtc->primary->state)->visible) {
6202                 intel_crtc_wait_for_pending_flips(crtc);
6203                 intel_pre_disable_primary(crtc);
6204         }
6205
6206         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6207         dev_priv->display.crtc_disable(crtc);
6208         intel_disable_shared_dpll(intel_crtc);
6209
6210         domains = intel_crtc->enabled_power_domains;
6211         for_each_power_domain(domain, domains)
6212                 intel_display_power_put(dev_priv, domain);
6213         intel_crtc->enabled_power_domains = 0;
6214 }
6215
6216 /*
6217  * turn all crtc's off, but do not adjust state
6218  * This has to be paired with a call to intel_modeset_setup_hw_state.
6219  */
6220 int intel_display_suspend(struct drm_device *dev)
6221 {
6222         struct drm_mode_config *config = &dev->mode_config;
6223         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6224         struct drm_atomic_state *state;
6225         struct drm_crtc *crtc;
6226         unsigned crtc_mask = 0;
6227         int ret = 0;
6228
6229         if (WARN_ON(!ctx))
6230                 return 0;
6231
6232         lockdep_assert_held(&ctx->ww_ctx);
6233         state = drm_atomic_state_alloc(dev);
6234         if (WARN_ON(!state))
6235                 return -ENOMEM;
6236
6237         state->acquire_ctx = ctx;
6238         state->allow_modeset = true;
6239
6240         for_each_crtc(dev, crtc) {
6241                 struct drm_crtc_state *crtc_state =
6242                         drm_atomic_get_crtc_state(state, crtc);
6243
6244                 ret = PTR_ERR_OR_ZERO(crtc_state);
6245                 if (ret)
6246                         goto free;
6247
6248                 if (!crtc_state->active)
6249                         continue;
6250
6251                 crtc_state->active = false;
6252                 crtc_mask |= 1 << drm_crtc_index(crtc);
6253         }
6254
6255         if (crtc_mask) {
6256                 ret = drm_atomic_commit(state);
6257
6258                 if (!ret) {
6259                         for_each_crtc(dev, crtc)
6260                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6261                                         crtc->state->active = true;
6262
6263                         return ret;
6264                 }
6265         }
6266
6267 free:
6268         if (ret)
6269                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6270         drm_atomic_state_free(state);
6271         return ret;
6272 }
6273
6274 /* Master function to enable/disable CRTC and corresponding power wells */
6275 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6276 {
6277         struct drm_device *dev = crtc->dev;
6278         struct drm_mode_config *config = &dev->mode_config;
6279         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281         struct intel_crtc_state *pipe_config;
6282         struct drm_atomic_state *state;
6283         int ret;
6284
6285         if (enable == intel_crtc->active)
6286                 return 0;
6287
6288         if (enable && !crtc->state->enable)
6289                 return 0;
6290
6291         /* this function should be called with drm_modeset_lock_all for now */
6292         if (WARN_ON(!ctx))
6293                 return -EIO;
6294         lockdep_assert_held(&ctx->ww_ctx);
6295
6296         state = drm_atomic_state_alloc(dev);
6297         if (WARN_ON(!state))
6298                 return -ENOMEM;
6299
6300         state->acquire_ctx = ctx;
6301         state->allow_modeset = true;
6302
6303         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6304         if (IS_ERR(pipe_config)) {
6305                 ret = PTR_ERR(pipe_config);
6306                 goto err;
6307         }
6308         pipe_config->base.active = enable;
6309
6310         ret = drm_atomic_commit(state);
6311         if (!ret)
6312                 return ret;
6313
6314 err:
6315         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6316         drm_atomic_state_free(state);
6317         return ret;
6318 }
6319
6320 /**
6321  * Sets the power management mode of the pipe and plane.
6322  */
6323 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6324 {
6325         struct drm_device *dev = crtc->dev;
6326         struct intel_encoder *intel_encoder;
6327         bool enable = false;
6328
6329         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6330                 enable |= intel_encoder->connectors_active;
6331
6332         intel_crtc_control(crtc, enable);
6333 }
6334
6335 void intel_encoder_destroy(struct drm_encoder *encoder)
6336 {
6337         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6338
6339         drm_encoder_cleanup(encoder);
6340         kfree(intel_encoder);
6341 }
6342
6343 /* Simple dpms helper for encoders with just one connector, no cloning and only
6344  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6345  * state of the entire output pipe. */
6346 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6347 {
6348         if (mode == DRM_MODE_DPMS_ON) {
6349                 encoder->connectors_active = true;
6350
6351                 intel_crtc_update_dpms(encoder->base.crtc);
6352         } else {
6353                 encoder->connectors_active = false;
6354
6355                 intel_crtc_update_dpms(encoder->base.crtc);
6356         }
6357 }
6358
6359 /* Cross check the actual hw state with our own modeset state tracking (and it's
6360  * internal consistency). */
6361 static void intel_connector_check_state(struct intel_connector *connector)
6362 {
6363         if (connector->get_hw_state(connector)) {
6364                 struct intel_encoder *encoder = connector->encoder;
6365                 struct drm_crtc *crtc;
6366                 bool encoder_enabled;
6367                 enum pipe pipe;
6368
6369                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6370                               connector->base.base.id,
6371                               connector->base.name);
6372
6373                 /* there is no real hw state for MST connectors */
6374                 if (connector->mst_port)
6375                         return;
6376
6377                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6378                      "wrong connector dpms state\n");
6379                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6380                      "active connector not linked to encoder\n");
6381
6382                 if (encoder) {
6383                         I915_STATE_WARN(!encoder->connectors_active,
6384                              "encoder->connectors_active not set\n");
6385
6386                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6387                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6388                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6389                                 return;
6390
6391                         crtc = encoder->base.crtc;
6392
6393                         I915_STATE_WARN(!crtc->state->enable,
6394                                         "crtc not enabled\n");
6395                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6396                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6397                              "encoder active on the wrong pipe\n");
6398                 }
6399         }
6400 }
6401
6402 int intel_connector_init(struct intel_connector *connector)
6403 {
6404         struct drm_connector_state *connector_state;
6405
6406         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6407         if (!connector_state)
6408                 return -ENOMEM;
6409
6410         connector->base.state = connector_state;
6411         return 0;
6412 }
6413
6414 struct intel_connector *intel_connector_alloc(void)
6415 {
6416         struct intel_connector *connector;
6417
6418         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6419         if (!connector)
6420                 return NULL;
6421
6422         if (intel_connector_init(connector) < 0) {
6423                 kfree(connector);
6424                 return NULL;
6425         }
6426
6427         return connector;
6428 }
6429
6430 /* Even simpler default implementation, if there's really no special case to
6431  * consider. */
6432 void intel_connector_dpms(struct drm_connector *connector, int mode)
6433 {
6434         /* All the simple cases only support two dpms states. */
6435         if (mode != DRM_MODE_DPMS_ON)
6436                 mode = DRM_MODE_DPMS_OFF;
6437
6438         if (mode == connector->dpms)
6439                 return;
6440
6441         connector->dpms = mode;
6442
6443         /* Only need to change hw state when actually enabled */
6444         if (connector->encoder)
6445                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6446
6447         intel_modeset_check_state(connector->dev);
6448 }
6449
6450 /* Simple connector->get_hw_state implementation for encoders that support only
6451  * one connector and no cloning and hence the encoder state determines the state
6452  * of the connector. */
6453 bool intel_connector_get_hw_state(struct intel_connector *connector)
6454 {
6455         enum pipe pipe = 0;
6456         struct intel_encoder *encoder = connector->encoder;
6457
6458         return encoder->get_hw_state(encoder, &pipe);
6459 }
6460
6461 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6462 {
6463         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6464                 return crtc_state->fdi_lanes;
6465
6466         return 0;
6467 }
6468
6469 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6470                                      struct intel_crtc_state *pipe_config)
6471 {
6472         struct drm_atomic_state *state = pipe_config->base.state;
6473         struct intel_crtc *other_crtc;
6474         struct intel_crtc_state *other_crtc_state;
6475
6476         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6477                       pipe_name(pipe), pipe_config->fdi_lanes);
6478         if (pipe_config->fdi_lanes > 4) {
6479                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6480                               pipe_name(pipe), pipe_config->fdi_lanes);
6481                 return -EINVAL;
6482         }
6483
6484         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6485                 if (pipe_config->fdi_lanes > 2) {
6486                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6487                                       pipe_config->fdi_lanes);
6488                         return -EINVAL;
6489                 } else {
6490                         return 0;
6491                 }
6492         }
6493
6494         if (INTEL_INFO(dev)->num_pipes == 2)
6495                 return 0;
6496
6497         /* Ivybridge 3 pipe is really complicated */
6498         switch (pipe) {
6499         case PIPE_A:
6500                 return 0;
6501         case PIPE_B:
6502                 if (pipe_config->fdi_lanes <= 2)
6503                         return 0;
6504
6505                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6506                 other_crtc_state =
6507                         intel_atomic_get_crtc_state(state, other_crtc);
6508                 if (IS_ERR(other_crtc_state))
6509                         return PTR_ERR(other_crtc_state);
6510
6511                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6512                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6513                                       pipe_name(pipe), pipe_config->fdi_lanes);
6514                         return -EINVAL;
6515                 }
6516                 return 0;
6517         case PIPE_C:
6518                 if (pipe_config->fdi_lanes > 2) {
6519                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6520                                       pipe_name(pipe), pipe_config->fdi_lanes);
6521                         return -EINVAL;
6522                 }
6523
6524                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6525                 other_crtc_state =
6526                         intel_atomic_get_crtc_state(state, other_crtc);
6527                 if (IS_ERR(other_crtc_state))
6528                         return PTR_ERR(other_crtc_state);
6529
6530                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6531                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6532                         return -EINVAL;
6533                 }
6534                 return 0;
6535         default:
6536                 BUG();
6537         }
6538 }
6539
6540 #define RETRY 1
6541 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6542                                        struct intel_crtc_state *pipe_config)
6543 {
6544         struct drm_device *dev = intel_crtc->base.dev;
6545         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6546         int lane, link_bw, fdi_dotclock, ret;
6547         bool needs_recompute = false;
6548
6549 retry:
6550         /* FDI is a binary signal running at ~2.7GHz, encoding
6551          * each output octet as 10 bits. The actual frequency
6552          * is stored as a divider into a 100MHz clock, and the
6553          * mode pixel clock is stored in units of 1KHz.
6554          * Hence the bw of each lane in terms of the mode signal
6555          * is:
6556          */
6557         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6558
6559         fdi_dotclock = adjusted_mode->crtc_clock;
6560
6561         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6562                                            pipe_config->pipe_bpp);
6563
6564         pipe_config->fdi_lanes = lane;
6565
6566         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6567                                link_bw, &pipe_config->fdi_m_n);
6568
6569         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6570                                        intel_crtc->pipe, pipe_config);
6571         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6572                 pipe_config->pipe_bpp -= 2*3;
6573                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574                               pipe_config->pipe_bpp);
6575                 needs_recompute = true;
6576                 pipe_config->bw_constrained = true;
6577
6578                 goto retry;
6579         }
6580
6581         if (needs_recompute)
6582                 return RETRY;
6583
6584         return ret;
6585 }
6586
6587 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588                                      struct intel_crtc_state *pipe_config)
6589 {
6590         if (pipe_config->pipe_bpp > 24)
6591                 return false;
6592
6593         /* HSW can handle pixel rate up to cdclk? */
6594         if (IS_HASWELL(dev_priv->dev))
6595                 return true;
6596
6597         /*
6598          * We compare against max which means we must take
6599          * the increased cdclk requirement into account when
6600          * calculating the new cdclk.
6601          *
6602          * Should measure whether using a lower cdclk w/o IPS
6603          */
6604         return ilk_pipe_pixel_rate(pipe_config) <=
6605                 dev_priv->max_cdclk_freq * 95 / 100;
6606 }
6607
6608 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6609                                    struct intel_crtc_state *pipe_config)
6610 {
6611         struct drm_device *dev = crtc->base.dev;
6612         struct drm_i915_private *dev_priv = dev->dev_private;
6613
6614         pipe_config->ips_enabled = i915.enable_ips &&
6615                 hsw_crtc_supports_ips(crtc) &&
6616                 pipe_config_supports_ips(dev_priv, pipe_config);
6617 }
6618
6619 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6620                                      struct intel_crtc_state *pipe_config)
6621 {
6622         struct drm_device *dev = crtc->base.dev;
6623         struct drm_i915_private *dev_priv = dev->dev_private;
6624         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6625
6626         /* FIXME should check pixel clock limits on all platforms */
6627         if (INTEL_INFO(dev)->gen < 4) {
6628                 int clock_limit = dev_priv->max_cdclk_freq;
6629
6630                 /*
6631                  * Enable pixel doubling when the dot clock
6632                  * is > 90% of the (display) core speed.
6633                  *
6634                  * GDG double wide on either pipe,
6635                  * otherwise pipe A only.
6636                  */
6637                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6638                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6639                         clock_limit *= 2;
6640                         pipe_config->double_wide = true;
6641                 }
6642
6643                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6644                         return -EINVAL;
6645         }
6646
6647         /*
6648          * Pipe horizontal size must be even in:
6649          * - DVO ganged mode
6650          * - LVDS dual channel mode
6651          * - Double wide pipe
6652          */
6653         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6654              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6655                 pipe_config->pipe_src_w &= ~1;
6656
6657         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6658          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6659          */
6660         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6661                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6662                 return -EINVAL;
6663
6664         if (HAS_IPS(dev))
6665                 hsw_compute_ips_config(crtc, pipe_config);
6666
6667         if (pipe_config->has_pch_encoder)
6668                 return ironlake_fdi_compute_config(crtc, pipe_config);
6669
6670         return 0;
6671 }
6672
6673 static int skylake_get_display_clock_speed(struct drm_device *dev)
6674 {
6675         struct drm_i915_private *dev_priv = to_i915(dev);
6676         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6677         uint32_t cdctl = I915_READ(CDCLK_CTL);
6678         uint32_t linkrate;
6679
6680         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6681                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6682
6683         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6684                 return 540000;
6685
6686         linkrate = (I915_READ(DPLL_CTRL1) &
6687                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6688
6689         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6690             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6691                 /* vco 8640 */
6692                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6693                 case CDCLK_FREQ_450_432:
6694                         return 432000;
6695                 case CDCLK_FREQ_337_308:
6696                         return 308570;
6697                 case CDCLK_FREQ_675_617:
6698                         return 617140;
6699                 default:
6700                         WARN(1, "Unknown cd freq selection\n");
6701                 }
6702         } else {
6703                 /* vco 8100 */
6704                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6705                 case CDCLK_FREQ_450_432:
6706                         return 450000;
6707                 case CDCLK_FREQ_337_308:
6708                         return 337500;
6709                 case CDCLK_FREQ_675_617:
6710                         return 675000;
6711                 default:
6712                         WARN(1, "Unknown cd freq selection\n");
6713                 }
6714         }
6715
6716         /* error case, do as if DPLL0 isn't enabled */
6717         return 24000;
6718 }
6719
6720 static int broxton_get_display_clock_speed(struct drm_device *dev)
6721 {
6722         struct drm_i915_private *dev_priv = to_i915(dev);
6723         uint32_t cdctl = I915_READ(CDCLK_CTL);
6724         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6725         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6726         int cdclk;
6727
6728         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6729                 return 19200;
6730
6731         cdclk = 19200 * pll_ratio / 2;
6732
6733         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6734         case BXT_CDCLK_CD2X_DIV_SEL_1:
6735                 return cdclk;  /* 576MHz or 624MHz */
6736         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6737                 return cdclk * 2 / 3; /* 384MHz */
6738         case BXT_CDCLK_CD2X_DIV_SEL_2:
6739                 return cdclk / 2; /* 288MHz */
6740         case BXT_CDCLK_CD2X_DIV_SEL_4:
6741                 return cdclk / 4; /* 144MHz */
6742         }
6743
6744         /* error case, do as if DE PLL isn't enabled */
6745         return 19200;
6746 }
6747
6748 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6749 {
6750         struct drm_i915_private *dev_priv = dev->dev_private;
6751         uint32_t lcpll = I915_READ(LCPLL_CTL);
6752         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6753
6754         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6755                 return 800000;
6756         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6757                 return 450000;
6758         else if (freq == LCPLL_CLK_FREQ_450)
6759                 return 450000;
6760         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6761                 return 540000;
6762         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6763                 return 337500;
6764         else
6765                 return 675000;
6766 }
6767
6768 static int haswell_get_display_clock_speed(struct drm_device *dev)
6769 {
6770         struct drm_i915_private *dev_priv = dev->dev_private;
6771         uint32_t lcpll = I915_READ(LCPLL_CTL);
6772         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6773
6774         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6775                 return 800000;
6776         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6777                 return 450000;
6778         else if (freq == LCPLL_CLK_FREQ_450)
6779                 return 450000;
6780         else if (IS_HSW_ULT(dev))
6781                 return 337500;
6782         else
6783                 return 540000;
6784 }
6785
6786 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6787 {
6788         struct drm_i915_private *dev_priv = dev->dev_private;
6789         u32 val;
6790         int divider;
6791
6792         if (dev_priv->hpll_freq == 0)
6793                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6794
6795         mutex_lock(&dev_priv->sb_lock);
6796         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6797         mutex_unlock(&dev_priv->sb_lock);
6798
6799         divider = val & DISPLAY_FREQUENCY_VALUES;
6800
6801         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6802              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6803              "cdclk change in progress\n");
6804
6805         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6806 }
6807
6808 static int ilk_get_display_clock_speed(struct drm_device *dev)
6809 {
6810         return 450000;
6811 }
6812
6813 static int i945_get_display_clock_speed(struct drm_device *dev)
6814 {
6815         return 400000;
6816 }
6817
6818 static int i915_get_display_clock_speed(struct drm_device *dev)
6819 {
6820         return 333333;
6821 }
6822
6823 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6824 {
6825         return 200000;
6826 }
6827
6828 static int pnv_get_display_clock_speed(struct drm_device *dev)
6829 {
6830         u16 gcfgc = 0;
6831
6832         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6833
6834         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6835         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6836                 return 266667;
6837         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6838                 return 333333;
6839         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6840                 return 444444;
6841         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6842                 return 200000;
6843         default:
6844                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6845         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6846                 return 133333;
6847         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6848                 return 166667;
6849         }
6850 }
6851
6852 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6853 {
6854         u16 gcfgc = 0;
6855
6856         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6857
6858         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6859                 return 133333;
6860         else {
6861                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6862                 case GC_DISPLAY_CLOCK_333_MHZ:
6863                         return 333333;
6864                 default:
6865                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6866                         return 190000;
6867                 }
6868         }
6869 }
6870
6871 static int i865_get_display_clock_speed(struct drm_device *dev)
6872 {
6873         return 266667;
6874 }
6875
6876 static int i85x_get_display_clock_speed(struct drm_device *dev)
6877 {
6878         u16 hpllcc = 0;
6879
6880         /*
6881          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6882          * encoding is different :(
6883          * FIXME is this the right way to detect 852GM/852GMV?
6884          */
6885         if (dev->pdev->revision == 0x1)
6886                 return 133333;
6887
6888         pci_bus_read_config_word(dev->pdev->bus,
6889                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6890
6891         /* Assume that the hardware is in the high speed state.  This
6892          * should be the default.
6893          */
6894         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6895         case GC_CLOCK_133_200:
6896         case GC_CLOCK_133_200_2:
6897         case GC_CLOCK_100_200:
6898                 return 200000;
6899         case GC_CLOCK_166_250:
6900                 return 250000;
6901         case GC_CLOCK_100_133:
6902                 return 133333;
6903         case GC_CLOCK_133_266:
6904         case GC_CLOCK_133_266_2:
6905         case GC_CLOCK_166_266:
6906                 return 266667;
6907         }
6908
6909         /* Shouldn't happen */
6910         return 0;
6911 }
6912
6913 static int i830_get_display_clock_speed(struct drm_device *dev)
6914 {
6915         return 133333;
6916 }
6917
6918 static unsigned int intel_hpll_vco(struct drm_device *dev)
6919 {
6920         struct drm_i915_private *dev_priv = dev->dev_private;
6921         static const unsigned int blb_vco[8] = {
6922                 [0] = 3200000,
6923                 [1] = 4000000,
6924                 [2] = 5333333,
6925                 [3] = 4800000,
6926                 [4] = 6400000,
6927         };
6928         static const unsigned int pnv_vco[8] = {
6929                 [0] = 3200000,
6930                 [1] = 4000000,
6931                 [2] = 5333333,
6932                 [3] = 4800000,
6933                 [4] = 2666667,
6934         };
6935         static const unsigned int cl_vco[8] = {
6936                 [0] = 3200000,
6937                 [1] = 4000000,
6938                 [2] = 5333333,
6939                 [3] = 6400000,
6940                 [4] = 3333333,
6941                 [5] = 3566667,
6942                 [6] = 4266667,
6943         };
6944         static const unsigned int elk_vco[8] = {
6945                 [0] = 3200000,
6946                 [1] = 4000000,
6947                 [2] = 5333333,
6948                 [3] = 4800000,
6949         };
6950         static const unsigned int ctg_vco[8] = {
6951                 [0] = 3200000,
6952                 [1] = 4000000,
6953                 [2] = 5333333,
6954                 [3] = 6400000,
6955                 [4] = 2666667,
6956                 [5] = 4266667,
6957         };
6958         const unsigned int *vco_table;
6959         unsigned int vco;
6960         uint8_t tmp = 0;
6961
6962         /* FIXME other chipsets? */
6963         if (IS_GM45(dev))
6964                 vco_table = ctg_vco;
6965         else if (IS_G4X(dev))
6966                 vco_table = elk_vco;
6967         else if (IS_CRESTLINE(dev))
6968                 vco_table = cl_vco;
6969         else if (IS_PINEVIEW(dev))
6970                 vco_table = pnv_vco;
6971         else if (IS_G33(dev))
6972                 vco_table = blb_vco;
6973         else
6974                 return 0;
6975
6976         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6977
6978         vco = vco_table[tmp & 0x7];
6979         if (vco == 0)
6980                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6981         else
6982                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6983
6984         return vco;
6985 }
6986
6987 static int gm45_get_display_clock_speed(struct drm_device *dev)
6988 {
6989         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6990         uint16_t tmp = 0;
6991
6992         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6993
6994         cdclk_sel = (tmp >> 12) & 0x1;
6995
6996         switch (vco) {
6997         case 2666667:
6998         case 4000000:
6999         case 5333333:
7000                 return cdclk_sel ? 333333 : 222222;
7001         case 3200000:
7002                 return cdclk_sel ? 320000 : 228571;
7003         default:
7004                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7005                 return 222222;
7006         }
7007 }
7008
7009 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7010 {
7011         static const uint8_t div_3200[] = { 16, 10,  8 };
7012         static const uint8_t div_4000[] = { 20, 12, 10 };
7013         static const uint8_t div_5333[] = { 24, 16, 14 };
7014         const uint8_t *div_table;
7015         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7016         uint16_t tmp = 0;
7017
7018         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7019
7020         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7021
7022         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7023                 goto fail;
7024
7025         switch (vco) {
7026         case 3200000:
7027                 div_table = div_3200;
7028                 break;
7029         case 4000000:
7030                 div_table = div_4000;
7031                 break;
7032         case 5333333:
7033                 div_table = div_5333;
7034                 break;
7035         default:
7036                 goto fail;
7037         }
7038
7039         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7040
7041 fail:
7042         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7043         return 200000;
7044 }
7045
7046 static int g33_get_display_clock_speed(struct drm_device *dev)
7047 {
7048         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7049         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7050         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7051         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7052         const uint8_t *div_table;
7053         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7054         uint16_t tmp = 0;
7055
7056         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7057
7058         cdclk_sel = (tmp >> 4) & 0x7;
7059
7060         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7061                 goto fail;
7062
7063         switch (vco) {
7064         case 3200000:
7065                 div_table = div_3200;
7066                 break;
7067         case 4000000:
7068                 div_table = div_4000;
7069                 break;
7070         case 4800000:
7071                 div_table = div_4800;
7072                 break;
7073         case 5333333:
7074                 div_table = div_5333;
7075                 break;
7076         default:
7077                 goto fail;
7078         }
7079
7080         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7081
7082 fail:
7083         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7084         return 190476;
7085 }
7086
7087 static void
7088 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7089 {
7090         while (*num > DATA_LINK_M_N_MASK ||
7091                *den > DATA_LINK_M_N_MASK) {
7092                 *num >>= 1;
7093                 *den >>= 1;
7094         }
7095 }
7096
7097 static void compute_m_n(unsigned int m, unsigned int n,
7098                         uint32_t *ret_m, uint32_t *ret_n)
7099 {
7100         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7101         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7102         intel_reduce_m_n_ratio(ret_m, ret_n);
7103 }
7104
7105 void
7106 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7107                        int pixel_clock, int link_clock,
7108                        struct intel_link_m_n *m_n)
7109 {
7110         m_n->tu = 64;
7111
7112         compute_m_n(bits_per_pixel * pixel_clock,
7113                     link_clock * nlanes * 8,
7114                     &m_n->gmch_m, &m_n->gmch_n);
7115
7116         compute_m_n(pixel_clock, link_clock,
7117                     &m_n->link_m, &m_n->link_n);
7118 }
7119
7120 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7121 {
7122         if (i915.panel_use_ssc >= 0)
7123                 return i915.panel_use_ssc != 0;
7124         return dev_priv->vbt.lvds_use_ssc
7125                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7126 }
7127
7128 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7129                            int num_connectors)
7130 {
7131         struct drm_device *dev = crtc_state->base.crtc->dev;
7132         struct drm_i915_private *dev_priv = dev->dev_private;
7133         int refclk;
7134
7135         WARN_ON(!crtc_state->base.state);
7136
7137         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7138                 refclk = 100000;
7139         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7140             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7141                 refclk = dev_priv->vbt.lvds_ssc_freq;
7142                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7143         } else if (!IS_GEN2(dev)) {
7144                 refclk = 96000;
7145         } else {
7146                 refclk = 48000;
7147         }
7148
7149         return refclk;
7150 }
7151
7152 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7153 {
7154         return (1 << dpll->n) << 16 | dpll->m2;
7155 }
7156
7157 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7158 {
7159         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7160 }
7161
7162 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7163                                      struct intel_crtc_state *crtc_state,
7164                                      intel_clock_t *reduced_clock)
7165 {
7166         struct drm_device *dev = crtc->base.dev;
7167         u32 fp, fp2 = 0;
7168
7169         if (IS_PINEVIEW(dev)) {
7170                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7171                 if (reduced_clock)
7172                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7173         } else {
7174                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7175                 if (reduced_clock)
7176                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7177         }
7178
7179         crtc_state->dpll_hw_state.fp0 = fp;
7180
7181         crtc->lowfreq_avail = false;
7182         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7183             reduced_clock) {
7184                 crtc_state->dpll_hw_state.fp1 = fp2;
7185                 crtc->lowfreq_avail = true;
7186         } else {
7187                 crtc_state->dpll_hw_state.fp1 = fp;
7188         }
7189 }
7190
7191 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7192                 pipe)
7193 {
7194         u32 reg_val;
7195
7196         /*
7197          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7198          * and set it to a reasonable value instead.
7199          */
7200         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7201         reg_val &= 0xffffff00;
7202         reg_val |= 0x00000030;
7203         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7204
7205         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7206         reg_val &= 0x8cffffff;
7207         reg_val = 0x8c000000;
7208         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7209
7210         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7211         reg_val &= 0xffffff00;
7212         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7213
7214         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7215         reg_val &= 0x00ffffff;
7216         reg_val |= 0xb0000000;
7217         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7218 }
7219
7220 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7221                                          struct intel_link_m_n *m_n)
7222 {
7223         struct drm_device *dev = crtc->base.dev;
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         int pipe = crtc->pipe;
7226
7227         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7228         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7229         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7230         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7231 }
7232
7233 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7234                                          struct intel_link_m_n *m_n,
7235                                          struct intel_link_m_n *m2_n2)
7236 {
7237         struct drm_device *dev = crtc->base.dev;
7238         struct drm_i915_private *dev_priv = dev->dev_private;
7239         int pipe = crtc->pipe;
7240         enum transcoder transcoder = crtc->config->cpu_transcoder;
7241
7242         if (INTEL_INFO(dev)->gen >= 5) {
7243                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7244                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7245                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7246                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7247                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7248                  * for gen < 8) and if DRRS is supported (to make sure the
7249                  * registers are not unnecessarily accessed).
7250                  */
7251                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7252                         crtc->config->has_drrs) {
7253                         I915_WRITE(PIPE_DATA_M2(transcoder),
7254                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7255                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7256                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7257                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7258                 }
7259         } else {
7260                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7261                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7262                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7263                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7264         }
7265 }
7266
7267 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7268 {
7269         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7270
7271         if (m_n == M1_N1) {
7272                 dp_m_n = &crtc->config->dp_m_n;
7273                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7274         } else if (m_n == M2_N2) {
7275
7276                 /*
7277                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7278                  * needs to be programmed into M1_N1.
7279                  */
7280                 dp_m_n = &crtc->config->dp_m2_n2;
7281         } else {
7282                 DRM_ERROR("Unsupported divider value\n");
7283                 return;
7284         }
7285
7286         if (crtc->config->has_pch_encoder)
7287                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7288         else
7289                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7290 }
7291
7292 static void vlv_compute_dpll(struct intel_crtc *crtc,
7293                              struct intel_crtc_state *pipe_config)
7294 {
7295         u32 dpll, dpll_md;
7296
7297         /*
7298          * Enable DPIO clock input. We should never disable the reference
7299          * clock for pipe B, since VGA hotplug / manual detection depends
7300          * on it.
7301          */
7302         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7303                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7304         /* We should never disable this, set it here for state tracking */
7305         if (crtc->pipe == PIPE_B)
7306                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7307         dpll |= DPLL_VCO_ENABLE;
7308         pipe_config->dpll_hw_state.dpll = dpll;
7309
7310         dpll_md = (pipe_config->pixel_multiplier - 1)
7311                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7312         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7313 }
7314
7315 static void vlv_prepare_pll(struct intel_crtc *crtc,
7316                             const struct intel_crtc_state *pipe_config)
7317 {
7318         struct drm_device *dev = crtc->base.dev;
7319         struct drm_i915_private *dev_priv = dev->dev_private;
7320         int pipe = crtc->pipe;
7321         u32 mdiv;
7322         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7323         u32 coreclk, reg_val;
7324
7325         mutex_lock(&dev_priv->sb_lock);
7326
7327         bestn = pipe_config->dpll.n;
7328         bestm1 = pipe_config->dpll.m1;
7329         bestm2 = pipe_config->dpll.m2;
7330         bestp1 = pipe_config->dpll.p1;
7331         bestp2 = pipe_config->dpll.p2;
7332
7333         /* See eDP HDMI DPIO driver vbios notes doc */
7334
7335         /* PLL B needs special handling */
7336         if (pipe == PIPE_B)
7337                 vlv_pllb_recal_opamp(dev_priv, pipe);
7338
7339         /* Set up Tx target for periodic Rcomp update */
7340         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7341
7342         /* Disable target IRef on PLL */
7343         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7344         reg_val &= 0x00ffffff;
7345         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7346
7347         /* Disable fast lock */
7348         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7349
7350         /* Set idtafcrecal before PLL is enabled */
7351         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7352         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7353         mdiv |= ((bestn << DPIO_N_SHIFT));
7354         mdiv |= (1 << DPIO_K_SHIFT);
7355
7356         /*
7357          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7358          * but we don't support that).
7359          * Note: don't use the DAC post divider as it seems unstable.
7360          */
7361         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7362         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7363
7364         mdiv |= DPIO_ENABLE_CALIBRATION;
7365         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7366
7367         /* Set HBR and RBR LPF coefficients */
7368         if (pipe_config->port_clock == 162000 ||
7369             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7370             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7371                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7372                                  0x009f0003);
7373         else
7374                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7375                                  0x00d0000f);
7376
7377         if (pipe_config->has_dp_encoder) {
7378                 /* Use SSC source */
7379                 if (pipe == PIPE_A)
7380                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7381                                          0x0df40000);
7382                 else
7383                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7384                                          0x0df70000);
7385         } else { /* HDMI or VGA */
7386                 /* Use bend source */
7387                 if (pipe == PIPE_A)
7388                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7389                                          0x0df70000);
7390                 else
7391                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392                                          0x0df40000);
7393         }
7394
7395         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7396         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7397         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7398             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7399                 coreclk |= 0x01000000;
7400         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7401
7402         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7403         mutex_unlock(&dev_priv->sb_lock);
7404 }
7405
7406 static void chv_compute_dpll(struct intel_crtc *crtc,
7407                              struct intel_crtc_state *pipe_config)
7408 {
7409         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7410                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7411                 DPLL_VCO_ENABLE;
7412         if (crtc->pipe != PIPE_A)
7413                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7414
7415         pipe_config->dpll_hw_state.dpll_md =
7416                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7417 }
7418
7419 static void chv_prepare_pll(struct intel_crtc *crtc,
7420                             const struct intel_crtc_state *pipe_config)
7421 {
7422         struct drm_device *dev = crtc->base.dev;
7423         struct drm_i915_private *dev_priv = dev->dev_private;
7424         int pipe = crtc->pipe;
7425         int dpll_reg = DPLL(crtc->pipe);
7426         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7427         u32 loopfilter, tribuf_calcntr;
7428         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7429         u32 dpio_val;
7430         int vco;
7431
7432         bestn = pipe_config->dpll.n;
7433         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7434         bestm1 = pipe_config->dpll.m1;
7435         bestm2 = pipe_config->dpll.m2 >> 22;
7436         bestp1 = pipe_config->dpll.p1;
7437         bestp2 = pipe_config->dpll.p2;
7438         vco = pipe_config->dpll.vco;
7439         dpio_val = 0;
7440         loopfilter = 0;
7441
7442         /*
7443          * Enable Refclk and SSC
7444          */
7445         I915_WRITE(dpll_reg,
7446                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7447
7448         mutex_lock(&dev_priv->sb_lock);
7449
7450         /* p1 and p2 divider */
7451         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7452                         5 << DPIO_CHV_S1_DIV_SHIFT |
7453                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7454                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7455                         1 << DPIO_CHV_K_DIV_SHIFT);
7456
7457         /* Feedback post-divider - m2 */
7458         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7459
7460         /* Feedback refclk divider - n and m1 */
7461         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7462                         DPIO_CHV_M1_DIV_BY_2 |
7463                         1 << DPIO_CHV_N_DIV_SHIFT);
7464
7465         /* M2 fraction division */
7466         if (bestm2_frac)
7467                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7468
7469         /* M2 fraction division enable */
7470         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7471         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7472         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7473         if (bestm2_frac)
7474                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7475         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7476
7477         /* Program digital lock detect threshold */
7478         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7479         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7480                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7481         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7482         if (!bestm2_frac)
7483                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7484         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7485
7486         /* Loop filter */
7487         if (vco == 5400000) {
7488                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7489                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7490                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7491                 tribuf_calcntr = 0x9;
7492         } else if (vco <= 6200000) {
7493                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7494                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7495                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7496                 tribuf_calcntr = 0x9;
7497         } else if (vco <= 6480000) {
7498                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7499                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7500                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501                 tribuf_calcntr = 0x8;
7502         } else {
7503                 /* Not supported. Apply the same limits as in the max case */
7504                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7505                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7506                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7507                 tribuf_calcntr = 0;
7508         }
7509         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7510
7511         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7512         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7513         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7514         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7515
7516         /* AFC Recal */
7517         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7518                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7519                         DPIO_AFC_RECAL);
7520
7521         mutex_unlock(&dev_priv->sb_lock);
7522 }
7523
7524 /**
7525  * vlv_force_pll_on - forcibly enable just the PLL
7526  * @dev_priv: i915 private structure
7527  * @pipe: pipe PLL to enable
7528  * @dpll: PLL configuration
7529  *
7530  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7531  * in cases where we need the PLL enabled even when @pipe is not going to
7532  * be enabled.
7533  */
7534 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7535                       const struct dpll *dpll)
7536 {
7537         struct intel_crtc *crtc =
7538                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7539         struct intel_crtc_state pipe_config = {
7540                 .base.crtc = &crtc->base,
7541                 .pixel_multiplier = 1,
7542                 .dpll = *dpll,
7543         };
7544
7545         if (IS_CHERRYVIEW(dev)) {
7546                 chv_compute_dpll(crtc, &pipe_config);
7547                 chv_prepare_pll(crtc, &pipe_config);
7548                 chv_enable_pll(crtc, &pipe_config);
7549         } else {
7550                 vlv_compute_dpll(crtc, &pipe_config);
7551                 vlv_prepare_pll(crtc, &pipe_config);
7552                 vlv_enable_pll(crtc, &pipe_config);
7553         }
7554 }
7555
7556 /**
7557  * vlv_force_pll_off - forcibly disable just the PLL
7558  * @dev_priv: i915 private structure
7559  * @pipe: pipe PLL to disable
7560  *
7561  * Disable the PLL for @pipe. To be used in cases where we need
7562  * the PLL enabled even when @pipe is not going to be enabled.
7563  */
7564 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7565 {
7566         if (IS_CHERRYVIEW(dev))
7567                 chv_disable_pll(to_i915(dev), pipe);
7568         else
7569                 vlv_disable_pll(to_i915(dev), pipe);
7570 }
7571
7572 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7573                               struct intel_crtc_state *crtc_state,
7574                               intel_clock_t *reduced_clock,
7575                               int num_connectors)
7576 {
7577         struct drm_device *dev = crtc->base.dev;
7578         struct drm_i915_private *dev_priv = dev->dev_private;
7579         u32 dpll;
7580         bool is_sdvo;
7581         struct dpll *clock = &crtc_state->dpll;
7582
7583         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7584
7585         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7586                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7587
7588         dpll = DPLL_VGA_MODE_DIS;
7589
7590         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7591                 dpll |= DPLLB_MODE_LVDS;
7592         else
7593                 dpll |= DPLLB_MODE_DAC_SERIAL;
7594
7595         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7596                 dpll |= (crtc_state->pixel_multiplier - 1)
7597                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7598         }
7599
7600         if (is_sdvo)
7601                 dpll |= DPLL_SDVO_HIGH_SPEED;
7602
7603         if (crtc_state->has_dp_encoder)
7604                 dpll |= DPLL_SDVO_HIGH_SPEED;
7605
7606         /* compute bitmask from p1 value */
7607         if (IS_PINEVIEW(dev))
7608                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7609         else {
7610                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611                 if (IS_G4X(dev) && reduced_clock)
7612                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7613         }
7614         switch (clock->p2) {
7615         case 5:
7616                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7617                 break;
7618         case 7:
7619                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7620                 break;
7621         case 10:
7622                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7623                 break;
7624         case 14:
7625                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7626                 break;
7627         }
7628         if (INTEL_INFO(dev)->gen >= 4)
7629                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7630
7631         if (crtc_state->sdvo_tv_clock)
7632                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7633         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7634                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7635                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7636         else
7637                 dpll |= PLL_REF_INPUT_DREFCLK;
7638
7639         dpll |= DPLL_VCO_ENABLE;
7640         crtc_state->dpll_hw_state.dpll = dpll;
7641
7642         if (INTEL_INFO(dev)->gen >= 4) {
7643                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7644                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7645                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7646         }
7647 }
7648
7649 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7650                               struct intel_crtc_state *crtc_state,
7651                               intel_clock_t *reduced_clock,
7652                               int num_connectors)
7653 {
7654         struct drm_device *dev = crtc->base.dev;
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656         u32 dpll;
7657         struct dpll *clock = &crtc_state->dpll;
7658
7659         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7660
7661         dpll = DPLL_VGA_MODE_DIS;
7662
7663         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7664                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7665         } else {
7666                 if (clock->p1 == 2)
7667                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7668                 else
7669                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7670                 if (clock->p2 == 4)
7671                         dpll |= PLL_P2_DIVIDE_BY_4;
7672         }
7673
7674         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7675                 dpll |= DPLL_DVO_2X_MODE;
7676
7677         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7678                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7679                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7680         else
7681                 dpll |= PLL_REF_INPUT_DREFCLK;
7682
7683         dpll |= DPLL_VCO_ENABLE;
7684         crtc_state->dpll_hw_state.dpll = dpll;
7685 }
7686
7687 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7688 {
7689         struct drm_device *dev = intel_crtc->base.dev;
7690         struct drm_i915_private *dev_priv = dev->dev_private;
7691         enum pipe pipe = intel_crtc->pipe;
7692         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7693         struct drm_display_mode *adjusted_mode =
7694                 &intel_crtc->config->base.adjusted_mode;
7695         uint32_t crtc_vtotal, crtc_vblank_end;
7696         int vsyncshift = 0;
7697
7698         /* We need to be careful not to changed the adjusted mode, for otherwise
7699          * the hw state checker will get angry at the mismatch. */
7700         crtc_vtotal = adjusted_mode->crtc_vtotal;
7701         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7702
7703         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7704                 /* the chip adds 2 halflines automatically */
7705                 crtc_vtotal -= 1;
7706                 crtc_vblank_end -= 1;
7707
7708                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7709                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7710                 else
7711                         vsyncshift = adjusted_mode->crtc_hsync_start -
7712                                 adjusted_mode->crtc_htotal / 2;
7713                 if (vsyncshift < 0)
7714                         vsyncshift += adjusted_mode->crtc_htotal;
7715         }
7716
7717         if (INTEL_INFO(dev)->gen > 3)
7718                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7719
7720         I915_WRITE(HTOTAL(cpu_transcoder),
7721                    (adjusted_mode->crtc_hdisplay - 1) |
7722                    ((adjusted_mode->crtc_htotal - 1) << 16));
7723         I915_WRITE(HBLANK(cpu_transcoder),
7724                    (adjusted_mode->crtc_hblank_start - 1) |
7725                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7726         I915_WRITE(HSYNC(cpu_transcoder),
7727                    (adjusted_mode->crtc_hsync_start - 1) |
7728                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7729
7730         I915_WRITE(VTOTAL(cpu_transcoder),
7731                    (adjusted_mode->crtc_vdisplay - 1) |
7732                    ((crtc_vtotal - 1) << 16));
7733         I915_WRITE(VBLANK(cpu_transcoder),
7734                    (adjusted_mode->crtc_vblank_start - 1) |
7735                    ((crtc_vblank_end - 1) << 16));
7736         I915_WRITE(VSYNC(cpu_transcoder),
7737                    (adjusted_mode->crtc_vsync_start - 1) |
7738                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7739
7740         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7741          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7742          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7743          * bits. */
7744         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7745             (pipe == PIPE_B || pipe == PIPE_C))
7746                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7747
7748         /* pipesrc controls the size that is scaled from, which should
7749          * always be the user's requested size.
7750          */
7751         I915_WRITE(PIPESRC(pipe),
7752                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7753                    (intel_crtc->config->pipe_src_h - 1));
7754 }
7755
7756 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7757                                    struct intel_crtc_state *pipe_config)
7758 {
7759         struct drm_device *dev = crtc->base.dev;
7760         struct drm_i915_private *dev_priv = dev->dev_private;
7761         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7762         uint32_t tmp;
7763
7764         tmp = I915_READ(HTOTAL(cpu_transcoder));
7765         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7766         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7767         tmp = I915_READ(HBLANK(cpu_transcoder));
7768         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7769         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7770         tmp = I915_READ(HSYNC(cpu_transcoder));
7771         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7772         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7773
7774         tmp = I915_READ(VTOTAL(cpu_transcoder));
7775         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7776         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7777         tmp = I915_READ(VBLANK(cpu_transcoder));
7778         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7779         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7780         tmp = I915_READ(VSYNC(cpu_transcoder));
7781         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7782         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7783
7784         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7785                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7786                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7787                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7788         }
7789
7790         tmp = I915_READ(PIPESRC(crtc->pipe));
7791         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7792         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7793
7794         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7795         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7796 }
7797
7798 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7799                                  struct intel_crtc_state *pipe_config)
7800 {
7801         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7802         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7803         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7804         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7805
7806         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7807         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7808         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7809         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7810
7811         mode->flags = pipe_config->base.adjusted_mode.flags;
7812         mode->type = DRM_MODE_TYPE_DRIVER;
7813
7814         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7815         mode->flags |= pipe_config->base.adjusted_mode.flags;
7816
7817         mode->hsync = drm_mode_hsync(mode);
7818         mode->vrefresh = drm_mode_vrefresh(mode);
7819         drm_mode_set_name(mode);
7820 }
7821
7822 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7823 {
7824         struct drm_device *dev = intel_crtc->base.dev;
7825         struct drm_i915_private *dev_priv = dev->dev_private;
7826         uint32_t pipeconf;
7827
7828         pipeconf = 0;
7829
7830         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7831             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7832                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7833
7834         if (intel_crtc->config->double_wide)
7835                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7836
7837         /* only g4x and later have fancy bpc/dither controls */
7838         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7839                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7840                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7841                         pipeconf |= PIPECONF_DITHER_EN |
7842                                     PIPECONF_DITHER_TYPE_SP;
7843
7844                 switch (intel_crtc->config->pipe_bpp) {
7845                 case 18:
7846                         pipeconf |= PIPECONF_6BPC;
7847                         break;
7848                 case 24:
7849                         pipeconf |= PIPECONF_8BPC;
7850                         break;
7851                 case 30:
7852                         pipeconf |= PIPECONF_10BPC;
7853                         break;
7854                 default:
7855                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7856                         BUG();
7857                 }
7858         }
7859
7860         if (HAS_PIPE_CXSR(dev)) {
7861                 if (intel_crtc->lowfreq_avail) {
7862                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7863                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7864                 } else {
7865                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7866                 }
7867         }
7868
7869         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7870                 if (INTEL_INFO(dev)->gen < 4 ||
7871                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7872                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7873                 else
7874                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7875         } else
7876                 pipeconf |= PIPECONF_PROGRESSIVE;
7877
7878         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7879                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7880
7881         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7882         POSTING_READ(PIPECONF(intel_crtc->pipe));
7883 }
7884
7885 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7886                                    struct intel_crtc_state *crtc_state)
7887 {
7888         struct drm_device *dev = crtc->base.dev;
7889         struct drm_i915_private *dev_priv = dev->dev_private;
7890         int refclk, num_connectors = 0;
7891         intel_clock_t clock;
7892         bool ok;
7893         bool is_dsi = false;
7894         struct intel_encoder *encoder;
7895         const intel_limit_t *limit;
7896         struct drm_atomic_state *state = crtc_state->base.state;
7897         struct drm_connector *connector;
7898         struct drm_connector_state *connector_state;
7899         int i;
7900
7901         memset(&crtc_state->dpll_hw_state, 0,
7902                sizeof(crtc_state->dpll_hw_state));
7903
7904         for_each_connector_in_state(state, connector, connector_state, i) {
7905                 if (connector_state->crtc != &crtc->base)
7906                         continue;
7907
7908                 encoder = to_intel_encoder(connector_state->best_encoder);
7909
7910                 switch (encoder->type) {
7911                 case INTEL_OUTPUT_DSI:
7912                         is_dsi = true;
7913                         break;
7914                 default:
7915                         break;
7916                 }
7917
7918                 num_connectors++;
7919         }
7920
7921         if (is_dsi)
7922                 return 0;
7923
7924         if (!crtc_state->clock_set) {
7925                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7926
7927                 /*
7928                  * Returns a set of divisors for the desired target clock with
7929                  * the given refclk, or FALSE.  The returned values represent
7930                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7931                  * 2) / p1 / p2.
7932                  */
7933                 limit = intel_limit(crtc_state, refclk);
7934                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7935                                                  crtc_state->port_clock,
7936                                                  refclk, NULL, &clock);
7937                 if (!ok) {
7938                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939                         return -EINVAL;
7940                 }
7941
7942                 /* Compat-code for transition, will disappear. */
7943                 crtc_state->dpll.n = clock.n;
7944                 crtc_state->dpll.m1 = clock.m1;
7945                 crtc_state->dpll.m2 = clock.m2;
7946                 crtc_state->dpll.p1 = clock.p1;
7947                 crtc_state->dpll.p2 = clock.p2;
7948         }
7949
7950         if (IS_GEN2(dev)) {
7951                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7952                                   num_connectors);
7953         } else if (IS_CHERRYVIEW(dev)) {
7954                 chv_compute_dpll(crtc, crtc_state);
7955         } else if (IS_VALLEYVIEW(dev)) {
7956                 vlv_compute_dpll(crtc, crtc_state);
7957         } else {
7958                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7959                                   num_connectors);
7960         }
7961
7962         return 0;
7963 }
7964
7965 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7966                                  struct intel_crtc_state *pipe_config)
7967 {
7968         struct drm_device *dev = crtc->base.dev;
7969         struct drm_i915_private *dev_priv = dev->dev_private;
7970         uint32_t tmp;
7971
7972         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7973                 return;
7974
7975         tmp = I915_READ(PFIT_CONTROL);
7976         if (!(tmp & PFIT_ENABLE))
7977                 return;
7978
7979         /* Check whether the pfit is attached to our pipe. */
7980         if (INTEL_INFO(dev)->gen < 4) {
7981                 if (crtc->pipe != PIPE_B)
7982                         return;
7983         } else {
7984                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7985                         return;
7986         }
7987
7988         pipe_config->gmch_pfit.control = tmp;
7989         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7990         if (INTEL_INFO(dev)->gen < 5)
7991                 pipe_config->gmch_pfit.lvds_border_bits =
7992                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7993 }
7994
7995 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7996                                struct intel_crtc_state *pipe_config)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         int pipe = pipe_config->cpu_transcoder;
8001         intel_clock_t clock;
8002         u32 mdiv;
8003         int refclk = 100000;
8004
8005         /* In case of MIPI DPLL will not even be used */
8006         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8007                 return;
8008
8009         mutex_lock(&dev_priv->sb_lock);
8010         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8011         mutex_unlock(&dev_priv->sb_lock);
8012
8013         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8014         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8015         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8016         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8017         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8018
8019         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8020 }
8021
8022 static void
8023 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024                               struct intel_initial_plane_config *plane_config)
8025 {
8026         struct drm_device *dev = crtc->base.dev;
8027         struct drm_i915_private *dev_priv = dev->dev_private;
8028         u32 val, base, offset;
8029         int pipe = crtc->pipe, plane = crtc->plane;
8030         int fourcc, pixel_format;
8031         unsigned int aligned_height;
8032         struct drm_framebuffer *fb;
8033         struct intel_framebuffer *intel_fb;
8034
8035         val = I915_READ(DSPCNTR(plane));
8036         if (!(val & DISPLAY_PLANE_ENABLE))
8037                 return;
8038
8039         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8040         if (!intel_fb) {
8041                 DRM_DEBUG_KMS("failed to alloc fb\n");
8042                 return;
8043         }
8044
8045         fb = &intel_fb->base;
8046
8047         if (INTEL_INFO(dev)->gen >= 4) {
8048                 if (val & DISPPLANE_TILED) {
8049                         plane_config->tiling = I915_TILING_X;
8050                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8051                 }
8052         }
8053
8054         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8055         fourcc = i9xx_format_to_fourcc(pixel_format);
8056         fb->pixel_format = fourcc;
8057         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8058
8059         if (INTEL_INFO(dev)->gen >= 4) {
8060                 if (plane_config->tiling)
8061                         offset = I915_READ(DSPTILEOFF(plane));
8062                 else
8063                         offset = I915_READ(DSPLINOFF(plane));
8064                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8065         } else {
8066                 base = I915_READ(DSPADDR(plane));
8067         }
8068         plane_config->base = base;
8069
8070         val = I915_READ(PIPESRC(pipe));
8071         fb->width = ((val >> 16) & 0xfff) + 1;
8072         fb->height = ((val >> 0) & 0xfff) + 1;
8073
8074         val = I915_READ(DSPSTRIDE(pipe));
8075         fb->pitches[0] = val & 0xffffffc0;
8076
8077         aligned_height = intel_fb_align_height(dev, fb->height,
8078                                                fb->pixel_format,
8079                                                fb->modifier[0]);
8080
8081         plane_config->size = fb->pitches[0] * aligned_height;
8082
8083         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084                       pipe_name(pipe), plane, fb->width, fb->height,
8085                       fb->bits_per_pixel, base, fb->pitches[0],
8086                       plane_config->size);
8087
8088         plane_config->fb = intel_fb;
8089 }
8090
8091 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8092                                struct intel_crtc_state *pipe_config)
8093 {
8094         struct drm_device *dev = crtc->base.dev;
8095         struct drm_i915_private *dev_priv = dev->dev_private;
8096         int pipe = pipe_config->cpu_transcoder;
8097         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098         intel_clock_t clock;
8099         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8100         int refclk = 100000;
8101
8102         mutex_lock(&dev_priv->sb_lock);
8103         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8104         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8105         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8106         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8107         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8108         mutex_unlock(&dev_priv->sb_lock);
8109
8110         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8111         clock.m2 = (pll_dw0 & 0xff) << 22;
8112         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8113                 clock.m2 |= pll_dw2 & 0x3fffff;
8114         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8115         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8116         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8117
8118         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8119 }
8120
8121 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8122                                  struct intel_crtc_state *pipe_config)
8123 {
8124         struct drm_device *dev = crtc->base.dev;
8125         struct drm_i915_private *dev_priv = dev->dev_private;
8126         uint32_t tmp;
8127
8128         if (!intel_display_power_is_enabled(dev_priv,
8129                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8130                 return false;
8131
8132         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8133         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8134
8135         tmp = I915_READ(PIPECONF(crtc->pipe));
8136         if (!(tmp & PIPECONF_ENABLE))
8137                 return false;
8138
8139         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8140                 switch (tmp & PIPECONF_BPC_MASK) {
8141                 case PIPECONF_6BPC:
8142                         pipe_config->pipe_bpp = 18;
8143                         break;
8144                 case PIPECONF_8BPC:
8145                         pipe_config->pipe_bpp = 24;
8146                         break;
8147                 case PIPECONF_10BPC:
8148                         pipe_config->pipe_bpp = 30;
8149                         break;
8150                 default:
8151                         break;
8152                 }
8153         }
8154
8155         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8156                 pipe_config->limited_color_range = true;
8157
8158         if (INTEL_INFO(dev)->gen < 4)
8159                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8160
8161         intel_get_pipe_timings(crtc, pipe_config);
8162
8163         i9xx_get_pfit_config(crtc, pipe_config);
8164
8165         if (INTEL_INFO(dev)->gen >= 4) {
8166                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8167                 pipe_config->pixel_multiplier =
8168                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8169                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8170                 pipe_config->dpll_hw_state.dpll_md = tmp;
8171         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8172                 tmp = I915_READ(DPLL(crtc->pipe));
8173                 pipe_config->pixel_multiplier =
8174                         ((tmp & SDVO_MULTIPLIER_MASK)
8175                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8176         } else {
8177                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8178                  * port and will be fixed up in the encoder->get_config
8179                  * function. */
8180                 pipe_config->pixel_multiplier = 1;
8181         }
8182         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8183         if (!IS_VALLEYVIEW(dev)) {
8184                 /*
8185                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8186                  * on 830. Filter it out here so that we don't
8187                  * report errors due to that.
8188                  */
8189                 if (IS_I830(dev))
8190                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8191
8192                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8193                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8194         } else {
8195                 /* Mask out read-only status bits. */
8196                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8197                                                      DPLL_PORTC_READY_MASK |
8198                                                      DPLL_PORTB_READY_MASK);
8199         }
8200
8201         if (IS_CHERRYVIEW(dev))
8202                 chv_crtc_clock_get(crtc, pipe_config);
8203         else if (IS_VALLEYVIEW(dev))
8204                 vlv_crtc_clock_get(crtc, pipe_config);
8205         else
8206                 i9xx_crtc_clock_get(crtc, pipe_config);
8207
8208         return true;
8209 }
8210
8211 static void ironlake_init_pch_refclk(struct drm_device *dev)
8212 {
8213         struct drm_i915_private *dev_priv = dev->dev_private;
8214         struct intel_encoder *encoder;
8215         u32 val, final;
8216         bool has_lvds = false;
8217         bool has_cpu_edp = false;
8218         bool has_panel = false;
8219         bool has_ck505 = false;
8220         bool can_ssc = false;
8221
8222         /* We need to take the global config into account */
8223         for_each_intel_encoder(dev, encoder) {
8224                 switch (encoder->type) {
8225                 case INTEL_OUTPUT_LVDS:
8226                         has_panel = true;
8227                         has_lvds = true;
8228                         break;
8229                 case INTEL_OUTPUT_EDP:
8230                         has_panel = true;
8231                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8232                                 has_cpu_edp = true;
8233                         break;
8234                 default:
8235                         break;
8236                 }
8237         }
8238
8239         if (HAS_PCH_IBX(dev)) {
8240                 has_ck505 = dev_priv->vbt.display_clock_mode;
8241                 can_ssc = has_ck505;
8242         } else {
8243                 has_ck505 = false;
8244                 can_ssc = true;
8245         }
8246
8247         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8248                       has_panel, has_lvds, has_ck505);
8249
8250         /* Ironlake: try to setup display ref clock before DPLL
8251          * enabling. This is only under driver's control after
8252          * PCH B stepping, previous chipset stepping should be
8253          * ignoring this setting.
8254          */
8255         val = I915_READ(PCH_DREF_CONTROL);
8256
8257         /* As we must carefully and slowly disable/enable each source in turn,
8258          * compute the final state we want first and check if we need to
8259          * make any changes at all.
8260          */
8261         final = val;
8262         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8263         if (has_ck505)
8264                 final |= DREF_NONSPREAD_CK505_ENABLE;
8265         else
8266                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8267
8268         final &= ~DREF_SSC_SOURCE_MASK;
8269         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8270         final &= ~DREF_SSC1_ENABLE;
8271
8272         if (has_panel) {
8273                 final |= DREF_SSC_SOURCE_ENABLE;
8274
8275                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8276                         final |= DREF_SSC1_ENABLE;
8277
8278                 if (has_cpu_edp) {
8279                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8280                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8281                         else
8282                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8283                 } else
8284                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8285         } else {
8286                 final |= DREF_SSC_SOURCE_DISABLE;
8287                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288         }
8289
8290         if (final == val)
8291                 return;
8292
8293         /* Always enable nonspread source */
8294         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8295
8296         if (has_ck505)
8297                 val |= DREF_NONSPREAD_CK505_ENABLE;
8298         else
8299                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8300
8301         if (has_panel) {
8302                 val &= ~DREF_SSC_SOURCE_MASK;
8303                 val |= DREF_SSC_SOURCE_ENABLE;
8304
8305                 /* SSC must be turned on before enabling the CPU output  */
8306                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8307                         DRM_DEBUG_KMS("Using SSC on panel\n");
8308                         val |= DREF_SSC1_ENABLE;
8309                 } else
8310                         val &= ~DREF_SSC1_ENABLE;
8311
8312                 /* Get SSC going before enabling the outputs */
8313                 I915_WRITE(PCH_DREF_CONTROL, val);
8314                 POSTING_READ(PCH_DREF_CONTROL);
8315                 udelay(200);
8316
8317                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8318
8319                 /* Enable CPU source on CPU attached eDP */
8320                 if (has_cpu_edp) {
8321                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8322                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8323                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8324                         } else
8325                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8326                 } else
8327                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328
8329                 I915_WRITE(PCH_DREF_CONTROL, val);
8330                 POSTING_READ(PCH_DREF_CONTROL);
8331                 udelay(200);
8332         } else {
8333                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8334
8335                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8336
8337                 /* Turn off CPU output */
8338                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8339
8340                 I915_WRITE(PCH_DREF_CONTROL, val);
8341                 POSTING_READ(PCH_DREF_CONTROL);
8342                 udelay(200);
8343
8344                 /* Turn off the SSC source */
8345                 val &= ~DREF_SSC_SOURCE_MASK;
8346                 val |= DREF_SSC_SOURCE_DISABLE;
8347
8348                 /* Turn off SSC1 */
8349                 val &= ~DREF_SSC1_ENABLE;
8350
8351                 I915_WRITE(PCH_DREF_CONTROL, val);
8352                 POSTING_READ(PCH_DREF_CONTROL);
8353                 udelay(200);
8354         }
8355
8356         BUG_ON(val != final);
8357 }
8358
8359 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8360 {
8361         uint32_t tmp;
8362
8363         tmp = I915_READ(SOUTH_CHICKEN2);
8364         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8365         I915_WRITE(SOUTH_CHICKEN2, tmp);
8366
8367         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8368                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8369                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8370
8371         tmp = I915_READ(SOUTH_CHICKEN2);
8372         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8373         I915_WRITE(SOUTH_CHICKEN2, tmp);
8374
8375         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8376                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8377                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8378 }
8379
8380 /* WaMPhyProgramming:hsw */
8381 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8382 {
8383         uint32_t tmp;
8384
8385         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8386         tmp &= ~(0xFF << 24);
8387         tmp |= (0x12 << 24);
8388         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8389
8390         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8391         tmp |= (1 << 11);
8392         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8393
8394         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8395         tmp |= (1 << 11);
8396         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8399         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8400         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8403         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8404         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8405
8406         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8407         tmp &= ~(7 << 13);
8408         tmp |= (5 << 13);
8409         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8410
8411         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8412         tmp &= ~(7 << 13);
8413         tmp |= (5 << 13);
8414         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8415
8416         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8417         tmp &= ~0xFF;
8418         tmp |= 0x1C;
8419         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8420
8421         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8422         tmp &= ~0xFF;
8423         tmp |= 0x1C;
8424         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8425
8426         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8427         tmp &= ~(0xFF << 16);
8428         tmp |= (0x1C << 16);
8429         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8430
8431         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8432         tmp &= ~(0xFF << 16);
8433         tmp |= (0x1C << 16);
8434         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8435
8436         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8437         tmp |= (1 << 27);
8438         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8439
8440         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8441         tmp |= (1 << 27);
8442         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8443
8444         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8445         tmp &= ~(0xF << 28);
8446         tmp |= (4 << 28);
8447         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8448
8449         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8450         tmp &= ~(0xF << 28);
8451         tmp |= (4 << 28);
8452         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8453 }
8454
8455 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8456  * Programming" based on the parameters passed:
8457  * - Sequence to enable CLKOUT_DP
8458  * - Sequence to enable CLKOUT_DP without spread
8459  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8460  */
8461 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8462                                  bool with_fdi)
8463 {
8464         struct drm_i915_private *dev_priv = dev->dev_private;
8465         uint32_t reg, tmp;
8466
8467         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8468                 with_spread = true;
8469         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8470                  with_fdi, "LP PCH doesn't have FDI\n"))
8471                 with_fdi = false;
8472
8473         mutex_lock(&dev_priv->sb_lock);
8474
8475         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8476         tmp &= ~SBI_SSCCTL_DISABLE;
8477         tmp |= SBI_SSCCTL_PATHALT;
8478         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8479
8480         udelay(24);
8481
8482         if (with_spread) {
8483                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8484                 tmp &= ~SBI_SSCCTL_PATHALT;
8485                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486
8487                 if (with_fdi) {
8488                         lpt_reset_fdi_mphy(dev_priv);
8489                         lpt_program_fdi_mphy(dev_priv);
8490                 }
8491         }
8492
8493         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8494                SBI_GEN0 : SBI_DBUFF0;
8495         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8496         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8497         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8498
8499         mutex_unlock(&dev_priv->sb_lock);
8500 }
8501
8502 /* Sequence to disable CLKOUT_DP */
8503 static void lpt_disable_clkout_dp(struct drm_device *dev)
8504 {
8505         struct drm_i915_private *dev_priv = dev->dev_private;
8506         uint32_t reg, tmp;
8507
8508         mutex_lock(&dev_priv->sb_lock);
8509
8510         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8511                SBI_GEN0 : SBI_DBUFF0;
8512         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8513         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8514         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8515
8516         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8517         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8518                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8519                         tmp |= SBI_SSCCTL_PATHALT;
8520                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8521                         udelay(32);
8522                 }
8523                 tmp |= SBI_SSCCTL_DISABLE;
8524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525         }
8526
8527         mutex_unlock(&dev_priv->sb_lock);
8528 }
8529
8530 static void lpt_init_pch_refclk(struct drm_device *dev)
8531 {
8532         struct intel_encoder *encoder;
8533         bool has_vga = false;
8534
8535         for_each_intel_encoder(dev, encoder) {
8536                 switch (encoder->type) {
8537                 case INTEL_OUTPUT_ANALOG:
8538                         has_vga = true;
8539                         break;
8540                 default:
8541                         break;
8542                 }
8543         }
8544
8545         if (has_vga)
8546                 lpt_enable_clkout_dp(dev, true, true);
8547         else
8548                 lpt_disable_clkout_dp(dev);
8549 }
8550
8551 /*
8552  * Initialize reference clocks when the driver loads
8553  */
8554 void intel_init_pch_refclk(struct drm_device *dev)
8555 {
8556         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8557                 ironlake_init_pch_refclk(dev);
8558         else if (HAS_PCH_LPT(dev))
8559                 lpt_init_pch_refclk(dev);
8560 }
8561
8562 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8563 {
8564         struct drm_device *dev = crtc_state->base.crtc->dev;
8565         struct drm_i915_private *dev_priv = dev->dev_private;
8566         struct drm_atomic_state *state = crtc_state->base.state;
8567         struct drm_connector *connector;
8568         struct drm_connector_state *connector_state;
8569         struct intel_encoder *encoder;
8570         int num_connectors = 0, i;
8571         bool is_lvds = false;
8572
8573         for_each_connector_in_state(state, connector, connector_state, i) {
8574                 if (connector_state->crtc != crtc_state->base.crtc)
8575                         continue;
8576
8577                 encoder = to_intel_encoder(connector_state->best_encoder);
8578
8579                 switch (encoder->type) {
8580                 case INTEL_OUTPUT_LVDS:
8581                         is_lvds = true;
8582                         break;
8583                 default:
8584                         break;
8585                 }
8586                 num_connectors++;
8587         }
8588
8589         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8590                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8591                               dev_priv->vbt.lvds_ssc_freq);
8592                 return dev_priv->vbt.lvds_ssc_freq;
8593         }
8594
8595         return 120000;
8596 }
8597
8598 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8599 {
8600         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8602         int pipe = intel_crtc->pipe;
8603         uint32_t val;
8604
8605         val = 0;
8606
8607         switch (intel_crtc->config->pipe_bpp) {
8608         case 18:
8609                 val |= PIPECONF_6BPC;
8610                 break;
8611         case 24:
8612                 val |= PIPECONF_8BPC;
8613                 break;
8614         case 30:
8615                 val |= PIPECONF_10BPC;
8616                 break;
8617         case 36:
8618                 val |= PIPECONF_12BPC;
8619                 break;
8620         default:
8621                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8622                 BUG();
8623         }
8624
8625         if (intel_crtc->config->dither)
8626                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8627
8628         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8629                 val |= PIPECONF_INTERLACED_ILK;
8630         else
8631                 val |= PIPECONF_PROGRESSIVE;
8632
8633         if (intel_crtc->config->limited_color_range)
8634                 val |= PIPECONF_COLOR_RANGE_SELECT;
8635
8636         I915_WRITE(PIPECONF(pipe), val);
8637         POSTING_READ(PIPECONF(pipe));
8638 }
8639
8640 /*
8641  * Set up the pipe CSC unit.
8642  *
8643  * Currently only full range RGB to limited range RGB conversion
8644  * is supported, but eventually this should handle various
8645  * RGB<->YCbCr scenarios as well.
8646  */
8647 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8648 {
8649         struct drm_device *dev = crtc->dev;
8650         struct drm_i915_private *dev_priv = dev->dev_private;
8651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8652         int pipe = intel_crtc->pipe;
8653         uint16_t coeff = 0x7800; /* 1.0 */
8654
8655         /*
8656          * TODO: Check what kind of values actually come out of the pipe
8657          * with these coeff/postoff values and adjust to get the best
8658          * accuracy. Perhaps we even need to take the bpc value into
8659          * consideration.
8660          */
8661
8662         if (intel_crtc->config->limited_color_range)
8663                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8664
8665         /*
8666          * GY/GU and RY/RU should be the other way around according
8667          * to BSpec, but reality doesn't agree. Just set them up in
8668          * a way that results in the correct picture.
8669          */
8670         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8671         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8672
8673         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8674         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8675
8676         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8677         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8678
8679         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8680         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8681         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8682
8683         if (INTEL_INFO(dev)->gen > 6) {
8684                 uint16_t postoff = 0;
8685
8686                 if (intel_crtc->config->limited_color_range)
8687                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8688
8689                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8690                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8691                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8692
8693                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8694         } else {
8695                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8696
8697                 if (intel_crtc->config->limited_color_range)
8698                         mode |= CSC_BLACK_SCREEN_OFFSET;
8699
8700                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8701         }
8702 }
8703
8704 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8705 {
8706         struct drm_device *dev = crtc->dev;
8707         struct drm_i915_private *dev_priv = dev->dev_private;
8708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8709         enum pipe pipe = intel_crtc->pipe;
8710         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8711         uint32_t val;
8712
8713         val = 0;
8714
8715         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8716                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8717
8718         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8719                 val |= PIPECONF_INTERLACED_ILK;
8720         else
8721                 val |= PIPECONF_PROGRESSIVE;
8722
8723         I915_WRITE(PIPECONF(cpu_transcoder), val);
8724         POSTING_READ(PIPECONF(cpu_transcoder));
8725
8726         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8727         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8728
8729         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8730                 val = 0;
8731
8732                 switch (intel_crtc->config->pipe_bpp) {
8733                 case 18:
8734                         val |= PIPEMISC_DITHER_6_BPC;
8735                         break;
8736                 case 24:
8737                         val |= PIPEMISC_DITHER_8_BPC;
8738                         break;
8739                 case 30:
8740                         val |= PIPEMISC_DITHER_10_BPC;
8741                         break;
8742                 case 36:
8743                         val |= PIPEMISC_DITHER_12_BPC;
8744                         break;
8745                 default:
8746                         /* Case prevented by pipe_config_set_bpp. */
8747                         BUG();
8748                 }
8749
8750                 if (intel_crtc->config->dither)
8751                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8752
8753                 I915_WRITE(PIPEMISC(pipe), val);
8754         }
8755 }
8756
8757 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8758                                     struct intel_crtc_state *crtc_state,
8759                                     intel_clock_t *clock,
8760                                     bool *has_reduced_clock,
8761                                     intel_clock_t *reduced_clock)
8762 {
8763         struct drm_device *dev = crtc->dev;
8764         struct drm_i915_private *dev_priv = dev->dev_private;
8765         int refclk;
8766         const intel_limit_t *limit;
8767         bool ret;
8768
8769         refclk = ironlake_get_refclk(crtc_state);
8770
8771         /*
8772          * Returns a set of divisors for the desired target clock with the given
8773          * refclk, or FALSE.  The returned values represent the clock equation:
8774          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8775          */
8776         limit = intel_limit(crtc_state, refclk);
8777         ret = dev_priv->display.find_dpll(limit, crtc_state,
8778                                           crtc_state->port_clock,
8779                                           refclk, NULL, clock);
8780         if (!ret)
8781                 return false;
8782
8783         return true;
8784 }
8785
8786 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8787 {
8788         /*
8789          * Account for spread spectrum to avoid
8790          * oversubscribing the link. Max center spread
8791          * is 2.5%; use 5% for safety's sake.
8792          */
8793         u32 bps = target_clock * bpp * 21 / 20;
8794         return DIV_ROUND_UP(bps, link_bw * 8);
8795 }
8796
8797 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8798 {
8799         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8800 }
8801
8802 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8803                                       struct intel_crtc_state *crtc_state,
8804                                       u32 *fp,
8805                                       intel_clock_t *reduced_clock, u32 *fp2)
8806 {
8807         struct drm_crtc *crtc = &intel_crtc->base;
8808         struct drm_device *dev = crtc->dev;
8809         struct drm_i915_private *dev_priv = dev->dev_private;
8810         struct drm_atomic_state *state = crtc_state->base.state;
8811         struct drm_connector *connector;
8812         struct drm_connector_state *connector_state;
8813         struct intel_encoder *encoder;
8814         uint32_t dpll;
8815         int factor, num_connectors = 0, i;
8816         bool is_lvds = false, is_sdvo = false;
8817
8818         for_each_connector_in_state(state, connector, connector_state, i) {
8819                 if (connector_state->crtc != crtc_state->base.crtc)
8820                         continue;
8821
8822                 encoder = to_intel_encoder(connector_state->best_encoder);
8823
8824                 switch (encoder->type) {
8825                 case INTEL_OUTPUT_LVDS:
8826                         is_lvds = true;
8827                         break;
8828                 case INTEL_OUTPUT_SDVO:
8829                 case INTEL_OUTPUT_HDMI:
8830                         is_sdvo = true;
8831                         break;
8832                 default:
8833                         break;
8834                 }
8835
8836                 num_connectors++;
8837         }
8838
8839         /* Enable autotuning of the PLL clock (if permissible) */
8840         factor = 21;
8841         if (is_lvds) {
8842                 if ((intel_panel_use_ssc(dev_priv) &&
8843                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8844                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8845                         factor = 25;
8846         } else if (crtc_state->sdvo_tv_clock)
8847                 factor = 20;
8848
8849         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8850                 *fp |= FP_CB_TUNE;
8851
8852         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8853                 *fp2 |= FP_CB_TUNE;
8854
8855         dpll = 0;
8856
8857         if (is_lvds)
8858                 dpll |= DPLLB_MODE_LVDS;
8859         else
8860                 dpll |= DPLLB_MODE_DAC_SERIAL;
8861
8862         dpll |= (crtc_state->pixel_multiplier - 1)
8863                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8864
8865         if (is_sdvo)
8866                 dpll |= DPLL_SDVO_HIGH_SPEED;
8867         if (crtc_state->has_dp_encoder)
8868                 dpll |= DPLL_SDVO_HIGH_SPEED;
8869
8870         /* compute bitmask from p1 value */
8871         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8872         /* also FPA1 */
8873         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8874
8875         switch (crtc_state->dpll.p2) {
8876         case 5:
8877                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8878                 break;
8879         case 7:
8880                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8881                 break;
8882         case 10:
8883                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8884                 break;
8885         case 14:
8886                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8887                 break;
8888         }
8889
8890         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8891                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8892         else
8893                 dpll |= PLL_REF_INPUT_DREFCLK;
8894
8895         return dpll | DPLL_VCO_ENABLE;
8896 }
8897
8898 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8899                                        struct intel_crtc_state *crtc_state)
8900 {
8901         struct drm_device *dev = crtc->base.dev;
8902         intel_clock_t clock, reduced_clock;
8903         u32 dpll = 0, fp = 0, fp2 = 0;
8904         bool ok, has_reduced_clock = false;
8905         bool is_lvds = false;
8906         struct intel_shared_dpll *pll;
8907
8908         memset(&crtc_state->dpll_hw_state, 0,
8909                sizeof(crtc_state->dpll_hw_state));
8910
8911         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8912
8913         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8914              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8915
8916         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8917                                      &has_reduced_clock, &reduced_clock);
8918         if (!ok && !crtc_state->clock_set) {
8919                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8920                 return -EINVAL;
8921         }
8922         /* Compat-code for transition, will disappear. */
8923         if (!crtc_state->clock_set) {
8924                 crtc_state->dpll.n = clock.n;
8925                 crtc_state->dpll.m1 = clock.m1;
8926                 crtc_state->dpll.m2 = clock.m2;
8927                 crtc_state->dpll.p1 = clock.p1;
8928                 crtc_state->dpll.p2 = clock.p2;
8929         }
8930
8931         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8932         if (crtc_state->has_pch_encoder) {
8933                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8934                 if (has_reduced_clock)
8935                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8936
8937                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8938                                              &fp, &reduced_clock,
8939                                              has_reduced_clock ? &fp2 : NULL);
8940
8941                 crtc_state->dpll_hw_state.dpll = dpll;
8942                 crtc_state->dpll_hw_state.fp0 = fp;
8943                 if (has_reduced_clock)
8944                         crtc_state->dpll_hw_state.fp1 = fp2;
8945                 else
8946                         crtc_state->dpll_hw_state.fp1 = fp;
8947
8948                 pll = intel_get_shared_dpll(crtc, crtc_state);
8949                 if (pll == NULL) {
8950                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8951                                          pipe_name(crtc->pipe));
8952                         return -EINVAL;
8953                 }
8954         }
8955
8956         if (is_lvds && has_reduced_clock)
8957                 crtc->lowfreq_avail = true;
8958         else
8959                 crtc->lowfreq_avail = false;
8960
8961         return 0;
8962 }
8963
8964 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8965                                          struct intel_link_m_n *m_n)
8966 {
8967         struct drm_device *dev = crtc->base.dev;
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         enum pipe pipe = crtc->pipe;
8970
8971         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8972         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8973         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8974                 & ~TU_SIZE_MASK;
8975         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8976         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8977                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8978 }
8979
8980 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8981                                          enum transcoder transcoder,
8982                                          struct intel_link_m_n *m_n,
8983                                          struct intel_link_m_n *m2_n2)
8984 {
8985         struct drm_device *dev = crtc->base.dev;
8986         struct drm_i915_private *dev_priv = dev->dev_private;
8987         enum pipe pipe = crtc->pipe;
8988
8989         if (INTEL_INFO(dev)->gen >= 5) {
8990                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8991                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8992                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8993                         & ~TU_SIZE_MASK;
8994                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8995                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8996                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8997                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8998                  * gen < 8) and if DRRS is supported (to make sure the
8999                  * registers are not unnecessarily read).
9000                  */
9001                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9002                         crtc->config->has_drrs) {
9003                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9004                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9005                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9006                                         & ~TU_SIZE_MASK;
9007                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9008                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9009                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9010                 }
9011         } else {
9012                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9013                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9014                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9015                         & ~TU_SIZE_MASK;
9016                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9017                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9018                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9019         }
9020 }
9021
9022 void intel_dp_get_m_n(struct intel_crtc *crtc,
9023                       struct intel_crtc_state *pipe_config)
9024 {
9025         if (pipe_config->has_pch_encoder)
9026                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9027         else
9028                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9029                                              &pipe_config->dp_m_n,
9030                                              &pipe_config->dp_m2_n2);
9031 }
9032
9033 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9034                                         struct intel_crtc_state *pipe_config)
9035 {
9036         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9037                                      &pipe_config->fdi_m_n, NULL);
9038 }
9039
9040 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9041                                     struct intel_crtc_state *pipe_config)
9042 {
9043         struct drm_device *dev = crtc->base.dev;
9044         struct drm_i915_private *dev_priv = dev->dev_private;
9045         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9046         uint32_t ps_ctrl = 0;
9047         int id = -1;
9048         int i;
9049
9050         /* find scaler attached to this pipe */
9051         for (i = 0; i < crtc->num_scalers; i++) {
9052                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9053                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9054                         id = i;
9055                         pipe_config->pch_pfit.enabled = true;
9056                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9057                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9058                         break;
9059                 }
9060         }
9061
9062         scaler_state->scaler_id = id;
9063         if (id >= 0) {
9064                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9065         } else {
9066                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9067         }
9068 }
9069
9070 static void
9071 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9072                                  struct intel_initial_plane_config *plane_config)
9073 {
9074         struct drm_device *dev = crtc->base.dev;
9075         struct drm_i915_private *dev_priv = dev->dev_private;
9076         u32 val, base, offset, stride_mult, tiling;
9077         int pipe = crtc->pipe;
9078         int fourcc, pixel_format;
9079         unsigned int aligned_height;
9080         struct drm_framebuffer *fb;
9081         struct intel_framebuffer *intel_fb;
9082
9083         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9084         if (!intel_fb) {
9085                 DRM_DEBUG_KMS("failed to alloc fb\n");
9086                 return;
9087         }
9088
9089         fb = &intel_fb->base;
9090
9091         val = I915_READ(PLANE_CTL(pipe, 0));
9092         if (!(val & PLANE_CTL_ENABLE))
9093                 goto error;
9094
9095         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9096         fourcc = skl_format_to_fourcc(pixel_format,
9097                                       val & PLANE_CTL_ORDER_RGBX,
9098                                       val & PLANE_CTL_ALPHA_MASK);
9099         fb->pixel_format = fourcc;
9100         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9101
9102         tiling = val & PLANE_CTL_TILED_MASK;
9103         switch (tiling) {
9104         case PLANE_CTL_TILED_LINEAR:
9105                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9106                 break;
9107         case PLANE_CTL_TILED_X:
9108                 plane_config->tiling = I915_TILING_X;
9109                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9110                 break;
9111         case PLANE_CTL_TILED_Y:
9112                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9113                 break;
9114         case PLANE_CTL_TILED_YF:
9115                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9116                 break;
9117         default:
9118                 MISSING_CASE(tiling);
9119                 goto error;
9120         }
9121
9122         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9123         plane_config->base = base;
9124
9125         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9126
9127         val = I915_READ(PLANE_SIZE(pipe, 0));
9128         fb->height = ((val >> 16) & 0xfff) + 1;
9129         fb->width = ((val >> 0) & 0x1fff) + 1;
9130
9131         val = I915_READ(PLANE_STRIDE(pipe, 0));
9132         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9133                                                 fb->pixel_format);
9134         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9135
9136         aligned_height = intel_fb_align_height(dev, fb->height,
9137                                                fb->pixel_format,
9138                                                fb->modifier[0]);
9139
9140         plane_config->size = fb->pitches[0] * aligned_height;
9141
9142         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9143                       pipe_name(pipe), fb->width, fb->height,
9144                       fb->bits_per_pixel, base, fb->pitches[0],
9145                       plane_config->size);
9146
9147         plane_config->fb = intel_fb;
9148         return;
9149
9150 error:
9151         kfree(fb);
9152 }
9153
9154 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9155                                      struct intel_crtc_state *pipe_config)
9156 {
9157         struct drm_device *dev = crtc->base.dev;
9158         struct drm_i915_private *dev_priv = dev->dev_private;
9159         uint32_t tmp;
9160
9161         tmp = I915_READ(PF_CTL(crtc->pipe));
9162
9163         if (tmp & PF_ENABLE) {
9164                 pipe_config->pch_pfit.enabled = true;
9165                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9166                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9167
9168                 /* We currently do not free assignements of panel fitters on
9169                  * ivb/hsw (since we don't use the higher upscaling modes which
9170                  * differentiates them) so just WARN about this case for now. */
9171                 if (IS_GEN7(dev)) {
9172                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9173                                 PF_PIPE_SEL_IVB(crtc->pipe));
9174                 }
9175         }
9176 }
9177
9178 static void
9179 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9180                                   struct intel_initial_plane_config *plane_config)
9181 {
9182         struct drm_device *dev = crtc->base.dev;
9183         struct drm_i915_private *dev_priv = dev->dev_private;
9184         u32 val, base, offset;
9185         int pipe = crtc->pipe;
9186         int fourcc, pixel_format;
9187         unsigned int aligned_height;
9188         struct drm_framebuffer *fb;
9189         struct intel_framebuffer *intel_fb;
9190
9191         val = I915_READ(DSPCNTR(pipe));
9192         if (!(val & DISPLAY_PLANE_ENABLE))
9193                 return;
9194
9195         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9196         if (!intel_fb) {
9197                 DRM_DEBUG_KMS("failed to alloc fb\n");
9198                 return;
9199         }
9200
9201         fb = &intel_fb->base;
9202
9203         if (INTEL_INFO(dev)->gen >= 4) {
9204                 if (val & DISPPLANE_TILED) {
9205                         plane_config->tiling = I915_TILING_X;
9206                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9207                 }
9208         }
9209
9210         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9211         fourcc = i9xx_format_to_fourcc(pixel_format);
9212         fb->pixel_format = fourcc;
9213         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9214
9215         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9216         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9217                 offset = I915_READ(DSPOFFSET(pipe));
9218         } else {
9219                 if (plane_config->tiling)
9220                         offset = I915_READ(DSPTILEOFF(pipe));
9221                 else
9222                         offset = I915_READ(DSPLINOFF(pipe));
9223         }
9224         plane_config->base = base;
9225
9226         val = I915_READ(PIPESRC(pipe));
9227         fb->width = ((val >> 16) & 0xfff) + 1;
9228         fb->height = ((val >> 0) & 0xfff) + 1;
9229
9230         val = I915_READ(DSPSTRIDE(pipe));
9231         fb->pitches[0] = val & 0xffffffc0;
9232
9233         aligned_height = intel_fb_align_height(dev, fb->height,
9234                                                fb->pixel_format,
9235                                                fb->modifier[0]);
9236
9237         plane_config->size = fb->pitches[0] * aligned_height;
9238
9239         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9240                       pipe_name(pipe), fb->width, fb->height,
9241                       fb->bits_per_pixel, base, fb->pitches[0],
9242                       plane_config->size);
9243
9244         plane_config->fb = intel_fb;
9245 }
9246
9247 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9248                                      struct intel_crtc_state *pipe_config)
9249 {
9250         struct drm_device *dev = crtc->base.dev;
9251         struct drm_i915_private *dev_priv = dev->dev_private;
9252         uint32_t tmp;
9253
9254         if (!intel_display_power_is_enabled(dev_priv,
9255                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9256                 return false;
9257
9258         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9259         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9260
9261         tmp = I915_READ(PIPECONF(crtc->pipe));
9262         if (!(tmp & PIPECONF_ENABLE))
9263                 return false;
9264
9265         switch (tmp & PIPECONF_BPC_MASK) {
9266         case PIPECONF_6BPC:
9267                 pipe_config->pipe_bpp = 18;
9268                 break;
9269         case PIPECONF_8BPC:
9270                 pipe_config->pipe_bpp = 24;
9271                 break;
9272         case PIPECONF_10BPC:
9273                 pipe_config->pipe_bpp = 30;
9274                 break;
9275         case PIPECONF_12BPC:
9276                 pipe_config->pipe_bpp = 36;
9277                 break;
9278         default:
9279                 break;
9280         }
9281
9282         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9283                 pipe_config->limited_color_range = true;
9284
9285         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9286                 struct intel_shared_dpll *pll;
9287
9288                 pipe_config->has_pch_encoder = true;
9289
9290                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9291                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9292                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9293
9294                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9295
9296                 if (HAS_PCH_IBX(dev_priv->dev)) {
9297                         pipe_config->shared_dpll =
9298                                 (enum intel_dpll_id) crtc->pipe;
9299                 } else {
9300                         tmp = I915_READ(PCH_DPLL_SEL);
9301                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9302                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9303                         else
9304                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9305                 }
9306
9307                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9308
9309                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9310                                            &pipe_config->dpll_hw_state));
9311
9312                 tmp = pipe_config->dpll_hw_state.dpll;
9313                 pipe_config->pixel_multiplier =
9314                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9315                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9316
9317                 ironlake_pch_clock_get(crtc, pipe_config);
9318         } else {
9319                 pipe_config->pixel_multiplier = 1;
9320         }
9321
9322         intel_get_pipe_timings(crtc, pipe_config);
9323
9324         ironlake_get_pfit_config(crtc, pipe_config);
9325
9326         return true;
9327 }
9328
9329 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9330 {
9331         struct drm_device *dev = dev_priv->dev;
9332         struct intel_crtc *crtc;
9333
9334         for_each_intel_crtc(dev, crtc)
9335                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9336                      pipe_name(crtc->pipe));
9337
9338         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9339         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9340         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9341         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9342         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9343         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9344              "CPU PWM1 enabled\n");
9345         if (IS_HASWELL(dev))
9346                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9347                      "CPU PWM2 enabled\n");
9348         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9349              "PCH PWM1 enabled\n");
9350         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9351              "Utility pin enabled\n");
9352         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9353
9354         /*
9355          * In theory we can still leave IRQs enabled, as long as only the HPD
9356          * interrupts remain enabled. We used to check for that, but since it's
9357          * gen-specific and since we only disable LCPLL after we fully disable
9358          * the interrupts, the check below should be enough.
9359          */
9360         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9361 }
9362
9363 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9364 {
9365         struct drm_device *dev = dev_priv->dev;
9366
9367         if (IS_HASWELL(dev))
9368                 return I915_READ(D_COMP_HSW);
9369         else
9370                 return I915_READ(D_COMP_BDW);
9371 }
9372
9373 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9374 {
9375         struct drm_device *dev = dev_priv->dev;
9376
9377         if (IS_HASWELL(dev)) {
9378                 mutex_lock(&dev_priv->rps.hw_lock);
9379                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9380                                             val))
9381                         DRM_ERROR("Failed to write to D_COMP\n");
9382                 mutex_unlock(&dev_priv->rps.hw_lock);
9383         } else {
9384                 I915_WRITE(D_COMP_BDW, val);
9385                 POSTING_READ(D_COMP_BDW);
9386         }
9387 }
9388
9389 /*
9390  * This function implements pieces of two sequences from BSpec:
9391  * - Sequence for display software to disable LCPLL
9392  * - Sequence for display software to allow package C8+
9393  * The steps implemented here are just the steps that actually touch the LCPLL
9394  * register. Callers should take care of disabling all the display engine
9395  * functions, doing the mode unset, fixing interrupts, etc.
9396  */
9397 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9398                               bool switch_to_fclk, bool allow_power_down)
9399 {
9400         uint32_t val;
9401
9402         assert_can_disable_lcpll(dev_priv);
9403
9404         val = I915_READ(LCPLL_CTL);
9405
9406         if (switch_to_fclk) {
9407                 val |= LCPLL_CD_SOURCE_FCLK;
9408                 I915_WRITE(LCPLL_CTL, val);
9409
9410                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9411                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9412                         DRM_ERROR("Switching to FCLK failed\n");
9413
9414                 val = I915_READ(LCPLL_CTL);
9415         }
9416
9417         val |= LCPLL_PLL_DISABLE;
9418         I915_WRITE(LCPLL_CTL, val);
9419         POSTING_READ(LCPLL_CTL);
9420
9421         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9422                 DRM_ERROR("LCPLL still locked\n");
9423
9424         val = hsw_read_dcomp(dev_priv);
9425         val |= D_COMP_COMP_DISABLE;
9426         hsw_write_dcomp(dev_priv, val);
9427         ndelay(100);
9428
9429         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9430                      1))
9431                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9432
9433         if (allow_power_down) {
9434                 val = I915_READ(LCPLL_CTL);
9435                 val |= LCPLL_POWER_DOWN_ALLOW;
9436                 I915_WRITE(LCPLL_CTL, val);
9437                 POSTING_READ(LCPLL_CTL);
9438         }
9439 }
9440
9441 /*
9442  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9443  * source.
9444  */
9445 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9446 {
9447         uint32_t val;
9448
9449         val = I915_READ(LCPLL_CTL);
9450
9451         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9452                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9453                 return;
9454
9455         /*
9456          * Make sure we're not on PC8 state before disabling PC8, otherwise
9457          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9458          */
9459         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9460
9461         if (val & LCPLL_POWER_DOWN_ALLOW) {
9462                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9463                 I915_WRITE(LCPLL_CTL, val);
9464                 POSTING_READ(LCPLL_CTL);
9465         }
9466
9467         val = hsw_read_dcomp(dev_priv);
9468         val |= D_COMP_COMP_FORCE;
9469         val &= ~D_COMP_COMP_DISABLE;
9470         hsw_write_dcomp(dev_priv, val);
9471
9472         val = I915_READ(LCPLL_CTL);
9473         val &= ~LCPLL_PLL_DISABLE;
9474         I915_WRITE(LCPLL_CTL, val);
9475
9476         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9477                 DRM_ERROR("LCPLL not locked yet\n");
9478
9479         if (val & LCPLL_CD_SOURCE_FCLK) {
9480                 val = I915_READ(LCPLL_CTL);
9481                 val &= ~LCPLL_CD_SOURCE_FCLK;
9482                 I915_WRITE(LCPLL_CTL, val);
9483
9484                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9485                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9486                         DRM_ERROR("Switching back to LCPLL failed\n");
9487         }
9488
9489         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9490         intel_update_cdclk(dev_priv->dev);
9491 }
9492
9493 /*
9494  * Package states C8 and deeper are really deep PC states that can only be
9495  * reached when all the devices on the system allow it, so even if the graphics
9496  * device allows PC8+, it doesn't mean the system will actually get to these
9497  * states. Our driver only allows PC8+ when going into runtime PM.
9498  *
9499  * The requirements for PC8+ are that all the outputs are disabled, the power
9500  * well is disabled and most interrupts are disabled, and these are also
9501  * requirements for runtime PM. When these conditions are met, we manually do
9502  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9503  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9504  * hang the machine.
9505  *
9506  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9507  * the state of some registers, so when we come back from PC8+ we need to
9508  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9509  * need to take care of the registers kept by RC6. Notice that this happens even
9510  * if we don't put the device in PCI D3 state (which is what currently happens
9511  * because of the runtime PM support).
9512  *
9513  * For more, read "Display Sequences for Package C8" on the hardware
9514  * documentation.
9515  */
9516 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9517 {
9518         struct drm_device *dev = dev_priv->dev;
9519         uint32_t val;
9520
9521         DRM_DEBUG_KMS("Enabling package C8+\n");
9522
9523         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9524                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9525                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9526                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9527         }
9528
9529         lpt_disable_clkout_dp(dev);
9530         hsw_disable_lcpll(dev_priv, true, true);
9531 }
9532
9533 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9534 {
9535         struct drm_device *dev = dev_priv->dev;
9536         uint32_t val;
9537
9538         DRM_DEBUG_KMS("Disabling package C8+\n");
9539
9540         hsw_restore_lcpll(dev_priv);
9541         lpt_init_pch_refclk(dev);
9542
9543         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9544                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9545                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9546                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9547         }
9548
9549         intel_prepare_ddi(dev);
9550 }
9551
9552 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9553 {
9554         struct drm_device *dev = old_state->dev;
9555         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9556
9557         broxton_set_cdclk(dev, req_cdclk);
9558 }
9559
9560 /* compute the max rate for new configuration */
9561 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9562 {
9563         struct intel_crtc *intel_crtc;
9564         struct intel_crtc_state *crtc_state;
9565         int max_pixel_rate = 0;
9566
9567         for_each_intel_crtc(state->dev, intel_crtc) {
9568                 int pixel_rate;
9569
9570                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9571                 if (IS_ERR(crtc_state))
9572                         return PTR_ERR(crtc_state);
9573
9574                 if (!crtc_state->base.enable)
9575                         continue;
9576
9577                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9578
9579                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9580                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9581                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9582
9583                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9584         }
9585
9586         return max_pixel_rate;
9587 }
9588
9589 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9590 {
9591         struct drm_i915_private *dev_priv = dev->dev_private;
9592         uint32_t val, data;
9593         int ret;
9594
9595         if (WARN((I915_READ(LCPLL_CTL) &
9596                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9597                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9598                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9599                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9600                  "trying to change cdclk frequency with cdclk not enabled\n"))
9601                 return;
9602
9603         mutex_lock(&dev_priv->rps.hw_lock);
9604         ret = sandybridge_pcode_write(dev_priv,
9605                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9606         mutex_unlock(&dev_priv->rps.hw_lock);
9607         if (ret) {
9608                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9609                 return;
9610         }
9611
9612         val = I915_READ(LCPLL_CTL);
9613         val |= LCPLL_CD_SOURCE_FCLK;
9614         I915_WRITE(LCPLL_CTL, val);
9615
9616         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9617                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9618                 DRM_ERROR("Switching to FCLK failed\n");
9619
9620         val = I915_READ(LCPLL_CTL);
9621         val &= ~LCPLL_CLK_FREQ_MASK;
9622
9623         switch (cdclk) {
9624         case 450000:
9625                 val |= LCPLL_CLK_FREQ_450;
9626                 data = 0;
9627                 break;
9628         case 540000:
9629                 val |= LCPLL_CLK_FREQ_54O_BDW;
9630                 data = 1;
9631                 break;
9632         case 337500:
9633                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9634                 data = 2;
9635                 break;
9636         case 675000:
9637                 val |= LCPLL_CLK_FREQ_675_BDW;
9638                 data = 3;
9639                 break;
9640         default:
9641                 WARN(1, "invalid cdclk frequency\n");
9642                 return;
9643         }
9644
9645         I915_WRITE(LCPLL_CTL, val);
9646
9647         val = I915_READ(LCPLL_CTL);
9648         val &= ~LCPLL_CD_SOURCE_FCLK;
9649         I915_WRITE(LCPLL_CTL, val);
9650
9651         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9652                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9653                 DRM_ERROR("Switching back to LCPLL failed\n");
9654
9655         mutex_lock(&dev_priv->rps.hw_lock);
9656         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9657         mutex_unlock(&dev_priv->rps.hw_lock);
9658
9659         intel_update_cdclk(dev);
9660
9661         WARN(cdclk != dev_priv->cdclk_freq,
9662              "cdclk requested %d kHz but got %d kHz\n",
9663              cdclk, dev_priv->cdclk_freq);
9664 }
9665
9666 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9667 {
9668         struct drm_i915_private *dev_priv = to_i915(state->dev);
9669         int max_pixclk = ilk_max_pixel_rate(state);
9670         int cdclk;
9671
9672         /*
9673          * FIXME should also account for plane ratio
9674          * once 64bpp pixel formats are supported.
9675          */
9676         if (max_pixclk > 540000)
9677                 cdclk = 675000;
9678         else if (max_pixclk > 450000)
9679                 cdclk = 540000;
9680         else if (max_pixclk > 337500)
9681                 cdclk = 450000;
9682         else
9683                 cdclk = 337500;
9684
9685         /*
9686          * FIXME move the cdclk caclulation to
9687          * compute_config() so we can fail gracegully.
9688          */
9689         if (cdclk > dev_priv->max_cdclk_freq) {
9690                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9691                           cdclk, dev_priv->max_cdclk_freq);
9692                 cdclk = dev_priv->max_cdclk_freq;
9693         }
9694
9695         to_intel_atomic_state(state)->cdclk = cdclk;
9696
9697         return 0;
9698 }
9699
9700 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9701 {
9702         struct drm_device *dev = old_state->dev;
9703         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9704
9705         broadwell_set_cdclk(dev, req_cdclk);
9706 }
9707
9708 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9709                                       struct intel_crtc_state *crtc_state)
9710 {
9711         if (!intel_ddi_pll_select(crtc, crtc_state))
9712                 return -EINVAL;
9713
9714         crtc->lowfreq_avail = false;
9715
9716         return 0;
9717 }
9718
9719 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9720                                 enum port port,
9721                                 struct intel_crtc_state *pipe_config)
9722 {
9723         switch (port) {
9724         case PORT_A:
9725                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9726                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9727                 break;
9728         case PORT_B:
9729                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9730                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9731                 break;
9732         case PORT_C:
9733                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9734                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9735                 break;
9736         default:
9737                 DRM_ERROR("Incorrect port type\n");
9738         }
9739 }
9740
9741 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9742                                 enum port port,
9743                                 struct intel_crtc_state *pipe_config)
9744 {
9745         u32 temp, dpll_ctl1;
9746
9747         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9748         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9749
9750         switch (pipe_config->ddi_pll_sel) {
9751         case SKL_DPLL0:
9752                 /*
9753                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9754                  * of the shared DPLL framework and thus needs to be read out
9755                  * separately
9756                  */
9757                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9758                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9759                 break;
9760         case SKL_DPLL1:
9761                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9762                 break;
9763         case SKL_DPLL2:
9764                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9765                 break;
9766         case SKL_DPLL3:
9767                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9768                 break;
9769         }
9770 }
9771
9772 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9773                                 enum port port,
9774                                 struct intel_crtc_state *pipe_config)
9775 {
9776         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9777
9778         switch (pipe_config->ddi_pll_sel) {
9779         case PORT_CLK_SEL_WRPLL1:
9780                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9781                 break;
9782         case PORT_CLK_SEL_WRPLL2:
9783                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9784                 break;
9785         }
9786 }
9787
9788 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9789                                        struct intel_crtc_state *pipe_config)
9790 {
9791         struct drm_device *dev = crtc->base.dev;
9792         struct drm_i915_private *dev_priv = dev->dev_private;
9793         struct intel_shared_dpll *pll;
9794         enum port port;
9795         uint32_t tmp;
9796
9797         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9798
9799         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9800
9801         if (IS_SKYLAKE(dev))
9802                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9803         else if (IS_BROXTON(dev))
9804                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9805         else
9806                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9807
9808         if (pipe_config->shared_dpll >= 0) {
9809                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9810
9811                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9812                                            &pipe_config->dpll_hw_state));
9813         }
9814
9815         /*
9816          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9817          * DDI E. So just check whether this pipe is wired to DDI E and whether
9818          * the PCH transcoder is on.
9819          */
9820         if (INTEL_INFO(dev)->gen < 9 &&
9821             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9822                 pipe_config->has_pch_encoder = true;
9823
9824                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9825                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9826                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9827
9828                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9829         }
9830 }
9831
9832 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9833                                     struct intel_crtc_state *pipe_config)
9834 {
9835         struct drm_device *dev = crtc->base.dev;
9836         struct drm_i915_private *dev_priv = dev->dev_private;
9837         enum intel_display_power_domain pfit_domain;
9838         uint32_t tmp;
9839
9840         if (!intel_display_power_is_enabled(dev_priv,
9841                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9842                 return false;
9843
9844         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9845         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9846
9847         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9848         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9849                 enum pipe trans_edp_pipe;
9850                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9851                 default:
9852                         WARN(1, "unknown pipe linked to edp transcoder\n");
9853                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9854                 case TRANS_DDI_EDP_INPUT_A_ON:
9855                         trans_edp_pipe = PIPE_A;
9856                         break;
9857                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9858                         trans_edp_pipe = PIPE_B;
9859                         break;
9860                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9861                         trans_edp_pipe = PIPE_C;
9862                         break;
9863                 }
9864
9865                 if (trans_edp_pipe == crtc->pipe)
9866                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9867         }
9868
9869         if (!intel_display_power_is_enabled(dev_priv,
9870                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9871                 return false;
9872
9873         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9874         if (!(tmp & PIPECONF_ENABLE))
9875                 return false;
9876
9877         haswell_get_ddi_port_state(crtc, pipe_config);
9878
9879         intel_get_pipe_timings(crtc, pipe_config);
9880
9881         if (INTEL_INFO(dev)->gen >= 9) {
9882                 skl_init_scalers(dev, crtc, pipe_config);
9883         }
9884
9885         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9886
9887         if (INTEL_INFO(dev)->gen >= 9) {
9888                 pipe_config->scaler_state.scaler_id = -1;
9889                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9890         }
9891
9892         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9893                 if (INTEL_INFO(dev)->gen == 9)
9894                         skylake_get_pfit_config(crtc, pipe_config);
9895                 else if (INTEL_INFO(dev)->gen < 9)
9896                         ironlake_get_pfit_config(crtc, pipe_config);
9897                 else
9898                         MISSING_CASE(INTEL_INFO(dev)->gen);
9899         }
9900
9901         if (IS_HASWELL(dev))
9902                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9903                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9904
9905         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9906                 pipe_config->pixel_multiplier =
9907                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9908         } else {
9909                 pipe_config->pixel_multiplier = 1;
9910         }
9911
9912         return true;
9913 }
9914
9915 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9916 {
9917         struct drm_device *dev = crtc->dev;
9918         struct drm_i915_private *dev_priv = dev->dev_private;
9919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920         uint32_t cntl = 0, size = 0;
9921
9922         if (base) {
9923                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9924                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9925                 unsigned int stride = roundup_pow_of_two(width) * 4;
9926
9927                 switch (stride) {
9928                 default:
9929                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9930                                   width, stride);
9931                         stride = 256;
9932                         /* fallthrough */
9933                 case 256:
9934                 case 512:
9935                 case 1024:
9936                 case 2048:
9937                         break;
9938                 }
9939
9940                 cntl |= CURSOR_ENABLE |
9941                         CURSOR_GAMMA_ENABLE |
9942                         CURSOR_FORMAT_ARGB |
9943                         CURSOR_STRIDE(stride);
9944
9945                 size = (height << 12) | width;
9946         }
9947
9948         if (intel_crtc->cursor_cntl != 0 &&
9949             (intel_crtc->cursor_base != base ||
9950              intel_crtc->cursor_size != size ||
9951              intel_crtc->cursor_cntl != cntl)) {
9952                 /* On these chipsets we can only modify the base/size/stride
9953                  * whilst the cursor is disabled.
9954                  */
9955                 I915_WRITE(_CURACNTR, 0);
9956                 POSTING_READ(_CURACNTR);
9957                 intel_crtc->cursor_cntl = 0;
9958         }
9959
9960         if (intel_crtc->cursor_base != base) {
9961                 I915_WRITE(_CURABASE, base);
9962                 intel_crtc->cursor_base = base;
9963         }
9964
9965         if (intel_crtc->cursor_size != size) {
9966                 I915_WRITE(CURSIZE, size);
9967                 intel_crtc->cursor_size = size;
9968         }
9969
9970         if (intel_crtc->cursor_cntl != cntl) {
9971                 I915_WRITE(_CURACNTR, cntl);
9972                 POSTING_READ(_CURACNTR);
9973                 intel_crtc->cursor_cntl = cntl;
9974         }
9975 }
9976
9977 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9978 {
9979         struct drm_device *dev = crtc->dev;
9980         struct drm_i915_private *dev_priv = dev->dev_private;
9981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9982         int pipe = intel_crtc->pipe;
9983         uint32_t cntl;
9984
9985         cntl = 0;
9986         if (base) {
9987                 cntl = MCURSOR_GAMMA_ENABLE;
9988                 switch (intel_crtc->base.cursor->state->crtc_w) {
9989                         case 64:
9990                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9991                                 break;
9992                         case 128:
9993                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9994                                 break;
9995                         case 256:
9996                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9997                                 break;
9998                         default:
9999                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10000                                 return;
10001                 }
10002                 cntl |= pipe << 28; /* Connect to correct pipe */
10003
10004                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10005                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10006         }
10007
10008         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10009                 cntl |= CURSOR_ROTATE_180;
10010
10011         if (intel_crtc->cursor_cntl != cntl) {
10012                 I915_WRITE(CURCNTR(pipe), cntl);
10013                 POSTING_READ(CURCNTR(pipe));
10014                 intel_crtc->cursor_cntl = cntl;
10015         }
10016
10017         /* and commit changes on next vblank */
10018         I915_WRITE(CURBASE(pipe), base);
10019         POSTING_READ(CURBASE(pipe));
10020
10021         intel_crtc->cursor_base = base;
10022 }
10023
10024 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10025 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10026                                      bool on)
10027 {
10028         struct drm_device *dev = crtc->dev;
10029         struct drm_i915_private *dev_priv = dev->dev_private;
10030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10031         int pipe = intel_crtc->pipe;
10032         int x = crtc->cursor_x;
10033         int y = crtc->cursor_y;
10034         u32 base = 0, pos = 0;
10035
10036         if (on)
10037                 base = intel_crtc->cursor_addr;
10038
10039         if (x >= intel_crtc->config->pipe_src_w)
10040                 base = 0;
10041
10042         if (y >= intel_crtc->config->pipe_src_h)
10043                 base = 0;
10044
10045         if (x < 0) {
10046                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10047                         base = 0;
10048
10049                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10050                 x = -x;
10051         }
10052         pos |= x << CURSOR_X_SHIFT;
10053
10054         if (y < 0) {
10055                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10056                         base = 0;
10057
10058                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10059                 y = -y;
10060         }
10061         pos |= y << CURSOR_Y_SHIFT;
10062
10063         if (base == 0 && intel_crtc->cursor_base == 0)
10064                 return;
10065
10066         I915_WRITE(CURPOS(pipe), pos);
10067
10068         /* ILK+ do this automagically */
10069         if (HAS_GMCH_DISPLAY(dev) &&
10070             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10071                 base += (intel_crtc->base.cursor->state->crtc_h *
10072                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10073         }
10074
10075         if (IS_845G(dev) || IS_I865G(dev))
10076                 i845_update_cursor(crtc, base);
10077         else
10078                 i9xx_update_cursor(crtc, base);
10079 }
10080
10081 static bool cursor_size_ok(struct drm_device *dev,
10082                            uint32_t width, uint32_t height)
10083 {
10084         if (width == 0 || height == 0)
10085                 return false;
10086
10087         /*
10088          * 845g/865g are special in that they are only limited by
10089          * the width of their cursors, the height is arbitrary up to
10090          * the precision of the register. Everything else requires
10091          * square cursors, limited to a few power-of-two sizes.
10092          */
10093         if (IS_845G(dev) || IS_I865G(dev)) {
10094                 if ((width & 63) != 0)
10095                         return false;
10096
10097                 if (width > (IS_845G(dev) ? 64 : 512))
10098                         return false;
10099
10100                 if (height > 1023)
10101                         return false;
10102         } else {
10103                 switch (width | height) {
10104                 case 256:
10105                 case 128:
10106                         if (IS_GEN2(dev))
10107                                 return false;
10108                 case 64:
10109                         break;
10110                 default:
10111                         return false;
10112                 }
10113         }
10114
10115         return true;
10116 }
10117
10118 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10119                                  u16 *blue, uint32_t start, uint32_t size)
10120 {
10121         int end = (start + size > 256) ? 256 : start + size, i;
10122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123
10124         for (i = start; i < end; i++) {
10125                 intel_crtc->lut_r[i] = red[i] >> 8;
10126                 intel_crtc->lut_g[i] = green[i] >> 8;
10127                 intel_crtc->lut_b[i] = blue[i] >> 8;
10128         }
10129
10130         intel_crtc_load_lut(crtc);
10131 }
10132
10133 /* VESA 640x480x72Hz mode to set on the pipe */
10134 static struct drm_display_mode load_detect_mode = {
10135         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10136                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10137 };
10138
10139 struct drm_framebuffer *
10140 __intel_framebuffer_create(struct drm_device *dev,
10141                            struct drm_mode_fb_cmd2 *mode_cmd,
10142                            struct drm_i915_gem_object *obj)
10143 {
10144         struct intel_framebuffer *intel_fb;
10145         int ret;
10146
10147         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10148         if (!intel_fb) {
10149                 drm_gem_object_unreference(&obj->base);
10150                 return ERR_PTR(-ENOMEM);
10151         }
10152
10153         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10154         if (ret)
10155                 goto err;
10156
10157         return &intel_fb->base;
10158 err:
10159         drm_gem_object_unreference(&obj->base);
10160         kfree(intel_fb);
10161
10162         return ERR_PTR(ret);
10163 }
10164
10165 static struct drm_framebuffer *
10166 intel_framebuffer_create(struct drm_device *dev,
10167                          struct drm_mode_fb_cmd2 *mode_cmd,
10168                          struct drm_i915_gem_object *obj)
10169 {
10170         struct drm_framebuffer *fb;
10171         int ret;
10172
10173         ret = i915_mutex_lock_interruptible(dev);
10174         if (ret)
10175                 return ERR_PTR(ret);
10176         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10177         mutex_unlock(&dev->struct_mutex);
10178
10179         return fb;
10180 }
10181
10182 static u32
10183 intel_framebuffer_pitch_for_width(int width, int bpp)
10184 {
10185         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10186         return ALIGN(pitch, 64);
10187 }
10188
10189 static u32
10190 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10191 {
10192         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10193         return PAGE_ALIGN(pitch * mode->vdisplay);
10194 }
10195
10196 static struct drm_framebuffer *
10197 intel_framebuffer_create_for_mode(struct drm_device *dev,
10198                                   struct drm_display_mode *mode,
10199                                   int depth, int bpp)
10200 {
10201         struct drm_i915_gem_object *obj;
10202         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10203
10204         obj = i915_gem_alloc_object(dev,
10205                                     intel_framebuffer_size_for_mode(mode, bpp));
10206         if (obj == NULL)
10207                 return ERR_PTR(-ENOMEM);
10208
10209         mode_cmd.width = mode->hdisplay;
10210         mode_cmd.height = mode->vdisplay;
10211         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10212                                                                 bpp);
10213         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10214
10215         return intel_framebuffer_create(dev, &mode_cmd, obj);
10216 }
10217
10218 static struct drm_framebuffer *
10219 mode_fits_in_fbdev(struct drm_device *dev,
10220                    struct drm_display_mode *mode)
10221 {
10222 #ifdef CONFIG_DRM_I915_FBDEV
10223         struct drm_i915_private *dev_priv = dev->dev_private;
10224         struct drm_i915_gem_object *obj;
10225         struct drm_framebuffer *fb;
10226
10227         if (!dev_priv->fbdev)
10228                 return NULL;
10229
10230         if (!dev_priv->fbdev->fb)
10231                 return NULL;
10232
10233         obj = dev_priv->fbdev->fb->obj;
10234         BUG_ON(!obj);
10235
10236         fb = &dev_priv->fbdev->fb->base;
10237         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10238                                                                fb->bits_per_pixel))
10239                 return NULL;
10240
10241         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10242                 return NULL;
10243
10244         return fb;
10245 #else
10246         return NULL;
10247 #endif
10248 }
10249
10250 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10251                                            struct drm_crtc *crtc,
10252                                            struct drm_display_mode *mode,
10253                                            struct drm_framebuffer *fb,
10254                                            int x, int y)
10255 {
10256         struct drm_plane_state *plane_state;
10257         int hdisplay, vdisplay;
10258         int ret;
10259
10260         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10261         if (IS_ERR(plane_state))
10262                 return PTR_ERR(plane_state);
10263
10264         if (mode)
10265                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10266         else
10267                 hdisplay = vdisplay = 0;
10268
10269         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10270         if (ret)
10271                 return ret;
10272         drm_atomic_set_fb_for_plane(plane_state, fb);
10273         plane_state->crtc_x = 0;
10274         plane_state->crtc_y = 0;
10275         plane_state->crtc_w = hdisplay;
10276         plane_state->crtc_h = vdisplay;
10277         plane_state->src_x = x << 16;
10278         plane_state->src_y = y << 16;
10279         plane_state->src_w = hdisplay << 16;
10280         plane_state->src_h = vdisplay << 16;
10281
10282         return 0;
10283 }
10284
10285 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10286                                 struct drm_display_mode *mode,
10287                                 struct intel_load_detect_pipe *old,
10288                                 struct drm_modeset_acquire_ctx *ctx)
10289 {
10290         struct intel_crtc *intel_crtc;
10291         struct intel_encoder *intel_encoder =
10292                 intel_attached_encoder(connector);
10293         struct drm_crtc *possible_crtc;
10294         struct drm_encoder *encoder = &intel_encoder->base;
10295         struct drm_crtc *crtc = NULL;
10296         struct drm_device *dev = encoder->dev;
10297         struct drm_framebuffer *fb;
10298         struct drm_mode_config *config = &dev->mode_config;
10299         struct drm_atomic_state *state = NULL;
10300         struct drm_connector_state *connector_state;
10301         struct intel_crtc_state *crtc_state;
10302         int ret, i = -1;
10303
10304         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10305                       connector->base.id, connector->name,
10306                       encoder->base.id, encoder->name);
10307
10308 retry:
10309         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10310         if (ret)
10311                 goto fail;
10312
10313         /*
10314          * Algorithm gets a little messy:
10315          *
10316          *   - if the connector already has an assigned crtc, use it (but make
10317          *     sure it's on first)
10318          *
10319          *   - try to find the first unused crtc that can drive this connector,
10320          *     and use that if we find one
10321          */
10322
10323         /* See if we already have a CRTC for this connector */
10324         if (encoder->crtc) {
10325                 crtc = encoder->crtc;
10326
10327                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10328                 if (ret)
10329                         goto fail;
10330                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10331                 if (ret)
10332                         goto fail;
10333
10334                 old->dpms_mode = connector->dpms;
10335                 old->load_detect_temp = false;
10336
10337                 /* Make sure the crtc and connector are running */
10338                 if (connector->dpms != DRM_MODE_DPMS_ON)
10339                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10340
10341                 return true;
10342         }
10343
10344         /* Find an unused one (if possible) */
10345         for_each_crtc(dev, possible_crtc) {
10346                 i++;
10347                 if (!(encoder->possible_crtcs & (1 << i)))
10348                         continue;
10349                 if (possible_crtc->state->enable)
10350                         continue;
10351
10352                 crtc = possible_crtc;
10353                 break;
10354         }
10355
10356         /*
10357          * If we didn't find an unused CRTC, don't use any.
10358          */
10359         if (!crtc) {
10360                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10361                 goto fail;
10362         }
10363
10364         ret = drm_modeset_lock(&crtc->mutex, ctx);
10365         if (ret)
10366                 goto fail;
10367         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10368         if (ret)
10369                 goto fail;
10370
10371         intel_crtc = to_intel_crtc(crtc);
10372         old->dpms_mode = connector->dpms;
10373         old->load_detect_temp = true;
10374         old->release_fb = NULL;
10375
10376         state = drm_atomic_state_alloc(dev);
10377         if (!state)
10378                 return false;
10379
10380         state->acquire_ctx = ctx;
10381
10382         connector_state = drm_atomic_get_connector_state(state, connector);
10383         if (IS_ERR(connector_state)) {
10384                 ret = PTR_ERR(connector_state);
10385                 goto fail;
10386         }
10387
10388         connector_state->crtc = crtc;
10389         connector_state->best_encoder = &intel_encoder->base;
10390
10391         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392         if (IS_ERR(crtc_state)) {
10393                 ret = PTR_ERR(crtc_state);
10394                 goto fail;
10395         }
10396
10397         crtc_state->base.active = crtc_state->base.enable = true;
10398
10399         if (!mode)
10400                 mode = &load_detect_mode;
10401
10402         /* We need a framebuffer large enough to accommodate all accesses
10403          * that the plane may generate whilst we perform load detection.
10404          * We can not rely on the fbcon either being present (we get called
10405          * during its initialisation to detect all boot displays, or it may
10406          * not even exist) or that it is large enough to satisfy the
10407          * requested mode.
10408          */
10409         fb = mode_fits_in_fbdev(dev, mode);
10410         if (fb == NULL) {
10411                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10412                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10413                 old->release_fb = fb;
10414         } else
10415                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10416         if (IS_ERR(fb)) {
10417                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10418                 goto fail;
10419         }
10420
10421         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10422         if (ret)
10423                 goto fail;
10424
10425         drm_mode_copy(&crtc_state->base.mode, mode);
10426
10427         if (drm_atomic_commit(state)) {
10428                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10429                 if (old->release_fb)
10430                         old->release_fb->funcs->destroy(old->release_fb);
10431                 goto fail;
10432         }
10433         crtc->primary->crtc = crtc;
10434
10435         /* let the connector get through one full cycle before testing */
10436         intel_wait_for_vblank(dev, intel_crtc->pipe);
10437         return true;
10438
10439 fail:
10440         drm_atomic_state_free(state);
10441         state = NULL;
10442
10443         if (ret == -EDEADLK) {
10444                 drm_modeset_backoff(ctx);
10445                 goto retry;
10446         }
10447
10448         return false;
10449 }
10450
10451 void intel_release_load_detect_pipe(struct drm_connector *connector,
10452                                     struct intel_load_detect_pipe *old,
10453                                     struct drm_modeset_acquire_ctx *ctx)
10454 {
10455         struct drm_device *dev = connector->dev;
10456         struct intel_encoder *intel_encoder =
10457                 intel_attached_encoder(connector);
10458         struct drm_encoder *encoder = &intel_encoder->base;
10459         struct drm_crtc *crtc = encoder->crtc;
10460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10461         struct drm_atomic_state *state;
10462         struct drm_connector_state *connector_state;
10463         struct intel_crtc_state *crtc_state;
10464         int ret;
10465
10466         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10467                       connector->base.id, connector->name,
10468                       encoder->base.id, encoder->name);
10469
10470         if (old->load_detect_temp) {
10471                 state = drm_atomic_state_alloc(dev);
10472                 if (!state)
10473                         goto fail;
10474
10475                 state->acquire_ctx = ctx;
10476
10477                 connector_state = drm_atomic_get_connector_state(state, connector);
10478                 if (IS_ERR(connector_state))
10479                         goto fail;
10480
10481                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10482                 if (IS_ERR(crtc_state))
10483                         goto fail;
10484
10485                 connector_state->best_encoder = NULL;
10486                 connector_state->crtc = NULL;
10487
10488                 crtc_state->base.enable = crtc_state->base.active = false;
10489
10490                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10491                                                       0, 0);
10492                 if (ret)
10493                         goto fail;
10494
10495                 ret = drm_atomic_commit(state);
10496                 if (ret)
10497                         goto fail;
10498
10499                 if (old->release_fb) {
10500                         drm_framebuffer_unregister_private(old->release_fb);
10501                         drm_framebuffer_unreference(old->release_fb);
10502                 }
10503
10504                 return;
10505         }
10506
10507         /* Switch crtc and encoder back off if necessary */
10508         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10509                 connector->funcs->dpms(connector, old->dpms_mode);
10510
10511         return;
10512 fail:
10513         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10514         drm_atomic_state_free(state);
10515 }
10516
10517 static int i9xx_pll_refclk(struct drm_device *dev,
10518                            const struct intel_crtc_state *pipe_config)
10519 {
10520         struct drm_i915_private *dev_priv = dev->dev_private;
10521         u32 dpll = pipe_config->dpll_hw_state.dpll;
10522
10523         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10524                 return dev_priv->vbt.lvds_ssc_freq;
10525         else if (HAS_PCH_SPLIT(dev))
10526                 return 120000;
10527         else if (!IS_GEN2(dev))
10528                 return 96000;
10529         else
10530                 return 48000;
10531 }
10532
10533 /* Returns the clock of the currently programmed mode of the given pipe. */
10534 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10535                                 struct intel_crtc_state *pipe_config)
10536 {
10537         struct drm_device *dev = crtc->base.dev;
10538         struct drm_i915_private *dev_priv = dev->dev_private;
10539         int pipe = pipe_config->cpu_transcoder;
10540         u32 dpll = pipe_config->dpll_hw_state.dpll;
10541         u32 fp;
10542         intel_clock_t clock;
10543         int port_clock;
10544         int refclk = i9xx_pll_refclk(dev, pipe_config);
10545
10546         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10547                 fp = pipe_config->dpll_hw_state.fp0;
10548         else
10549                 fp = pipe_config->dpll_hw_state.fp1;
10550
10551         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10552         if (IS_PINEVIEW(dev)) {
10553                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10554                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10555         } else {
10556                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10557                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10558         }
10559
10560         if (!IS_GEN2(dev)) {
10561                 if (IS_PINEVIEW(dev))
10562                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10563                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10564                 else
10565                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10566                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10567
10568                 switch (dpll & DPLL_MODE_MASK) {
10569                 case DPLLB_MODE_DAC_SERIAL:
10570                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10571                                 5 : 10;
10572                         break;
10573                 case DPLLB_MODE_LVDS:
10574                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10575                                 7 : 14;
10576                         break;
10577                 default:
10578                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10579                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10580                         return;
10581                 }
10582
10583                 if (IS_PINEVIEW(dev))
10584                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10585                 else
10586                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10587         } else {
10588                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10589                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10590
10591                 if (is_lvds) {
10592                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10593                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10594
10595                         if (lvds & LVDS_CLKB_POWER_UP)
10596                                 clock.p2 = 7;
10597                         else
10598                                 clock.p2 = 14;
10599                 } else {
10600                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10601                                 clock.p1 = 2;
10602                         else {
10603                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10604                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10605                         }
10606                         if (dpll & PLL_P2_DIVIDE_BY_4)
10607                                 clock.p2 = 4;
10608                         else
10609                                 clock.p2 = 2;
10610                 }
10611
10612                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10613         }
10614
10615         /*
10616          * This value includes pixel_multiplier. We will use
10617          * port_clock to compute adjusted_mode.crtc_clock in the
10618          * encoder's get_config() function.
10619          */
10620         pipe_config->port_clock = port_clock;
10621 }
10622
10623 int intel_dotclock_calculate(int link_freq,
10624                              const struct intel_link_m_n *m_n)
10625 {
10626         /*
10627          * The calculation for the data clock is:
10628          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10629          * But we want to avoid losing precison if possible, so:
10630          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10631          *
10632          * and the link clock is simpler:
10633          * link_clock = (m * link_clock) / n
10634          */
10635
10636         if (!m_n->link_n)
10637                 return 0;
10638
10639         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10640 }
10641
10642 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10643                                    struct intel_crtc_state *pipe_config)
10644 {
10645         struct drm_device *dev = crtc->base.dev;
10646
10647         /* read out port_clock from the DPLL */
10648         i9xx_crtc_clock_get(crtc, pipe_config);
10649
10650         /*
10651          * This value does not include pixel_multiplier.
10652          * We will check that port_clock and adjusted_mode.crtc_clock
10653          * agree once we know their relationship in the encoder's
10654          * get_config() function.
10655          */
10656         pipe_config->base.adjusted_mode.crtc_clock =
10657                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10658                                          &pipe_config->fdi_m_n);
10659 }
10660
10661 /** Returns the currently programmed mode of the given pipe. */
10662 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10663                                              struct drm_crtc *crtc)
10664 {
10665         struct drm_i915_private *dev_priv = dev->dev_private;
10666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10667         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10668         struct drm_display_mode *mode;
10669         struct intel_crtc_state pipe_config;
10670         int htot = I915_READ(HTOTAL(cpu_transcoder));
10671         int hsync = I915_READ(HSYNC(cpu_transcoder));
10672         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10673         int vsync = I915_READ(VSYNC(cpu_transcoder));
10674         enum pipe pipe = intel_crtc->pipe;
10675
10676         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10677         if (!mode)
10678                 return NULL;
10679
10680         /*
10681          * Construct a pipe_config sufficient for getting the clock info
10682          * back out of crtc_clock_get.
10683          *
10684          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10685          * to use a real value here instead.
10686          */
10687         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10688         pipe_config.pixel_multiplier = 1;
10689         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10690         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10691         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10692         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10693
10694         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10695         mode->hdisplay = (htot & 0xffff) + 1;
10696         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10697         mode->hsync_start = (hsync & 0xffff) + 1;
10698         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10699         mode->vdisplay = (vtot & 0xffff) + 1;
10700         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10701         mode->vsync_start = (vsync & 0xffff) + 1;
10702         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10703
10704         drm_mode_set_name(mode);
10705
10706         return mode;
10707 }
10708
10709 void intel_mark_busy(struct drm_device *dev)
10710 {
10711         struct drm_i915_private *dev_priv = dev->dev_private;
10712
10713         if (dev_priv->mm.busy)
10714                 return;
10715
10716         intel_runtime_pm_get(dev_priv);
10717         i915_update_gfx_val(dev_priv);
10718         if (INTEL_INFO(dev)->gen >= 6)
10719                 gen6_rps_busy(dev_priv);
10720         dev_priv->mm.busy = true;
10721 }
10722
10723 void intel_mark_idle(struct drm_device *dev)
10724 {
10725         struct drm_i915_private *dev_priv = dev->dev_private;
10726
10727         if (!dev_priv->mm.busy)
10728                 return;
10729
10730         dev_priv->mm.busy = false;
10731
10732         if (INTEL_INFO(dev)->gen >= 6)
10733                 gen6_rps_idle(dev->dev_private);
10734
10735         intel_runtime_pm_put(dev_priv);
10736 }
10737
10738 static void intel_crtc_destroy(struct drm_crtc *crtc)
10739 {
10740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741         struct drm_device *dev = crtc->dev;
10742         struct intel_unpin_work *work;
10743
10744         spin_lock_irq(&dev->event_lock);
10745         work = intel_crtc->unpin_work;
10746         intel_crtc->unpin_work = NULL;
10747         spin_unlock_irq(&dev->event_lock);
10748
10749         if (work) {
10750                 cancel_work_sync(&work->work);
10751                 kfree(work);
10752         }
10753
10754         drm_crtc_cleanup(crtc);
10755
10756         kfree(intel_crtc);
10757 }
10758
10759 static void intel_unpin_work_fn(struct work_struct *__work)
10760 {
10761         struct intel_unpin_work *work =
10762                 container_of(__work, struct intel_unpin_work, work);
10763         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10764         struct drm_device *dev = crtc->base.dev;
10765         struct drm_i915_private *dev_priv = dev->dev_private;
10766         struct drm_plane *primary = crtc->base.primary;
10767
10768         mutex_lock(&dev->struct_mutex);
10769         intel_unpin_fb_obj(work->old_fb, primary->state);
10770         drm_gem_object_unreference(&work->pending_flip_obj->base);
10771
10772         intel_fbc_update(dev_priv);
10773
10774         if (work->flip_queued_req)
10775                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10776         mutex_unlock(&dev->struct_mutex);
10777
10778         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10779         drm_framebuffer_unreference(work->old_fb);
10780
10781         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10782         atomic_dec(&crtc->unpin_work_count);
10783
10784         kfree(work);
10785 }
10786
10787 static void do_intel_finish_page_flip(struct drm_device *dev,
10788                                       struct drm_crtc *crtc)
10789 {
10790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10791         struct intel_unpin_work *work;
10792         unsigned long flags;
10793
10794         /* Ignore early vblank irqs */
10795         if (intel_crtc == NULL)
10796                 return;
10797
10798         /*
10799          * This is called both by irq handlers and the reset code (to complete
10800          * lost pageflips) so needs the full irqsave spinlocks.
10801          */
10802         spin_lock_irqsave(&dev->event_lock, flags);
10803         work = intel_crtc->unpin_work;
10804
10805         /* Ensure we don't miss a work->pending update ... */
10806         smp_rmb();
10807
10808         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10809                 spin_unlock_irqrestore(&dev->event_lock, flags);
10810                 return;
10811         }
10812
10813         page_flip_completed(intel_crtc);
10814
10815         spin_unlock_irqrestore(&dev->event_lock, flags);
10816 }
10817
10818 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10819 {
10820         struct drm_i915_private *dev_priv = dev->dev_private;
10821         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10822
10823         do_intel_finish_page_flip(dev, crtc);
10824 }
10825
10826 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10827 {
10828         struct drm_i915_private *dev_priv = dev->dev_private;
10829         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10830
10831         do_intel_finish_page_flip(dev, crtc);
10832 }
10833
10834 /* Is 'a' after or equal to 'b'? */
10835 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10836 {
10837         return !((a - b) & 0x80000000);
10838 }
10839
10840 static bool page_flip_finished(struct intel_crtc *crtc)
10841 {
10842         struct drm_device *dev = crtc->base.dev;
10843         struct drm_i915_private *dev_priv = dev->dev_private;
10844
10845         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10846             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10847                 return true;
10848
10849         /*
10850          * The relevant registers doen't exist on pre-ctg.
10851          * As the flip done interrupt doesn't trigger for mmio
10852          * flips on gmch platforms, a flip count check isn't
10853          * really needed there. But since ctg has the registers,
10854          * include it in the check anyway.
10855          */
10856         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10857                 return true;
10858
10859         /*
10860          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10861          * used the same base address. In that case the mmio flip might
10862          * have completed, but the CS hasn't even executed the flip yet.
10863          *
10864          * A flip count check isn't enough as the CS might have updated
10865          * the base address just after start of vblank, but before we
10866          * managed to process the interrupt. This means we'd complete the
10867          * CS flip too soon.
10868          *
10869          * Combining both checks should get us a good enough result. It may
10870          * still happen that the CS flip has been executed, but has not
10871          * yet actually completed. But in case the base address is the same
10872          * anyway, we don't really care.
10873          */
10874         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10875                 crtc->unpin_work->gtt_offset &&
10876                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10877                                     crtc->unpin_work->flip_count);
10878 }
10879
10880 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10881 {
10882         struct drm_i915_private *dev_priv = dev->dev_private;
10883         struct intel_crtc *intel_crtc =
10884                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10885         unsigned long flags;
10886
10887
10888         /*
10889          * This is called both by irq handlers and the reset code (to complete
10890          * lost pageflips) so needs the full irqsave spinlocks.
10891          *
10892          * NB: An MMIO update of the plane base pointer will also
10893          * generate a page-flip completion irq, i.e. every modeset
10894          * is also accompanied by a spurious intel_prepare_page_flip().
10895          */
10896         spin_lock_irqsave(&dev->event_lock, flags);
10897         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10898                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10899         spin_unlock_irqrestore(&dev->event_lock, flags);
10900 }
10901
10902 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10903 {
10904         /* Ensure that the work item is consistent when activating it ... */
10905         smp_wmb();
10906         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10907         /* and that it is marked active as soon as the irq could fire. */
10908         smp_wmb();
10909 }
10910
10911 static int intel_gen2_queue_flip(struct drm_device *dev,
10912                                  struct drm_crtc *crtc,
10913                                  struct drm_framebuffer *fb,
10914                                  struct drm_i915_gem_object *obj,
10915                                  struct drm_i915_gem_request *req,
10916                                  uint32_t flags)
10917 {
10918         struct intel_engine_cs *ring = req->ring;
10919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10920         u32 flip_mask;
10921         int ret;
10922
10923         ret = intel_ring_begin(req, 6);
10924         if (ret)
10925                 return ret;
10926
10927         /* Can't queue multiple flips, so wait for the previous
10928          * one to finish before executing the next.
10929          */
10930         if (intel_crtc->plane)
10931                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10932         else
10933                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10934         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10935         intel_ring_emit(ring, MI_NOOP);
10936         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10937                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10938         intel_ring_emit(ring, fb->pitches[0]);
10939         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10940         intel_ring_emit(ring, 0); /* aux display base address, unused */
10941
10942         intel_mark_page_flip_active(intel_crtc);
10943         return 0;
10944 }
10945
10946 static int intel_gen3_queue_flip(struct drm_device *dev,
10947                                  struct drm_crtc *crtc,
10948                                  struct drm_framebuffer *fb,
10949                                  struct drm_i915_gem_object *obj,
10950                                  struct drm_i915_gem_request *req,
10951                                  uint32_t flags)
10952 {
10953         struct intel_engine_cs *ring = req->ring;
10954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10955         u32 flip_mask;
10956         int ret;
10957
10958         ret = intel_ring_begin(req, 6);
10959         if (ret)
10960                 return ret;
10961
10962         if (intel_crtc->plane)
10963                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10964         else
10965                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10966         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10967         intel_ring_emit(ring, MI_NOOP);
10968         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970         intel_ring_emit(ring, fb->pitches[0]);
10971         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972         intel_ring_emit(ring, MI_NOOP);
10973
10974         intel_mark_page_flip_active(intel_crtc);
10975         return 0;
10976 }
10977
10978 static int intel_gen4_queue_flip(struct drm_device *dev,
10979                                  struct drm_crtc *crtc,
10980                                  struct drm_framebuffer *fb,
10981                                  struct drm_i915_gem_object *obj,
10982                                  struct drm_i915_gem_request *req,
10983                                  uint32_t flags)
10984 {
10985         struct intel_engine_cs *ring = req->ring;
10986         struct drm_i915_private *dev_priv = dev->dev_private;
10987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10988         uint32_t pf, pipesrc;
10989         int ret;
10990
10991         ret = intel_ring_begin(req, 4);
10992         if (ret)
10993                 return ret;
10994
10995         /* i965+ uses the linear or tiled offsets from the
10996          * Display Registers (which do not change across a page-flip)
10997          * so we need only reprogram the base address.
10998          */
10999         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11000                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11001         intel_ring_emit(ring, fb->pitches[0]);
11002         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11003                         obj->tiling_mode);
11004
11005         /* XXX Enabling the panel-fitter across page-flip is so far
11006          * untested on non-native modes, so ignore it for now.
11007          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11008          */
11009         pf = 0;
11010         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11011         intel_ring_emit(ring, pf | pipesrc);
11012
11013         intel_mark_page_flip_active(intel_crtc);
11014         return 0;
11015 }
11016
11017 static int intel_gen6_queue_flip(struct drm_device *dev,
11018                                  struct drm_crtc *crtc,
11019                                  struct drm_framebuffer *fb,
11020                                  struct drm_i915_gem_object *obj,
11021                                  struct drm_i915_gem_request *req,
11022                                  uint32_t flags)
11023 {
11024         struct intel_engine_cs *ring = req->ring;
11025         struct drm_i915_private *dev_priv = dev->dev_private;
11026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11027         uint32_t pf, pipesrc;
11028         int ret;
11029
11030         ret = intel_ring_begin(req, 4);
11031         if (ret)
11032                 return ret;
11033
11034         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11035                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11036         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11037         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11038
11039         /* Contrary to the suggestions in the documentation,
11040          * "Enable Panel Fitter" does not seem to be required when page
11041          * flipping with a non-native mode, and worse causes a normal
11042          * modeset to fail.
11043          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11044          */
11045         pf = 0;
11046         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11047         intel_ring_emit(ring, pf | pipesrc);
11048
11049         intel_mark_page_flip_active(intel_crtc);
11050         return 0;
11051 }
11052
11053 static int intel_gen7_queue_flip(struct drm_device *dev,
11054                                  struct drm_crtc *crtc,
11055                                  struct drm_framebuffer *fb,
11056                                  struct drm_i915_gem_object *obj,
11057                                  struct drm_i915_gem_request *req,
11058                                  uint32_t flags)
11059 {
11060         struct intel_engine_cs *ring = req->ring;
11061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11062         uint32_t plane_bit = 0;
11063         int len, ret;
11064
11065         switch (intel_crtc->plane) {
11066         case PLANE_A:
11067                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11068                 break;
11069         case PLANE_B:
11070                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11071                 break;
11072         case PLANE_C:
11073                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11074                 break;
11075         default:
11076                 WARN_ONCE(1, "unknown plane in flip command\n");
11077                 return -ENODEV;
11078         }
11079
11080         len = 4;
11081         if (ring->id == RCS) {
11082                 len += 6;
11083                 /*
11084                  * On Gen 8, SRM is now taking an extra dword to accommodate
11085                  * 48bits addresses, and we need a NOOP for the batch size to
11086                  * stay even.
11087                  */
11088                 if (IS_GEN8(dev))
11089                         len += 2;
11090         }
11091
11092         /*
11093          * BSpec MI_DISPLAY_FLIP for IVB:
11094          * "The full packet must be contained within the same cache line."
11095          *
11096          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11097          * cacheline, if we ever start emitting more commands before
11098          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11099          * then do the cacheline alignment, and finally emit the
11100          * MI_DISPLAY_FLIP.
11101          */
11102         ret = intel_ring_cacheline_align(req);
11103         if (ret)
11104                 return ret;
11105
11106         ret = intel_ring_begin(req, len);
11107         if (ret)
11108                 return ret;
11109
11110         /* Unmask the flip-done completion message. Note that the bspec says that
11111          * we should do this for both the BCS and RCS, and that we must not unmask
11112          * more than one flip event at any time (or ensure that one flip message
11113          * can be sent by waiting for flip-done prior to queueing new flips).
11114          * Experimentation says that BCS works despite DERRMR masking all
11115          * flip-done completion events and that unmasking all planes at once
11116          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11117          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11118          */
11119         if (ring->id == RCS) {
11120                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11121                 intel_ring_emit(ring, DERRMR);
11122                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11123                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11124                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11125                 if (IS_GEN8(dev))
11126                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11127                                               MI_SRM_LRM_GLOBAL_GTT);
11128                 else
11129                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11130                                               MI_SRM_LRM_GLOBAL_GTT);
11131                 intel_ring_emit(ring, DERRMR);
11132                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11133                 if (IS_GEN8(dev)) {
11134                         intel_ring_emit(ring, 0);
11135                         intel_ring_emit(ring, MI_NOOP);
11136                 }
11137         }
11138
11139         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11140         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11141         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11142         intel_ring_emit(ring, (MI_NOOP));
11143
11144         intel_mark_page_flip_active(intel_crtc);
11145         return 0;
11146 }
11147
11148 static bool use_mmio_flip(struct intel_engine_cs *ring,
11149                           struct drm_i915_gem_object *obj)
11150 {
11151         /*
11152          * This is not being used for older platforms, because
11153          * non-availability of flip done interrupt forces us to use
11154          * CS flips. Older platforms derive flip done using some clever
11155          * tricks involving the flip_pending status bits and vblank irqs.
11156          * So using MMIO flips there would disrupt this mechanism.
11157          */
11158
11159         if (ring == NULL)
11160                 return true;
11161
11162         if (INTEL_INFO(ring->dev)->gen < 5)
11163                 return false;
11164
11165         if (i915.use_mmio_flip < 0)
11166                 return false;
11167         else if (i915.use_mmio_flip > 0)
11168                 return true;
11169         else if (i915.enable_execlists)
11170                 return true;
11171         else
11172                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11173 }
11174
11175 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11176 {
11177         struct drm_device *dev = intel_crtc->base.dev;
11178         struct drm_i915_private *dev_priv = dev->dev_private;
11179         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11180         const enum pipe pipe = intel_crtc->pipe;
11181         u32 ctl, stride;
11182
11183         ctl = I915_READ(PLANE_CTL(pipe, 0));
11184         ctl &= ~PLANE_CTL_TILED_MASK;
11185         switch (fb->modifier[0]) {
11186         case DRM_FORMAT_MOD_NONE:
11187                 break;
11188         case I915_FORMAT_MOD_X_TILED:
11189                 ctl |= PLANE_CTL_TILED_X;
11190                 break;
11191         case I915_FORMAT_MOD_Y_TILED:
11192                 ctl |= PLANE_CTL_TILED_Y;
11193                 break;
11194         case I915_FORMAT_MOD_Yf_TILED:
11195                 ctl |= PLANE_CTL_TILED_YF;
11196                 break;
11197         default:
11198                 MISSING_CASE(fb->modifier[0]);
11199         }
11200
11201         /*
11202          * The stride is either expressed as a multiple of 64 bytes chunks for
11203          * linear buffers or in number of tiles for tiled buffers.
11204          */
11205         stride = fb->pitches[0] /
11206                  intel_fb_stride_alignment(dev, fb->modifier[0],
11207                                            fb->pixel_format);
11208
11209         /*
11210          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11211          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11212          */
11213         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11214         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11215
11216         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11217         POSTING_READ(PLANE_SURF(pipe, 0));
11218 }
11219
11220 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11221 {
11222         struct drm_device *dev = intel_crtc->base.dev;
11223         struct drm_i915_private *dev_priv = dev->dev_private;
11224         struct intel_framebuffer *intel_fb =
11225                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11226         struct drm_i915_gem_object *obj = intel_fb->obj;
11227         u32 dspcntr;
11228         u32 reg;
11229
11230         reg = DSPCNTR(intel_crtc->plane);
11231         dspcntr = I915_READ(reg);
11232
11233         if (obj->tiling_mode != I915_TILING_NONE)
11234                 dspcntr |= DISPPLANE_TILED;
11235         else
11236                 dspcntr &= ~DISPPLANE_TILED;
11237
11238         I915_WRITE(reg, dspcntr);
11239
11240         I915_WRITE(DSPSURF(intel_crtc->plane),
11241                    intel_crtc->unpin_work->gtt_offset);
11242         POSTING_READ(DSPSURF(intel_crtc->plane));
11243
11244 }
11245
11246 /*
11247  * XXX: This is the temporary way to update the plane registers until we get
11248  * around to using the usual plane update functions for MMIO flips
11249  */
11250 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11251 {
11252         struct drm_device *dev = intel_crtc->base.dev;
11253         u32 start_vbl_count;
11254
11255         intel_mark_page_flip_active(intel_crtc);
11256
11257         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11258
11259         if (INTEL_INFO(dev)->gen >= 9)
11260                 skl_do_mmio_flip(intel_crtc);
11261         else
11262                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11263                 ilk_do_mmio_flip(intel_crtc);
11264
11265         intel_pipe_update_end(intel_crtc, start_vbl_count);
11266 }
11267
11268 static void intel_mmio_flip_work_func(struct work_struct *work)
11269 {
11270         struct intel_mmio_flip *mmio_flip =
11271                 container_of(work, struct intel_mmio_flip, work);
11272
11273         if (mmio_flip->req)
11274                 WARN_ON(__i915_wait_request(mmio_flip->req,
11275                                             mmio_flip->crtc->reset_counter,
11276                                             false, NULL,
11277                                             &mmio_flip->i915->rps.mmioflips));
11278
11279         intel_do_mmio_flip(mmio_flip->crtc);
11280
11281         i915_gem_request_unreference__unlocked(mmio_flip->req);
11282         kfree(mmio_flip);
11283 }
11284
11285 static int intel_queue_mmio_flip(struct drm_device *dev,
11286                                  struct drm_crtc *crtc,
11287                                  struct drm_framebuffer *fb,
11288                                  struct drm_i915_gem_object *obj,
11289                                  struct intel_engine_cs *ring,
11290                                  uint32_t flags)
11291 {
11292         struct intel_mmio_flip *mmio_flip;
11293
11294         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11295         if (mmio_flip == NULL)
11296                 return -ENOMEM;
11297
11298         mmio_flip->i915 = to_i915(dev);
11299         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11300         mmio_flip->crtc = to_intel_crtc(crtc);
11301
11302         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11303         schedule_work(&mmio_flip->work);
11304
11305         return 0;
11306 }
11307
11308 static int intel_default_queue_flip(struct drm_device *dev,
11309                                     struct drm_crtc *crtc,
11310                                     struct drm_framebuffer *fb,
11311                                     struct drm_i915_gem_object *obj,
11312                                     struct drm_i915_gem_request *req,
11313                                     uint32_t flags)
11314 {
11315         return -ENODEV;
11316 }
11317
11318 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11319                                          struct drm_crtc *crtc)
11320 {
11321         struct drm_i915_private *dev_priv = dev->dev_private;
11322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11323         struct intel_unpin_work *work = intel_crtc->unpin_work;
11324         u32 addr;
11325
11326         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11327                 return true;
11328
11329         if (!work->enable_stall_check)
11330                 return false;
11331
11332         if (work->flip_ready_vblank == 0) {
11333                 if (work->flip_queued_req &&
11334                     !i915_gem_request_completed(work->flip_queued_req, true))
11335                         return false;
11336
11337                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11338         }
11339
11340         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11341                 return false;
11342
11343         /* Potential stall - if we see that the flip has happened,
11344          * assume a missed interrupt. */
11345         if (INTEL_INFO(dev)->gen >= 4)
11346                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11347         else
11348                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11349
11350         /* There is a potential issue here with a false positive after a flip
11351          * to the same address. We could address this by checking for a
11352          * non-incrementing frame counter.
11353          */
11354         return addr == work->gtt_offset;
11355 }
11356
11357 void intel_check_page_flip(struct drm_device *dev, int pipe)
11358 {
11359         struct drm_i915_private *dev_priv = dev->dev_private;
11360         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11362         struct intel_unpin_work *work;
11363
11364         WARN_ON(!in_interrupt());
11365
11366         if (crtc == NULL)
11367                 return;
11368
11369         spin_lock(&dev->event_lock);
11370         work = intel_crtc->unpin_work;
11371         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11372                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11373                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11374                 page_flip_completed(intel_crtc);
11375                 work = NULL;
11376         }
11377         if (work != NULL &&
11378             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11379                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11380         spin_unlock(&dev->event_lock);
11381 }
11382
11383 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11384                                 struct drm_framebuffer *fb,
11385                                 struct drm_pending_vblank_event *event,
11386                                 uint32_t page_flip_flags)
11387 {
11388         struct drm_device *dev = crtc->dev;
11389         struct drm_i915_private *dev_priv = dev->dev_private;
11390         struct drm_framebuffer *old_fb = crtc->primary->fb;
11391         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11393         struct drm_plane *primary = crtc->primary;
11394         enum pipe pipe = intel_crtc->pipe;
11395         struct intel_unpin_work *work;
11396         struct intel_engine_cs *ring;
11397         bool mmio_flip;
11398         struct drm_i915_gem_request *request = NULL;
11399         int ret;
11400
11401         /*
11402          * drm_mode_page_flip_ioctl() should already catch this, but double
11403          * check to be safe.  In the future we may enable pageflipping from
11404          * a disabled primary plane.
11405          */
11406         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11407                 return -EBUSY;
11408
11409         /* Can't change pixel format via MI display flips. */
11410         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11411                 return -EINVAL;
11412
11413         /*
11414          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11415          * Note that pitch changes could also affect these register.
11416          */
11417         if (INTEL_INFO(dev)->gen > 3 &&
11418             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11419              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11420                 return -EINVAL;
11421
11422         if (i915_terminally_wedged(&dev_priv->gpu_error))
11423                 goto out_hang;
11424
11425         work = kzalloc(sizeof(*work), GFP_KERNEL);
11426         if (work == NULL)
11427                 return -ENOMEM;
11428
11429         work->event = event;
11430         work->crtc = crtc;
11431         work->old_fb = old_fb;
11432         INIT_WORK(&work->work, intel_unpin_work_fn);
11433
11434         ret = drm_crtc_vblank_get(crtc);
11435         if (ret)
11436                 goto free_work;
11437
11438         /* We borrow the event spin lock for protecting unpin_work */
11439         spin_lock_irq(&dev->event_lock);
11440         if (intel_crtc->unpin_work) {
11441                 /* Before declaring the flip queue wedged, check if
11442                  * the hardware completed the operation behind our backs.
11443                  */
11444                 if (__intel_pageflip_stall_check(dev, crtc)) {
11445                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11446                         page_flip_completed(intel_crtc);
11447                 } else {
11448                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11449                         spin_unlock_irq(&dev->event_lock);
11450
11451                         drm_crtc_vblank_put(crtc);
11452                         kfree(work);
11453                         return -EBUSY;
11454                 }
11455         }
11456         intel_crtc->unpin_work = work;
11457         spin_unlock_irq(&dev->event_lock);
11458
11459         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11460                 flush_workqueue(dev_priv->wq);
11461
11462         /* Reference the objects for the scheduled work. */
11463         drm_framebuffer_reference(work->old_fb);
11464         drm_gem_object_reference(&obj->base);
11465
11466         crtc->primary->fb = fb;
11467         update_state_fb(crtc->primary);
11468
11469         work->pending_flip_obj = obj;
11470
11471         ret = i915_mutex_lock_interruptible(dev);
11472         if (ret)
11473                 goto cleanup;
11474
11475         atomic_inc(&intel_crtc->unpin_work_count);
11476         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11477
11478         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11479                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11480
11481         if (IS_VALLEYVIEW(dev)) {
11482                 ring = &dev_priv->ring[BCS];
11483                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11484                         /* vlv: DISPLAY_FLIP fails to change tiling */
11485                         ring = NULL;
11486         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11487                 ring = &dev_priv->ring[BCS];
11488         } else if (INTEL_INFO(dev)->gen >= 7) {
11489                 ring = i915_gem_request_get_ring(obj->last_write_req);
11490                 if (ring == NULL || ring->id != RCS)
11491                         ring = &dev_priv->ring[BCS];
11492         } else {
11493                 ring = &dev_priv->ring[RCS];
11494         }
11495
11496         mmio_flip = use_mmio_flip(ring, obj);
11497
11498         /* When using CS flips, we want to emit semaphores between rings.
11499          * However, when using mmio flips we will create a task to do the
11500          * synchronisation, so all we want here is to pin the framebuffer
11501          * into the display plane and skip any waits.
11502          */
11503         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11504                                          crtc->primary->state,
11505                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11506         if (ret)
11507                 goto cleanup_pending;
11508
11509         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11510                                                   + intel_crtc->dspaddr_offset;
11511
11512         if (mmio_flip) {
11513                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11514                                             page_flip_flags);
11515                 if (ret)
11516                         goto cleanup_unpin;
11517
11518                 i915_gem_request_assign(&work->flip_queued_req,
11519                                         obj->last_write_req);
11520         } else {
11521                 if (!request) {
11522                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11523                         if (ret)
11524                                 goto cleanup_unpin;
11525                 }
11526
11527                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11528                                                    page_flip_flags);
11529                 if (ret)
11530                         goto cleanup_unpin;
11531
11532                 i915_gem_request_assign(&work->flip_queued_req, request);
11533         }
11534
11535         if (request)
11536                 i915_add_request_no_flush(request);
11537
11538         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11539         work->enable_stall_check = true;
11540
11541         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11542                           to_intel_plane(primary)->frontbuffer_bit);
11543         mutex_unlock(&dev->struct_mutex);
11544
11545         intel_fbc_disable(dev_priv);
11546         intel_frontbuffer_flip_prepare(dev,
11547                                        to_intel_plane(primary)->frontbuffer_bit);
11548
11549         trace_i915_flip_request(intel_crtc->plane, obj);
11550
11551         return 0;
11552
11553 cleanup_unpin:
11554         intel_unpin_fb_obj(fb, crtc->primary->state);
11555 cleanup_pending:
11556         if (request)
11557                 i915_gem_request_cancel(request);
11558         atomic_dec(&intel_crtc->unpin_work_count);
11559         mutex_unlock(&dev->struct_mutex);
11560 cleanup:
11561         crtc->primary->fb = old_fb;
11562         update_state_fb(crtc->primary);
11563
11564         drm_gem_object_unreference_unlocked(&obj->base);
11565         drm_framebuffer_unreference(work->old_fb);
11566
11567         spin_lock_irq(&dev->event_lock);
11568         intel_crtc->unpin_work = NULL;
11569         spin_unlock_irq(&dev->event_lock);
11570
11571         drm_crtc_vblank_put(crtc);
11572 free_work:
11573         kfree(work);
11574
11575         if (ret == -EIO) {
11576                 struct drm_atomic_state *state;
11577                 struct drm_plane_state *plane_state;
11578
11579 out_hang:
11580                 state = drm_atomic_state_alloc(dev);
11581                 if (!state)
11582                         return -ENOMEM;
11583                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11584
11585 retry:
11586                 plane_state = drm_atomic_get_plane_state(state, primary);
11587                 ret = PTR_ERR_OR_ZERO(plane_state);
11588                 if (!ret) {
11589                         drm_atomic_set_fb_for_plane(plane_state, fb);
11590
11591                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11592                         if (!ret)
11593                                 ret = drm_atomic_commit(state);
11594                 }
11595
11596                 if (ret == -EDEADLK) {
11597                         drm_modeset_backoff(state->acquire_ctx);
11598                         drm_atomic_state_clear(state);
11599                         goto retry;
11600                 }
11601
11602                 if (ret)
11603                         drm_atomic_state_free(state);
11604
11605                 if (ret == 0 && event) {
11606                         spin_lock_irq(&dev->event_lock);
11607                         drm_send_vblank_event(dev, pipe, event);
11608                         spin_unlock_irq(&dev->event_lock);
11609                 }
11610         }
11611         return ret;
11612 }
11613
11614
11615 /**
11616  * intel_wm_need_update - Check whether watermarks need updating
11617  * @plane: drm plane
11618  * @state: new plane state
11619  *
11620  * Check current plane state versus the new one to determine whether
11621  * watermarks need to be recalculated.
11622  *
11623  * Returns true or false.
11624  */
11625 static bool intel_wm_need_update(struct drm_plane *plane,
11626                                  struct drm_plane_state *state)
11627 {
11628         /* Update watermarks on tiling changes. */
11629         if (!plane->state->fb || !state->fb ||
11630             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11631             plane->state->rotation != state->rotation)
11632                 return true;
11633
11634         if (plane->state->crtc_w != state->crtc_w)
11635                 return true;
11636
11637         return false;
11638 }
11639
11640 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11641                                     struct drm_plane_state *plane_state)
11642 {
11643         struct drm_crtc *crtc = crtc_state->crtc;
11644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11645         struct drm_plane *plane = plane_state->plane;
11646         struct drm_device *dev = crtc->dev;
11647         struct drm_i915_private *dev_priv = dev->dev_private;
11648         struct intel_plane_state *old_plane_state =
11649                 to_intel_plane_state(plane->state);
11650         int idx = intel_crtc->base.base.id, ret;
11651         int i = drm_plane_index(plane);
11652         bool mode_changed = needs_modeset(crtc_state);
11653         bool was_crtc_enabled = crtc->state->active;
11654         bool is_crtc_enabled = crtc_state->active;
11655
11656         bool turn_off, turn_on, visible, was_visible;
11657         struct drm_framebuffer *fb = plane_state->fb;
11658
11659         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11660             plane->type != DRM_PLANE_TYPE_CURSOR) {
11661                 ret = skl_update_scaler_plane(
11662                         to_intel_crtc_state(crtc_state),
11663                         to_intel_plane_state(plane_state));
11664                 if (ret)
11665                         return ret;
11666         }
11667
11668         /*
11669          * Disabling a plane is always okay; we just need to update
11670          * fb tracking in a special way since cleanup_fb() won't
11671          * get called by the plane helpers.
11672          */
11673         if (old_plane_state->base.fb && !fb)
11674                 intel_crtc->atomic.disabled_planes |= 1 << i;
11675
11676         was_visible = old_plane_state->visible;
11677         visible = to_intel_plane_state(plane_state)->visible;
11678
11679         if (!was_crtc_enabled && WARN_ON(was_visible))
11680                 was_visible = false;
11681
11682         if (!is_crtc_enabled && WARN_ON(visible))
11683                 visible = false;
11684
11685         if (!was_visible && !visible)
11686                 return 0;
11687
11688         turn_off = was_visible && (!visible || mode_changed);
11689         turn_on = visible && (!was_visible || mode_changed);
11690
11691         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11692                          plane->base.id, fb ? fb->base.id : -1);
11693
11694         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11695                          plane->base.id, was_visible, visible,
11696                          turn_off, turn_on, mode_changed);
11697
11698         if (turn_on) {
11699                 intel_crtc->atomic.update_wm_pre = true;
11700                 /* must disable cxsr around plane enable/disable */
11701                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11702                         intel_crtc->atomic.disable_cxsr = true;
11703                         /* to potentially re-enable cxsr */
11704                         intel_crtc->atomic.wait_vblank = true;
11705                         intel_crtc->atomic.update_wm_post = true;
11706                 }
11707         } else if (turn_off) {
11708                 intel_crtc->atomic.update_wm_post = true;
11709                 /* must disable cxsr around plane enable/disable */
11710                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11711                         if (is_crtc_enabled)
11712                                 intel_crtc->atomic.wait_vblank = true;
11713                         intel_crtc->atomic.disable_cxsr = true;
11714                 }
11715         } else if (intel_wm_need_update(plane, plane_state)) {
11716                 intel_crtc->atomic.update_wm_pre = true;
11717         }
11718
11719         if (visible)
11720                 intel_crtc->atomic.fb_bits |=
11721                         to_intel_plane(plane)->frontbuffer_bit;
11722
11723         switch (plane->type) {
11724         case DRM_PLANE_TYPE_PRIMARY:
11725                 intel_crtc->atomic.wait_for_flips = true;
11726                 intel_crtc->atomic.pre_disable_primary = turn_off;
11727                 intel_crtc->atomic.post_enable_primary = turn_on;
11728
11729                 if (turn_off) {
11730                         /*
11731                          * FIXME: Actually if we will still have any other
11732                          * plane enabled on the pipe we could let IPS enabled
11733                          * still, but for now lets consider that when we make
11734                          * primary invisible by setting DSPCNTR to 0 on
11735                          * update_primary_plane function IPS needs to be
11736                          * disable.
11737                          */
11738                         intel_crtc->atomic.disable_ips = true;
11739
11740                         intel_crtc->atomic.disable_fbc = true;
11741                 }
11742
11743                 /*
11744                  * FBC does not work on some platforms for rotated
11745                  * planes, so disable it when rotation is not 0 and
11746                  * update it when rotation is set back to 0.
11747                  *
11748                  * FIXME: This is redundant with the fbc update done in
11749                  * the primary plane enable function except that that
11750                  * one is done too late. We eventually need to unify
11751                  * this.
11752                  */
11753
11754                 if (visible &&
11755                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11756                     dev_priv->fbc.crtc == intel_crtc &&
11757                     plane_state->rotation != BIT(DRM_ROTATE_0))
11758                         intel_crtc->atomic.disable_fbc = true;
11759
11760                 /*
11761                  * BDW signals flip done immediately if the plane
11762                  * is disabled, even if the plane enable is already
11763                  * armed to occur at the next vblank :(
11764                  */
11765                 if (turn_on && IS_BROADWELL(dev))
11766                         intel_crtc->atomic.wait_vblank = true;
11767
11768                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11769                 break;
11770         case DRM_PLANE_TYPE_CURSOR:
11771                 break;
11772         case DRM_PLANE_TYPE_OVERLAY:
11773                 if (turn_off && !mode_changed) {
11774                         intel_crtc->atomic.wait_vblank = true;
11775                         intel_crtc->atomic.update_sprite_watermarks |=
11776                                 1 << i;
11777                 }
11778         }
11779         return 0;
11780 }
11781
11782 static bool encoders_cloneable(const struct intel_encoder *a,
11783                                const struct intel_encoder *b)
11784 {
11785         /* masks could be asymmetric, so check both ways */
11786         return a == b || (a->cloneable & (1 << b->type) &&
11787                           b->cloneable & (1 << a->type));
11788 }
11789
11790 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11791                                          struct intel_crtc *crtc,
11792                                          struct intel_encoder *encoder)
11793 {
11794         struct intel_encoder *source_encoder;
11795         struct drm_connector *connector;
11796         struct drm_connector_state *connector_state;
11797         int i;
11798
11799         for_each_connector_in_state(state, connector, connector_state, i) {
11800                 if (connector_state->crtc != &crtc->base)
11801                         continue;
11802
11803                 source_encoder =
11804                         to_intel_encoder(connector_state->best_encoder);
11805                 if (!encoders_cloneable(encoder, source_encoder))
11806                         return false;
11807         }
11808
11809         return true;
11810 }
11811
11812 static bool check_encoder_cloning(struct drm_atomic_state *state,
11813                                   struct intel_crtc *crtc)
11814 {
11815         struct intel_encoder *encoder;
11816         struct drm_connector *connector;
11817         struct drm_connector_state *connector_state;
11818         int i;
11819
11820         for_each_connector_in_state(state, connector, connector_state, i) {
11821                 if (connector_state->crtc != &crtc->base)
11822                         continue;
11823
11824                 encoder = to_intel_encoder(connector_state->best_encoder);
11825                 if (!check_single_encoder_cloning(state, crtc, encoder))
11826                         return false;
11827         }
11828
11829         return true;
11830 }
11831
11832 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11833                                    struct drm_crtc_state *crtc_state)
11834 {
11835         struct drm_device *dev = crtc->dev;
11836         struct drm_i915_private *dev_priv = dev->dev_private;
11837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11838         struct intel_crtc_state *pipe_config =
11839                 to_intel_crtc_state(crtc_state);
11840         struct drm_atomic_state *state = crtc_state->state;
11841         int ret, idx = crtc->base.id;
11842         bool mode_changed = needs_modeset(crtc_state);
11843
11844         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11845                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11846                 return -EINVAL;
11847         }
11848
11849         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11850                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11851                 idx, crtc->state->active, intel_crtc->active);
11852
11853         if (mode_changed && !crtc_state->active)
11854                 intel_crtc->atomic.update_wm_post = true;
11855
11856         if (mode_changed && crtc_state->enable &&
11857             dev_priv->display.crtc_compute_clock &&
11858             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11859                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11860                                                            pipe_config);
11861                 if (ret)
11862                         return ret;
11863         }
11864
11865         ret = 0;
11866         if (INTEL_INFO(dev)->gen >= 9) {
11867                 if (mode_changed)
11868                         ret = skl_update_scaler_crtc(pipe_config);
11869
11870                 if (!ret)
11871                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11872                                                          pipe_config);
11873         }
11874
11875         return ret;
11876 }
11877
11878 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11879         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11880         .load_lut = intel_crtc_load_lut,
11881         .atomic_begin = intel_begin_crtc_commit,
11882         .atomic_flush = intel_finish_crtc_commit,
11883         .atomic_check = intel_crtc_atomic_check,
11884 };
11885
11886 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11887 {
11888         struct intel_connector *connector;
11889
11890         for_each_intel_connector(dev, connector) {
11891                 if (connector->base.encoder) {
11892                         connector->base.state->best_encoder =
11893                                 connector->base.encoder;
11894                         connector->base.state->crtc =
11895                                 connector->base.encoder->crtc;
11896                 } else {
11897                         connector->base.state->best_encoder = NULL;
11898                         connector->base.state->crtc = NULL;
11899                 }
11900         }
11901 }
11902
11903 static void
11904 connected_sink_compute_bpp(struct intel_connector *connector,
11905                            struct intel_crtc_state *pipe_config)
11906 {
11907         int bpp = pipe_config->pipe_bpp;
11908
11909         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11910                 connector->base.base.id,
11911                 connector->base.name);
11912
11913         /* Don't use an invalid EDID bpc value */
11914         if (connector->base.display_info.bpc &&
11915             connector->base.display_info.bpc * 3 < bpp) {
11916                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11917                               bpp, connector->base.display_info.bpc*3);
11918                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11919         }
11920
11921         /* Clamp bpp to 8 on screens without EDID 1.4 */
11922         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11923                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11924                               bpp);
11925                 pipe_config->pipe_bpp = 24;
11926         }
11927 }
11928
11929 static int
11930 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11931                           struct intel_crtc_state *pipe_config)
11932 {
11933         struct drm_device *dev = crtc->base.dev;
11934         struct drm_atomic_state *state;
11935         struct drm_connector *connector;
11936         struct drm_connector_state *connector_state;
11937         int bpp, i;
11938
11939         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11940                 bpp = 10*3;
11941         else if (INTEL_INFO(dev)->gen >= 5)
11942                 bpp = 12*3;
11943         else
11944                 bpp = 8*3;
11945
11946
11947         pipe_config->pipe_bpp = bpp;
11948
11949         state = pipe_config->base.state;
11950
11951         /* Clamp display bpp to EDID value */
11952         for_each_connector_in_state(state, connector, connector_state, i) {
11953                 if (connector_state->crtc != &crtc->base)
11954                         continue;
11955
11956                 connected_sink_compute_bpp(to_intel_connector(connector),
11957                                            pipe_config);
11958         }
11959
11960         return bpp;
11961 }
11962
11963 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11964 {
11965         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11966                         "type: 0x%x flags: 0x%x\n",
11967                 mode->crtc_clock,
11968                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11969                 mode->crtc_hsync_end, mode->crtc_htotal,
11970                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11971                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11972 }
11973
11974 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11975                                    struct intel_crtc_state *pipe_config,
11976                                    const char *context)
11977 {
11978         struct drm_device *dev = crtc->base.dev;
11979         struct drm_plane *plane;
11980         struct intel_plane *intel_plane;
11981         struct intel_plane_state *state;
11982         struct drm_framebuffer *fb;
11983
11984         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11985                       context, pipe_config, pipe_name(crtc->pipe));
11986
11987         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11988         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11989                       pipe_config->pipe_bpp, pipe_config->dither);
11990         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11991                       pipe_config->has_pch_encoder,
11992                       pipe_config->fdi_lanes,
11993                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11994                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11995                       pipe_config->fdi_m_n.tu);
11996         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11997                       pipe_config->has_dp_encoder,
11998                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11999                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12000                       pipe_config->dp_m_n.tu);
12001
12002         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12003                       pipe_config->has_dp_encoder,
12004                       pipe_config->dp_m2_n2.gmch_m,
12005                       pipe_config->dp_m2_n2.gmch_n,
12006                       pipe_config->dp_m2_n2.link_m,
12007                       pipe_config->dp_m2_n2.link_n,
12008                       pipe_config->dp_m2_n2.tu);
12009
12010         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12011                       pipe_config->has_audio,
12012                       pipe_config->has_infoframe);
12013
12014         DRM_DEBUG_KMS("requested mode:\n");
12015         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12016         DRM_DEBUG_KMS("adjusted mode:\n");
12017         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12018         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12019         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12020         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12021                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12022         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12023                       crtc->num_scalers,
12024                       pipe_config->scaler_state.scaler_users,
12025                       pipe_config->scaler_state.scaler_id);
12026         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12027                       pipe_config->gmch_pfit.control,
12028                       pipe_config->gmch_pfit.pgm_ratios,
12029                       pipe_config->gmch_pfit.lvds_border_bits);
12030         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12031                       pipe_config->pch_pfit.pos,
12032                       pipe_config->pch_pfit.size,
12033                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12034         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12035         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12036
12037         if (IS_BROXTON(dev)) {
12038                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12039                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12040                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12041                               pipe_config->ddi_pll_sel,
12042                               pipe_config->dpll_hw_state.ebb0,
12043                               pipe_config->dpll_hw_state.ebb4,
12044                               pipe_config->dpll_hw_state.pll0,
12045                               pipe_config->dpll_hw_state.pll1,
12046                               pipe_config->dpll_hw_state.pll2,
12047                               pipe_config->dpll_hw_state.pll3,
12048                               pipe_config->dpll_hw_state.pll6,
12049                               pipe_config->dpll_hw_state.pll8,
12050                               pipe_config->dpll_hw_state.pll9,
12051                               pipe_config->dpll_hw_state.pll10,
12052                               pipe_config->dpll_hw_state.pcsdw12);
12053         } else if (IS_SKYLAKE(dev)) {
12054                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12055                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12056                               pipe_config->ddi_pll_sel,
12057                               pipe_config->dpll_hw_state.ctrl1,
12058                               pipe_config->dpll_hw_state.cfgcr1,
12059                               pipe_config->dpll_hw_state.cfgcr2);
12060         } else if (HAS_DDI(dev)) {
12061                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12062                               pipe_config->ddi_pll_sel,
12063                               pipe_config->dpll_hw_state.wrpll);
12064         } else {
12065                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12066                               "fp0: 0x%x, fp1: 0x%x\n",
12067                               pipe_config->dpll_hw_state.dpll,
12068                               pipe_config->dpll_hw_state.dpll_md,
12069                               pipe_config->dpll_hw_state.fp0,
12070                               pipe_config->dpll_hw_state.fp1);
12071         }
12072
12073         DRM_DEBUG_KMS("planes on this crtc\n");
12074         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12075                 intel_plane = to_intel_plane(plane);
12076                 if (intel_plane->pipe != crtc->pipe)
12077                         continue;
12078
12079                 state = to_intel_plane_state(plane->state);
12080                 fb = state->base.fb;
12081                 if (!fb) {
12082                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12083                                 "disabled, scaler_id = %d\n",
12084                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12085                                 plane->base.id, intel_plane->pipe,
12086                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12087                                 drm_plane_index(plane), state->scaler_id);
12088                         continue;
12089                 }
12090
12091                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12092                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12093                         plane->base.id, intel_plane->pipe,
12094                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12095                         drm_plane_index(plane));
12096                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12097                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12098                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12099                         state->scaler_id,
12100                         state->src.x1 >> 16, state->src.y1 >> 16,
12101                         drm_rect_width(&state->src) >> 16,
12102                         drm_rect_height(&state->src) >> 16,
12103                         state->dst.x1, state->dst.y1,
12104                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12105         }
12106 }
12107
12108 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12109 {
12110         struct drm_device *dev = state->dev;
12111         struct intel_encoder *encoder;
12112         struct drm_connector *connector;
12113         struct drm_connector_state *connector_state;
12114         unsigned int used_ports = 0;
12115         int i;
12116
12117         /*
12118          * Walk the connector list instead of the encoder
12119          * list to detect the problem on ddi platforms
12120          * where there's just one encoder per digital port.
12121          */
12122         for_each_connector_in_state(state, connector, connector_state, i) {
12123                 if (!connector_state->best_encoder)
12124                         continue;
12125
12126                 encoder = to_intel_encoder(connector_state->best_encoder);
12127
12128                 WARN_ON(!connector_state->crtc);
12129
12130                 switch (encoder->type) {
12131                         unsigned int port_mask;
12132                 case INTEL_OUTPUT_UNKNOWN:
12133                         if (WARN_ON(!HAS_DDI(dev)))
12134                                 break;
12135                 case INTEL_OUTPUT_DISPLAYPORT:
12136                 case INTEL_OUTPUT_HDMI:
12137                 case INTEL_OUTPUT_EDP:
12138                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12139
12140                         /* the same port mustn't appear more than once */
12141                         if (used_ports & port_mask)
12142                                 return false;
12143
12144                         used_ports |= port_mask;
12145                 default:
12146                         break;
12147                 }
12148         }
12149
12150         return true;
12151 }
12152
12153 static void
12154 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12155 {
12156         struct drm_crtc_state tmp_state;
12157         struct intel_crtc_scaler_state scaler_state;
12158         struct intel_dpll_hw_state dpll_hw_state;
12159         enum intel_dpll_id shared_dpll;
12160         uint32_t ddi_pll_sel;
12161
12162         /* FIXME: before the switch to atomic started, a new pipe_config was
12163          * kzalloc'd. Code that depends on any field being zero should be
12164          * fixed, so that the crtc_state can be safely duplicated. For now,
12165          * only fields that are know to not cause problems are preserved. */
12166
12167         tmp_state = crtc_state->base;
12168         scaler_state = crtc_state->scaler_state;
12169         shared_dpll = crtc_state->shared_dpll;
12170         dpll_hw_state = crtc_state->dpll_hw_state;
12171         ddi_pll_sel = crtc_state->ddi_pll_sel;
12172
12173         memset(crtc_state, 0, sizeof *crtc_state);
12174
12175         crtc_state->base = tmp_state;
12176         crtc_state->scaler_state = scaler_state;
12177         crtc_state->shared_dpll = shared_dpll;
12178         crtc_state->dpll_hw_state = dpll_hw_state;
12179         crtc_state->ddi_pll_sel = ddi_pll_sel;
12180 }
12181
12182 static int
12183 intel_modeset_pipe_config(struct drm_crtc *crtc,
12184                           struct intel_crtc_state *pipe_config)
12185 {
12186         struct drm_atomic_state *state = pipe_config->base.state;
12187         struct intel_encoder *encoder;
12188         struct drm_connector *connector;
12189         struct drm_connector_state *connector_state;
12190         int base_bpp, ret = -EINVAL;
12191         int i;
12192         bool retry = true;
12193
12194         clear_intel_crtc_state(pipe_config);
12195
12196         pipe_config->cpu_transcoder =
12197                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12198
12199         /*
12200          * Sanitize sync polarity flags based on requested ones. If neither
12201          * positive or negative polarity is requested, treat this as meaning
12202          * negative polarity.
12203          */
12204         if (!(pipe_config->base.adjusted_mode.flags &
12205               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12206                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12207
12208         if (!(pipe_config->base.adjusted_mode.flags &
12209               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12210                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12211
12212         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12213          * plane pixel format and any sink constraints into account. Returns the
12214          * source plane bpp so that dithering can be selected on mismatches
12215          * after encoders and crtc also have had their say. */
12216         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12217                                              pipe_config);
12218         if (base_bpp < 0)
12219                 goto fail;
12220
12221         /*
12222          * Determine the real pipe dimensions. Note that stereo modes can
12223          * increase the actual pipe size due to the frame doubling and
12224          * insertion of additional space for blanks between the frame. This
12225          * is stored in the crtc timings. We use the requested mode to do this
12226          * computation to clearly distinguish it from the adjusted mode, which
12227          * can be changed by the connectors in the below retry loop.
12228          */
12229         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12230                                &pipe_config->pipe_src_w,
12231                                &pipe_config->pipe_src_h);
12232
12233 encoder_retry:
12234         /* Ensure the port clock defaults are reset when retrying. */
12235         pipe_config->port_clock = 0;
12236         pipe_config->pixel_multiplier = 1;
12237
12238         /* Fill in default crtc timings, allow encoders to overwrite them. */
12239         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12240                               CRTC_STEREO_DOUBLE);
12241
12242         /* Pass our mode to the connectors and the CRTC to give them a chance to
12243          * adjust it according to limitations or connector properties, and also
12244          * a chance to reject the mode entirely.
12245          */
12246         for_each_connector_in_state(state, connector, connector_state, i) {
12247                 if (connector_state->crtc != crtc)
12248                         continue;
12249
12250                 encoder = to_intel_encoder(connector_state->best_encoder);
12251
12252                 if (!(encoder->compute_config(encoder, pipe_config))) {
12253                         DRM_DEBUG_KMS("Encoder config failure\n");
12254                         goto fail;
12255                 }
12256         }
12257
12258         /* Set default port clock if not overwritten by the encoder. Needs to be
12259          * done afterwards in case the encoder adjusts the mode. */
12260         if (!pipe_config->port_clock)
12261                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12262                         * pipe_config->pixel_multiplier;
12263
12264         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12265         if (ret < 0) {
12266                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12267                 goto fail;
12268         }
12269
12270         if (ret == RETRY) {
12271                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12272                         ret = -EINVAL;
12273                         goto fail;
12274                 }
12275
12276                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12277                 retry = false;
12278                 goto encoder_retry;
12279         }
12280
12281         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12282         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12283                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12284
12285 fail:
12286         return ret;
12287 }
12288
12289 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12290 {
12291         struct drm_encoder *encoder;
12292         struct drm_device *dev = crtc->dev;
12293
12294         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12295                 if (encoder->crtc == crtc)
12296                         return true;
12297
12298         return false;
12299 }
12300
12301 static void
12302 intel_modeset_update_state(struct drm_atomic_state *state)
12303 {
12304         struct drm_device *dev = state->dev;
12305         struct intel_encoder *intel_encoder;
12306         struct drm_crtc *crtc;
12307         struct drm_crtc_state *crtc_state;
12308         struct drm_connector *connector;
12309         int i;
12310
12311         intel_shared_dpll_commit(state);
12312
12313         for_each_intel_encoder(dev, intel_encoder) {
12314                 if (!intel_encoder->base.crtc)
12315                         continue;
12316
12317                 crtc = intel_encoder->base.crtc;
12318                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12319                 if (!crtc_state || !needs_modeset(crtc->state))
12320                         continue;
12321
12322                 intel_encoder->connectors_active = false;
12323         }
12324
12325         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12326
12327         /* Double check state. */
12328         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12329                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12330
12331                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12332
12333                 /* Update hwmode for vblank functions */
12334                 if (crtc->state->active)
12335                         crtc->hwmode = crtc->state->adjusted_mode;
12336                 else
12337                         crtc->hwmode.crtc_clock = 0;
12338         }
12339
12340         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12341                 if (!connector->encoder || !connector->encoder->crtc)
12342                         continue;
12343
12344                 crtc = connector->encoder->crtc;
12345                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12346                 if (!crtc_state || !needs_modeset(crtc->state))
12347                         continue;
12348
12349                 if (crtc->state->active) {
12350                         struct drm_property *dpms_property =
12351                                 dev->mode_config.dpms_property;
12352
12353                         connector->dpms = DRM_MODE_DPMS_ON;
12354                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12355
12356                         intel_encoder = to_intel_encoder(connector->encoder);
12357                         intel_encoder->connectors_active = true;
12358                 } else
12359                         connector->dpms = DRM_MODE_DPMS_OFF;
12360         }
12361 }
12362
12363 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12364 {
12365         int diff;
12366
12367         if (clock1 == clock2)
12368                 return true;
12369
12370         if (!clock1 || !clock2)
12371                 return false;
12372
12373         diff = abs(clock1 - clock2);
12374
12375         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12376                 return true;
12377
12378         return false;
12379 }
12380
12381 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12382         list_for_each_entry((intel_crtc), \
12383                             &(dev)->mode_config.crtc_list, \
12384                             base.head) \
12385                 if (mask & (1 <<(intel_crtc)->pipe))
12386
12387
12388 static bool
12389 intel_compare_m_n(unsigned int m, unsigned int n,
12390                   unsigned int m2, unsigned int n2,
12391                   bool exact)
12392 {
12393         if (m == m2 && n == n2)
12394                 return true;
12395
12396         if (exact || !m || !n || !m2 || !n2)
12397                 return false;
12398
12399         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12400
12401         if (m > m2) {
12402                 while (m > m2) {
12403                         m2 <<= 1;
12404                         n2 <<= 1;
12405                 }
12406         } else if (m < m2) {
12407                 while (m < m2) {
12408                         m <<= 1;
12409                         n <<= 1;
12410                 }
12411         }
12412
12413         return m == m2 && n == n2;
12414 }
12415
12416 static bool
12417 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12418                        struct intel_link_m_n *m2_n2,
12419                        bool adjust)
12420 {
12421         if (m_n->tu == m2_n2->tu &&
12422             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12423                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12424             intel_compare_m_n(m_n->link_m, m_n->link_n,
12425                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12426                 if (adjust)
12427                         *m2_n2 = *m_n;
12428
12429                 return true;
12430         }
12431
12432         return false;
12433 }
12434
12435 static bool
12436 intel_pipe_config_compare(struct drm_device *dev,
12437                           struct intel_crtc_state *current_config,
12438                           struct intel_crtc_state *pipe_config,
12439                           bool adjust)
12440 {
12441         bool ret = true;
12442
12443 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12444         do { \
12445                 if (!adjust) \
12446                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12447                 else \
12448                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12449         } while (0)
12450
12451 #define PIPE_CONF_CHECK_X(name) \
12452         if (current_config->name != pipe_config->name) { \
12453                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12454                           "(expected 0x%08x, found 0x%08x)\n", \
12455                           current_config->name, \
12456                           pipe_config->name); \
12457                 ret = false; \
12458         }
12459
12460 #define PIPE_CONF_CHECK_I(name) \
12461         if (current_config->name != pipe_config->name) { \
12462                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12463                           "(expected %i, found %i)\n", \
12464                           current_config->name, \
12465                           pipe_config->name); \
12466                 ret = false; \
12467         }
12468
12469 #define PIPE_CONF_CHECK_M_N(name) \
12470         if (!intel_compare_link_m_n(&current_config->name, \
12471                                     &pipe_config->name,\
12472                                     adjust)) { \
12473                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12474                           "(expected tu %i gmch %i/%i link %i/%i, " \
12475                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12476                           current_config->name.tu, \
12477                           current_config->name.gmch_m, \
12478                           current_config->name.gmch_n, \
12479                           current_config->name.link_m, \
12480                           current_config->name.link_n, \
12481                           pipe_config->name.tu, \
12482                           pipe_config->name.gmch_m, \
12483                           pipe_config->name.gmch_n, \
12484                           pipe_config->name.link_m, \
12485                           pipe_config->name.link_n); \
12486                 ret = false; \
12487         }
12488
12489 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12490         if (!intel_compare_link_m_n(&current_config->name, \
12491                                     &pipe_config->name, adjust) && \
12492             !intel_compare_link_m_n(&current_config->alt_name, \
12493                                     &pipe_config->name, adjust)) { \
12494                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12495                           "(expected tu %i gmch %i/%i link %i/%i, " \
12496                           "or tu %i gmch %i/%i link %i/%i, " \
12497                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12498                           current_config->name.tu, \
12499                           current_config->name.gmch_m, \
12500                           current_config->name.gmch_n, \
12501                           current_config->name.link_m, \
12502                           current_config->name.link_n, \
12503                           current_config->alt_name.tu, \
12504                           current_config->alt_name.gmch_m, \
12505                           current_config->alt_name.gmch_n, \
12506                           current_config->alt_name.link_m, \
12507                           current_config->alt_name.link_n, \
12508                           pipe_config->name.tu, \
12509                           pipe_config->name.gmch_m, \
12510                           pipe_config->name.gmch_n, \
12511                           pipe_config->name.link_m, \
12512                           pipe_config->name.link_n); \
12513                 ret = false; \
12514         }
12515
12516 /* This is required for BDW+ where there is only one set of registers for
12517  * switching between high and low RR.
12518  * This macro can be used whenever a comparison has to be made between one
12519  * hw state and multiple sw state variables.
12520  */
12521 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12522         if ((current_config->name != pipe_config->name) && \
12523                 (current_config->alt_name != pipe_config->name)) { \
12524                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12525                                   "(expected %i or %i, found %i)\n", \
12526                                   current_config->name, \
12527                                   current_config->alt_name, \
12528                                   pipe_config->name); \
12529                         ret = false; \
12530         }
12531
12532 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12533         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12534                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12535                           "(expected %i, found %i)\n", \
12536                           current_config->name & (mask), \
12537                           pipe_config->name & (mask)); \
12538                 ret = false; \
12539         }
12540
12541 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12542         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12543                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12544                           "(expected %i, found %i)\n", \
12545                           current_config->name, \
12546                           pipe_config->name); \
12547                 ret = false; \
12548         }
12549
12550 #define PIPE_CONF_QUIRK(quirk)  \
12551         ((current_config->quirks | pipe_config->quirks) & (quirk))
12552
12553         PIPE_CONF_CHECK_I(cpu_transcoder);
12554
12555         PIPE_CONF_CHECK_I(has_pch_encoder);
12556         PIPE_CONF_CHECK_I(fdi_lanes);
12557         PIPE_CONF_CHECK_M_N(fdi_m_n);
12558
12559         PIPE_CONF_CHECK_I(has_dp_encoder);
12560
12561         if (INTEL_INFO(dev)->gen < 8) {
12562                 PIPE_CONF_CHECK_M_N(dp_m_n);
12563
12564                 PIPE_CONF_CHECK_I(has_drrs);
12565                 if (current_config->has_drrs)
12566                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12567         } else
12568                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12569
12570         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12571         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12572         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12573         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12574         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12575         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12576
12577         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12578         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12579         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12580         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12581         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12582         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12583
12584         PIPE_CONF_CHECK_I(pixel_multiplier);
12585         PIPE_CONF_CHECK_I(has_hdmi_sink);
12586         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12587             IS_VALLEYVIEW(dev))
12588                 PIPE_CONF_CHECK_I(limited_color_range);
12589         PIPE_CONF_CHECK_I(has_infoframe);
12590
12591         PIPE_CONF_CHECK_I(has_audio);
12592
12593         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12594                               DRM_MODE_FLAG_INTERLACE);
12595
12596         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12597                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12598                                       DRM_MODE_FLAG_PHSYNC);
12599                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12600                                       DRM_MODE_FLAG_NHSYNC);
12601                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12602                                       DRM_MODE_FLAG_PVSYNC);
12603                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12604                                       DRM_MODE_FLAG_NVSYNC);
12605         }
12606
12607         PIPE_CONF_CHECK_I(pipe_src_w);
12608         PIPE_CONF_CHECK_I(pipe_src_h);
12609
12610         /*
12611          * FIXME: BIOS likes to set up a cloned config with lvds+external
12612          * screen. Since we don't yet re-compute the pipe config when moving
12613          * just the lvds port away to another pipe the sw tracking won't match.
12614          *
12615          * Proper atomic modesets with recomputed global state will fix this.
12616          * Until then just don't check gmch state for inherited modes.
12617          */
12618         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12619                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12620                 /* pfit ratios are autocomputed by the hw on gen4+ */
12621                 if (INTEL_INFO(dev)->gen < 4)
12622                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12623                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12624         }
12625
12626         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12627         if (current_config->pch_pfit.enabled) {
12628                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12629                 PIPE_CONF_CHECK_I(pch_pfit.size);
12630         }
12631
12632         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12633
12634         /* BDW+ don't expose a synchronous way to read the state */
12635         if (IS_HASWELL(dev))
12636                 PIPE_CONF_CHECK_I(ips_enabled);
12637
12638         PIPE_CONF_CHECK_I(double_wide);
12639
12640         PIPE_CONF_CHECK_X(ddi_pll_sel);
12641
12642         PIPE_CONF_CHECK_I(shared_dpll);
12643         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12644         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12645         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12646         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12647         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12648         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12649         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12650         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12651
12652         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12653                 PIPE_CONF_CHECK_I(pipe_bpp);
12654
12655         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12656         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12657
12658 #undef PIPE_CONF_CHECK_X
12659 #undef PIPE_CONF_CHECK_I
12660 #undef PIPE_CONF_CHECK_I_ALT
12661 #undef PIPE_CONF_CHECK_FLAGS
12662 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12663 #undef PIPE_CONF_QUIRK
12664 #undef INTEL_ERR_OR_DBG_KMS
12665
12666         return ret;
12667 }
12668
12669 static void check_wm_state(struct drm_device *dev)
12670 {
12671         struct drm_i915_private *dev_priv = dev->dev_private;
12672         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12673         struct intel_crtc *intel_crtc;
12674         int plane;
12675
12676         if (INTEL_INFO(dev)->gen < 9)
12677                 return;
12678
12679         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12680         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12681
12682         for_each_intel_crtc(dev, intel_crtc) {
12683                 struct skl_ddb_entry *hw_entry, *sw_entry;
12684                 const enum pipe pipe = intel_crtc->pipe;
12685
12686                 if (!intel_crtc->active)
12687                         continue;
12688
12689                 /* planes */
12690                 for_each_plane(dev_priv, pipe, plane) {
12691                         hw_entry = &hw_ddb.plane[pipe][plane];
12692                         sw_entry = &sw_ddb->plane[pipe][plane];
12693
12694                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12695                                 continue;
12696
12697                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12698                                   "(expected (%u,%u), found (%u,%u))\n",
12699                                   pipe_name(pipe), plane + 1,
12700                                   sw_entry->start, sw_entry->end,
12701                                   hw_entry->start, hw_entry->end);
12702                 }
12703
12704                 /* cursor */
12705                 hw_entry = &hw_ddb.cursor[pipe];
12706                 sw_entry = &sw_ddb->cursor[pipe];
12707
12708                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12709                         continue;
12710
12711                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12712                           "(expected (%u,%u), found (%u,%u))\n",
12713                           pipe_name(pipe),
12714                           sw_entry->start, sw_entry->end,
12715                           hw_entry->start, hw_entry->end);
12716         }
12717 }
12718
12719 static void
12720 check_connector_state(struct drm_device *dev)
12721 {
12722         struct intel_connector *connector;
12723
12724         for_each_intel_connector(dev, connector) {
12725                 struct drm_encoder *encoder = connector->base.encoder;
12726                 struct drm_connector_state *state = connector->base.state;
12727
12728                 /* This also checks the encoder/connector hw state with the
12729                  * ->get_hw_state callbacks. */
12730                 intel_connector_check_state(connector);
12731
12732                 I915_STATE_WARN(state->best_encoder != encoder,
12733                      "connector's staged encoder doesn't match current encoder\n");
12734         }
12735 }
12736
12737 static void
12738 check_encoder_state(struct drm_device *dev)
12739 {
12740         struct intel_encoder *encoder;
12741         struct intel_connector *connector;
12742
12743         for_each_intel_encoder(dev, encoder) {
12744                 bool enabled = false;
12745                 bool active = false;
12746                 enum pipe pipe, tracked_pipe;
12747
12748                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12749                               encoder->base.base.id,
12750                               encoder->base.name);
12751
12752                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12753                      "encoder's active_connectors set, but no crtc\n");
12754
12755                 for_each_intel_connector(dev, connector) {
12756                         if (connector->base.encoder != &encoder->base)
12757                                 continue;
12758                         enabled = true;
12759                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12760                                 active = true;
12761
12762                         I915_STATE_WARN(connector->base.state->crtc !=
12763                                         encoder->base.crtc,
12764                              "connector's crtc doesn't match encoder crtc\n");
12765                 }
12766                 /*
12767                  * for MST connectors if we unplug the connector is gone
12768                  * away but the encoder is still connected to a crtc
12769                  * until a modeset happens in response to the hotplug.
12770                  */
12771                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12772                         continue;
12773
12774                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12775                      "encoder's enabled state mismatch "
12776                      "(expected %i, found %i)\n",
12777                      !!encoder->base.crtc, enabled);
12778                 I915_STATE_WARN(active && !encoder->base.crtc,
12779                      "active encoder with no crtc\n");
12780
12781                 I915_STATE_WARN(encoder->connectors_active != active,
12782                      "encoder's computed active state doesn't match tracked active state "
12783                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12784
12785                 active = encoder->get_hw_state(encoder, &pipe);
12786                 I915_STATE_WARN(active != encoder->connectors_active,
12787                      "encoder's hw state doesn't match sw tracking "
12788                      "(expected %i, found %i)\n",
12789                      encoder->connectors_active, active);
12790
12791                 if (!encoder->base.crtc)
12792                         continue;
12793
12794                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12795                 I915_STATE_WARN(active && pipe != tracked_pipe,
12796                      "active encoder's pipe doesn't match"
12797                      "(expected %i, found %i)\n",
12798                      tracked_pipe, pipe);
12799
12800         }
12801 }
12802
12803 static void
12804 check_crtc_state(struct drm_device *dev)
12805 {
12806         struct drm_i915_private *dev_priv = dev->dev_private;
12807         struct intel_crtc *crtc;
12808         struct intel_encoder *encoder;
12809         struct intel_crtc_state pipe_config;
12810
12811         for_each_intel_crtc(dev, crtc) {
12812                 bool enabled = false;
12813                 bool active = false;
12814
12815                 memset(&pipe_config, 0, sizeof(pipe_config));
12816
12817                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12818                               crtc->base.base.id);
12819
12820                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12821                      "active crtc, but not enabled in sw tracking\n");
12822
12823                 for_each_intel_encoder(dev, encoder) {
12824                         if (encoder->base.crtc != &crtc->base)
12825                                 continue;
12826                         enabled = true;
12827                         if (encoder->connectors_active)
12828                                 active = true;
12829                 }
12830
12831                 I915_STATE_WARN(active != crtc->active,
12832                      "crtc's computed active state doesn't match tracked active state "
12833                      "(expected %i, found %i)\n", active, crtc->active);
12834                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12835                      "crtc's computed enabled state doesn't match tracked enabled state "
12836                      "(expected %i, found %i)\n", enabled,
12837                                 crtc->base.state->enable);
12838
12839                 active = dev_priv->display.get_pipe_config(crtc,
12840                                                            &pipe_config);
12841
12842                 /* hw state is inconsistent with the pipe quirk */
12843                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12844                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12845                         active = crtc->active;
12846
12847                 for_each_intel_encoder(dev, encoder) {
12848                         enum pipe pipe;
12849                         if (encoder->base.crtc != &crtc->base)
12850                                 continue;
12851                         if (encoder->get_hw_state(encoder, &pipe))
12852                                 encoder->get_config(encoder, &pipe_config);
12853                 }
12854
12855                 I915_STATE_WARN(crtc->active != active,
12856                      "crtc active state doesn't match with hw state "
12857                      "(expected %i, found %i)\n", crtc->active, active);
12858
12859                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12860                      "transitional active state does not match atomic hw state "
12861                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12862
12863                 if (!active)
12864                         continue;
12865
12866                 if (!intel_pipe_config_compare(dev, crtc->config,
12867                                                &pipe_config, false)) {
12868                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12869                         intel_dump_pipe_config(crtc, &pipe_config,
12870                                                "[hw state]");
12871                         intel_dump_pipe_config(crtc, crtc->config,
12872                                                "[sw state]");
12873                 }
12874         }
12875 }
12876
12877 static void
12878 check_shared_dpll_state(struct drm_device *dev)
12879 {
12880         struct drm_i915_private *dev_priv = dev->dev_private;
12881         struct intel_crtc *crtc;
12882         struct intel_dpll_hw_state dpll_hw_state;
12883         int i;
12884
12885         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12886                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12887                 int enabled_crtcs = 0, active_crtcs = 0;
12888                 bool active;
12889
12890                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12891
12892                 DRM_DEBUG_KMS("%s\n", pll->name);
12893
12894                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12895
12896                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12897                      "more active pll users than references: %i vs %i\n",
12898                      pll->active, hweight32(pll->config.crtc_mask));
12899                 I915_STATE_WARN(pll->active && !pll->on,
12900                      "pll in active use but not on in sw tracking\n");
12901                 I915_STATE_WARN(pll->on && !pll->active,
12902                      "pll in on but not on in use in sw tracking\n");
12903                 I915_STATE_WARN(pll->on != active,
12904                      "pll on state mismatch (expected %i, found %i)\n",
12905                      pll->on, active);
12906
12907                 for_each_intel_crtc(dev, crtc) {
12908                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12909                                 enabled_crtcs++;
12910                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12911                                 active_crtcs++;
12912                 }
12913                 I915_STATE_WARN(pll->active != active_crtcs,
12914                      "pll active crtcs mismatch (expected %i, found %i)\n",
12915                      pll->active, active_crtcs);
12916                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12917                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12918                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12919
12920                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12921                                        sizeof(dpll_hw_state)),
12922                      "pll hw state mismatch\n");
12923         }
12924 }
12925
12926 void
12927 intel_modeset_check_state(struct drm_device *dev)
12928 {
12929         check_wm_state(dev);
12930         check_connector_state(dev);
12931         check_encoder_state(dev);
12932         check_crtc_state(dev);
12933         check_shared_dpll_state(dev);
12934 }
12935
12936 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12937                                      int dotclock)
12938 {
12939         /*
12940          * FDI already provided one idea for the dotclock.
12941          * Yell if the encoder disagrees.
12942          */
12943         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12944              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12945              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12946 }
12947
12948 static void update_scanline_offset(struct intel_crtc *crtc)
12949 {
12950         struct drm_device *dev = crtc->base.dev;
12951
12952         /*
12953          * The scanline counter increments at the leading edge of hsync.
12954          *
12955          * On most platforms it starts counting from vtotal-1 on the
12956          * first active line. That means the scanline counter value is
12957          * always one less than what we would expect. Ie. just after
12958          * start of vblank, which also occurs at start of hsync (on the
12959          * last active line), the scanline counter will read vblank_start-1.
12960          *
12961          * On gen2 the scanline counter starts counting from 1 instead
12962          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12963          * to keep the value positive), instead of adding one.
12964          *
12965          * On HSW+ the behaviour of the scanline counter depends on the output
12966          * type. For DP ports it behaves like most other platforms, but on HDMI
12967          * there's an extra 1 line difference. So we need to add two instead of
12968          * one to the value.
12969          */
12970         if (IS_GEN2(dev)) {
12971                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12972                 int vtotal;
12973
12974                 vtotal = mode->crtc_vtotal;
12975                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12976                         vtotal /= 2;
12977
12978                 crtc->scanline_offset = vtotal - 1;
12979         } else if (HAS_DDI(dev) &&
12980                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12981                 crtc->scanline_offset = 2;
12982         } else
12983                 crtc->scanline_offset = 1;
12984 }
12985
12986 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12987 {
12988         struct drm_device *dev = state->dev;
12989         struct drm_i915_private *dev_priv = to_i915(dev);
12990         struct intel_shared_dpll_config *shared_dpll = NULL;
12991         struct intel_crtc *intel_crtc;
12992         struct intel_crtc_state *intel_crtc_state;
12993         struct drm_crtc *crtc;
12994         struct drm_crtc_state *crtc_state;
12995         int i;
12996
12997         if (!dev_priv->display.crtc_compute_clock)
12998                 return;
12999
13000         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13001                 int dpll;
13002
13003                 intel_crtc = to_intel_crtc(crtc);
13004                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13005                 dpll = intel_crtc_state->shared_dpll;
13006
13007                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13008                         continue;
13009
13010                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13011
13012                 if (!shared_dpll)
13013                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13014
13015                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13016         }
13017 }
13018
13019 /*
13020  * This implements the workaround described in the "notes" section of the mode
13021  * set sequence documentation. When going from no pipes or single pipe to
13022  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13023  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13024  */
13025 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13026 {
13027         struct drm_crtc_state *crtc_state;
13028         struct intel_crtc *intel_crtc;
13029         struct drm_crtc *crtc;
13030         struct intel_crtc_state *first_crtc_state = NULL;
13031         struct intel_crtc_state *other_crtc_state = NULL;
13032         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13033         int i;
13034
13035         /* look at all crtc's that are going to be enabled in during modeset */
13036         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13037                 intel_crtc = to_intel_crtc(crtc);
13038
13039                 if (!crtc_state->active || !needs_modeset(crtc_state))
13040                         continue;
13041
13042                 if (first_crtc_state) {
13043                         other_crtc_state = to_intel_crtc_state(crtc_state);
13044                         break;
13045                 } else {
13046                         first_crtc_state = to_intel_crtc_state(crtc_state);
13047                         first_pipe = intel_crtc->pipe;
13048                 }
13049         }
13050
13051         /* No workaround needed? */
13052         if (!first_crtc_state)
13053                 return 0;
13054
13055         /* w/a possibly needed, check how many crtc's are already enabled. */
13056         for_each_intel_crtc(state->dev, intel_crtc) {
13057                 struct intel_crtc_state *pipe_config;
13058
13059                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13060                 if (IS_ERR(pipe_config))
13061                         return PTR_ERR(pipe_config);
13062
13063                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13064
13065                 if (!pipe_config->base.active ||
13066                     needs_modeset(&pipe_config->base))
13067                         continue;
13068
13069                 /* 2 or more enabled crtcs means no need for w/a */
13070                 if (enabled_pipe != INVALID_PIPE)
13071                         return 0;
13072
13073                 enabled_pipe = intel_crtc->pipe;
13074         }
13075
13076         if (enabled_pipe != INVALID_PIPE)
13077                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13078         else if (other_crtc_state)
13079                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13080
13081         return 0;
13082 }
13083
13084 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13085 {
13086         struct drm_crtc *crtc;
13087         struct drm_crtc_state *crtc_state;
13088         int ret = 0;
13089
13090         /* add all active pipes to the state */
13091         for_each_crtc(state->dev, crtc) {
13092                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13093                 if (IS_ERR(crtc_state))
13094                         return PTR_ERR(crtc_state);
13095
13096                 if (!crtc_state->active || needs_modeset(crtc_state))
13097                         continue;
13098
13099                 crtc_state->mode_changed = true;
13100
13101                 ret = drm_atomic_add_affected_connectors(state, crtc);
13102                 if (ret)
13103                         break;
13104
13105                 ret = drm_atomic_add_affected_planes(state, crtc);
13106                 if (ret)
13107                         break;
13108         }
13109
13110         return ret;
13111 }
13112
13113
13114 static int intel_modeset_checks(struct drm_atomic_state *state)
13115 {
13116         struct drm_device *dev = state->dev;
13117         struct drm_i915_private *dev_priv = dev->dev_private;
13118         int ret;
13119
13120         if (!check_digital_port_conflicts(state)) {
13121                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13122                 return -EINVAL;
13123         }
13124
13125         /*
13126          * See if the config requires any additional preparation, e.g.
13127          * to adjust global state with pipes off.  We need to do this
13128          * here so we can get the modeset_pipe updated config for the new
13129          * mode set on this crtc.  For other crtcs we need to use the
13130          * adjusted_mode bits in the crtc directly.
13131          */
13132         if (dev_priv->display.modeset_calc_cdclk) {
13133                 unsigned int cdclk;
13134
13135                 ret = dev_priv->display.modeset_calc_cdclk(state);
13136
13137                 cdclk = to_intel_atomic_state(state)->cdclk;
13138                 if (!ret && cdclk != dev_priv->cdclk_freq)
13139                         ret = intel_modeset_all_pipes(state);
13140
13141                 if (ret < 0)
13142                         return ret;
13143         } else
13144                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13145
13146         intel_modeset_clear_plls(state);
13147
13148         if (IS_HASWELL(dev))
13149                 return haswell_mode_set_planes_workaround(state);
13150
13151         return 0;
13152 }
13153
13154 /**
13155  * intel_atomic_check - validate state object
13156  * @dev: drm device
13157  * @state: state to validate
13158  */
13159 static int intel_atomic_check(struct drm_device *dev,
13160                               struct drm_atomic_state *state)
13161 {
13162         struct drm_crtc *crtc;
13163         struct drm_crtc_state *crtc_state;
13164         int ret, i;
13165         bool any_ms = false;
13166
13167         ret = drm_atomic_helper_check_modeset(dev, state);
13168         if (ret)
13169                 return ret;
13170
13171         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13172                 struct intel_crtc_state *pipe_config =
13173                         to_intel_crtc_state(crtc_state);
13174                 bool modeset, recalc = false;
13175
13176                 if (!crtc_state->enable) {
13177                         if (needs_modeset(crtc_state))
13178                                 any_ms = true;
13179                         continue;
13180                 }
13181
13182                 modeset = needs_modeset(crtc_state);
13183                 /* see comment in intel_modeset_readout_hw_state */
13184                 if (!modeset && crtc_state->mode_blob != crtc->state->mode_blob &&
13185                     pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE)
13186                         recalc = true;
13187
13188                 if (!modeset && !recalc)
13189                         continue;
13190
13191                 if (recalc) {
13192                         ret = drm_atomic_add_affected_connectors(state, crtc);
13193                         if (ret)
13194                                 return ret;
13195                 }
13196
13197                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13198                 if (ret)
13199                         return ret;
13200
13201                 if (recalc && (!i915.fastboot ||
13202                     !intel_pipe_config_compare(state->dev,
13203                                         to_intel_crtc_state(crtc->state),
13204                                         pipe_config, true))) {
13205                         modeset = crtc_state->mode_changed = true;
13206
13207                         ret = drm_atomic_add_affected_planes(state, crtc);
13208                         if (ret)
13209                                 return ret;
13210                 }
13211
13212                 any_ms = modeset;
13213                 intel_dump_pipe_config(to_intel_crtc(crtc),
13214                                        pipe_config,
13215                                        modeset ? "[modeset]" : "[fastboot]");
13216         }
13217
13218         if (any_ms) {
13219                 ret = intel_modeset_checks(state);
13220
13221                 if (ret)
13222                         return ret;
13223         } else
13224                 to_intel_atomic_state(state)->cdclk =
13225                         to_i915(state->dev)->cdclk_freq;
13226
13227         return drm_atomic_helper_check_planes(state->dev, state);
13228 }
13229
13230 /**
13231  * intel_atomic_commit - commit validated state object
13232  * @dev: DRM device
13233  * @state: the top-level driver state object
13234  * @async: asynchronous commit
13235  *
13236  * This function commits a top-level state object that has been validated
13237  * with drm_atomic_helper_check().
13238  *
13239  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13240  * we can only handle plane-related operations and do not yet support
13241  * asynchronous commit.
13242  *
13243  * RETURNS
13244  * Zero for success or -errno.
13245  */
13246 static int intel_atomic_commit(struct drm_device *dev,
13247                                struct drm_atomic_state *state,
13248                                bool async)
13249 {
13250         struct drm_i915_private *dev_priv = dev->dev_private;
13251         struct drm_crtc *crtc;
13252         struct drm_crtc_state *crtc_state;
13253         int ret = 0;
13254         int i;
13255         bool any_ms = false;
13256
13257         if (async) {
13258                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13259                 return -EINVAL;
13260         }
13261
13262         ret = drm_atomic_helper_prepare_planes(dev, state);
13263         if (ret)
13264                 return ret;
13265
13266         drm_atomic_helper_swap_state(dev, state);
13267
13268         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13269                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13270
13271                 if (!needs_modeset(crtc->state))
13272                         continue;
13273
13274                 any_ms = true;
13275                 intel_pre_plane_update(intel_crtc);
13276
13277                 if (crtc_state->active) {
13278                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13279                         dev_priv->display.crtc_disable(crtc);
13280                         intel_crtc->active = false;
13281                         intel_disable_shared_dpll(intel_crtc);
13282                 }
13283         }
13284
13285         /* Only after disabling all output pipelines that will be changed can we
13286          * update the the output configuration. */
13287         intel_modeset_update_state(state);
13288
13289         /* The state has been swaped above, so state actually contains the
13290          * old state now. */
13291         if (any_ms)
13292                 modeset_update_crtc_power_domains(state);
13293
13294         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13295         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13296                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13297                 bool modeset = needs_modeset(crtc->state);
13298
13299                 if (modeset && crtc->state->active) {
13300                         update_scanline_offset(to_intel_crtc(crtc));
13301                         dev_priv->display.crtc_enable(crtc);
13302                 }
13303
13304                 if (!modeset)
13305                         intel_pre_plane_update(intel_crtc);
13306
13307                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13308                 intel_post_plane_update(intel_crtc);
13309         }
13310
13311         /* FIXME: add subpixel order */
13312
13313         drm_atomic_helper_wait_for_vblanks(dev, state);
13314         drm_atomic_helper_cleanup_planes(dev, state);
13315         drm_atomic_state_free(state);
13316
13317         if (any_ms)
13318                 intel_modeset_check_state(dev);
13319
13320         return 0;
13321 }
13322
13323 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13324 {
13325         struct drm_device *dev = crtc->dev;
13326         struct drm_atomic_state *state;
13327         struct drm_crtc_state *crtc_state;
13328         int ret;
13329
13330         state = drm_atomic_state_alloc(dev);
13331         if (!state) {
13332                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13333                               crtc->base.id);
13334                 return;
13335         }
13336
13337         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13338
13339 retry:
13340         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13341         ret = PTR_ERR_OR_ZERO(crtc_state);
13342         if (!ret) {
13343                 if (!crtc_state->active)
13344                         goto out;
13345
13346                 crtc_state->mode_changed = true;
13347                 ret = drm_atomic_commit(state);
13348         }
13349
13350         if (ret == -EDEADLK) {
13351                 drm_atomic_state_clear(state);
13352                 drm_modeset_backoff(state->acquire_ctx);
13353                 goto retry;
13354         }
13355
13356         if (ret)
13357 out:
13358                 drm_atomic_state_free(state);
13359 }
13360
13361 #undef for_each_intel_crtc_masked
13362
13363 static const struct drm_crtc_funcs intel_crtc_funcs = {
13364         .gamma_set = intel_crtc_gamma_set,
13365         .set_config = drm_atomic_helper_set_config,
13366         .destroy = intel_crtc_destroy,
13367         .page_flip = intel_crtc_page_flip,
13368         .atomic_duplicate_state = intel_crtc_duplicate_state,
13369         .atomic_destroy_state = intel_crtc_destroy_state,
13370 };
13371
13372 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13373                                       struct intel_shared_dpll *pll,
13374                                       struct intel_dpll_hw_state *hw_state)
13375 {
13376         uint32_t val;
13377
13378         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13379                 return false;
13380
13381         val = I915_READ(PCH_DPLL(pll->id));
13382         hw_state->dpll = val;
13383         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13384         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13385
13386         return val & DPLL_VCO_ENABLE;
13387 }
13388
13389 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13390                                   struct intel_shared_dpll *pll)
13391 {
13392         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13393         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13394 }
13395
13396 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13397                                 struct intel_shared_dpll *pll)
13398 {
13399         /* PCH refclock must be enabled first */
13400         ibx_assert_pch_refclk_enabled(dev_priv);
13401
13402         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13403
13404         /* Wait for the clocks to stabilize. */
13405         POSTING_READ(PCH_DPLL(pll->id));
13406         udelay(150);
13407
13408         /* The pixel multiplier can only be updated once the
13409          * DPLL is enabled and the clocks are stable.
13410          *
13411          * So write it again.
13412          */
13413         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13414         POSTING_READ(PCH_DPLL(pll->id));
13415         udelay(200);
13416 }
13417
13418 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13419                                  struct intel_shared_dpll *pll)
13420 {
13421         struct drm_device *dev = dev_priv->dev;
13422         struct intel_crtc *crtc;
13423
13424         /* Make sure no transcoder isn't still depending on us. */
13425         for_each_intel_crtc(dev, crtc) {
13426                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13427                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13428         }
13429
13430         I915_WRITE(PCH_DPLL(pll->id), 0);
13431         POSTING_READ(PCH_DPLL(pll->id));
13432         udelay(200);
13433 }
13434
13435 static char *ibx_pch_dpll_names[] = {
13436         "PCH DPLL A",
13437         "PCH DPLL B",
13438 };
13439
13440 static void ibx_pch_dpll_init(struct drm_device *dev)
13441 {
13442         struct drm_i915_private *dev_priv = dev->dev_private;
13443         int i;
13444
13445         dev_priv->num_shared_dpll = 2;
13446
13447         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13448                 dev_priv->shared_dplls[i].id = i;
13449                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13450                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13451                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13452                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13453                 dev_priv->shared_dplls[i].get_hw_state =
13454                         ibx_pch_dpll_get_hw_state;
13455         }
13456 }
13457
13458 static void intel_shared_dpll_init(struct drm_device *dev)
13459 {
13460         struct drm_i915_private *dev_priv = dev->dev_private;
13461
13462         intel_update_cdclk(dev);
13463
13464         if (HAS_DDI(dev))
13465                 intel_ddi_pll_init(dev);
13466         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13467                 ibx_pch_dpll_init(dev);
13468         else
13469                 dev_priv->num_shared_dpll = 0;
13470
13471         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13472 }
13473
13474 /**
13475  * intel_prepare_plane_fb - Prepare fb for usage on plane
13476  * @plane: drm plane to prepare for
13477  * @fb: framebuffer to prepare for presentation
13478  *
13479  * Prepares a framebuffer for usage on a display plane.  Generally this
13480  * involves pinning the underlying object and updating the frontbuffer tracking
13481  * bits.  Some older platforms need special physical address handling for
13482  * cursor planes.
13483  *
13484  * Returns 0 on success, negative error code on failure.
13485  */
13486 int
13487 intel_prepare_plane_fb(struct drm_plane *plane,
13488                        struct drm_framebuffer *fb,
13489                        const struct drm_plane_state *new_state)
13490 {
13491         struct drm_device *dev = plane->dev;
13492         struct intel_plane *intel_plane = to_intel_plane(plane);
13493         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13494         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13495         int ret = 0;
13496
13497         if (!obj)
13498                 return 0;
13499
13500         mutex_lock(&dev->struct_mutex);
13501
13502         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13503             INTEL_INFO(dev)->cursor_needs_physical) {
13504                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13505                 ret = i915_gem_object_attach_phys(obj, align);
13506                 if (ret)
13507                         DRM_DEBUG_KMS("failed to attach phys object\n");
13508         } else {
13509                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13510         }
13511
13512         if (ret == 0)
13513                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13514
13515         mutex_unlock(&dev->struct_mutex);
13516
13517         return ret;
13518 }
13519
13520 /**
13521  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13522  * @plane: drm plane to clean up for
13523  * @fb: old framebuffer that was on plane
13524  *
13525  * Cleans up a framebuffer that has just been removed from a plane.
13526  */
13527 void
13528 intel_cleanup_plane_fb(struct drm_plane *plane,
13529                        struct drm_framebuffer *fb,
13530                        const struct drm_plane_state *old_state)
13531 {
13532         struct drm_device *dev = plane->dev;
13533         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13534
13535         if (WARN_ON(!obj))
13536                 return;
13537
13538         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13539             !INTEL_INFO(dev)->cursor_needs_physical) {
13540                 mutex_lock(&dev->struct_mutex);
13541                 intel_unpin_fb_obj(fb, old_state);
13542                 mutex_unlock(&dev->struct_mutex);
13543         }
13544 }
13545
13546 int
13547 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13548 {
13549         int max_scale;
13550         struct drm_device *dev;
13551         struct drm_i915_private *dev_priv;
13552         int crtc_clock, cdclk;
13553
13554         if (!intel_crtc || !crtc_state)
13555                 return DRM_PLANE_HELPER_NO_SCALING;
13556
13557         dev = intel_crtc->base.dev;
13558         dev_priv = dev->dev_private;
13559         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13560         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13561
13562         if (!crtc_clock || !cdclk)
13563                 return DRM_PLANE_HELPER_NO_SCALING;
13564
13565         /*
13566          * skl max scale is lower of:
13567          *    close to 3 but not 3, -1 is for that purpose
13568          *            or
13569          *    cdclk/crtc_clock
13570          */
13571         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13572
13573         return max_scale;
13574 }
13575
13576 static int
13577 intel_check_primary_plane(struct drm_plane *plane,
13578                           struct intel_crtc_state *crtc_state,
13579                           struct intel_plane_state *state)
13580 {
13581         struct drm_crtc *crtc = state->base.crtc;
13582         struct drm_framebuffer *fb = state->base.fb;
13583         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13584         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13585         bool can_position = false;
13586
13587         /* use scaler when colorkey is not required */
13588         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13589             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13590                 min_scale = 1;
13591                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13592                 can_position = true;
13593         }
13594
13595         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13596                                              &state->dst, &state->clip,
13597                                              min_scale, max_scale,
13598                                              can_position, true,
13599                                              &state->visible);
13600 }
13601
13602 static void
13603 intel_commit_primary_plane(struct drm_plane *plane,
13604                            struct intel_plane_state *state)
13605 {
13606         struct drm_crtc *crtc = state->base.crtc;
13607         struct drm_framebuffer *fb = state->base.fb;
13608         struct drm_device *dev = plane->dev;
13609         struct drm_i915_private *dev_priv = dev->dev_private;
13610         struct intel_crtc *intel_crtc;
13611         struct drm_rect *src = &state->src;
13612
13613         crtc = crtc ? crtc : plane->crtc;
13614         intel_crtc = to_intel_crtc(crtc);
13615
13616         plane->fb = fb;
13617         crtc->x = src->x1 >> 16;
13618         crtc->y = src->y1 >> 16;
13619
13620         if (!crtc->state->active)
13621                 return;
13622
13623         if (state->visible)
13624                 /* FIXME: kill this fastboot hack */
13625                 intel_update_pipe_size(intel_crtc);
13626
13627         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13628 }
13629
13630 static void
13631 intel_disable_primary_plane(struct drm_plane *plane,
13632                             struct drm_crtc *crtc)
13633 {
13634         struct drm_device *dev = plane->dev;
13635         struct drm_i915_private *dev_priv = dev->dev_private;
13636
13637         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13638 }
13639
13640 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13641 {
13642         struct drm_device *dev = crtc->dev;
13643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13644
13645         if (intel_crtc->atomic.update_wm_pre)
13646                 intel_update_watermarks(crtc);
13647
13648         /* Perform vblank evasion around commit operation */
13649         if (crtc->state->active)
13650                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13651
13652         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13653                 skl_detach_scalers(intel_crtc);
13654 }
13655
13656 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13657 {
13658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13659
13660         if (crtc->state->active)
13661                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13662 }
13663
13664 /**
13665  * intel_plane_destroy - destroy a plane
13666  * @plane: plane to destroy
13667  *
13668  * Common destruction function for all types of planes (primary, cursor,
13669  * sprite).
13670  */
13671 void intel_plane_destroy(struct drm_plane *plane)
13672 {
13673         struct intel_plane *intel_plane = to_intel_plane(plane);
13674         drm_plane_cleanup(plane);
13675         kfree(intel_plane);
13676 }
13677
13678 const struct drm_plane_funcs intel_plane_funcs = {
13679         .update_plane = drm_atomic_helper_update_plane,
13680         .disable_plane = drm_atomic_helper_disable_plane,
13681         .destroy = intel_plane_destroy,
13682         .set_property = drm_atomic_helper_plane_set_property,
13683         .atomic_get_property = intel_plane_atomic_get_property,
13684         .atomic_set_property = intel_plane_atomic_set_property,
13685         .atomic_duplicate_state = intel_plane_duplicate_state,
13686         .atomic_destroy_state = intel_plane_destroy_state,
13687
13688 };
13689
13690 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13691                                                     int pipe)
13692 {
13693         struct intel_plane *primary;
13694         struct intel_plane_state *state;
13695         const uint32_t *intel_primary_formats;
13696         int num_formats;
13697
13698         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13699         if (primary == NULL)
13700                 return NULL;
13701
13702         state = intel_create_plane_state(&primary->base);
13703         if (!state) {
13704                 kfree(primary);
13705                 return NULL;
13706         }
13707         primary->base.state = &state->base;
13708
13709         primary->can_scale = false;
13710         primary->max_downscale = 1;
13711         if (INTEL_INFO(dev)->gen >= 9) {
13712                 primary->can_scale = true;
13713                 state->scaler_id = -1;
13714         }
13715         primary->pipe = pipe;
13716         primary->plane = pipe;
13717         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13718         primary->check_plane = intel_check_primary_plane;
13719         primary->commit_plane = intel_commit_primary_plane;
13720         primary->disable_plane = intel_disable_primary_plane;
13721         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13722                 primary->plane = !pipe;
13723
13724         if (INTEL_INFO(dev)->gen >= 9) {
13725                 intel_primary_formats = skl_primary_formats;
13726                 num_formats = ARRAY_SIZE(skl_primary_formats);
13727         } else if (INTEL_INFO(dev)->gen >= 4) {
13728                 intel_primary_formats = i965_primary_formats;
13729                 num_formats = ARRAY_SIZE(i965_primary_formats);
13730         } else {
13731                 intel_primary_formats = i8xx_primary_formats;
13732                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13733         }
13734
13735         drm_universal_plane_init(dev, &primary->base, 0,
13736                                  &intel_plane_funcs,
13737                                  intel_primary_formats, num_formats,
13738                                  DRM_PLANE_TYPE_PRIMARY);
13739
13740         if (INTEL_INFO(dev)->gen >= 4)
13741                 intel_create_rotation_property(dev, primary);
13742
13743         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13744
13745         return &primary->base;
13746 }
13747
13748 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13749 {
13750         if (!dev->mode_config.rotation_property) {
13751                 unsigned long flags = BIT(DRM_ROTATE_0) |
13752                         BIT(DRM_ROTATE_180);
13753
13754                 if (INTEL_INFO(dev)->gen >= 9)
13755                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13756
13757                 dev->mode_config.rotation_property =
13758                         drm_mode_create_rotation_property(dev, flags);
13759         }
13760         if (dev->mode_config.rotation_property)
13761                 drm_object_attach_property(&plane->base.base,
13762                                 dev->mode_config.rotation_property,
13763                                 plane->base.state->rotation);
13764 }
13765
13766 static int
13767 intel_check_cursor_plane(struct drm_plane *plane,
13768                          struct intel_crtc_state *crtc_state,
13769                          struct intel_plane_state *state)
13770 {
13771         struct drm_crtc *crtc = crtc_state->base.crtc;
13772         struct drm_framebuffer *fb = state->base.fb;
13773         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13774         unsigned stride;
13775         int ret;
13776
13777         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13778                                             &state->dst, &state->clip,
13779                                             DRM_PLANE_HELPER_NO_SCALING,
13780                                             DRM_PLANE_HELPER_NO_SCALING,
13781                                             true, true, &state->visible);
13782         if (ret)
13783                 return ret;
13784
13785         /* if we want to turn off the cursor ignore width and height */
13786         if (!obj)
13787                 return 0;
13788
13789         /* Check for which cursor types we support */
13790         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13791                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13792                           state->base.crtc_w, state->base.crtc_h);
13793                 return -EINVAL;
13794         }
13795
13796         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13797         if (obj->base.size < stride * state->base.crtc_h) {
13798                 DRM_DEBUG_KMS("buffer is too small\n");
13799                 return -ENOMEM;
13800         }
13801
13802         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13803                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13804                 return -EINVAL;
13805         }
13806
13807         return 0;
13808 }
13809
13810 static void
13811 intel_disable_cursor_plane(struct drm_plane *plane,
13812                            struct drm_crtc *crtc)
13813 {
13814         intel_crtc_update_cursor(crtc, false);
13815 }
13816
13817 static void
13818 intel_commit_cursor_plane(struct drm_plane *plane,
13819                           struct intel_plane_state *state)
13820 {
13821         struct drm_crtc *crtc = state->base.crtc;
13822         struct drm_device *dev = plane->dev;
13823         struct intel_crtc *intel_crtc;
13824         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13825         uint32_t addr;
13826
13827         crtc = crtc ? crtc : plane->crtc;
13828         intel_crtc = to_intel_crtc(crtc);
13829
13830         plane->fb = state->base.fb;
13831         crtc->cursor_x = state->base.crtc_x;
13832         crtc->cursor_y = state->base.crtc_y;
13833
13834         if (intel_crtc->cursor_bo == obj)
13835                 goto update;
13836
13837         if (!obj)
13838                 addr = 0;
13839         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13840                 addr = i915_gem_obj_ggtt_offset(obj);
13841         else
13842                 addr = obj->phys_handle->busaddr;
13843
13844         intel_crtc->cursor_addr = addr;
13845         intel_crtc->cursor_bo = obj;
13846
13847 update:
13848         if (crtc->state->active)
13849                 intel_crtc_update_cursor(crtc, state->visible);
13850 }
13851
13852 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13853                                                    int pipe)
13854 {
13855         struct intel_plane *cursor;
13856         struct intel_plane_state *state;
13857
13858         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13859         if (cursor == NULL)
13860                 return NULL;
13861
13862         state = intel_create_plane_state(&cursor->base);
13863         if (!state) {
13864                 kfree(cursor);
13865                 return NULL;
13866         }
13867         cursor->base.state = &state->base;
13868
13869         cursor->can_scale = false;
13870         cursor->max_downscale = 1;
13871         cursor->pipe = pipe;
13872         cursor->plane = pipe;
13873         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13874         cursor->check_plane = intel_check_cursor_plane;
13875         cursor->commit_plane = intel_commit_cursor_plane;
13876         cursor->disable_plane = intel_disable_cursor_plane;
13877
13878         drm_universal_plane_init(dev, &cursor->base, 0,
13879                                  &intel_plane_funcs,
13880                                  intel_cursor_formats,
13881                                  ARRAY_SIZE(intel_cursor_formats),
13882                                  DRM_PLANE_TYPE_CURSOR);
13883
13884         if (INTEL_INFO(dev)->gen >= 4) {
13885                 if (!dev->mode_config.rotation_property)
13886                         dev->mode_config.rotation_property =
13887                                 drm_mode_create_rotation_property(dev,
13888                                                         BIT(DRM_ROTATE_0) |
13889                                                         BIT(DRM_ROTATE_180));
13890                 if (dev->mode_config.rotation_property)
13891                         drm_object_attach_property(&cursor->base.base,
13892                                 dev->mode_config.rotation_property,
13893                                 state->base.rotation);
13894         }
13895
13896         if (INTEL_INFO(dev)->gen >=9)
13897                 state->scaler_id = -1;
13898
13899         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13900
13901         return &cursor->base;
13902 }
13903
13904 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13905         struct intel_crtc_state *crtc_state)
13906 {
13907         int i;
13908         struct intel_scaler *intel_scaler;
13909         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13910
13911         for (i = 0; i < intel_crtc->num_scalers; i++) {
13912                 intel_scaler = &scaler_state->scalers[i];
13913                 intel_scaler->in_use = 0;
13914                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13915         }
13916
13917         scaler_state->scaler_id = -1;
13918 }
13919
13920 static void intel_crtc_init(struct drm_device *dev, int pipe)
13921 {
13922         struct drm_i915_private *dev_priv = dev->dev_private;
13923         struct intel_crtc *intel_crtc;
13924         struct intel_crtc_state *crtc_state = NULL;
13925         struct drm_plane *primary = NULL;
13926         struct drm_plane *cursor = NULL;
13927         int i, ret;
13928
13929         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13930         if (intel_crtc == NULL)
13931                 return;
13932
13933         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13934         if (!crtc_state)
13935                 goto fail;
13936         intel_crtc->config = crtc_state;
13937         intel_crtc->base.state = &crtc_state->base;
13938         crtc_state->base.crtc = &intel_crtc->base;
13939
13940         /* initialize shared scalers */
13941         if (INTEL_INFO(dev)->gen >= 9) {
13942                 if (pipe == PIPE_C)
13943                         intel_crtc->num_scalers = 1;
13944                 else
13945                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13946
13947                 skl_init_scalers(dev, intel_crtc, crtc_state);
13948         }
13949
13950         primary = intel_primary_plane_create(dev, pipe);
13951         if (!primary)
13952                 goto fail;
13953
13954         cursor = intel_cursor_plane_create(dev, pipe);
13955         if (!cursor)
13956                 goto fail;
13957
13958         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13959                                         cursor, &intel_crtc_funcs);
13960         if (ret)
13961                 goto fail;
13962
13963         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13964         for (i = 0; i < 256; i++) {
13965                 intel_crtc->lut_r[i] = i;
13966                 intel_crtc->lut_g[i] = i;
13967                 intel_crtc->lut_b[i] = i;
13968         }
13969
13970         /*
13971          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13972          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13973          */
13974         intel_crtc->pipe = pipe;
13975         intel_crtc->plane = pipe;
13976         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13977                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13978                 intel_crtc->plane = !pipe;
13979         }
13980
13981         intel_crtc->cursor_base = ~0;
13982         intel_crtc->cursor_cntl = ~0;
13983         intel_crtc->cursor_size = ~0;
13984
13985         intel_crtc->wm.cxsr_allowed = true;
13986
13987         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13988                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13989         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13990         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13991
13992         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13993
13994         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13995         return;
13996
13997 fail:
13998         if (primary)
13999                 drm_plane_cleanup(primary);
14000         if (cursor)
14001                 drm_plane_cleanup(cursor);
14002         kfree(crtc_state);
14003         kfree(intel_crtc);
14004 }
14005
14006 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14007 {
14008         struct drm_encoder *encoder = connector->base.encoder;
14009         struct drm_device *dev = connector->base.dev;
14010
14011         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14012
14013         if (!encoder || WARN_ON(!encoder->crtc))
14014                 return INVALID_PIPE;
14015
14016         return to_intel_crtc(encoder->crtc)->pipe;
14017 }
14018
14019 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14020                                 struct drm_file *file)
14021 {
14022         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14023         struct drm_crtc *drmmode_crtc;
14024         struct intel_crtc *crtc;
14025
14026         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14027
14028         if (!drmmode_crtc) {
14029                 DRM_ERROR("no such CRTC id\n");
14030                 return -ENOENT;
14031         }
14032
14033         crtc = to_intel_crtc(drmmode_crtc);
14034         pipe_from_crtc_id->pipe = crtc->pipe;
14035
14036         return 0;
14037 }
14038
14039 static int intel_encoder_clones(struct intel_encoder *encoder)
14040 {
14041         struct drm_device *dev = encoder->base.dev;
14042         struct intel_encoder *source_encoder;
14043         int index_mask = 0;
14044         int entry = 0;
14045
14046         for_each_intel_encoder(dev, source_encoder) {
14047                 if (encoders_cloneable(encoder, source_encoder))
14048                         index_mask |= (1 << entry);
14049
14050                 entry++;
14051         }
14052
14053         return index_mask;
14054 }
14055
14056 static bool has_edp_a(struct drm_device *dev)
14057 {
14058         struct drm_i915_private *dev_priv = dev->dev_private;
14059
14060         if (!IS_MOBILE(dev))
14061                 return false;
14062
14063         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14064                 return false;
14065
14066         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14067                 return false;
14068
14069         return true;
14070 }
14071
14072 static bool intel_crt_present(struct drm_device *dev)
14073 {
14074         struct drm_i915_private *dev_priv = dev->dev_private;
14075
14076         if (INTEL_INFO(dev)->gen >= 9)
14077                 return false;
14078
14079         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14080                 return false;
14081
14082         if (IS_CHERRYVIEW(dev))
14083                 return false;
14084
14085         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14086                 return false;
14087
14088         return true;
14089 }
14090
14091 static void intel_setup_outputs(struct drm_device *dev)
14092 {
14093         struct drm_i915_private *dev_priv = dev->dev_private;
14094         struct intel_encoder *encoder;
14095         bool dpd_is_edp = false;
14096
14097         intel_lvds_init(dev);
14098
14099         if (intel_crt_present(dev))
14100                 intel_crt_init(dev);
14101
14102         if (IS_BROXTON(dev)) {
14103                 /*
14104                  * FIXME: Broxton doesn't support port detection via the
14105                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14106                  * detect the ports.
14107                  */
14108                 intel_ddi_init(dev, PORT_A);
14109                 intel_ddi_init(dev, PORT_B);
14110                 intel_ddi_init(dev, PORT_C);
14111         } else if (HAS_DDI(dev)) {
14112                 int found;
14113
14114                 /*
14115                  * Haswell uses DDI functions to detect digital outputs.
14116                  * On SKL pre-D0 the strap isn't connected, so we assume
14117                  * it's there.
14118                  */
14119                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14120                 /* WaIgnoreDDIAStrap: skl */
14121                 if (found ||
14122                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14123                         intel_ddi_init(dev, PORT_A);
14124
14125                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14126                  * register */
14127                 found = I915_READ(SFUSE_STRAP);
14128
14129                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14130                         intel_ddi_init(dev, PORT_B);
14131                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14132                         intel_ddi_init(dev, PORT_C);
14133                 if (found & SFUSE_STRAP_DDID_DETECTED)
14134                         intel_ddi_init(dev, PORT_D);
14135         } else if (HAS_PCH_SPLIT(dev)) {
14136                 int found;
14137                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14138
14139                 if (has_edp_a(dev))
14140                         intel_dp_init(dev, DP_A, PORT_A);
14141
14142                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14143                         /* PCH SDVOB multiplex with HDMIB */
14144                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14145                         if (!found)
14146                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14147                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14148                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14149                 }
14150
14151                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14152                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14153
14154                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14155                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14156
14157                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14158                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14159
14160                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14161                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14162         } else if (IS_VALLEYVIEW(dev)) {
14163                 /*
14164                  * The DP_DETECTED bit is the latched state of the DDC
14165                  * SDA pin at boot. However since eDP doesn't require DDC
14166                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14167                  * eDP ports may have been muxed to an alternate function.
14168                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14169                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14170                  * detect eDP ports.
14171                  */
14172                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14173                     !intel_dp_is_edp(dev, PORT_B))
14174                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14175                                         PORT_B);
14176                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14177                     intel_dp_is_edp(dev, PORT_B))
14178                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14179
14180                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14181                     !intel_dp_is_edp(dev, PORT_C))
14182                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14183                                         PORT_C);
14184                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14185                     intel_dp_is_edp(dev, PORT_C))
14186                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14187
14188                 if (IS_CHERRYVIEW(dev)) {
14189                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14190                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14191                                                 PORT_D);
14192                         /* eDP not supported on port D, so don't check VBT */
14193                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14194                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14195                 }
14196
14197                 intel_dsi_init(dev);
14198         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14199                 bool found = false;
14200
14201                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14202                         DRM_DEBUG_KMS("probing SDVOB\n");
14203                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14204                         if (!found && IS_G4X(dev)) {
14205                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14206                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14207                         }
14208
14209                         if (!found && IS_G4X(dev))
14210                                 intel_dp_init(dev, DP_B, PORT_B);
14211                 }
14212
14213                 /* Before G4X SDVOC doesn't have its own detect register */
14214
14215                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14216                         DRM_DEBUG_KMS("probing SDVOC\n");
14217                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14218                 }
14219
14220                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14221
14222                         if (IS_G4X(dev)) {
14223                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14224                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14225                         }
14226                         if (IS_G4X(dev))
14227                                 intel_dp_init(dev, DP_C, PORT_C);
14228                 }
14229
14230                 if (IS_G4X(dev) &&
14231                     (I915_READ(DP_D) & DP_DETECTED))
14232                         intel_dp_init(dev, DP_D, PORT_D);
14233         } else if (IS_GEN2(dev))
14234                 intel_dvo_init(dev);
14235
14236         if (SUPPORTS_TV(dev))
14237                 intel_tv_init(dev);
14238
14239         intel_psr_init(dev);
14240
14241         for_each_intel_encoder(dev, encoder) {
14242                 encoder->base.possible_crtcs = encoder->crtc_mask;
14243                 encoder->base.possible_clones =
14244                         intel_encoder_clones(encoder);
14245         }
14246
14247         intel_init_pch_refclk(dev);
14248
14249         drm_helper_move_panel_connectors_to_head(dev);
14250 }
14251
14252 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14253 {
14254         struct drm_device *dev = fb->dev;
14255         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14256
14257         drm_framebuffer_cleanup(fb);
14258         mutex_lock(&dev->struct_mutex);
14259         WARN_ON(!intel_fb->obj->framebuffer_references--);
14260         drm_gem_object_unreference(&intel_fb->obj->base);
14261         mutex_unlock(&dev->struct_mutex);
14262         kfree(intel_fb);
14263 }
14264
14265 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14266                                                 struct drm_file *file,
14267                                                 unsigned int *handle)
14268 {
14269         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14270         struct drm_i915_gem_object *obj = intel_fb->obj;
14271
14272         return drm_gem_handle_create(file, &obj->base, handle);
14273 }
14274
14275 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14276                                         struct drm_file *file,
14277                                         unsigned flags, unsigned color,
14278                                         struct drm_clip_rect *clips,
14279                                         unsigned num_clips)
14280 {
14281         struct drm_device *dev = fb->dev;
14282         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14283         struct drm_i915_gem_object *obj = intel_fb->obj;
14284
14285         mutex_lock(&dev->struct_mutex);
14286         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14287         mutex_unlock(&dev->struct_mutex);
14288
14289         return 0;
14290 }
14291
14292 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14293         .destroy = intel_user_framebuffer_destroy,
14294         .create_handle = intel_user_framebuffer_create_handle,
14295         .dirty = intel_user_framebuffer_dirty,
14296 };
14297
14298 static
14299 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14300                          uint32_t pixel_format)
14301 {
14302         u32 gen = INTEL_INFO(dev)->gen;
14303
14304         if (gen >= 9) {
14305                 /* "The stride in bytes must not exceed the of the size of 8K
14306                  *  pixels and 32K bytes."
14307                  */
14308                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14309         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14310                 return 32*1024;
14311         } else if (gen >= 4) {
14312                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14313                         return 16*1024;
14314                 else
14315                         return 32*1024;
14316         } else if (gen >= 3) {
14317                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14318                         return 8*1024;
14319                 else
14320                         return 16*1024;
14321         } else {
14322                 /* XXX DSPC is limited to 4k tiled */
14323                 return 8*1024;
14324         }
14325 }
14326
14327 static int intel_framebuffer_init(struct drm_device *dev,
14328                                   struct intel_framebuffer *intel_fb,
14329                                   struct drm_mode_fb_cmd2 *mode_cmd,
14330                                   struct drm_i915_gem_object *obj)
14331 {
14332         unsigned int aligned_height;
14333         int ret;
14334         u32 pitch_limit, stride_alignment;
14335
14336         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14337
14338         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14339                 /* Enforce that fb modifier and tiling mode match, but only for
14340                  * X-tiled. This is needed for FBC. */
14341                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14342                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14343                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14344                         return -EINVAL;
14345                 }
14346         } else {
14347                 if (obj->tiling_mode == I915_TILING_X)
14348                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14349                 else if (obj->tiling_mode == I915_TILING_Y) {
14350                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14351                         return -EINVAL;
14352                 }
14353         }
14354
14355         /* Passed in modifier sanity checking. */
14356         switch (mode_cmd->modifier[0]) {
14357         case I915_FORMAT_MOD_Y_TILED:
14358         case I915_FORMAT_MOD_Yf_TILED:
14359                 if (INTEL_INFO(dev)->gen < 9) {
14360                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14361                                   mode_cmd->modifier[0]);
14362                         return -EINVAL;
14363                 }
14364         case DRM_FORMAT_MOD_NONE:
14365         case I915_FORMAT_MOD_X_TILED:
14366                 break;
14367         default:
14368                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14369                           mode_cmd->modifier[0]);
14370                 return -EINVAL;
14371         }
14372
14373         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14374                                                      mode_cmd->pixel_format);
14375         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14376                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14377                           mode_cmd->pitches[0], stride_alignment);
14378                 return -EINVAL;
14379         }
14380
14381         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14382                                            mode_cmd->pixel_format);
14383         if (mode_cmd->pitches[0] > pitch_limit) {
14384                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14385                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14386                           "tiled" : "linear",
14387                           mode_cmd->pitches[0], pitch_limit);
14388                 return -EINVAL;
14389         }
14390
14391         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14392             mode_cmd->pitches[0] != obj->stride) {
14393                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14394                           mode_cmd->pitches[0], obj->stride);
14395                 return -EINVAL;
14396         }
14397
14398         /* Reject formats not supported by any plane early. */
14399         switch (mode_cmd->pixel_format) {
14400         case DRM_FORMAT_C8:
14401         case DRM_FORMAT_RGB565:
14402         case DRM_FORMAT_XRGB8888:
14403         case DRM_FORMAT_ARGB8888:
14404                 break;
14405         case DRM_FORMAT_XRGB1555:
14406                 if (INTEL_INFO(dev)->gen > 3) {
14407                         DRM_DEBUG("unsupported pixel format: %s\n",
14408                                   drm_get_format_name(mode_cmd->pixel_format));
14409                         return -EINVAL;
14410                 }
14411                 break;
14412         case DRM_FORMAT_ABGR8888:
14413                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14414                         DRM_DEBUG("unsupported pixel format: %s\n",
14415                                   drm_get_format_name(mode_cmd->pixel_format));
14416                         return -EINVAL;
14417                 }
14418                 break;
14419         case DRM_FORMAT_XBGR8888:
14420         case DRM_FORMAT_XRGB2101010:
14421         case DRM_FORMAT_XBGR2101010:
14422                 if (INTEL_INFO(dev)->gen < 4) {
14423                         DRM_DEBUG("unsupported pixel format: %s\n",
14424                                   drm_get_format_name(mode_cmd->pixel_format));
14425                         return -EINVAL;
14426                 }
14427                 break;
14428         case DRM_FORMAT_ABGR2101010:
14429                 if (!IS_VALLEYVIEW(dev)) {
14430                         DRM_DEBUG("unsupported pixel format: %s\n",
14431                                   drm_get_format_name(mode_cmd->pixel_format));
14432                         return -EINVAL;
14433                 }
14434                 break;
14435         case DRM_FORMAT_YUYV:
14436         case DRM_FORMAT_UYVY:
14437         case DRM_FORMAT_YVYU:
14438         case DRM_FORMAT_VYUY:
14439                 if (INTEL_INFO(dev)->gen < 5) {
14440                         DRM_DEBUG("unsupported pixel format: %s\n",
14441                                   drm_get_format_name(mode_cmd->pixel_format));
14442                         return -EINVAL;
14443                 }
14444                 break;
14445         default:
14446                 DRM_DEBUG("unsupported pixel format: %s\n",
14447                           drm_get_format_name(mode_cmd->pixel_format));
14448                 return -EINVAL;
14449         }
14450
14451         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14452         if (mode_cmd->offsets[0] != 0)
14453                 return -EINVAL;
14454
14455         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14456                                                mode_cmd->pixel_format,
14457                                                mode_cmd->modifier[0]);
14458         /* FIXME drm helper for size checks (especially planar formats)? */
14459         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14460                 return -EINVAL;
14461
14462         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14463         intel_fb->obj = obj;
14464         intel_fb->obj->framebuffer_references++;
14465
14466         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14467         if (ret) {
14468                 DRM_ERROR("framebuffer init failed %d\n", ret);
14469                 return ret;
14470         }
14471
14472         return 0;
14473 }
14474
14475 static struct drm_framebuffer *
14476 intel_user_framebuffer_create(struct drm_device *dev,
14477                               struct drm_file *filp,
14478                               struct drm_mode_fb_cmd2 *mode_cmd)
14479 {
14480         struct drm_i915_gem_object *obj;
14481
14482         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14483                                                 mode_cmd->handles[0]));
14484         if (&obj->base == NULL)
14485                 return ERR_PTR(-ENOENT);
14486
14487         return intel_framebuffer_create(dev, mode_cmd, obj);
14488 }
14489
14490 #ifndef CONFIG_DRM_I915_FBDEV
14491 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14492 {
14493 }
14494 #endif
14495
14496 static const struct drm_mode_config_funcs intel_mode_funcs = {
14497         .fb_create = intel_user_framebuffer_create,
14498         .output_poll_changed = intel_fbdev_output_poll_changed,
14499         .atomic_check = intel_atomic_check,
14500         .atomic_commit = intel_atomic_commit,
14501         .atomic_state_alloc = intel_atomic_state_alloc,
14502         .atomic_state_clear = intel_atomic_state_clear,
14503 };
14504
14505 /* Set up chip specific display functions */
14506 static void intel_init_display(struct drm_device *dev)
14507 {
14508         struct drm_i915_private *dev_priv = dev->dev_private;
14509
14510         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14511                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14512         else if (IS_CHERRYVIEW(dev))
14513                 dev_priv->display.find_dpll = chv_find_best_dpll;
14514         else if (IS_VALLEYVIEW(dev))
14515                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14516         else if (IS_PINEVIEW(dev))
14517                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14518         else
14519                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14520
14521         if (INTEL_INFO(dev)->gen >= 9) {
14522                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14523                 dev_priv->display.get_initial_plane_config =
14524                         skylake_get_initial_plane_config;
14525                 dev_priv->display.crtc_compute_clock =
14526                         haswell_crtc_compute_clock;
14527                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14528                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14529                 dev_priv->display.update_primary_plane =
14530                         skylake_update_primary_plane;
14531         } else if (HAS_DDI(dev)) {
14532                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14533                 dev_priv->display.get_initial_plane_config =
14534                         ironlake_get_initial_plane_config;
14535                 dev_priv->display.crtc_compute_clock =
14536                         haswell_crtc_compute_clock;
14537                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14538                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14539                 dev_priv->display.update_primary_plane =
14540                         ironlake_update_primary_plane;
14541         } else if (HAS_PCH_SPLIT(dev)) {
14542                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14543                 dev_priv->display.get_initial_plane_config =
14544                         ironlake_get_initial_plane_config;
14545                 dev_priv->display.crtc_compute_clock =
14546                         ironlake_crtc_compute_clock;
14547                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14548                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14549                 dev_priv->display.update_primary_plane =
14550                         ironlake_update_primary_plane;
14551         } else if (IS_VALLEYVIEW(dev)) {
14552                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14553                 dev_priv->display.get_initial_plane_config =
14554                         i9xx_get_initial_plane_config;
14555                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14556                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14557                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14558                 dev_priv->display.update_primary_plane =
14559                         i9xx_update_primary_plane;
14560         } else {
14561                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14562                 dev_priv->display.get_initial_plane_config =
14563                         i9xx_get_initial_plane_config;
14564                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14565                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14566                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14567                 dev_priv->display.update_primary_plane =
14568                         i9xx_update_primary_plane;
14569         }
14570
14571         /* Returns the core display clock speed */
14572         if (IS_SKYLAKE(dev))
14573                 dev_priv->display.get_display_clock_speed =
14574                         skylake_get_display_clock_speed;
14575         else if (IS_BROXTON(dev))
14576                 dev_priv->display.get_display_clock_speed =
14577                         broxton_get_display_clock_speed;
14578         else if (IS_BROADWELL(dev))
14579                 dev_priv->display.get_display_clock_speed =
14580                         broadwell_get_display_clock_speed;
14581         else if (IS_HASWELL(dev))
14582                 dev_priv->display.get_display_clock_speed =
14583                         haswell_get_display_clock_speed;
14584         else if (IS_VALLEYVIEW(dev))
14585                 dev_priv->display.get_display_clock_speed =
14586                         valleyview_get_display_clock_speed;
14587         else if (IS_GEN5(dev))
14588                 dev_priv->display.get_display_clock_speed =
14589                         ilk_get_display_clock_speed;
14590         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14591                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14592                 dev_priv->display.get_display_clock_speed =
14593                         i945_get_display_clock_speed;
14594         else if (IS_GM45(dev))
14595                 dev_priv->display.get_display_clock_speed =
14596                         gm45_get_display_clock_speed;
14597         else if (IS_CRESTLINE(dev))
14598                 dev_priv->display.get_display_clock_speed =
14599                         i965gm_get_display_clock_speed;
14600         else if (IS_PINEVIEW(dev))
14601                 dev_priv->display.get_display_clock_speed =
14602                         pnv_get_display_clock_speed;
14603         else if (IS_G33(dev) || IS_G4X(dev))
14604                 dev_priv->display.get_display_clock_speed =
14605                         g33_get_display_clock_speed;
14606         else if (IS_I915G(dev))
14607                 dev_priv->display.get_display_clock_speed =
14608                         i915_get_display_clock_speed;
14609         else if (IS_I945GM(dev) || IS_845G(dev))
14610                 dev_priv->display.get_display_clock_speed =
14611                         i9xx_misc_get_display_clock_speed;
14612         else if (IS_PINEVIEW(dev))
14613                 dev_priv->display.get_display_clock_speed =
14614                         pnv_get_display_clock_speed;
14615         else if (IS_I915GM(dev))
14616                 dev_priv->display.get_display_clock_speed =
14617                         i915gm_get_display_clock_speed;
14618         else if (IS_I865G(dev))
14619                 dev_priv->display.get_display_clock_speed =
14620                         i865_get_display_clock_speed;
14621         else if (IS_I85X(dev))
14622                 dev_priv->display.get_display_clock_speed =
14623                         i85x_get_display_clock_speed;
14624         else { /* 830 */
14625                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14626                 dev_priv->display.get_display_clock_speed =
14627                         i830_get_display_clock_speed;
14628         }
14629
14630         if (IS_GEN5(dev)) {
14631                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14632         } else if (IS_GEN6(dev)) {
14633                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14634         } else if (IS_IVYBRIDGE(dev)) {
14635                 /* FIXME: detect B0+ stepping and use auto training */
14636                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14637         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14638                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14639                 if (IS_BROADWELL(dev)) {
14640                         dev_priv->display.modeset_commit_cdclk =
14641                                 broadwell_modeset_commit_cdclk;
14642                         dev_priv->display.modeset_calc_cdclk =
14643                                 broadwell_modeset_calc_cdclk;
14644                 }
14645         } else if (IS_VALLEYVIEW(dev)) {
14646                 dev_priv->display.modeset_commit_cdclk =
14647                         valleyview_modeset_commit_cdclk;
14648                 dev_priv->display.modeset_calc_cdclk =
14649                         valleyview_modeset_calc_cdclk;
14650         } else if (IS_BROXTON(dev)) {
14651                 dev_priv->display.modeset_commit_cdclk =
14652                         broxton_modeset_commit_cdclk;
14653                 dev_priv->display.modeset_calc_cdclk =
14654                         broxton_modeset_calc_cdclk;
14655         }
14656
14657         switch (INTEL_INFO(dev)->gen) {
14658         case 2:
14659                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14660                 break;
14661
14662         case 3:
14663                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14664                 break;
14665
14666         case 4:
14667         case 5:
14668                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14669                 break;
14670
14671         case 6:
14672                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14673                 break;
14674         case 7:
14675         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14676                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14677                 break;
14678         case 9:
14679                 /* Drop through - unsupported since execlist only. */
14680         default:
14681                 /* Default just returns -ENODEV to indicate unsupported */
14682                 dev_priv->display.queue_flip = intel_default_queue_flip;
14683         }
14684
14685         intel_panel_init_backlight_funcs(dev);
14686
14687         mutex_init(&dev_priv->pps_mutex);
14688 }
14689
14690 /*
14691  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14692  * resume, or other times.  This quirk makes sure that's the case for
14693  * affected systems.
14694  */
14695 static void quirk_pipea_force(struct drm_device *dev)
14696 {
14697         struct drm_i915_private *dev_priv = dev->dev_private;
14698
14699         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14700         DRM_INFO("applying pipe a force quirk\n");
14701 }
14702
14703 static void quirk_pipeb_force(struct drm_device *dev)
14704 {
14705         struct drm_i915_private *dev_priv = dev->dev_private;
14706
14707         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14708         DRM_INFO("applying pipe b force quirk\n");
14709 }
14710
14711 /*
14712  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14713  */
14714 static void quirk_ssc_force_disable(struct drm_device *dev)
14715 {
14716         struct drm_i915_private *dev_priv = dev->dev_private;
14717         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14718         DRM_INFO("applying lvds SSC disable quirk\n");
14719 }
14720
14721 /*
14722  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14723  * brightness value
14724  */
14725 static void quirk_invert_brightness(struct drm_device *dev)
14726 {
14727         struct drm_i915_private *dev_priv = dev->dev_private;
14728         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14729         DRM_INFO("applying inverted panel brightness quirk\n");
14730 }
14731
14732 /* Some VBT's incorrectly indicate no backlight is present */
14733 static void quirk_backlight_present(struct drm_device *dev)
14734 {
14735         struct drm_i915_private *dev_priv = dev->dev_private;
14736         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14737         DRM_INFO("applying backlight present quirk\n");
14738 }
14739
14740 struct intel_quirk {
14741         int device;
14742         int subsystem_vendor;
14743         int subsystem_device;
14744         void (*hook)(struct drm_device *dev);
14745 };
14746
14747 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14748 struct intel_dmi_quirk {
14749         void (*hook)(struct drm_device *dev);
14750         const struct dmi_system_id (*dmi_id_list)[];
14751 };
14752
14753 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14754 {
14755         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14756         return 1;
14757 }
14758
14759 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14760         {
14761                 .dmi_id_list = &(const struct dmi_system_id[]) {
14762                         {
14763                                 .callback = intel_dmi_reverse_brightness,
14764                                 .ident = "NCR Corporation",
14765                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14766                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14767                                 },
14768                         },
14769                         { }  /* terminating entry */
14770                 },
14771                 .hook = quirk_invert_brightness,
14772         },
14773 };
14774
14775 static struct intel_quirk intel_quirks[] = {
14776         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14777         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14778
14779         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14780         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14781
14782         /* 830 needs to leave pipe A & dpll A up */
14783         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14784
14785         /* 830 needs to leave pipe B & dpll B up */
14786         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14787
14788         /* Lenovo U160 cannot use SSC on LVDS */
14789         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14790
14791         /* Sony Vaio Y cannot use SSC on LVDS */
14792         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14793
14794         /* Acer Aspire 5734Z must invert backlight brightness */
14795         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14796
14797         /* Acer/eMachines G725 */
14798         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14799
14800         /* Acer/eMachines e725 */
14801         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14802
14803         /* Acer/Packard Bell NCL20 */
14804         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14805
14806         /* Acer Aspire 4736Z */
14807         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14808
14809         /* Acer Aspire 5336 */
14810         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14811
14812         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14813         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14814
14815         /* Acer C720 Chromebook (Core i3 4005U) */
14816         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14817
14818         /* Apple Macbook 2,1 (Core 2 T7400) */
14819         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14820
14821         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14822         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14823
14824         /* HP Chromebook 14 (Celeron 2955U) */
14825         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14826
14827         /* Dell Chromebook 11 */
14828         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14829 };
14830
14831 static void intel_init_quirks(struct drm_device *dev)
14832 {
14833         struct pci_dev *d = dev->pdev;
14834         int i;
14835
14836         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14837                 struct intel_quirk *q = &intel_quirks[i];
14838
14839                 if (d->device == q->device &&
14840                     (d->subsystem_vendor == q->subsystem_vendor ||
14841                      q->subsystem_vendor == PCI_ANY_ID) &&
14842                     (d->subsystem_device == q->subsystem_device ||
14843                      q->subsystem_device == PCI_ANY_ID))
14844                         q->hook(dev);
14845         }
14846         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14847                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14848                         intel_dmi_quirks[i].hook(dev);
14849         }
14850 }
14851
14852 /* Disable the VGA plane that we never use */
14853 static void i915_disable_vga(struct drm_device *dev)
14854 {
14855         struct drm_i915_private *dev_priv = dev->dev_private;
14856         u8 sr1;
14857         u32 vga_reg = i915_vgacntrl_reg(dev);
14858
14859         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14860         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14861         outb(SR01, VGA_SR_INDEX);
14862         sr1 = inb(VGA_SR_DATA);
14863         outb(sr1 | 1<<5, VGA_SR_DATA);
14864         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14865         udelay(300);
14866
14867         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14868         POSTING_READ(vga_reg);
14869 }
14870
14871 void intel_modeset_init_hw(struct drm_device *dev)
14872 {
14873         intel_update_cdclk(dev);
14874         intel_prepare_ddi(dev);
14875         intel_init_clock_gating(dev);
14876         intel_enable_gt_powersave(dev);
14877 }
14878
14879 void intel_modeset_init(struct drm_device *dev)
14880 {
14881         struct drm_i915_private *dev_priv = dev->dev_private;
14882         int sprite, ret;
14883         enum pipe pipe;
14884         struct intel_crtc *crtc;
14885
14886         drm_mode_config_init(dev);
14887
14888         dev->mode_config.min_width = 0;
14889         dev->mode_config.min_height = 0;
14890
14891         dev->mode_config.preferred_depth = 24;
14892         dev->mode_config.prefer_shadow = 1;
14893
14894         dev->mode_config.allow_fb_modifiers = true;
14895
14896         dev->mode_config.funcs = &intel_mode_funcs;
14897
14898         intel_init_quirks(dev);
14899
14900         intel_init_pm(dev);
14901
14902         if (INTEL_INFO(dev)->num_pipes == 0)
14903                 return;
14904
14905         intel_init_display(dev);
14906         intel_init_audio(dev);
14907
14908         if (IS_GEN2(dev)) {
14909                 dev->mode_config.max_width = 2048;
14910                 dev->mode_config.max_height = 2048;
14911         } else if (IS_GEN3(dev)) {
14912                 dev->mode_config.max_width = 4096;
14913                 dev->mode_config.max_height = 4096;
14914         } else {
14915                 dev->mode_config.max_width = 8192;
14916                 dev->mode_config.max_height = 8192;
14917         }
14918
14919         if (IS_845G(dev) || IS_I865G(dev)) {
14920                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14921                 dev->mode_config.cursor_height = 1023;
14922         } else if (IS_GEN2(dev)) {
14923                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14924                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14925         } else {
14926                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14927                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14928         }
14929
14930         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14931
14932         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14933                       INTEL_INFO(dev)->num_pipes,
14934                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14935
14936         for_each_pipe(dev_priv, pipe) {
14937                 intel_crtc_init(dev, pipe);
14938                 for_each_sprite(dev_priv, pipe, sprite) {
14939                         ret = intel_plane_init(dev, pipe, sprite);
14940                         if (ret)
14941                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14942                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14943                 }
14944         }
14945
14946         intel_init_dpio(dev);
14947
14948         intel_shared_dpll_init(dev);
14949
14950         /* Just disable it once at startup */
14951         i915_disable_vga(dev);
14952         intel_setup_outputs(dev);
14953
14954         /* Just in case the BIOS is doing something questionable. */
14955         intel_fbc_disable(dev_priv);
14956
14957         drm_modeset_lock_all(dev);
14958         intel_modeset_setup_hw_state(dev);
14959         drm_modeset_unlock_all(dev);
14960
14961         for_each_intel_crtc(dev, crtc) {
14962                 struct intel_initial_plane_config plane_config = {};
14963
14964                 if (!crtc->active)
14965                         continue;
14966
14967                 /*
14968                  * Note that reserving the BIOS fb up front prevents us
14969                  * from stuffing other stolen allocations like the ring
14970                  * on top.  This prevents some ugliness at boot time, and
14971                  * can even allow for smooth boot transitions if the BIOS
14972                  * fb is large enough for the active pipe configuration.
14973                  */
14974                 dev_priv->display.get_initial_plane_config(crtc,
14975                                                            &plane_config);
14976
14977                 /*
14978                  * If the fb is shared between multiple heads, we'll
14979                  * just get the first one.
14980                  */
14981                 intel_find_initial_plane_obj(crtc, &plane_config);
14982         }
14983 }
14984
14985 static void intel_enable_pipe_a(struct drm_device *dev)
14986 {
14987         struct intel_connector *connector;
14988         struct drm_connector *crt = NULL;
14989         struct intel_load_detect_pipe load_detect_temp;
14990         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14991
14992         /* We can't just switch on the pipe A, we need to set things up with a
14993          * proper mode and output configuration. As a gross hack, enable pipe A
14994          * by enabling the load detect pipe once. */
14995         for_each_intel_connector(dev, connector) {
14996                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14997                         crt = &connector->base;
14998                         break;
14999                 }
15000         }
15001
15002         if (!crt)
15003                 return;
15004
15005         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15006                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15007 }
15008
15009 static bool
15010 intel_check_plane_mapping(struct intel_crtc *crtc)
15011 {
15012         struct drm_device *dev = crtc->base.dev;
15013         struct drm_i915_private *dev_priv = dev->dev_private;
15014         u32 reg, val;
15015
15016         if (INTEL_INFO(dev)->num_pipes == 1)
15017                 return true;
15018
15019         reg = DSPCNTR(!crtc->plane);
15020         val = I915_READ(reg);
15021
15022         if ((val & DISPLAY_PLANE_ENABLE) &&
15023             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15024                 return false;
15025
15026         return true;
15027 }
15028
15029 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15030 {
15031         struct drm_device *dev = crtc->base.dev;
15032         struct drm_i915_private *dev_priv = dev->dev_private;
15033         struct intel_encoder *encoder;
15034         u32 reg;
15035         bool enable;
15036
15037         /* Clear any frame start delays used for debugging left by the BIOS */
15038         reg = PIPECONF(crtc->config->cpu_transcoder);
15039         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15040
15041         /* restore vblank interrupts to correct state */
15042         drm_crtc_vblank_reset(&crtc->base);
15043         if (crtc->active) {
15044                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15045                 update_scanline_offset(crtc);
15046                 drm_crtc_vblank_on(&crtc->base);
15047         }
15048
15049         /* We need to sanitize the plane -> pipe mapping first because this will
15050          * disable the crtc (and hence change the state) if it is wrong. Note
15051          * that gen4+ has a fixed plane -> pipe mapping.  */
15052         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15053                 bool plane;
15054
15055                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15056                               crtc->base.base.id);
15057
15058                 /* Pipe has the wrong plane attached and the plane is active.
15059                  * Temporarily change the plane mapping and disable everything
15060                  * ...  */
15061                 plane = crtc->plane;
15062                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15063                 crtc->plane = !plane;
15064                 intel_crtc_disable_noatomic(&crtc->base);
15065                 crtc->plane = plane;
15066         }
15067
15068         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15069             crtc->pipe == PIPE_A && !crtc->active) {
15070                 /* BIOS forgot to enable pipe A, this mostly happens after
15071                  * resume. Force-enable the pipe to fix this, the update_dpms
15072                  * call below we restore the pipe to the right state, but leave
15073                  * the required bits on. */
15074                 intel_enable_pipe_a(dev);
15075         }
15076
15077         /* Adjust the state of the output pipe according to whether we
15078          * have active connectors/encoders. */
15079         enable = false;
15080         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15081                 enable |= encoder->connectors_active;
15082
15083         if (!enable)
15084                 intel_crtc_disable_noatomic(&crtc->base);
15085
15086         if (crtc->active != crtc->base.state->active) {
15087
15088                 /* This can happen either due to bugs in the get_hw_state
15089                  * functions or because of calls to intel_crtc_disable_noatomic,
15090                  * or because the pipe is force-enabled due to the
15091                  * pipe A quirk. */
15092                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15093                               crtc->base.base.id,
15094                               crtc->base.state->enable ? "enabled" : "disabled",
15095                               crtc->active ? "enabled" : "disabled");
15096
15097                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15098                 crtc->base.state->active = crtc->active;
15099                 crtc->base.enabled = crtc->active;
15100
15101                 /* Because we only establish the connector -> encoder ->
15102                  * crtc links if something is active, this means the
15103                  * crtc is now deactivated. Break the links. connector
15104                  * -> encoder links are only establish when things are
15105                  *  actually up, hence no need to break them. */
15106                 WARN_ON(crtc->active);
15107
15108                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15109                         WARN_ON(encoder->connectors_active);
15110                         encoder->base.crtc = NULL;
15111                 }
15112         }
15113
15114         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15115                 /*
15116                  * We start out with underrun reporting disabled to avoid races.
15117                  * For correct bookkeeping mark this on active crtcs.
15118                  *
15119                  * Also on gmch platforms we dont have any hardware bits to
15120                  * disable the underrun reporting. Which means we need to start
15121                  * out with underrun reporting disabled also on inactive pipes,
15122                  * since otherwise we'll complain about the garbage we read when
15123                  * e.g. coming up after runtime pm.
15124                  *
15125                  * No protection against concurrent access is required - at
15126                  * worst a fifo underrun happens which also sets this to false.
15127                  */
15128                 crtc->cpu_fifo_underrun_disabled = true;
15129                 crtc->pch_fifo_underrun_disabled = true;
15130         }
15131 }
15132
15133 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15134 {
15135         struct intel_connector *connector;
15136         struct drm_device *dev = encoder->base.dev;
15137
15138         /* We need to check both for a crtc link (meaning that the
15139          * encoder is active and trying to read from a pipe) and the
15140          * pipe itself being active. */
15141         bool has_active_crtc = encoder->base.crtc &&
15142                 to_intel_crtc(encoder->base.crtc)->active;
15143
15144         if (encoder->connectors_active && !has_active_crtc) {
15145                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15146                               encoder->base.base.id,
15147                               encoder->base.name);
15148
15149                 /* Connector is active, but has no active pipe. This is
15150                  * fallout from our resume register restoring. Disable
15151                  * the encoder manually again. */
15152                 if (encoder->base.crtc) {
15153                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15154                                       encoder->base.base.id,
15155                                       encoder->base.name);
15156                         encoder->disable(encoder);
15157                         if (encoder->post_disable)
15158                                 encoder->post_disable(encoder);
15159                 }
15160                 encoder->base.crtc = NULL;
15161                 encoder->connectors_active = false;
15162
15163                 /* Inconsistent output/port/pipe state happens presumably due to
15164                  * a bug in one of the get_hw_state functions. Or someplace else
15165                  * in our code, like the register restore mess on resume. Clamp
15166                  * things to off as a safer default. */
15167                 for_each_intel_connector(dev, connector) {
15168                         if (connector->encoder != encoder)
15169                                 continue;
15170                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15171                         connector->base.encoder = NULL;
15172                 }
15173         }
15174         /* Enabled encoders without active connectors will be fixed in
15175          * the crtc fixup. */
15176 }
15177
15178 void i915_redisable_vga_power_on(struct drm_device *dev)
15179 {
15180         struct drm_i915_private *dev_priv = dev->dev_private;
15181         u32 vga_reg = i915_vgacntrl_reg(dev);
15182
15183         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15184                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15185                 i915_disable_vga(dev);
15186         }
15187 }
15188
15189 void i915_redisable_vga(struct drm_device *dev)
15190 {
15191         struct drm_i915_private *dev_priv = dev->dev_private;
15192
15193         /* This function can be called both from intel_modeset_setup_hw_state or
15194          * at a very early point in our resume sequence, where the power well
15195          * structures are not yet restored. Since this function is at a very
15196          * paranoid "someone might have enabled VGA while we were not looking"
15197          * level, just check if the power well is enabled instead of trying to
15198          * follow the "don't touch the power well if we don't need it" policy
15199          * the rest of the driver uses. */
15200         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15201                 return;
15202
15203         i915_redisable_vga_power_on(dev);
15204 }
15205
15206 static bool primary_get_hw_state(struct intel_crtc *crtc)
15207 {
15208         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15209
15210         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15211 }
15212
15213 static void readout_plane_state(struct intel_crtc *crtc,
15214                                 struct intel_crtc_state *crtc_state)
15215 {
15216         struct intel_plane *p;
15217         struct intel_plane_state *plane_state;
15218         bool active = crtc_state->base.active;
15219
15220         for_each_intel_plane(crtc->base.dev, p) {
15221                 if (crtc->pipe != p->pipe)
15222                         continue;
15223
15224                 plane_state = to_intel_plane_state(p->base.state);
15225
15226                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15227                         plane_state->visible = primary_get_hw_state(crtc);
15228                 else {
15229                         if (active)
15230                                 p->disable_plane(&p->base, &crtc->base);
15231
15232                         plane_state->visible = false;
15233                 }
15234         }
15235 }
15236
15237 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15238 {
15239         struct drm_i915_private *dev_priv = dev->dev_private;
15240         enum pipe pipe;
15241         struct intel_crtc *crtc;
15242         struct intel_encoder *encoder;
15243         struct intel_connector *connector;
15244         int i;
15245
15246         for_each_intel_crtc(dev, crtc) {
15247                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15248                 memset(crtc->config, 0, sizeof(*crtc->config));
15249                 crtc->config->base.crtc = &crtc->base;
15250
15251                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15252
15253                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15254                                                                  crtc->config);
15255
15256                 crtc->base.state->active = crtc->active;
15257                 crtc->base.enabled = crtc->active;
15258
15259                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15260                 if (crtc->base.state->active) {
15261                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15262                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15263                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15264
15265                         /*
15266                          * The initial mode needs to be set in order to keep
15267                          * the atomic core happy. It wants a valid mode if the
15268                          * crtc's enabled, so we do the above call.
15269                          *
15270                          * At this point some state updated by the connectors
15271                          * in their ->detect() callback has not run yet, so
15272                          * no recalculation can be done yet.
15273                          *
15274                          * Even if we could do a recalculation and modeset
15275                          * right now it would cause a double modeset if
15276                          * fbdev or userspace chooses a different initial mode.
15277                          *
15278                          * So to prevent the double modeset, fail the memcmp
15279                          * test in drm_atomic_set_mode_for_crtc to get a new
15280                          * mode blob, and compare if the mode blob changed
15281                          * when the PIPE_CONFIG_QUIRK_INHERITED_MODE quirk is
15282                          * set.
15283                          *
15284                          * If that happens, someone indicated they wanted a
15285                          * mode change, which means it's safe to do a full
15286                          * recalculation.
15287                          */
15288                         crtc->base.state->mode.private_flags = ~0;
15289                 }
15290
15291                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15292                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15293
15294                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15295                               crtc->base.base.id,
15296                               crtc->active ? "enabled" : "disabled");
15297         }
15298
15299         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15300                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15301
15302                 pll->on = pll->get_hw_state(dev_priv, pll,
15303                                             &pll->config.hw_state);
15304                 pll->active = 0;
15305                 pll->config.crtc_mask = 0;
15306                 for_each_intel_crtc(dev, crtc) {
15307                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15308                                 pll->active++;
15309                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15310                         }
15311                 }
15312
15313                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15314                               pll->name, pll->config.crtc_mask, pll->on);
15315
15316                 if (pll->config.crtc_mask)
15317                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15318         }
15319
15320         for_each_intel_encoder(dev, encoder) {
15321                 pipe = 0;
15322
15323                 if (encoder->get_hw_state(encoder, &pipe)) {
15324                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15325                         encoder->base.crtc = &crtc->base;
15326                         encoder->get_config(encoder, crtc->config);
15327                 } else {
15328                         encoder->base.crtc = NULL;
15329                 }
15330
15331                 encoder->connectors_active = false;
15332                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15333                               encoder->base.base.id,
15334                               encoder->base.name,
15335                               encoder->base.crtc ? "enabled" : "disabled",
15336                               pipe_name(pipe));
15337         }
15338
15339         for_each_intel_connector(dev, connector) {
15340                 if (connector->get_hw_state(connector)) {
15341                         connector->base.dpms = DRM_MODE_DPMS_ON;
15342                         connector->encoder->connectors_active = true;
15343                         connector->base.encoder = &connector->encoder->base;
15344                 } else {
15345                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15346                         connector->base.encoder = NULL;
15347                 }
15348                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15349                               connector->base.base.id,
15350                               connector->base.name,
15351                               connector->base.encoder ? "enabled" : "disabled");
15352         }
15353 }
15354
15355 /* Scan out the current hw modeset state,
15356  * and sanitizes it to the current state
15357  */
15358 static void
15359 intel_modeset_setup_hw_state(struct drm_device *dev)
15360 {
15361         struct drm_i915_private *dev_priv = dev->dev_private;
15362         enum pipe pipe;
15363         struct intel_crtc *crtc;
15364         struct intel_encoder *encoder;
15365         int i;
15366
15367         intel_modeset_readout_hw_state(dev);
15368
15369         /* HW state is read out, now we need to sanitize this mess. */
15370         for_each_intel_encoder(dev, encoder) {
15371                 intel_sanitize_encoder(encoder);
15372         }
15373
15374         for_each_pipe(dev_priv, pipe) {
15375                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15376                 intel_sanitize_crtc(crtc);
15377                 intel_dump_pipe_config(crtc, crtc->config,
15378                                        "[setup_hw_state]");
15379         }
15380
15381         intel_modeset_update_connector_atomic_state(dev);
15382
15383         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15384                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15385
15386                 if (!pll->on || pll->active)
15387                         continue;
15388
15389                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15390
15391                 pll->disable(dev_priv, pll);
15392                 pll->on = false;
15393         }
15394
15395         if (IS_VALLEYVIEW(dev))
15396                 vlv_wm_get_hw_state(dev);
15397         else if (IS_GEN9(dev))
15398                 skl_wm_get_hw_state(dev);
15399         else if (HAS_PCH_SPLIT(dev))
15400                 ilk_wm_get_hw_state(dev);
15401
15402         for_each_intel_crtc(dev, crtc) {
15403                 unsigned long put_domains;
15404
15405                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15406                 if (WARN_ON(put_domains))
15407                         modeset_put_power_domains(dev_priv, put_domains);
15408         }
15409         intel_display_set_init_power(dev_priv, false);
15410 }
15411
15412 void intel_display_resume(struct drm_device *dev)
15413 {
15414         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15415         struct intel_connector *conn;
15416         struct intel_plane *plane;
15417         struct drm_crtc *crtc;
15418         int ret;
15419
15420         if (!state)
15421                 return;
15422
15423         state->acquire_ctx = dev->mode_config.acquire_ctx;
15424
15425         /* preserve complete old state, including dpll */
15426         intel_atomic_get_shared_dpll_state(state);
15427
15428         for_each_crtc(dev, crtc) {
15429                 struct drm_crtc_state *crtc_state =
15430                         drm_atomic_get_crtc_state(state, crtc);
15431
15432                 ret = PTR_ERR_OR_ZERO(crtc_state);
15433                 if (ret)
15434                         goto err;
15435
15436                 /* force a restore */
15437                 crtc_state->mode_changed = true;
15438         }
15439
15440         for_each_intel_plane(dev, plane) {
15441                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15442                 if (ret)
15443                         goto err;
15444         }
15445
15446         for_each_intel_connector(dev, conn) {
15447                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15448                 if (ret)
15449                         goto err;
15450         }
15451
15452         intel_modeset_setup_hw_state(dev);
15453
15454         i915_redisable_vga(dev);
15455         ret = drm_atomic_commit(state);
15456         if (!ret)
15457                 return;
15458
15459 err:
15460         DRM_ERROR("Restoring old state failed with %i\n", ret);
15461         drm_atomic_state_free(state);
15462 }
15463
15464 void intel_modeset_gem_init(struct drm_device *dev)
15465 {
15466         struct drm_i915_private *dev_priv = dev->dev_private;
15467         struct drm_crtc *c;
15468         struct drm_i915_gem_object *obj;
15469         int ret;
15470
15471         mutex_lock(&dev->struct_mutex);
15472         intel_init_gt_powersave(dev);
15473         mutex_unlock(&dev->struct_mutex);
15474
15475         /*
15476          * There may be no VBT; and if the BIOS enabled SSC we can
15477          * just keep using it to avoid unnecessary flicker.  Whereas if the
15478          * BIOS isn't using it, don't assume it will work even if the VBT
15479          * indicates as much.
15480          */
15481         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15482                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15483                                                 DREF_SSC1_ENABLE);
15484
15485         intel_modeset_init_hw(dev);
15486
15487         intel_setup_overlay(dev);
15488
15489         /*
15490          * Make sure any fbs we allocated at startup are properly
15491          * pinned & fenced.  When we do the allocation it's too early
15492          * for this.
15493          */
15494         for_each_crtc(dev, c) {
15495                 obj = intel_fb_obj(c->primary->fb);
15496                 if (obj == NULL)
15497                         continue;
15498
15499                 mutex_lock(&dev->struct_mutex);
15500                 ret = intel_pin_and_fence_fb_obj(c->primary,
15501                                                  c->primary->fb,
15502                                                  c->primary->state,
15503                                                  NULL, NULL);
15504                 mutex_unlock(&dev->struct_mutex);
15505                 if (ret) {
15506                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15507                                   to_intel_crtc(c)->pipe);
15508                         drm_framebuffer_unreference(c->primary->fb);
15509                         c->primary->fb = NULL;
15510                         c->primary->crtc = c->primary->state->crtc = NULL;
15511                         update_state_fb(c->primary);
15512                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15513                 }
15514         }
15515
15516         intel_backlight_register(dev);
15517 }
15518
15519 void intel_connector_unregister(struct intel_connector *intel_connector)
15520 {
15521         struct drm_connector *connector = &intel_connector->base;
15522
15523         intel_panel_destroy_backlight(connector);
15524         drm_connector_unregister(connector);
15525 }
15526
15527 void intel_modeset_cleanup(struct drm_device *dev)
15528 {
15529         struct drm_i915_private *dev_priv = dev->dev_private;
15530         struct drm_connector *connector;
15531
15532         intel_disable_gt_powersave(dev);
15533
15534         intel_backlight_unregister(dev);
15535
15536         /*
15537          * Interrupts and polling as the first thing to avoid creating havoc.
15538          * Too much stuff here (turning of connectors, ...) would
15539          * experience fancy races otherwise.
15540          */
15541         intel_irq_uninstall(dev_priv);
15542
15543         /*
15544          * Due to the hpd irq storm handling the hotplug work can re-arm the
15545          * poll handlers. Hence disable polling after hpd handling is shut down.
15546          */
15547         drm_kms_helper_poll_fini(dev);
15548
15549         intel_unregister_dsm_handler();
15550
15551         intel_fbc_disable(dev_priv);
15552
15553         /* flush any delayed tasks or pending work */
15554         flush_scheduled_work();
15555
15556         /* destroy the backlight and sysfs files before encoders/connectors */
15557         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15558                 struct intel_connector *intel_connector;
15559
15560                 intel_connector = to_intel_connector(connector);
15561                 intel_connector->unregister(intel_connector);
15562         }
15563
15564         drm_mode_config_cleanup(dev);
15565
15566         intel_cleanup_overlay(dev);
15567
15568         mutex_lock(&dev->struct_mutex);
15569         intel_cleanup_gt_powersave(dev);
15570         mutex_unlock(&dev->struct_mutex);
15571 }
15572
15573 /*
15574  * Return which encoder is currently attached for connector.
15575  */
15576 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15577 {
15578         return &intel_attached_encoder(connector)->base;
15579 }
15580
15581 void intel_connector_attach_encoder(struct intel_connector *connector,
15582                                     struct intel_encoder *encoder)
15583 {
15584         connector->encoder = encoder;
15585         drm_mode_connector_attach_encoder(&connector->base,
15586                                           &encoder->base);
15587 }
15588
15589 /*
15590  * set vga decode state - true == enable VGA decode
15591  */
15592 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15593 {
15594         struct drm_i915_private *dev_priv = dev->dev_private;
15595         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15596         u16 gmch_ctrl;
15597
15598         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15599                 DRM_ERROR("failed to read control word\n");
15600                 return -EIO;
15601         }
15602
15603         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15604                 return 0;
15605
15606         if (state)
15607                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15608         else
15609                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15610
15611         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15612                 DRM_ERROR("failed to write control word\n");
15613                 return -EIO;
15614         }
15615
15616         return 0;
15617 }
15618
15619 struct intel_display_error_state {
15620
15621         u32 power_well_driver;
15622
15623         int num_transcoders;
15624
15625         struct intel_cursor_error_state {
15626                 u32 control;
15627                 u32 position;
15628                 u32 base;
15629                 u32 size;
15630         } cursor[I915_MAX_PIPES];
15631
15632         struct intel_pipe_error_state {
15633                 bool power_domain_on;
15634                 u32 source;
15635                 u32 stat;
15636         } pipe[I915_MAX_PIPES];
15637
15638         struct intel_plane_error_state {
15639                 u32 control;
15640                 u32 stride;
15641                 u32 size;
15642                 u32 pos;
15643                 u32 addr;
15644                 u32 surface;
15645                 u32 tile_offset;
15646         } plane[I915_MAX_PIPES];
15647
15648         struct intel_transcoder_error_state {
15649                 bool power_domain_on;
15650                 enum transcoder cpu_transcoder;
15651
15652                 u32 conf;
15653
15654                 u32 htotal;
15655                 u32 hblank;
15656                 u32 hsync;
15657                 u32 vtotal;
15658                 u32 vblank;
15659                 u32 vsync;
15660         } transcoder[4];
15661 };
15662
15663 struct intel_display_error_state *
15664 intel_display_capture_error_state(struct drm_device *dev)
15665 {
15666         struct drm_i915_private *dev_priv = dev->dev_private;
15667         struct intel_display_error_state *error;
15668         int transcoders[] = {
15669                 TRANSCODER_A,
15670                 TRANSCODER_B,
15671                 TRANSCODER_C,
15672                 TRANSCODER_EDP,
15673         };
15674         int i;
15675
15676         if (INTEL_INFO(dev)->num_pipes == 0)
15677                 return NULL;
15678
15679         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15680         if (error == NULL)
15681                 return NULL;
15682
15683         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15684                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15685
15686         for_each_pipe(dev_priv, i) {
15687                 error->pipe[i].power_domain_on =
15688                         __intel_display_power_is_enabled(dev_priv,
15689                                                          POWER_DOMAIN_PIPE(i));
15690                 if (!error->pipe[i].power_domain_on)
15691                         continue;
15692
15693                 error->cursor[i].control = I915_READ(CURCNTR(i));
15694                 error->cursor[i].position = I915_READ(CURPOS(i));
15695                 error->cursor[i].base = I915_READ(CURBASE(i));
15696
15697                 error->plane[i].control = I915_READ(DSPCNTR(i));
15698                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15699                 if (INTEL_INFO(dev)->gen <= 3) {
15700                         error->plane[i].size = I915_READ(DSPSIZE(i));
15701                         error->plane[i].pos = I915_READ(DSPPOS(i));
15702                 }
15703                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15704                         error->plane[i].addr = I915_READ(DSPADDR(i));
15705                 if (INTEL_INFO(dev)->gen >= 4) {
15706                         error->plane[i].surface = I915_READ(DSPSURF(i));
15707                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15708                 }
15709
15710                 error->pipe[i].source = I915_READ(PIPESRC(i));
15711
15712                 if (HAS_GMCH_DISPLAY(dev))
15713                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15714         }
15715
15716         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15717         if (HAS_DDI(dev_priv->dev))
15718                 error->num_transcoders++; /* Account for eDP. */
15719
15720         for (i = 0; i < error->num_transcoders; i++) {
15721                 enum transcoder cpu_transcoder = transcoders[i];
15722
15723                 error->transcoder[i].power_domain_on =
15724                         __intel_display_power_is_enabled(dev_priv,
15725                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15726                 if (!error->transcoder[i].power_domain_on)
15727                         continue;
15728
15729                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15730
15731                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15732                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15733                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15734                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15735                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15736                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15737                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15738         }
15739
15740         return error;
15741 }
15742
15743 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15744
15745 void
15746 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15747                                 struct drm_device *dev,
15748                                 struct intel_display_error_state *error)
15749 {
15750         struct drm_i915_private *dev_priv = dev->dev_private;
15751         int i;
15752
15753         if (!error)
15754                 return;
15755
15756         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15757         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15758                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15759                            error->power_well_driver);
15760         for_each_pipe(dev_priv, i) {
15761                 err_printf(m, "Pipe [%d]:\n", i);
15762                 err_printf(m, "  Power: %s\n",
15763                            error->pipe[i].power_domain_on ? "on" : "off");
15764                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15765                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15766
15767                 err_printf(m, "Plane [%d]:\n", i);
15768                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15769                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15770                 if (INTEL_INFO(dev)->gen <= 3) {
15771                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15772                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15773                 }
15774                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15775                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15776                 if (INTEL_INFO(dev)->gen >= 4) {
15777                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15778                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15779                 }
15780
15781                 err_printf(m, "Cursor [%d]:\n", i);
15782                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15783                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15784                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15785         }
15786
15787         for (i = 0; i < error->num_transcoders; i++) {
15788                 err_printf(m, "CPU transcoder: %c\n",
15789                            transcoder_name(error->transcoder[i].cpu_transcoder));
15790                 err_printf(m, "  Power: %s\n",
15791                            error->transcoder[i].power_domain_on ? "on" : "off");
15792                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15793                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15794                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15795                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15796                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15797                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15798                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15799         }
15800 }
15801
15802 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15803 {
15804         struct intel_crtc *crtc;
15805
15806         for_each_intel_crtc(dev, crtc) {
15807                 struct intel_unpin_work *work;
15808
15809                 spin_lock_irq(&dev->event_lock);
15810
15811                 work = crtc->unpin_work;
15812
15813                 if (work && work->event &&
15814                     work->event->base.file_priv == file) {
15815                         kfree(work->event);
15816                         work->event = NULL;
15817                 }
15818
15819                 spin_unlock_irq(&dev->event_lock);
15820         }
15821 }