drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         i915_reg_t reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         i915_reg_t pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1484                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1485                         return false;
1486         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488                         return false;
1489         } else {
1490                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1491                         return false;
1492         }
1493         return true;
1494 }
1495
1496 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1497                               enum pipe pipe, u32 val)
1498 {
1499         if ((val & SDVO_ENABLE) == 0)
1500                 return false;
1501
1502         if (HAS_PCH_CPT(dev_priv->dev)) {
1503                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1504                         return false;
1505         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1506                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507                         return false;
1508         } else {
1509                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1510                         return false;
1511         }
1512         return true;
1513 }
1514
1515 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1516                               enum pipe pipe, u32 val)
1517 {
1518         if ((val & LVDS_PORT_EN) == 0)
1519                 return false;
1520
1521         if (HAS_PCH_CPT(dev_priv->dev)) {
1522                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523                         return false;
1524         } else {
1525                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1526                         return false;
1527         }
1528         return true;
1529 }
1530
1531 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1532                               enum pipe pipe, u32 val)
1533 {
1534         if ((val & ADPA_DAC_ENABLE) == 0)
1535                 return false;
1536         if (HAS_PCH_CPT(dev_priv->dev)) {
1537                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538                         return false;
1539         } else {
1540                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1541                         return false;
1542         }
1543         return true;
1544 }
1545
1546 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1547                                    enum pipe pipe, i915_reg_t reg,
1548                                    u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              i915_mmio_reg_offset(reg), pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, i915_reg_t reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              i915_mmio_reg_offset(reg), pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         i915_reg_t reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         i915_reg_t reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Wait for the clocks to stabilize. */
1717         POSTING_READ(reg);
1718         udelay(150);
1719
1720         if (INTEL_INFO(dev)->gen >= 4) {
1721                 I915_WRITE(DPLL_MD(crtc->pipe),
1722                            crtc->config->dpll_hw_state.dpll_md);
1723         } else {
1724                 /* The pixel multiplier can only be updated once the
1725                  * DPLL is enabled and the clocks are stable.
1726                  *
1727                  * So write it again.
1728                  */
1729                 I915_WRITE(reg, dpll);
1730         }
1731
1732         /* We do this three times for luck */
1733         I915_WRITE(reg, dpll);
1734         POSTING_READ(reg);
1735         udelay(150); /* wait for warmup */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745  * i9xx_disable_pll - disable a PLL
1746  * @dev_priv: i915 private structure
1747  * @pipe: pipe PLL to disable
1748  *
1749  * Disable the PLL for @pipe, making sure the pipe is off first.
1750  *
1751  * Note!  This is for pre-ILK only.
1752  */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755         struct drm_device *dev = crtc->base.dev;
1756         struct drm_i915_private *dev_priv = dev->dev_private;
1757         enum pipe pipe = crtc->pipe;
1758
1759         /* Disable DVO 2x clock on both PLLs if necessary */
1760         if (IS_I830(dev) &&
1761             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762             !intel_num_dvo_pipes(dev)) {
1763                 I915_WRITE(DPLL(PIPE_B),
1764                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765                 I915_WRITE(DPLL(PIPE_A),
1766                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767         }
1768
1769         /* Don't disable pipe or pipe PLLs if needed */
1770         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772                 return;
1773
1774         /* Make sure the pipe isn't still relying on us */
1775         assert_pipe_disabled(dev_priv, pipe);
1776
1777         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778         POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783         u32 val;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         /*
1789          * Leave integrated clock source and reference clock enabled for pipe B.
1790          * The latter is needed for VGA hotplug / manual detection.
1791          */
1792         val = DPLL_VGA_MODE_DIS;
1793         if (pipe == PIPE_B)
1794                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795         I915_WRITE(DPLL(pipe), val);
1796         POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803         u32 val;
1804
1805         /* Make sure the pipe isn't still relying on us */
1806         assert_pipe_disabled(dev_priv, pipe);
1807
1808         /* Set PLL en = 0 */
1809         val = DPLL_SSC_REF_CLK_CHV |
1810                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811         if (pipe != PIPE_A)
1812                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813         I915_WRITE(DPLL(pipe), val);
1814         POSTING_READ(DPLL(pipe));
1815
1816         mutex_lock(&dev_priv->sb_lock);
1817
1818         /* Disable 10bit clock to display controller */
1819         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820         val &= ~DPIO_DCLKP_EN;
1821         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823         mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827                          struct intel_digital_port *dport,
1828                          unsigned int expected_mask)
1829 {
1830         u32 port_mask;
1831         i915_reg_t dpll_reg;
1832
1833         switch (dport->port) {
1834         case PORT_B:
1835                 port_mask = DPLL_PORTB_READY_MASK;
1836                 dpll_reg = DPLL(0);
1837                 break;
1838         case PORT_C:
1839                 port_mask = DPLL_PORTC_READY_MASK;
1840                 dpll_reg = DPLL(0);
1841                 expected_mask <<= 4;
1842                 break;
1843         case PORT_D:
1844                 port_mask = DPLL_PORTD_READY_MASK;
1845                 dpll_reg = DPIO_PHY_STATUS;
1846                 break;
1847         default:
1848                 BUG();
1849         }
1850
1851         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858         struct drm_device *dev = crtc->base.dev;
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862         if (WARN_ON(pll == NULL))
1863                 return;
1864
1865         WARN_ON(!pll->config.crtc_mask);
1866         if (pll->active == 0) {
1867                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868                 WARN_ON(pll->on);
1869                 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871                 pll->mode_set(dev_priv, pll);
1872         }
1873 }
1874
1875 /**
1876  * intel_enable_shared_dpll - enable PCH PLL
1877  * @dev_priv: i915 private structure
1878  * @pipe: pipe PLL to enable
1879  *
1880  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881  * drives the transcoder clock.
1882  */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885         struct drm_device *dev = crtc->base.dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889         if (WARN_ON(pll == NULL))
1890                 return;
1891
1892         if (WARN_ON(pll->config.crtc_mask == 0))
1893                 return;
1894
1895         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896                       pll->name, pll->active, pll->on,
1897                       crtc->base.base.id);
1898
1899         if (pll->active++) {
1900                 WARN_ON(!pll->on);
1901                 assert_shared_dpll_enabled(dev_priv, pll);
1902                 return;
1903         }
1904         WARN_ON(pll->on);
1905
1906         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909         pll->enable(dev_priv, pll);
1910         pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915         struct drm_device *dev = crtc->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919         /* PCH only available on ILK+ */
1920         if (INTEL_INFO(dev)->gen < 5)
1921                 return;
1922
1923         if (pll == NULL)
1924                 return;
1925
1926         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927                 return;
1928
1929         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930                       pll->name, pll->active, pll->on,
1931                       crtc->base.base.id);
1932
1933         if (WARN_ON(pll->active == 0)) {
1934                 assert_shared_dpll_disabled(dev_priv, pll);
1935                 return;
1936         }
1937
1938         assert_shared_dpll_enabled(dev_priv, pll);
1939         WARN_ON(!pll->on);
1940         if (--pll->active)
1941                 return;
1942
1943         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944         pll->disable(dev_priv, pll);
1945         pll->on = false;
1946
1947         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951                                            enum pipe pipe)
1952 {
1953         struct drm_device *dev = dev_priv->dev;
1954         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956         i915_reg_t reg;
1957         uint32_t val, pipeconf_val;
1958
1959         /* PCH only available on ILK+ */
1960         BUG_ON(!HAS_PCH_SPLIT(dev));
1961
1962         /* Make sure PCH DPLL is enabled */
1963         assert_shared_dpll_enabled(dev_priv,
1964                                    intel_crtc_to_shared_dpll(intel_crtc));
1965
1966         /* FDI must be feeding us bits for PCH ports */
1967         assert_fdi_tx_enabled(dev_priv, pipe);
1968         assert_fdi_rx_enabled(dev_priv, pipe);
1969
1970         if (HAS_PCH_CPT(dev)) {
1971                 /* Workaround: Set the timing override bit before enabling the
1972                  * pch transcoder. */
1973                 reg = TRANS_CHICKEN2(pipe);
1974                 val = I915_READ(reg);
1975                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1976                 I915_WRITE(reg, val);
1977         }
1978
1979         reg = PCH_TRANSCONF(pipe);
1980         val = I915_READ(reg);
1981         pipeconf_val = I915_READ(PIPECONF(pipe));
1982
1983         if (HAS_PCH_IBX(dev_priv->dev)) {
1984                 /*
1985                  * Make the BPC in transcoder be consistent with
1986                  * that in pipeconf reg. For HDMI we must use 8bpc
1987                  * here for both 8bpc and 12bpc.
1988                  */
1989                 val &= ~PIPECONF_BPC_MASK;
1990                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1991                         val |= PIPECONF_8BPC;
1992                 else
1993                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1994         }
1995
1996         val &= ~TRANS_INTERLACE_MASK;
1997         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1998                 if (HAS_PCH_IBX(dev_priv->dev) &&
1999                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2000                         val |= TRANS_LEGACY_INTERLACED_ILK;
2001                 else
2002                         val |= TRANS_INTERLACED;
2003         else
2004                 val |= TRANS_PROGRESSIVE;
2005
2006         I915_WRITE(reg, val | TRANS_ENABLE);
2007         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2008                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2009 }
2010
2011 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2012                                       enum transcoder cpu_transcoder)
2013 {
2014         u32 val, pipeconf_val;
2015
2016         /* PCH only available on ILK+ */
2017         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018
2019         /* FDI must be feeding us bits for PCH ports */
2020         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2021         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022
2023         /* Workaround: set timing override bit. */
2024         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2025         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2026         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2027
2028         val = TRANS_ENABLE;
2029         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030
2031         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2032             PIPECONF_INTERLACED_ILK)
2033                 val |= TRANS_INTERLACED;
2034         else
2035                 val |= TRANS_PROGRESSIVE;
2036
2037         I915_WRITE(LPT_TRANSCONF, val);
2038         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2039                 DRM_ERROR("Failed to enable PCH transcoder\n");
2040 }
2041
2042 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2043                                             enum pipe pipe)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         i915_reg_t reg;
2047         uint32_t val;
2048
2049         /* FDI relies on the transcoder */
2050         assert_fdi_tx_disabled(dev_priv, pipe);
2051         assert_fdi_rx_disabled(dev_priv, pipe);
2052
2053         /* Ports must be off as well */
2054         assert_pch_ports_disabled(dev_priv, pipe);
2055
2056         reg = PCH_TRANSCONF(pipe);
2057         val = I915_READ(reg);
2058         val &= ~TRANS_ENABLE;
2059         I915_WRITE(reg, val);
2060         /* wait for PCH transcoder off, transcoder state */
2061         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2062                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2063
2064         if (HAS_PCH_CPT(dev)) {
2065                 /* Workaround: Clear the timing override chicken bit again. */
2066                 reg = TRANS_CHICKEN2(pipe);
2067                 val = I915_READ(reg);
2068                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2069                 I915_WRITE(reg, val);
2070         }
2071 }
2072
2073 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2074 {
2075         u32 val;
2076
2077         val = I915_READ(LPT_TRANSCONF);
2078         val &= ~TRANS_ENABLE;
2079         I915_WRITE(LPT_TRANSCONF, val);
2080         /* wait for PCH transcoder off, transcoder state */
2081         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2082                 DRM_ERROR("Failed to disable PCH transcoder\n");
2083
2084         /* Workaround: clear timing override bit. */
2085         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2086         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2087         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2088 }
2089
2090 /**
2091  * intel_enable_pipe - enable a pipe, asserting requirements
2092  * @crtc: crtc responsible for the pipe
2093  *
2094  * Enable @crtc's pipe, making sure that various hardware specific requirements
2095  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2096  */
2097 static void intel_enable_pipe(struct intel_crtc *crtc)
2098 {
2099         struct drm_device *dev = crtc->base.dev;
2100         struct drm_i915_private *dev_priv = dev->dev_private;
2101         enum pipe pipe = crtc->pipe;
2102         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2103         enum pipe pch_transcoder;
2104         i915_reg_t reg;
2105         u32 val;
2106
2107         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108
2109         assert_planes_disabled(dev_priv, pipe);
2110         assert_cursor_disabled(dev_priv, pipe);
2111         assert_sprites_disabled(dev_priv, pipe);
2112
2113         if (HAS_PCH_LPT(dev_priv->dev))
2114                 pch_transcoder = TRANSCODER_A;
2115         else
2116                 pch_transcoder = pipe;
2117
2118         /*
2119          * A pipe without a PLL won't actually be able to drive bits from
2120          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2121          * need the check.
2122          */
2123         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2124                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2125                         assert_dsi_pll_enabled(dev_priv);
2126                 else
2127                         assert_pll_enabled(dev_priv, pipe);
2128         else {
2129                 if (crtc->config->has_pch_encoder) {
2130                         /* if driving the PCH, we need FDI enabled */
2131                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2132                         assert_fdi_tx_pll_enabled(dev_priv,
2133                                                   (enum pipe) cpu_transcoder);
2134                 }
2135                 /* FIXME: assert CPU port conditions for SNB+ */
2136         }
2137
2138         reg = PIPECONF(cpu_transcoder);
2139         val = I915_READ(reg);
2140         if (val & PIPECONF_ENABLE) {
2141                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2142                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2143                 return;
2144         }
2145
2146         I915_WRITE(reg, val | PIPECONF_ENABLE);
2147         POSTING_READ(reg);
2148 }
2149
2150 /**
2151  * intel_disable_pipe - disable a pipe, asserting requirements
2152  * @crtc: crtc whose pipes is to be disabled
2153  *
2154  * Disable the pipe of @crtc, making sure that various hardware
2155  * specific requirements are met, if applicable, e.g. plane
2156  * disabled, panel fitter off, etc.
2157  *
2158  * Will wait until the pipe has shut down before returning.
2159  */
2160 static void intel_disable_pipe(struct intel_crtc *crtc)
2161 {
2162         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2163         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2164         enum pipe pipe = crtc->pipe;
2165         i915_reg_t reg;
2166         u32 val;
2167
2168         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2169
2170         /*
2171          * Make sure planes won't keep trying to pump pixels to us,
2172          * or we might hang the display.
2173          */
2174         assert_planes_disabled(dev_priv, pipe);
2175         assert_cursor_disabled(dev_priv, pipe);
2176         assert_sprites_disabled(dev_priv, pipe);
2177
2178         reg = PIPECONF(cpu_transcoder);
2179         val = I915_READ(reg);
2180         if ((val & PIPECONF_ENABLE) == 0)
2181                 return;
2182
2183         /*
2184          * Double wide has implications for planes
2185          * so best keep it disabled when not needed.
2186          */
2187         if (crtc->config->double_wide)
2188                 val &= ~PIPECONF_DOUBLE_WIDE;
2189
2190         /* Don't disable pipe or pipe PLLs if needed */
2191         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2192             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2193                 val &= ~PIPECONF_ENABLE;
2194
2195         I915_WRITE(reg, val);
2196         if ((val & PIPECONF_ENABLE) == 0)
2197                 intel_wait_for_pipe_off(crtc);
2198 }
2199
2200 static bool need_vtd_wa(struct drm_device *dev)
2201 {
2202 #ifdef CONFIG_INTEL_IOMMU
2203         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2204                 return true;
2205 #endif
2206         return false;
2207 }
2208
2209 unsigned int
2210 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2211                   uint64_t fb_format_modifier, unsigned int plane)
2212 {
2213         unsigned int tile_height;
2214         uint32_t pixel_bytes;
2215
2216         switch (fb_format_modifier) {
2217         case DRM_FORMAT_MOD_NONE:
2218                 tile_height = 1;
2219                 break;
2220         case I915_FORMAT_MOD_X_TILED:
2221                 tile_height = IS_GEN2(dev) ? 16 : 8;
2222                 break;
2223         case I915_FORMAT_MOD_Y_TILED:
2224                 tile_height = 32;
2225                 break;
2226         case I915_FORMAT_MOD_Yf_TILED:
2227                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2228                 switch (pixel_bytes) {
2229                 default:
2230                 case 1:
2231                         tile_height = 64;
2232                         break;
2233                 case 2:
2234                 case 4:
2235                         tile_height = 32;
2236                         break;
2237                 case 8:
2238                         tile_height = 16;
2239                         break;
2240                 case 16:
2241                         WARN_ONCE(1,
2242                                   "128-bit pixels are not supported for display!");
2243                         tile_height = 16;
2244                         break;
2245                 }
2246                 break;
2247         default:
2248                 MISSING_CASE(fb_format_modifier);
2249                 tile_height = 1;
2250                 break;
2251         }
2252
2253         return tile_height;
2254 }
2255
2256 unsigned int
2257 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2258                       uint32_t pixel_format, uint64_t fb_format_modifier)
2259 {
2260         return ALIGN(height, intel_tile_height(dev, pixel_format,
2261                                                fb_format_modifier, 0));
2262 }
2263
2264 static void
2265 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2266                         const struct drm_plane_state *plane_state)
2267 {
2268         struct intel_rotation_info *info = &view->rotation_info;
2269         unsigned int tile_height, tile_pitch;
2270
2271         *view = i915_ggtt_view_normal;
2272
2273         if (!plane_state)
2274                 return;
2275
2276         if (!intel_rotation_90_or_270(plane_state->rotation))
2277                 return;
2278
2279         *view = i915_ggtt_view_rotated;
2280
2281         info->height = fb->height;
2282         info->pixel_format = fb->pixel_format;
2283         info->pitch = fb->pitches[0];
2284         info->uv_offset = fb->offsets[1];
2285         info->fb_modifier = fb->modifier[0];
2286
2287         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2288                                         fb->modifier[0], 0);
2289         tile_pitch = PAGE_SIZE / tile_height;
2290         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2291         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2292         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2293
2294         if (info->pixel_format == DRM_FORMAT_NV12) {
2295                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296                                                 fb->modifier[0], 1);
2297                 tile_pitch = PAGE_SIZE / tile_height;
2298                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2300                                                      tile_height);
2301                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2302                                 PAGE_SIZE;
2303         }
2304 }
2305
2306 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2307 {
2308         if (INTEL_INFO(dev_priv)->gen >= 9)
2309                 return 256 * 1024;
2310         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2311                  IS_VALLEYVIEW(dev_priv))
2312                 return 128 * 1024;
2313         else if (INTEL_INFO(dev_priv)->gen >= 4)
2314                 return 4 * 1024;
2315         else
2316                 return 0;
2317 }
2318
2319 int
2320 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2321                            struct drm_framebuffer *fb,
2322                            const struct drm_plane_state *plane_state)
2323 {
2324         struct drm_device *dev = fb->dev;
2325         struct drm_i915_private *dev_priv = dev->dev_private;
2326         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2327         struct i915_ggtt_view view;
2328         u32 alignment;
2329         int ret;
2330
2331         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2332
2333         switch (fb->modifier[0]) {
2334         case DRM_FORMAT_MOD_NONE:
2335                 alignment = intel_linear_alignment(dev_priv);
2336                 break;
2337         case I915_FORMAT_MOD_X_TILED:
2338                 if (INTEL_INFO(dev)->gen >= 9)
2339                         alignment = 256 * 1024;
2340                 else {
2341                         /* pin() will align the object as required by fence */
2342                         alignment = 0;
2343                 }
2344                 break;
2345         case I915_FORMAT_MOD_Y_TILED:
2346         case I915_FORMAT_MOD_Yf_TILED:
2347                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2348                           "Y tiling bo slipped through, driver bug!\n"))
2349                         return -EINVAL;
2350                 alignment = 1 * 1024 * 1024;
2351                 break;
2352         default:
2353                 MISSING_CASE(fb->modifier[0]);
2354                 return -EINVAL;
2355         }
2356
2357         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2358
2359         /* Note that the w/a also requires 64 PTE of padding following the
2360          * bo. We currently fill all unused PTE with the shadow page and so
2361          * we should always have valid PTE following the scanout preventing
2362          * the VT-d warning.
2363          */
2364         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2365                 alignment = 256 * 1024;
2366
2367         /*
2368          * Global gtt pte registers are special registers which actually forward
2369          * writes to a chunk of system memory. Which means that there is no risk
2370          * that the register values disappear as soon as we call
2371          * intel_runtime_pm_put(), so it is correct to wrap only the
2372          * pin/unpin/fence and not more.
2373          */
2374         intel_runtime_pm_get(dev_priv);
2375
2376         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2377                                                    &view);
2378         if (ret)
2379                 goto err_pm;
2380
2381         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2382          * fence, whereas 965+ only requires a fence if using
2383          * framebuffer compression.  For simplicity, we always install
2384          * a fence as the cost is not that onerous.
2385          */
2386         ret = i915_gem_object_get_fence(obj);
2387         if (ret == -EDEADLK) {
2388                 /*
2389                  * -EDEADLK means there are no free fences
2390                  * no pending flips.
2391                  *
2392                  * This is propagated to atomic, but it uses
2393                  * -EDEADLK to force a locking recovery, so
2394                  * change the returned error to -EBUSY.
2395                  */
2396                 ret = -EBUSY;
2397                 goto err_unpin;
2398         } else if (ret)
2399                 goto err_unpin;
2400
2401         i915_gem_object_pin_fence(obj);
2402
2403         intel_runtime_pm_put(dev_priv);
2404         return 0;
2405
2406 err_unpin:
2407         i915_gem_object_unpin_from_display_plane(obj, &view);
2408 err_pm:
2409         intel_runtime_pm_put(dev_priv);
2410         return ret;
2411 }
2412
2413 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2414                                const struct drm_plane_state *plane_state)
2415 {
2416         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2417         struct i915_ggtt_view view;
2418
2419         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2420
2421         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2422
2423         i915_gem_object_unpin_fence(obj);
2424         i915_gem_object_unpin_from_display_plane(obj, &view);
2425 }
2426
2427 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2428  * is assumed to be a power-of-two. */
2429 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2430                                              int *x, int *y,
2431                                              unsigned int tiling_mode,
2432                                              unsigned int cpp,
2433                                              unsigned int pitch)
2434 {
2435         if (tiling_mode != I915_TILING_NONE) {
2436                 unsigned int tile_rows, tiles;
2437
2438                 tile_rows = *y / 8;
2439                 *y %= 8;
2440
2441                 tiles = *x / (512/cpp);
2442                 *x %= 512/cpp;
2443
2444                 return tile_rows * pitch * 8 + tiles * 4096;
2445         } else {
2446                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2447                 unsigned int offset;
2448
2449                 offset = *y * pitch + *x * cpp;
2450                 *y = (offset & alignment) / pitch;
2451                 *x = ((offset & alignment) - *y * pitch) / cpp;
2452                 return offset & ~alignment;
2453         }
2454 }
2455
2456 static int i9xx_format_to_fourcc(int format)
2457 {
2458         switch (format) {
2459         case DISPPLANE_8BPP:
2460                 return DRM_FORMAT_C8;
2461         case DISPPLANE_BGRX555:
2462                 return DRM_FORMAT_XRGB1555;
2463         case DISPPLANE_BGRX565:
2464                 return DRM_FORMAT_RGB565;
2465         default:
2466         case DISPPLANE_BGRX888:
2467                 return DRM_FORMAT_XRGB8888;
2468         case DISPPLANE_RGBX888:
2469                 return DRM_FORMAT_XBGR8888;
2470         case DISPPLANE_BGRX101010:
2471                 return DRM_FORMAT_XRGB2101010;
2472         case DISPPLANE_RGBX101010:
2473                 return DRM_FORMAT_XBGR2101010;
2474         }
2475 }
2476
2477 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2478 {
2479         switch (format) {
2480         case PLANE_CTL_FORMAT_RGB_565:
2481                 return DRM_FORMAT_RGB565;
2482         default:
2483         case PLANE_CTL_FORMAT_XRGB_8888:
2484                 if (rgb_order) {
2485                         if (alpha)
2486                                 return DRM_FORMAT_ABGR8888;
2487                         else
2488                                 return DRM_FORMAT_XBGR8888;
2489                 } else {
2490                         if (alpha)
2491                                 return DRM_FORMAT_ARGB8888;
2492                         else
2493                                 return DRM_FORMAT_XRGB8888;
2494                 }
2495         case PLANE_CTL_FORMAT_XRGB_2101010:
2496                 if (rgb_order)
2497                         return DRM_FORMAT_XBGR2101010;
2498                 else
2499                         return DRM_FORMAT_XRGB2101010;
2500         }
2501 }
2502
2503 static bool
2504 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2505                               struct intel_initial_plane_config *plane_config)
2506 {
2507         struct drm_device *dev = crtc->base.dev;
2508         struct drm_i915_private *dev_priv = to_i915(dev);
2509         struct drm_i915_gem_object *obj = NULL;
2510         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2511         struct drm_framebuffer *fb = &plane_config->fb->base;
2512         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2513         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2514                                     PAGE_SIZE);
2515
2516         size_aligned -= base_aligned;
2517
2518         if (plane_config->size == 0)
2519                 return false;
2520
2521         /* If the FB is too big, just don't use it since fbdev is not very
2522          * important and we should probably use that space with FBC or other
2523          * features. */
2524         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2525                 return false;
2526
2527         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528                                                              base_aligned,
2529                                                              base_aligned,
2530                                                              size_aligned);
2531         if (!obj)
2532                 return false;
2533
2534         obj->tiling_mode = plane_config->tiling;
2535         if (obj->tiling_mode == I915_TILING_X)
2536                 obj->stride = fb->pitches[0];
2537
2538         mode_cmd.pixel_format = fb->pixel_format;
2539         mode_cmd.width = fb->width;
2540         mode_cmd.height = fb->height;
2541         mode_cmd.pitches[0] = fb->pitches[0];
2542         mode_cmd.modifier[0] = fb->modifier[0];
2543         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544
2545         mutex_lock(&dev->struct_mutex);
2546         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2547                                    &mode_cmd, obj)) {
2548                 DRM_DEBUG_KMS("intel fb init failed\n");
2549                 goto out_unref_obj;
2550         }
2551         mutex_unlock(&dev->struct_mutex);
2552
2553         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554         return true;
2555
2556 out_unref_obj:
2557         drm_gem_object_unreference(&obj->base);
2558         mutex_unlock(&dev->struct_mutex);
2559         return false;
2560 }
2561
2562 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2563 static void
2564 update_state_fb(struct drm_plane *plane)
2565 {
2566         if (plane->fb == plane->state->fb)
2567                 return;
2568
2569         if (plane->state->fb)
2570                 drm_framebuffer_unreference(plane->state->fb);
2571         plane->state->fb = plane->fb;
2572         if (plane->state->fb)
2573                 drm_framebuffer_reference(plane->state->fb);
2574 }
2575
2576 static void
2577 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2578                              struct intel_initial_plane_config *plane_config)
2579 {
2580         struct drm_device *dev = intel_crtc->base.dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct drm_crtc *c;
2583         struct intel_crtc *i;
2584         struct drm_i915_gem_object *obj;
2585         struct drm_plane *primary = intel_crtc->base.primary;
2586         struct drm_plane_state *plane_state = primary->state;
2587         struct drm_framebuffer *fb;
2588
2589         if (!plane_config->fb)
2590                 return;
2591
2592         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2593                 fb = &plane_config->fb->base;
2594                 goto valid_fb;
2595         }
2596
2597         kfree(plane_config->fb);
2598
2599         /*
2600          * Failed to alloc the obj, check to see if we should share
2601          * an fb with another CRTC instead
2602          */
2603         for_each_crtc(dev, c) {
2604                 i = to_intel_crtc(c);
2605
2606                 if (c == &intel_crtc->base)
2607                         continue;
2608
2609                 if (!i->active)
2610                         continue;
2611
2612                 fb = c->primary->fb;
2613                 if (!fb)
2614                         continue;
2615
2616                 obj = intel_fb_obj(fb);
2617                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2618                         drm_framebuffer_reference(fb);
2619                         goto valid_fb;
2620                 }
2621         }
2622
2623         return;
2624
2625 valid_fb:
2626         plane_state->src_x = plane_state->src_y = 0;
2627         plane_state->src_w = fb->width << 16;
2628         plane_state->src_h = fb->height << 16;
2629
2630         plane_state->crtc_x = plane_state->src_y = 0;
2631         plane_state->crtc_w = fb->width;
2632         plane_state->crtc_h = fb->height;
2633
2634         obj = intel_fb_obj(fb);
2635         if (obj->tiling_mode != I915_TILING_NONE)
2636                 dev_priv->preserve_bios_swizzle = true;
2637
2638         drm_framebuffer_reference(fb);
2639         primary->fb = primary->state->fb = fb;
2640         primary->crtc = primary->state->crtc = &intel_crtc->base;
2641         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2642         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2643 }
2644
2645 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646                                       struct drm_framebuffer *fb,
2647                                       int x, int y)
2648 {
2649         struct drm_device *dev = crtc->dev;
2650         struct drm_i915_private *dev_priv = dev->dev_private;
2651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652         struct drm_plane *primary = crtc->primary;
2653         bool visible = to_intel_plane_state(primary->state)->visible;
2654         struct drm_i915_gem_object *obj;
2655         int plane = intel_crtc->plane;
2656         unsigned long linear_offset;
2657         u32 dspcntr;
2658         i915_reg_t reg = DSPCNTR(plane);
2659         int pixel_size;
2660
2661         if (!visible || !fb) {
2662                 I915_WRITE(reg, 0);
2663                 if (INTEL_INFO(dev)->gen >= 4)
2664                         I915_WRITE(DSPSURF(plane), 0);
2665                 else
2666                         I915_WRITE(DSPADDR(plane), 0);
2667                 POSTING_READ(reg);
2668                 return;
2669         }
2670
2671         obj = intel_fb_obj(fb);
2672         if (WARN_ON(obj == NULL))
2673                 return;
2674
2675         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
2677         dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
2679         dspcntr |= DISPLAY_PLANE_ENABLE;
2680
2681         if (INTEL_INFO(dev)->gen < 4) {
2682                 if (intel_crtc->pipe == PIPE_B)
2683                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685                 /* pipesrc and dspsize control the size that is scaled from,
2686                  * which should always be the user's requested size.
2687                  */
2688                 I915_WRITE(DSPSIZE(plane),
2689                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690                            (intel_crtc->config->pipe_src_w - 1));
2691                 I915_WRITE(DSPPOS(plane), 0);
2692         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693                 I915_WRITE(PRIMSIZE(plane),
2694                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695                            (intel_crtc->config->pipe_src_w - 1));
2696                 I915_WRITE(PRIMPOS(plane), 0);
2697                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698         }
2699
2700         switch (fb->pixel_format) {
2701         case DRM_FORMAT_C8:
2702                 dspcntr |= DISPPLANE_8BPP;
2703                 break;
2704         case DRM_FORMAT_XRGB1555:
2705                 dspcntr |= DISPPLANE_BGRX555;
2706                 break;
2707         case DRM_FORMAT_RGB565:
2708                 dspcntr |= DISPPLANE_BGRX565;
2709                 break;
2710         case DRM_FORMAT_XRGB8888:
2711                 dspcntr |= DISPPLANE_BGRX888;
2712                 break;
2713         case DRM_FORMAT_XBGR8888:
2714                 dspcntr |= DISPPLANE_RGBX888;
2715                 break;
2716         case DRM_FORMAT_XRGB2101010:
2717                 dspcntr |= DISPPLANE_BGRX101010;
2718                 break;
2719         case DRM_FORMAT_XBGR2101010:
2720                 dspcntr |= DISPPLANE_RGBX101010;
2721                 break;
2722         default:
2723                 BUG();
2724         }
2725
2726         if (INTEL_INFO(dev)->gen >= 4 &&
2727             obj->tiling_mode != I915_TILING_NONE)
2728                 dspcntr |= DISPPLANE_TILED;
2729
2730         if (IS_G4X(dev))
2731                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2732
2733         linear_offset = y * fb->pitches[0] + x * pixel_size;
2734
2735         if (INTEL_INFO(dev)->gen >= 4) {
2736                 intel_crtc->dspaddr_offset =
2737                         intel_gen4_compute_page_offset(dev_priv,
2738                                                        &x, &y, obj->tiling_mode,
2739                                                        pixel_size,
2740                                                        fb->pitches[0]);
2741                 linear_offset -= intel_crtc->dspaddr_offset;
2742         } else {
2743                 intel_crtc->dspaddr_offset = linear_offset;
2744         }
2745
2746         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2747                 dspcntr |= DISPPLANE_ROTATE_180;
2748
2749                 x += (intel_crtc->config->pipe_src_w - 1);
2750                 y += (intel_crtc->config->pipe_src_h - 1);
2751
2752                 /* Finding the last pixel of the last line of the display
2753                 data and adding to linear_offset*/
2754                 linear_offset +=
2755                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2756                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2757         }
2758
2759         intel_crtc->adjusted_x = x;
2760         intel_crtc->adjusted_y = y;
2761
2762         I915_WRITE(reg, dspcntr);
2763
2764         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765         if (INTEL_INFO(dev)->gen >= 4) {
2766                 I915_WRITE(DSPSURF(plane),
2767                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2768                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770         } else
2771                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2772         POSTING_READ(reg);
2773 }
2774
2775 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776                                           struct drm_framebuffer *fb,
2777                                           int x, int y)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         struct drm_plane *primary = crtc->primary;
2783         bool visible = to_intel_plane_state(primary->state)->visible;
2784         struct drm_i915_gem_object *obj;
2785         int plane = intel_crtc->plane;
2786         unsigned long linear_offset;
2787         u32 dspcntr;
2788         i915_reg_t reg = DSPCNTR(plane);
2789         int pixel_size;
2790
2791         if (!visible || !fb) {
2792                 I915_WRITE(reg, 0);
2793                 I915_WRITE(DSPSURF(plane), 0);
2794                 POSTING_READ(reg);
2795                 return;
2796         }
2797
2798         obj = intel_fb_obj(fb);
2799         if (WARN_ON(obj == NULL))
2800                 return;
2801
2802         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
2804         dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
2806         dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811         switch (fb->pixel_format) {
2812         case DRM_FORMAT_C8:
2813                 dspcntr |= DISPPLANE_8BPP;
2814                 break;
2815         case DRM_FORMAT_RGB565:
2816                 dspcntr |= DISPPLANE_BGRX565;
2817                 break;
2818         case DRM_FORMAT_XRGB8888:
2819                 dspcntr |= DISPPLANE_BGRX888;
2820                 break;
2821         case DRM_FORMAT_XBGR8888:
2822                 dspcntr |= DISPPLANE_RGBX888;
2823                 break;
2824         case DRM_FORMAT_XRGB2101010:
2825                 dspcntr |= DISPPLANE_BGRX101010;
2826                 break;
2827         case DRM_FORMAT_XBGR2101010:
2828                 dspcntr |= DISPPLANE_RGBX101010;
2829                 break;
2830         default:
2831                 BUG();
2832         }
2833
2834         if (obj->tiling_mode != I915_TILING_NONE)
2835                 dspcntr |= DISPPLANE_TILED;
2836
2837         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2839
2840         linear_offset = y * fb->pitches[0] + x * pixel_size;
2841         intel_crtc->dspaddr_offset =
2842                 intel_gen4_compute_page_offset(dev_priv,
2843                                                &x, &y, obj->tiling_mode,
2844                                                pixel_size,
2845                                                fb->pitches[0]);
2846         linear_offset -= intel_crtc->dspaddr_offset;
2847         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2848                 dspcntr |= DISPPLANE_ROTATE_180;
2849
2850                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2851                         x += (intel_crtc->config->pipe_src_w - 1);
2852                         y += (intel_crtc->config->pipe_src_h - 1);
2853
2854                         /* Finding the last pixel of the last line of the display
2855                         data and adding to linear_offset*/
2856                         linear_offset +=
2857                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2858                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2859                 }
2860         }
2861
2862         intel_crtc->adjusted_x = x;
2863         intel_crtc->adjusted_y = y;
2864
2865         I915_WRITE(reg, dspcntr);
2866
2867         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2868         I915_WRITE(DSPSURF(plane),
2869                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2870         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2871                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872         } else {
2873                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875         }
2876         POSTING_READ(reg);
2877 }
2878
2879 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880                               uint32_t pixel_format)
2881 {
2882         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884         /*
2885          * The stride is either expressed as a multiple of 64 bytes
2886          * chunks for linear buffers or in number of tiles for tiled
2887          * buffers.
2888          */
2889         switch (fb_modifier) {
2890         case DRM_FORMAT_MOD_NONE:
2891                 return 64;
2892         case I915_FORMAT_MOD_X_TILED:
2893                 if (INTEL_INFO(dev)->gen == 2)
2894                         return 128;
2895                 return 512;
2896         case I915_FORMAT_MOD_Y_TILED:
2897                 /* No need to check for old gens and Y tiling since this is
2898                  * about the display engine and those will be blocked before
2899                  * we get here.
2900                  */
2901                 return 128;
2902         case I915_FORMAT_MOD_Yf_TILED:
2903                 if (bits_per_pixel == 8)
2904                         return 64;
2905                 else
2906                         return 128;
2907         default:
2908                 MISSING_CASE(fb_modifier);
2909                 return 64;
2910         }
2911 }
2912
2913 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2914                            struct drm_i915_gem_object *obj,
2915                            unsigned int plane)
2916 {
2917         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918         struct i915_vma *vma;
2919         u64 offset;
2920
2921         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2922                 view = &i915_ggtt_view_rotated;
2923
2924         vma = i915_gem_obj_to_ggtt_view(obj, view);
2925         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2926                 view->type))
2927                 return -1;
2928
2929         offset = vma->node.start;
2930
2931         if (plane == 1) {
2932                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2933                           PAGE_SIZE;
2934         }
2935
2936         WARN_ON(upper_32_bits(offset));
2937
2938         return lower_32_bits(offset);
2939 }
2940
2941 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2942 {
2943         struct drm_device *dev = intel_crtc->base.dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945
2946         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2947         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2948         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2949 }
2950
2951 /*
2952  * This function detaches (aka. unbinds) unused scalers in hardware
2953  */
2954 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2955 {
2956         struct intel_crtc_scaler_state *scaler_state;
2957         int i;
2958
2959         scaler_state = &intel_crtc->config->scaler_state;
2960
2961         /* loop through and disable scalers that aren't in use */
2962         for (i = 0; i < intel_crtc->num_scalers; i++) {
2963                 if (!scaler_state->scalers[i].in_use)
2964                         skl_detach_scaler(intel_crtc, i);
2965         }
2966 }
2967
2968 u32 skl_plane_ctl_format(uint32_t pixel_format)
2969 {
2970         switch (pixel_format) {
2971         case DRM_FORMAT_C8:
2972                 return PLANE_CTL_FORMAT_INDEXED;
2973         case DRM_FORMAT_RGB565:
2974                 return PLANE_CTL_FORMAT_RGB_565;
2975         case DRM_FORMAT_XBGR8888:
2976                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2977         case DRM_FORMAT_XRGB8888:
2978                 return PLANE_CTL_FORMAT_XRGB_8888;
2979         /*
2980          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2981          * to be already pre-multiplied. We need to add a knob (or a different
2982          * DRM_FORMAT) for user-space to configure that.
2983          */
2984         case DRM_FORMAT_ABGR8888:
2985                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2986                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2987         case DRM_FORMAT_ARGB8888:
2988                 return PLANE_CTL_FORMAT_XRGB_8888 |
2989                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2990         case DRM_FORMAT_XRGB2101010:
2991                 return PLANE_CTL_FORMAT_XRGB_2101010;
2992         case DRM_FORMAT_XBGR2101010:
2993                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2994         case DRM_FORMAT_YUYV:
2995                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2996         case DRM_FORMAT_YVYU:
2997                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2998         case DRM_FORMAT_UYVY:
2999                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3000         case DRM_FORMAT_VYUY:
3001                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3002         default:
3003                 MISSING_CASE(pixel_format);
3004         }
3005
3006         return 0;
3007 }
3008
3009 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3010 {
3011         switch (fb_modifier) {
3012         case DRM_FORMAT_MOD_NONE:
3013                 break;
3014         case I915_FORMAT_MOD_X_TILED:
3015                 return PLANE_CTL_TILED_X;
3016         case I915_FORMAT_MOD_Y_TILED:
3017                 return PLANE_CTL_TILED_Y;
3018         case I915_FORMAT_MOD_Yf_TILED:
3019                 return PLANE_CTL_TILED_YF;
3020         default:
3021                 MISSING_CASE(fb_modifier);
3022         }
3023
3024         return 0;
3025 }
3026
3027 u32 skl_plane_ctl_rotation(unsigned int rotation)
3028 {
3029         switch (rotation) {
3030         case BIT(DRM_ROTATE_0):
3031                 break;
3032         /*
3033          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3034          * while i915 HW rotation is clockwise, thats why this swapping.
3035          */
3036         case BIT(DRM_ROTATE_90):
3037                 return PLANE_CTL_ROTATE_270;
3038         case BIT(DRM_ROTATE_180):
3039                 return PLANE_CTL_ROTATE_180;
3040         case BIT(DRM_ROTATE_270):
3041                 return PLANE_CTL_ROTATE_90;
3042         default:
3043                 MISSING_CASE(rotation);
3044         }
3045
3046         return 0;
3047 }
3048
3049 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3050                                          struct drm_framebuffer *fb,
3051                                          int x, int y)
3052 {
3053         struct drm_device *dev = crtc->dev;
3054         struct drm_i915_private *dev_priv = dev->dev_private;
3055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3056         struct drm_plane *plane = crtc->primary;
3057         bool visible = to_intel_plane_state(plane->state)->visible;
3058         struct drm_i915_gem_object *obj;
3059         int pipe = intel_crtc->pipe;
3060         u32 plane_ctl, stride_div, stride;
3061         u32 tile_height, plane_offset, plane_size;
3062         unsigned int rotation;
3063         int x_offset, y_offset;
3064         u32 surf_addr;
3065         struct intel_crtc_state *crtc_state = intel_crtc->config;
3066         struct intel_plane_state *plane_state;
3067         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3068         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3069         int scaler_id = -1;
3070
3071         plane_state = to_intel_plane_state(plane->state);
3072
3073         if (!visible || !fb) {
3074                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3075                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3076                 POSTING_READ(PLANE_CTL(pipe, 0));
3077                 return;
3078         }
3079
3080         plane_ctl = PLANE_CTL_ENABLE |
3081                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3082                     PLANE_CTL_PIPE_CSC_ENABLE;
3083
3084         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3085         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3086         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3087
3088         rotation = plane->state->rotation;
3089         plane_ctl |= skl_plane_ctl_rotation(rotation);
3090
3091         obj = intel_fb_obj(fb);
3092         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3093                                                fb->pixel_format);
3094         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3095
3096         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3097
3098         scaler_id = plane_state->scaler_id;
3099         src_x = plane_state->src.x1 >> 16;
3100         src_y = plane_state->src.y1 >> 16;
3101         src_w = drm_rect_width(&plane_state->src) >> 16;
3102         src_h = drm_rect_height(&plane_state->src) >> 16;
3103         dst_x = plane_state->dst.x1;
3104         dst_y = plane_state->dst.y1;
3105         dst_w = drm_rect_width(&plane_state->dst);
3106         dst_h = drm_rect_height(&plane_state->dst);
3107
3108         WARN_ON(x != src_x || y != src_y);
3109
3110         if (intel_rotation_90_or_270(rotation)) {
3111                 /* stride = Surface height in tiles */
3112                 tile_height = intel_tile_height(dev, fb->pixel_format,
3113                                                 fb->modifier[0], 0);
3114                 stride = DIV_ROUND_UP(fb->height, tile_height);
3115                 x_offset = stride * tile_height - y - src_h;
3116                 y_offset = x;
3117                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3118         } else {
3119                 stride = fb->pitches[0] / stride_div;
3120                 x_offset = x;
3121                 y_offset = y;
3122                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3123         }
3124         plane_offset = y_offset << 16 | x_offset;
3125
3126         intel_crtc->adjusted_x = x_offset;
3127         intel_crtc->adjusted_y = y_offset;
3128
3129         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3130         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3131         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3132         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3133
3134         if (scaler_id >= 0) {
3135                 uint32_t ps_ctrl = 0;
3136
3137                 WARN_ON(!dst_w || !dst_h);
3138                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3139                         crtc_state->scaler_state.scalers[scaler_id].mode;
3140                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3141                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3142                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3143                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3144                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3145         } else {
3146                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3147         }
3148
3149         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3150
3151         POSTING_READ(PLANE_SURF(pipe, 0));
3152 }
3153
3154 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3155 static int
3156 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3157                            int x, int y, enum mode_set_atomic state)
3158 {
3159         struct drm_device *dev = crtc->dev;
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161
3162         if (dev_priv->fbc.disable_fbc)
3163                 dev_priv->fbc.disable_fbc(dev_priv);
3164
3165         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3166
3167         return 0;
3168 }
3169
3170 static void intel_complete_page_flips(struct drm_device *dev)
3171 {
3172         struct drm_crtc *crtc;
3173
3174         for_each_crtc(dev, crtc) {
3175                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176                 enum plane plane = intel_crtc->plane;
3177
3178                 intel_prepare_page_flip(dev, plane);
3179                 intel_finish_page_flip_plane(dev, plane);
3180         }
3181 }
3182
3183 static void intel_update_primary_planes(struct drm_device *dev)
3184 {
3185         struct drm_crtc *crtc;
3186
3187         for_each_crtc(dev, crtc) {
3188                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3189                 struct intel_plane_state *plane_state;
3190
3191                 drm_modeset_lock_crtc(crtc, &plane->base);
3192                 plane_state = to_intel_plane_state(plane->base.state);
3193
3194                 if (crtc->state->active && plane_state->base.fb)
3195                         plane->commit_plane(&plane->base, plane_state);
3196
3197                 drm_modeset_unlock_crtc(crtc);
3198         }
3199 }
3200
3201 void intel_prepare_reset(struct drm_device *dev)
3202 {
3203         /* no reset support for gen2 */
3204         if (IS_GEN2(dev))
3205                 return;
3206
3207         /* reset doesn't touch the display */
3208         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3209                 return;
3210
3211         drm_modeset_lock_all(dev);
3212         /*
3213          * Disabling the crtcs gracefully seems nicer. Also the
3214          * g33 docs say we should at least disable all the planes.
3215          */
3216         intel_display_suspend(dev);
3217 }
3218
3219 void intel_finish_reset(struct drm_device *dev)
3220 {
3221         struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223         /*
3224          * Flips in the rings will be nuked by the reset,
3225          * so complete all pending flips so that user space
3226          * will get its events and not get stuck.
3227          */
3228         intel_complete_page_flips(dev);
3229
3230         /* no reset support for gen2 */
3231         if (IS_GEN2(dev))
3232                 return;
3233
3234         /* reset doesn't touch the display */
3235         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236                 /*
3237                  * Flips in the rings have been nuked by the reset,
3238                  * so update the base address of all primary
3239                  * planes to the the last fb to make sure we're
3240                  * showing the correct fb after a reset.
3241                  *
3242                  * FIXME: Atomic will make this obsolete since we won't schedule
3243                  * CS-based flips (which might get lost in gpu resets) any more.
3244                  */
3245                 intel_update_primary_planes(dev);
3246                 return;
3247         }
3248
3249         /*
3250          * The display has been reset as well,
3251          * so need a full re-initialization.
3252          */
3253         intel_runtime_pm_disable_interrupts(dev_priv);
3254         intel_runtime_pm_enable_interrupts(dev_priv);
3255
3256         intel_modeset_init_hw(dev);
3257
3258         spin_lock_irq(&dev_priv->irq_lock);
3259         if (dev_priv->display.hpd_irq_setup)
3260                 dev_priv->display.hpd_irq_setup(dev);
3261         spin_unlock_irq(&dev_priv->irq_lock);
3262
3263         intel_display_resume(dev);
3264
3265         intel_hpd_init(dev_priv);
3266
3267         drm_modeset_unlock_all(dev);
3268 }
3269
3270 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3271 {
3272         struct drm_device *dev = crtc->dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275         bool pending;
3276
3277         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3278             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3279                 return false;
3280
3281         spin_lock_irq(&dev->event_lock);
3282         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3283         spin_unlock_irq(&dev->event_lock);
3284
3285         return pending;
3286 }
3287
3288 static void intel_update_pipe_config(struct intel_crtc *crtc,
3289                                      struct intel_crtc_state *old_crtc_state)
3290 {
3291         struct drm_device *dev = crtc->base.dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc_state *pipe_config =
3294                 to_intel_crtc_state(crtc->base.state);
3295
3296         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3297         crtc->base.mode = crtc->base.state->mode;
3298
3299         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3300                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3301                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3302
3303         if (HAS_DDI(dev))
3304                 intel_set_pipe_csc(&crtc->base);
3305
3306         /*
3307          * Update pipe size and adjust fitter if needed: the reason for this is
3308          * that in compute_mode_changes we check the native mode (not the pfit
3309          * mode) to see if we can flip rather than do a full mode set. In the
3310          * fastboot case, we'll flip, but if we don't update the pipesrc and
3311          * pfit state, we'll end up with a big fb scanned out into the wrong
3312          * sized surface.
3313          */
3314
3315         I915_WRITE(PIPESRC(crtc->pipe),
3316                    ((pipe_config->pipe_src_w - 1) << 16) |
3317                    (pipe_config->pipe_src_h - 1));
3318
3319         /* on skylake this is done by detaching scalers */
3320         if (INTEL_INFO(dev)->gen >= 9) {
3321                 skl_detach_scalers(crtc);
3322
3323                 if (pipe_config->pch_pfit.enabled)
3324                         skylake_pfit_enable(crtc);
3325         } else if (HAS_PCH_SPLIT(dev)) {
3326                 if (pipe_config->pch_pfit.enabled)
3327                         ironlake_pfit_enable(crtc);
3328                 else if (old_crtc_state->pch_pfit.enabled)
3329                         ironlake_pfit_disable(crtc, true);
3330         }
3331 }
3332
3333 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3334 {
3335         struct drm_device *dev = crtc->dev;
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338         int pipe = intel_crtc->pipe;
3339         i915_reg_t reg;
3340         u32 temp;
3341
3342         /* enable normal train */
3343         reg = FDI_TX_CTL(pipe);
3344         temp = I915_READ(reg);
3345         if (IS_IVYBRIDGE(dev)) {
3346                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3347                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3348         } else {
3349                 temp &= ~FDI_LINK_TRAIN_NONE;
3350                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3351         }
3352         I915_WRITE(reg, temp);
3353
3354         reg = FDI_RX_CTL(pipe);
3355         temp = I915_READ(reg);
3356         if (HAS_PCH_CPT(dev)) {
3357                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3358                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3359         } else {
3360                 temp &= ~FDI_LINK_TRAIN_NONE;
3361                 temp |= FDI_LINK_TRAIN_NONE;
3362         }
3363         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3364
3365         /* wait one idle pattern time */
3366         POSTING_READ(reg);
3367         udelay(1000);
3368
3369         /* IVB wants error correction enabled */
3370         if (IS_IVYBRIDGE(dev))
3371                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3372                            FDI_FE_ERRC_ENABLE);
3373 }
3374
3375 /* The FDI link training functions for ILK/Ibexpeak. */
3376 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3377 {
3378         struct drm_device *dev = crtc->dev;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381         int pipe = intel_crtc->pipe;
3382         i915_reg_t reg;
3383         u32 temp, tries;
3384
3385         /* FDI needs bits from pipe first */
3386         assert_pipe_enabled(dev_priv, pipe);
3387
3388         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3389            for train result */
3390         reg = FDI_RX_IMR(pipe);
3391         temp = I915_READ(reg);
3392         temp &= ~FDI_RX_SYMBOL_LOCK;
3393         temp &= ~FDI_RX_BIT_LOCK;
3394         I915_WRITE(reg, temp);
3395         I915_READ(reg);
3396         udelay(150);
3397
3398         /* enable CPU FDI TX and PCH FDI RX */
3399         reg = FDI_TX_CTL(pipe);
3400         temp = I915_READ(reg);
3401         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3402         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3403         temp &= ~FDI_LINK_TRAIN_NONE;
3404         temp |= FDI_LINK_TRAIN_PATTERN_1;
3405         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3406
3407         reg = FDI_RX_CTL(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_LINK_TRAIN_NONE;
3410         temp |= FDI_LINK_TRAIN_PATTERN_1;
3411         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3412
3413         POSTING_READ(reg);
3414         udelay(150);
3415
3416         /* Ironlake workaround, enable clock pointer after FDI enable*/
3417         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3418         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3419                    FDI_RX_PHASE_SYNC_POINTER_EN);
3420
3421         reg = FDI_RX_IIR(pipe);
3422         for (tries = 0; tries < 5; tries++) {
3423                 temp = I915_READ(reg);
3424                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3425
3426                 if ((temp & FDI_RX_BIT_LOCK)) {
3427                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3428                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3429                         break;
3430                 }
3431         }
3432         if (tries == 5)
3433                 DRM_ERROR("FDI train 1 fail!\n");
3434
3435         /* Train 2 */
3436         reg = FDI_TX_CTL(pipe);
3437         temp = I915_READ(reg);
3438         temp &= ~FDI_LINK_TRAIN_NONE;
3439         temp |= FDI_LINK_TRAIN_PATTERN_2;
3440         I915_WRITE(reg, temp);
3441
3442         reg = FDI_RX_CTL(pipe);
3443         temp = I915_READ(reg);
3444         temp &= ~FDI_LINK_TRAIN_NONE;
3445         temp |= FDI_LINK_TRAIN_PATTERN_2;
3446         I915_WRITE(reg, temp);
3447
3448         POSTING_READ(reg);
3449         udelay(150);
3450
3451         reg = FDI_RX_IIR(pipe);
3452         for (tries = 0; tries < 5; tries++) {
3453                 temp = I915_READ(reg);
3454                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3455
3456                 if (temp & FDI_RX_SYMBOL_LOCK) {
3457                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3458                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3459                         break;
3460                 }
3461         }
3462         if (tries == 5)
3463                 DRM_ERROR("FDI train 2 fail!\n");
3464
3465         DRM_DEBUG_KMS("FDI train done\n");
3466
3467 }
3468
3469 static const int snb_b_fdi_train_param[] = {
3470         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3471         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3472         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3473         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3474 };
3475
3476 /* The FDI link training functions for SNB/Cougarpoint. */
3477 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3478 {
3479         struct drm_device *dev = crtc->dev;
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482         int pipe = intel_crtc->pipe;
3483         i915_reg_t reg;
3484         u32 temp, i, retry;
3485
3486         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3487            for train result */
3488         reg = FDI_RX_IMR(pipe);
3489         temp = I915_READ(reg);
3490         temp &= ~FDI_RX_SYMBOL_LOCK;
3491         temp &= ~FDI_RX_BIT_LOCK;
3492         I915_WRITE(reg, temp);
3493
3494         POSTING_READ(reg);
3495         udelay(150);
3496
3497         /* enable CPU FDI TX and PCH FDI RX */
3498         reg = FDI_TX_CTL(pipe);
3499         temp = I915_READ(reg);
3500         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3501         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3502         temp &= ~FDI_LINK_TRAIN_NONE;
3503         temp |= FDI_LINK_TRAIN_PATTERN_1;
3504         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3505         /* SNB-B */
3506         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3507         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3508
3509         I915_WRITE(FDI_RX_MISC(pipe),
3510                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3511
3512         reg = FDI_RX_CTL(pipe);
3513         temp = I915_READ(reg);
3514         if (HAS_PCH_CPT(dev)) {
3515                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517         } else {
3518                 temp &= ~FDI_LINK_TRAIN_NONE;
3519                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520         }
3521         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3522
3523         POSTING_READ(reg);
3524         udelay(150);
3525
3526         for (i = 0; i < 4; i++) {
3527                 reg = FDI_TX_CTL(pipe);
3528                 temp = I915_READ(reg);
3529                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530                 temp |= snb_b_fdi_train_param[i];
3531                 I915_WRITE(reg, temp);
3532
3533                 POSTING_READ(reg);
3534                 udelay(500);
3535
3536                 for (retry = 0; retry < 5; retry++) {
3537                         reg = FDI_RX_IIR(pipe);
3538                         temp = I915_READ(reg);
3539                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540                         if (temp & FDI_RX_BIT_LOCK) {
3541                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3543                                 break;
3544                         }
3545                         udelay(50);
3546                 }
3547                 if (retry < 5)
3548                         break;
3549         }
3550         if (i == 4)
3551                 DRM_ERROR("FDI train 1 fail!\n");
3552
3553         /* Train 2 */
3554         reg = FDI_TX_CTL(pipe);
3555         temp = I915_READ(reg);
3556         temp &= ~FDI_LINK_TRAIN_NONE;
3557         temp |= FDI_LINK_TRAIN_PATTERN_2;
3558         if (IS_GEN6(dev)) {
3559                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560                 /* SNB-B */
3561                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3562         }
3563         I915_WRITE(reg, temp);
3564
3565         reg = FDI_RX_CTL(pipe);
3566         temp = I915_READ(reg);
3567         if (HAS_PCH_CPT(dev)) {
3568                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3570         } else {
3571                 temp &= ~FDI_LINK_TRAIN_NONE;
3572                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573         }
3574         I915_WRITE(reg, temp);
3575
3576         POSTING_READ(reg);
3577         udelay(150);
3578
3579         for (i = 0; i < 4; i++) {
3580                 reg = FDI_TX_CTL(pipe);
3581                 temp = I915_READ(reg);
3582                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583                 temp |= snb_b_fdi_train_param[i];
3584                 I915_WRITE(reg, temp);
3585
3586                 POSTING_READ(reg);
3587                 udelay(500);
3588
3589                 for (retry = 0; retry < 5; retry++) {
3590                         reg = FDI_RX_IIR(pipe);
3591                         temp = I915_READ(reg);
3592                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593                         if (temp & FDI_RX_SYMBOL_LOCK) {
3594                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3596                                 break;
3597                         }
3598                         udelay(50);
3599                 }
3600                 if (retry < 5)
3601                         break;
3602         }
3603         if (i == 4)
3604                 DRM_ERROR("FDI train 2 fail!\n");
3605
3606         DRM_DEBUG_KMS("FDI train done.\n");
3607 }
3608
3609 /* Manual link training for Ivy Bridge A0 parts */
3610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3611 {
3612         struct drm_device *dev = crtc->dev;
3613         struct drm_i915_private *dev_priv = dev->dev_private;
3614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615         int pipe = intel_crtc->pipe;
3616         i915_reg_t reg;
3617         u32 temp, i, j;
3618
3619         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3620            for train result */
3621         reg = FDI_RX_IMR(pipe);
3622         temp = I915_READ(reg);
3623         temp &= ~FDI_RX_SYMBOL_LOCK;
3624         temp &= ~FDI_RX_BIT_LOCK;
3625         I915_WRITE(reg, temp);
3626
3627         POSTING_READ(reg);
3628         udelay(150);
3629
3630         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3631                       I915_READ(FDI_RX_IIR(pipe)));
3632
3633         /* Try each vswing and preemphasis setting twice before moving on */
3634         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3635                 /* disable first in case we need to retry */
3636                 reg = FDI_TX_CTL(pipe);
3637                 temp = I915_READ(reg);
3638                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3639                 temp &= ~FDI_TX_ENABLE;
3640                 I915_WRITE(reg, temp);
3641
3642                 reg = FDI_RX_CTL(pipe);
3643                 temp = I915_READ(reg);
3644                 temp &= ~FDI_LINK_TRAIN_AUTO;
3645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3646                 temp &= ~FDI_RX_ENABLE;
3647                 I915_WRITE(reg, temp);
3648
3649                 /* enable CPU FDI TX and PCH FDI RX */
3650                 reg = FDI_TX_CTL(pipe);
3651                 temp = I915_READ(reg);
3652                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3653                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3654                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3655                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3656                 temp |= snb_b_fdi_train_param[j/2];
3657                 temp |= FDI_COMPOSITE_SYNC;
3658                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3659
3660                 I915_WRITE(FDI_RX_MISC(pipe),
3661                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3662
3663                 reg = FDI_RX_CTL(pipe);
3664                 temp = I915_READ(reg);
3665                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3666                 temp |= FDI_COMPOSITE_SYNC;
3667                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3668
3669                 POSTING_READ(reg);
3670                 udelay(1); /* should be 0.5us */
3671
3672                 for (i = 0; i < 4; i++) {
3673                         reg = FDI_RX_IIR(pipe);
3674                         temp = I915_READ(reg);
3675                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3676
3677                         if (temp & FDI_RX_BIT_LOCK ||
3678                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3679                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3680                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3681                                               i);
3682                                 break;
3683                         }
3684                         udelay(1); /* should be 0.5us */
3685                 }
3686                 if (i == 4) {
3687                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3688                         continue;
3689                 }
3690
3691                 /* Train 2 */
3692                 reg = FDI_TX_CTL(pipe);
3693                 temp = I915_READ(reg);
3694                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3695                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3696                 I915_WRITE(reg, temp);
3697
3698                 reg = FDI_RX_CTL(pipe);
3699                 temp = I915_READ(reg);
3700                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3701                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3702                 I915_WRITE(reg, temp);
3703
3704                 POSTING_READ(reg);
3705                 udelay(2); /* should be 1.5us */
3706
3707                 for (i = 0; i < 4; i++) {
3708                         reg = FDI_RX_IIR(pipe);
3709                         temp = I915_READ(reg);
3710                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3711
3712                         if (temp & FDI_RX_SYMBOL_LOCK ||
3713                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3714                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3715                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3716                                               i);
3717                                 goto train_done;
3718                         }
3719                         udelay(2); /* should be 1.5us */
3720                 }
3721                 if (i == 4)
3722                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3723         }
3724
3725 train_done:
3726         DRM_DEBUG_KMS("FDI train done.\n");
3727 }
3728
3729 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3730 {
3731         struct drm_device *dev = intel_crtc->base.dev;
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733         int pipe = intel_crtc->pipe;
3734         i915_reg_t reg;
3735         u32 temp;
3736
3737         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3738         reg = FDI_RX_CTL(pipe);
3739         temp = I915_READ(reg);
3740         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3741         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3742         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3743         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3744
3745         POSTING_READ(reg);
3746         udelay(200);
3747
3748         /* Switch from Rawclk to PCDclk */
3749         temp = I915_READ(reg);
3750         I915_WRITE(reg, temp | FDI_PCDCLK);
3751
3752         POSTING_READ(reg);
3753         udelay(200);
3754
3755         /* Enable CPU FDI TX PLL, always on for Ironlake */
3756         reg = FDI_TX_CTL(pipe);
3757         temp = I915_READ(reg);
3758         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3759                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3760
3761                 POSTING_READ(reg);
3762                 udelay(100);
3763         }
3764 }
3765
3766 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3767 {
3768         struct drm_device *dev = intel_crtc->base.dev;
3769         struct drm_i915_private *dev_priv = dev->dev_private;
3770         int pipe = intel_crtc->pipe;
3771         i915_reg_t reg;
3772         u32 temp;
3773
3774         /* Switch from PCDclk to Rawclk */
3775         reg = FDI_RX_CTL(pipe);
3776         temp = I915_READ(reg);
3777         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3778
3779         /* Disable CPU FDI TX PLL */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3783
3784         POSTING_READ(reg);
3785         udelay(100);
3786
3787         reg = FDI_RX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3790
3791         /* Wait for the clocks to turn off. */
3792         POSTING_READ(reg);
3793         udelay(100);
3794 }
3795
3796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3797 {
3798         struct drm_device *dev = crtc->dev;
3799         struct drm_i915_private *dev_priv = dev->dev_private;
3800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801         int pipe = intel_crtc->pipe;
3802         i915_reg_t reg;
3803         u32 temp;
3804
3805         /* disable CPU FDI tx and PCH FDI rx */
3806         reg = FDI_TX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3809         POSTING_READ(reg);
3810
3811         reg = FDI_RX_CTL(pipe);
3812         temp = I915_READ(reg);
3813         temp &= ~(0x7 << 16);
3814         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3815         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3816
3817         POSTING_READ(reg);
3818         udelay(100);
3819
3820         /* Ironlake workaround, disable clock pointer after downing FDI */
3821         if (HAS_PCH_IBX(dev))
3822                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3823
3824         /* still set train pattern 1 */
3825         reg = FDI_TX_CTL(pipe);
3826         temp = I915_READ(reg);
3827         temp &= ~FDI_LINK_TRAIN_NONE;
3828         temp |= FDI_LINK_TRAIN_PATTERN_1;
3829         I915_WRITE(reg, temp);
3830
3831         reg = FDI_RX_CTL(pipe);
3832         temp = I915_READ(reg);
3833         if (HAS_PCH_CPT(dev)) {
3834                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3835                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3836         } else {
3837                 temp &= ~FDI_LINK_TRAIN_NONE;
3838                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839         }
3840         /* BPC in FDI rx is consistent with that in PIPECONF */
3841         temp &= ~(0x07 << 16);
3842         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3843         I915_WRITE(reg, temp);
3844
3845         POSTING_READ(reg);
3846         udelay(100);
3847 }
3848
3849 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3850 {
3851         struct intel_crtc *crtc;
3852
3853         /* Note that we don't need to be called with mode_config.lock here
3854          * as our list of CRTC objects is static for the lifetime of the
3855          * device and so cannot disappear as we iterate. Similarly, we can
3856          * happily treat the predicates as racy, atomic checks as userspace
3857          * cannot claim and pin a new fb without at least acquring the
3858          * struct_mutex and so serialising with us.
3859          */
3860         for_each_intel_crtc(dev, crtc) {
3861                 if (atomic_read(&crtc->unpin_work_count) == 0)
3862                         continue;
3863
3864                 if (crtc->unpin_work)
3865                         intel_wait_for_vblank(dev, crtc->pipe);
3866
3867                 return true;
3868         }
3869
3870         return false;
3871 }
3872
3873 static void page_flip_completed(struct intel_crtc *intel_crtc)
3874 {
3875         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3876         struct intel_unpin_work *work = intel_crtc->unpin_work;
3877
3878         /* ensure that the unpin work is consistent wrt ->pending. */
3879         smp_rmb();
3880         intel_crtc->unpin_work = NULL;
3881
3882         if (work->event)
3883                 drm_send_vblank_event(intel_crtc->base.dev,
3884                                       intel_crtc->pipe,
3885                                       work->event);
3886
3887         drm_crtc_vblank_put(&intel_crtc->base);
3888
3889         wake_up_all(&dev_priv->pending_flip_queue);
3890         queue_work(dev_priv->wq, &work->work);
3891
3892         trace_i915_flip_complete(intel_crtc->plane,
3893                                  work->pending_flip_obj);
3894 }
3895
3896 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3897 {
3898         struct drm_device *dev = crtc->dev;
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         long ret;
3901
3902         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3903
3904         ret = wait_event_interruptible_timeout(
3905                                         dev_priv->pending_flip_queue,
3906                                         !intel_crtc_has_pending_flip(crtc),
3907                                         60*HZ);
3908
3909         if (ret < 0)
3910                 return ret;
3911
3912         if (ret == 0) {
3913                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3914
3915                 spin_lock_irq(&dev->event_lock);
3916                 if (intel_crtc->unpin_work) {
3917                         WARN_ONCE(1, "Removing stuck page flip\n");
3918                         page_flip_completed(intel_crtc);
3919                 }
3920                 spin_unlock_irq(&dev->event_lock);
3921         }
3922
3923         return 0;
3924 }
3925
3926 /* Program iCLKIP clock to the desired frequency */
3927 static void lpt_program_iclkip(struct drm_crtc *crtc)
3928 {
3929         struct drm_device *dev = crtc->dev;
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3932         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3933         u32 temp;
3934
3935         mutex_lock(&dev_priv->sb_lock);
3936
3937         /* It is necessary to ungate the pixclk gate prior to programming
3938          * the divisors, and gate it back when it is done.
3939          */
3940         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3941
3942         /* Disable SSCCTL */
3943         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3944                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3945                                 SBI_SSCCTL_DISABLE,
3946                         SBI_ICLK);
3947
3948         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3949         if (clock == 20000) {
3950                 auxdiv = 1;
3951                 divsel = 0x41;
3952                 phaseinc = 0x20;
3953         } else {
3954                 /* The iCLK virtual clock root frequency is in MHz,
3955                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3956                  * divisors, it is necessary to divide one by another, so we
3957                  * convert the virtual clock precision to KHz here for higher
3958                  * precision.
3959                  */
3960                 u32 iclk_virtual_root_freq = 172800 * 1000;
3961                 u32 iclk_pi_range = 64;
3962                 u32 desired_divisor, msb_divisor_value, pi_value;
3963
3964                 desired_divisor = (iclk_virtual_root_freq / clock);
3965                 msb_divisor_value = desired_divisor / iclk_pi_range;
3966                 pi_value = desired_divisor % iclk_pi_range;
3967
3968                 auxdiv = 0;
3969                 divsel = msb_divisor_value - 2;
3970                 phaseinc = pi_value;
3971         }
3972
3973         /* This should not happen with any sane values */
3974         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3975                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3976         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3977                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3978
3979         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3980                         clock,
3981                         auxdiv,
3982                         divsel,
3983                         phasedir,
3984                         phaseinc);
3985
3986         /* Program SSCDIVINTPHASE6 */
3987         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3988         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3989         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3990         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3991         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3992         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3993         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3994         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3995
3996         /* Program SSCAUXDIV */
3997         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3998         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3999         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4000         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4001
4002         /* Enable modulator and associated divider */
4003         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4004         temp &= ~SBI_SSCCTL_DISABLE;
4005         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4006
4007         /* Wait for initialization time */
4008         udelay(24);
4009
4010         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4011
4012         mutex_unlock(&dev_priv->sb_lock);
4013 }
4014
4015 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4016                                                 enum pipe pch_transcoder)
4017 {
4018         struct drm_device *dev = crtc->base.dev;
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4021
4022         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4023                    I915_READ(HTOTAL(cpu_transcoder)));
4024         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4025                    I915_READ(HBLANK(cpu_transcoder)));
4026         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4027                    I915_READ(HSYNC(cpu_transcoder)));
4028
4029         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4030                    I915_READ(VTOTAL(cpu_transcoder)));
4031         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4032                    I915_READ(VBLANK(cpu_transcoder)));
4033         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4034                    I915_READ(VSYNC(cpu_transcoder)));
4035         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4036                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4037 }
4038
4039 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4040 {
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         uint32_t temp;
4043
4044         temp = I915_READ(SOUTH_CHICKEN1);
4045         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4046                 return;
4047
4048         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4049         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4050
4051         temp &= ~FDI_BC_BIFURCATION_SELECT;
4052         if (enable)
4053                 temp |= FDI_BC_BIFURCATION_SELECT;
4054
4055         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4056         I915_WRITE(SOUTH_CHICKEN1, temp);
4057         POSTING_READ(SOUTH_CHICKEN1);
4058 }
4059
4060 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4061 {
4062         struct drm_device *dev = intel_crtc->base.dev;
4063
4064         switch (intel_crtc->pipe) {
4065         case PIPE_A:
4066                 break;
4067         case PIPE_B:
4068                 if (intel_crtc->config->fdi_lanes > 2)
4069                         cpt_set_fdi_bc_bifurcation(dev, false);
4070                 else
4071                         cpt_set_fdi_bc_bifurcation(dev, true);
4072
4073                 break;
4074         case PIPE_C:
4075                 cpt_set_fdi_bc_bifurcation(dev, true);
4076
4077                 break;
4078         default:
4079                 BUG();
4080         }
4081 }
4082
4083 /* Return which DP Port should be selected for Transcoder DP control */
4084 static enum port
4085 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4086 {
4087         struct drm_device *dev = crtc->dev;
4088         struct intel_encoder *encoder;
4089
4090         for_each_encoder_on_crtc(dev, crtc, encoder) {
4091                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4092                     encoder->type == INTEL_OUTPUT_EDP)
4093                         return enc_to_dig_port(&encoder->base)->port;
4094         }
4095
4096         return -1;
4097 }
4098
4099 /*
4100  * Enable PCH resources required for PCH ports:
4101  *   - PCH PLLs
4102  *   - FDI training & RX/TX
4103  *   - update transcoder timings
4104  *   - DP transcoding bits
4105  *   - transcoder
4106  */
4107 static void ironlake_pch_enable(struct drm_crtc *crtc)
4108 {
4109         struct drm_device *dev = crtc->dev;
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4112         int pipe = intel_crtc->pipe;
4113         u32 temp;
4114
4115         assert_pch_transcoder_disabled(dev_priv, pipe);
4116
4117         if (IS_IVYBRIDGE(dev))
4118                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4119
4120         /* Write the TU size bits before fdi link training, so that error
4121          * detection works. */
4122         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4123                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4124
4125         /* For PCH output, training FDI link */
4126         dev_priv->display.fdi_link_train(crtc);
4127
4128         /* We need to program the right clock selection before writing the pixel
4129          * mutliplier into the DPLL. */
4130         if (HAS_PCH_CPT(dev)) {
4131                 u32 sel;
4132
4133                 temp = I915_READ(PCH_DPLL_SEL);
4134                 temp |= TRANS_DPLL_ENABLE(pipe);
4135                 sel = TRANS_DPLLB_SEL(pipe);
4136                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4137                         temp |= sel;
4138                 else
4139                         temp &= ~sel;
4140                 I915_WRITE(PCH_DPLL_SEL, temp);
4141         }
4142
4143         /* XXX: pch pll's can be enabled any time before we enable the PCH
4144          * transcoder, and we actually should do this to not upset any PCH
4145          * transcoder that already use the clock when we share it.
4146          *
4147          * Note that enable_shared_dpll tries to do the right thing, but
4148          * get_shared_dpll unconditionally resets the pll - we need that to have
4149          * the right LVDS enable sequence. */
4150         intel_enable_shared_dpll(intel_crtc);
4151
4152         /* set transcoder timing, panel must allow it */
4153         assert_panel_unlocked(dev_priv, pipe);
4154         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4155
4156         intel_fdi_normal_train(crtc);
4157
4158         /* For PCH DP, enable TRANS_DP_CTL */
4159         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4160                 const struct drm_display_mode *adjusted_mode =
4161                         &intel_crtc->config->base.adjusted_mode;
4162                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4163                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4164                 temp = I915_READ(reg);
4165                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4166                           TRANS_DP_SYNC_MASK |
4167                           TRANS_DP_BPC_MASK);
4168                 temp |= TRANS_DP_OUTPUT_ENABLE;
4169                 temp |= bpc << 9; /* same format but at 11:9 */
4170
4171                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4172                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4173                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4174                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4175
4176                 switch (intel_trans_dp_port_sel(crtc)) {
4177                 case PORT_B:
4178                         temp |= TRANS_DP_PORT_SEL_B;
4179                         break;
4180                 case PORT_C:
4181                         temp |= TRANS_DP_PORT_SEL_C;
4182                         break;
4183                 case PORT_D:
4184                         temp |= TRANS_DP_PORT_SEL_D;
4185                         break;
4186                 default:
4187                         BUG();
4188                 }
4189
4190                 I915_WRITE(reg, temp);
4191         }
4192
4193         ironlake_enable_pch_transcoder(dev_priv, pipe);
4194 }
4195
4196 static void lpt_pch_enable(struct drm_crtc *crtc)
4197 {
4198         struct drm_device *dev = crtc->dev;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4202
4203         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4204
4205         lpt_program_iclkip(crtc);
4206
4207         /* Set transcoder timing. */
4208         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4209
4210         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4211 }
4212
4213 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4214                                                 struct intel_crtc_state *crtc_state)
4215 {
4216         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4217         struct intel_shared_dpll *pll;
4218         struct intel_shared_dpll_config *shared_dpll;
4219         enum intel_dpll_id i;
4220
4221         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4222
4223         if (HAS_PCH_IBX(dev_priv->dev)) {
4224                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4225                 i = (enum intel_dpll_id) crtc->pipe;
4226                 pll = &dev_priv->shared_dplls[i];
4227
4228                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4229                               crtc->base.base.id, pll->name);
4230
4231                 WARN_ON(shared_dpll[i].crtc_mask);
4232
4233                 goto found;
4234         }
4235
4236         if (IS_BROXTON(dev_priv->dev)) {
4237                 /* PLL is attached to port in bxt */
4238                 struct intel_encoder *encoder;
4239                 struct intel_digital_port *intel_dig_port;
4240
4241                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4242                 if (WARN_ON(!encoder))
4243                         return NULL;
4244
4245                 intel_dig_port = enc_to_dig_port(&encoder->base);
4246                 /* 1:1 mapping between ports and PLLs */
4247                 i = (enum intel_dpll_id)intel_dig_port->port;
4248                 pll = &dev_priv->shared_dplls[i];
4249                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4250                         crtc->base.base.id, pll->name);
4251                 WARN_ON(shared_dpll[i].crtc_mask);
4252
4253                 goto found;
4254         }
4255
4256         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4257                 pll = &dev_priv->shared_dplls[i];
4258
4259                 /* Only want to check enabled timings first */
4260                 if (shared_dpll[i].crtc_mask == 0)
4261                         continue;
4262
4263                 if (memcmp(&crtc_state->dpll_hw_state,
4264                            &shared_dpll[i].hw_state,
4265                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4266                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4267                                       crtc->base.base.id, pll->name,
4268                                       shared_dpll[i].crtc_mask,
4269                                       pll->active);
4270                         goto found;
4271                 }
4272         }
4273
4274         /* Ok no matching timings, maybe there's a free one? */
4275         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4276                 pll = &dev_priv->shared_dplls[i];
4277                 if (shared_dpll[i].crtc_mask == 0) {
4278                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4279                                       crtc->base.base.id, pll->name);
4280                         goto found;
4281                 }
4282         }
4283
4284         return NULL;
4285
4286 found:
4287         if (shared_dpll[i].crtc_mask == 0)
4288                 shared_dpll[i].hw_state =
4289                         crtc_state->dpll_hw_state;
4290
4291         crtc_state->shared_dpll = i;
4292         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4293                          pipe_name(crtc->pipe));
4294
4295         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4296
4297         return pll;
4298 }
4299
4300 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4301 {
4302         struct drm_i915_private *dev_priv = to_i915(state->dev);
4303         struct intel_shared_dpll_config *shared_dpll;
4304         struct intel_shared_dpll *pll;
4305         enum intel_dpll_id i;
4306
4307         if (!to_intel_atomic_state(state)->dpll_set)
4308                 return;
4309
4310         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4311         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4312                 pll = &dev_priv->shared_dplls[i];
4313                 pll->config = shared_dpll[i];
4314         }
4315 }
4316
4317 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4318 {
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         i915_reg_t dslreg = PIPEDSL(pipe);
4321         u32 temp;
4322
4323         temp = I915_READ(dslreg);
4324         udelay(500);
4325         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4326                 if (wait_for(I915_READ(dslreg) != temp, 5))
4327                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4328         }
4329 }
4330
4331 static int
4332 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4333                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4334                   int src_w, int src_h, int dst_w, int dst_h)
4335 {
4336         struct intel_crtc_scaler_state *scaler_state =
4337                 &crtc_state->scaler_state;
4338         struct intel_crtc *intel_crtc =
4339                 to_intel_crtc(crtc_state->base.crtc);
4340         int need_scaling;
4341
4342         need_scaling = intel_rotation_90_or_270(rotation) ?
4343                 (src_h != dst_w || src_w != dst_h):
4344                 (src_w != dst_w || src_h != dst_h);
4345
4346         /*
4347          * if plane is being disabled or scaler is no more required or force detach
4348          *  - free scaler binded to this plane/crtc
4349          *  - in order to do this, update crtc->scaler_usage
4350          *
4351          * Here scaler state in crtc_state is set free so that
4352          * scaler can be assigned to other user. Actual register
4353          * update to free the scaler is done in plane/panel-fit programming.
4354          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4355          */
4356         if (force_detach || !need_scaling) {
4357                 if (*scaler_id >= 0) {
4358                         scaler_state->scaler_users &= ~(1 << scaler_user);
4359                         scaler_state->scalers[*scaler_id].in_use = 0;
4360
4361                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4362                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4363                                 intel_crtc->pipe, scaler_user, *scaler_id,
4364                                 scaler_state->scaler_users);
4365                         *scaler_id = -1;
4366                 }
4367                 return 0;
4368         }
4369
4370         /* range checks */
4371         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4372                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4373
4374                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4375                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4376                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4377                         "size is out of scaler range\n",
4378                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4379                 return -EINVAL;
4380         }
4381
4382         /* mark this plane as a scaler user in crtc_state */
4383         scaler_state->scaler_users |= (1 << scaler_user);
4384         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4385                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4386                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4387                 scaler_state->scaler_users);
4388
4389         return 0;
4390 }
4391
4392 /**
4393  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4394  *
4395  * @state: crtc's scaler state
4396  *
4397  * Return
4398  *     0 - scaler_usage updated successfully
4399  *    error - requested scaling cannot be supported or other error condition
4400  */
4401 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4402 {
4403         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4404         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4405
4406         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4407                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4408
4409         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4410                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4411                 state->pipe_src_w, state->pipe_src_h,
4412                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4413 }
4414
4415 /**
4416  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4417  *
4418  * @state: crtc's scaler state
4419  * @plane_state: atomic plane state to update
4420  *
4421  * Return
4422  *     0 - scaler_usage updated successfully
4423  *    error - requested scaling cannot be supported or other error condition
4424  */
4425 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4426                                    struct intel_plane_state *plane_state)
4427 {
4428
4429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4430         struct intel_plane *intel_plane =
4431                 to_intel_plane(plane_state->base.plane);
4432         struct drm_framebuffer *fb = plane_state->base.fb;
4433         int ret;
4434
4435         bool force_detach = !fb || !plane_state->visible;
4436
4437         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4438                       intel_plane->base.base.id, intel_crtc->pipe,
4439                       drm_plane_index(&intel_plane->base));
4440
4441         ret = skl_update_scaler(crtc_state, force_detach,
4442                                 drm_plane_index(&intel_plane->base),
4443                                 &plane_state->scaler_id,
4444                                 plane_state->base.rotation,
4445                                 drm_rect_width(&plane_state->src) >> 16,
4446                                 drm_rect_height(&plane_state->src) >> 16,
4447                                 drm_rect_width(&plane_state->dst),
4448                                 drm_rect_height(&plane_state->dst));
4449
4450         if (ret || plane_state->scaler_id < 0)
4451                 return ret;
4452
4453         /* check colorkey */
4454         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4455                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4456                               intel_plane->base.base.id);
4457                 return -EINVAL;
4458         }
4459
4460         /* Check src format */
4461         switch (fb->pixel_format) {
4462         case DRM_FORMAT_RGB565:
4463         case DRM_FORMAT_XBGR8888:
4464         case DRM_FORMAT_XRGB8888:
4465         case DRM_FORMAT_ABGR8888:
4466         case DRM_FORMAT_ARGB8888:
4467         case DRM_FORMAT_XRGB2101010:
4468         case DRM_FORMAT_XBGR2101010:
4469         case DRM_FORMAT_YUYV:
4470         case DRM_FORMAT_YVYU:
4471         case DRM_FORMAT_UYVY:
4472         case DRM_FORMAT_VYUY:
4473                 break;
4474         default:
4475                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4476                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4477                 return -EINVAL;
4478         }
4479
4480         return 0;
4481 }
4482
4483 static void skylake_scaler_disable(struct intel_crtc *crtc)
4484 {
4485         int i;
4486
4487         for (i = 0; i < crtc->num_scalers; i++)
4488                 skl_detach_scaler(crtc, i);
4489 }
4490
4491 static void skylake_pfit_enable(struct intel_crtc *crtc)
4492 {
4493         struct drm_device *dev = crtc->base.dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         int pipe = crtc->pipe;
4496         struct intel_crtc_scaler_state *scaler_state =
4497                 &crtc->config->scaler_state;
4498
4499         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4500
4501         if (crtc->config->pch_pfit.enabled) {
4502                 int id;
4503
4504                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4505                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4506                         return;
4507                 }
4508
4509                 id = scaler_state->scaler_id;
4510                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4511                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4512                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4513                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4514
4515                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4516         }
4517 }
4518
4519 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4520 {
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int pipe = crtc->pipe;
4524
4525         if (crtc->config->pch_pfit.enabled) {
4526                 /* Force use of hard-coded filter coefficients
4527                  * as some pre-programmed values are broken,
4528                  * e.g. x201.
4529                  */
4530                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4531                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4532                                                  PF_PIPE_SEL_IVB(pipe));
4533                 else
4534                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4535                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4536                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4537         }
4538 }
4539
4540 void hsw_enable_ips(struct intel_crtc *crtc)
4541 {
4542         struct drm_device *dev = crtc->base.dev;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544
4545         if (!crtc->config->ips_enabled)
4546                 return;
4547
4548         /* We can only enable IPS after we enable a plane and wait for a vblank */
4549         intel_wait_for_vblank(dev, crtc->pipe);
4550
4551         assert_plane_enabled(dev_priv, crtc->plane);
4552         if (IS_BROADWELL(dev)) {
4553                 mutex_lock(&dev_priv->rps.hw_lock);
4554                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4555                 mutex_unlock(&dev_priv->rps.hw_lock);
4556                 /* Quoting Art Runyan: "its not safe to expect any particular
4557                  * value in IPS_CTL bit 31 after enabling IPS through the
4558                  * mailbox." Moreover, the mailbox may return a bogus state,
4559                  * so we need to just enable it and continue on.
4560                  */
4561         } else {
4562                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4563                 /* The bit only becomes 1 in the next vblank, so this wait here
4564                  * is essentially intel_wait_for_vblank. If we don't have this
4565                  * and don't wait for vblanks until the end of crtc_enable, then
4566                  * the HW state readout code will complain that the expected
4567                  * IPS_CTL value is not the one we read. */
4568                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4569                         DRM_ERROR("Timed out waiting for IPS enable\n");
4570         }
4571 }
4572
4573 void hsw_disable_ips(struct intel_crtc *crtc)
4574 {
4575         struct drm_device *dev = crtc->base.dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577
4578         if (!crtc->config->ips_enabled)
4579                 return;
4580
4581         assert_plane_enabled(dev_priv, crtc->plane);
4582         if (IS_BROADWELL(dev)) {
4583                 mutex_lock(&dev_priv->rps.hw_lock);
4584                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4585                 mutex_unlock(&dev_priv->rps.hw_lock);
4586                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4587                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4588                         DRM_ERROR("Timed out waiting for IPS disable\n");
4589         } else {
4590                 I915_WRITE(IPS_CTL, 0);
4591                 POSTING_READ(IPS_CTL);
4592         }
4593
4594         /* We need to wait for a vblank before we can disable the plane. */
4595         intel_wait_for_vblank(dev, crtc->pipe);
4596 }
4597
4598 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4599 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4600 {
4601         struct drm_device *dev = crtc->dev;
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604         enum pipe pipe = intel_crtc->pipe;
4605         int i;
4606         bool reenable_ips = false;
4607
4608         /* The clocks have to be on to load the palette. */
4609         if (!crtc->state->active)
4610                 return;
4611
4612         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4613                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4614                         assert_dsi_pll_enabled(dev_priv);
4615                 else
4616                         assert_pll_enabled(dev_priv, pipe);
4617         }
4618
4619         /* Workaround : Do not read or write the pipe palette/gamma data while
4620          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4621          */
4622         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4623             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4624              GAMMA_MODE_MODE_SPLIT)) {
4625                 hsw_disable_ips(intel_crtc);
4626                 reenable_ips = true;
4627         }
4628
4629         for (i = 0; i < 256; i++) {
4630                 i915_reg_t palreg;
4631
4632                 if (HAS_GMCH_DISPLAY(dev))
4633                         palreg = PALETTE(pipe, i);
4634                 else
4635                         palreg = LGC_PALETTE(pipe, i);
4636
4637                 I915_WRITE(palreg,
4638                            (intel_crtc->lut_r[i] << 16) |
4639                            (intel_crtc->lut_g[i] << 8) |
4640                            intel_crtc->lut_b[i]);
4641         }
4642
4643         if (reenable_ips)
4644                 hsw_enable_ips(intel_crtc);
4645 }
4646
4647 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4648 {
4649         if (intel_crtc->overlay) {
4650                 struct drm_device *dev = intel_crtc->base.dev;
4651                 struct drm_i915_private *dev_priv = dev->dev_private;
4652
4653                 mutex_lock(&dev->struct_mutex);
4654                 dev_priv->mm.interruptible = false;
4655                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4656                 dev_priv->mm.interruptible = true;
4657                 mutex_unlock(&dev->struct_mutex);
4658         }
4659
4660         /* Let userspace switch the overlay on again. In most cases userspace
4661          * has to recompute where to put it anyway.
4662          */
4663 }
4664
4665 /**
4666  * intel_post_enable_primary - Perform operations after enabling primary plane
4667  * @crtc: the CRTC whose primary plane was just enabled
4668  *
4669  * Performs potentially sleeping operations that must be done after the primary
4670  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4671  * called due to an explicit primary plane update, or due to an implicit
4672  * re-enable that is caused when a sprite plane is updated to no longer
4673  * completely hide the primary plane.
4674  */
4675 static void
4676 intel_post_enable_primary(struct drm_crtc *crtc)
4677 {
4678         struct drm_device *dev = crtc->dev;
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681         int pipe = intel_crtc->pipe;
4682
4683         /*
4684          * BDW signals flip done immediately if the plane
4685          * is disabled, even if the plane enable is already
4686          * armed to occur at the next vblank :(
4687          */
4688         if (IS_BROADWELL(dev))
4689                 intel_wait_for_vblank(dev, pipe);
4690
4691         /*
4692          * FIXME IPS should be fine as long as one plane is
4693          * enabled, but in practice it seems to have problems
4694          * when going from primary only to sprite only and vice
4695          * versa.
4696          */
4697         hsw_enable_ips(intel_crtc);
4698
4699         /*
4700          * Gen2 reports pipe underruns whenever all planes are disabled.
4701          * So don't enable underrun reporting before at least some planes
4702          * are enabled.
4703          * FIXME: Need to fix the logic to work when we turn off all planes
4704          * but leave the pipe running.
4705          */
4706         if (IS_GEN2(dev))
4707                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4708
4709         /* Underruns don't always raise interrupts, so check manually. */
4710         intel_check_cpu_fifo_underruns(dev_priv);
4711         intel_check_pch_fifo_underruns(dev_priv);
4712 }
4713
4714 /**
4715  * intel_pre_disable_primary - Perform operations before disabling primary plane
4716  * @crtc: the CRTC whose primary plane is to be disabled
4717  *
4718  * Performs potentially sleeping operations that must be done before the
4719  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4720  * be called due to an explicit primary plane update, or due to an implicit
4721  * disable that is caused when a sprite plane completely hides the primary
4722  * plane.
4723  */
4724 static void
4725 intel_pre_disable_primary(struct drm_crtc *crtc)
4726 {
4727         struct drm_device *dev = crtc->dev;
4728         struct drm_i915_private *dev_priv = dev->dev_private;
4729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730         int pipe = intel_crtc->pipe;
4731
4732         /*
4733          * Gen2 reports pipe underruns whenever all planes are disabled.
4734          * So diasble underrun reporting before all the planes get disabled.
4735          * FIXME: Need to fix the logic to work when we turn off all planes
4736          * but leave the pipe running.
4737          */
4738         if (IS_GEN2(dev))
4739                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4740
4741         /*
4742          * Vblank time updates from the shadow to live plane control register
4743          * are blocked if the memory self-refresh mode is active at that
4744          * moment. So to make sure the plane gets truly disabled, disable
4745          * first the self-refresh mode. The self-refresh enable bit in turn
4746          * will be checked/applied by the HW only at the next frame start
4747          * event which is after the vblank start event, so we need to have a
4748          * wait-for-vblank between disabling the plane and the pipe.
4749          */
4750         if (HAS_GMCH_DISPLAY(dev)) {
4751                 intel_set_memory_cxsr(dev_priv, false);
4752                 dev_priv->wm.vlv.cxsr = false;
4753                 intel_wait_for_vblank(dev, pipe);
4754         }
4755
4756         /*
4757          * FIXME IPS should be fine as long as one plane is
4758          * enabled, but in practice it seems to have problems
4759          * when going from primary only to sprite only and vice
4760          * versa.
4761          */
4762         hsw_disable_ips(intel_crtc);
4763 }
4764
4765 static void intel_post_plane_update(struct intel_crtc *crtc)
4766 {
4767         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4768         struct drm_device *dev = crtc->base.dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770
4771         if (atomic->wait_vblank)
4772                 intel_wait_for_vblank(dev, crtc->pipe);
4773
4774         intel_frontbuffer_flip(dev, atomic->fb_bits);
4775
4776         if (atomic->disable_cxsr)
4777                 crtc->wm.cxsr_allowed = true;
4778
4779         if (crtc->atomic.update_wm_post)
4780                 intel_update_watermarks(&crtc->base);
4781
4782         if (atomic->update_fbc)
4783                 intel_fbc_update(dev_priv);
4784
4785         if (atomic->post_enable_primary)
4786                 intel_post_enable_primary(&crtc->base);
4787
4788         memset(atomic, 0, sizeof(*atomic));
4789 }
4790
4791 static void intel_pre_plane_update(struct intel_crtc *crtc)
4792 {
4793         struct drm_device *dev = crtc->base.dev;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4796
4797         if (atomic->disable_fbc)
4798                 intel_fbc_disable_crtc(crtc);
4799
4800         if (crtc->atomic.disable_ips)
4801                 hsw_disable_ips(crtc);
4802
4803         if (atomic->pre_disable_primary)
4804                 intel_pre_disable_primary(&crtc->base);
4805
4806         if (atomic->disable_cxsr) {
4807                 crtc->wm.cxsr_allowed = false;
4808                 intel_set_memory_cxsr(dev_priv, false);
4809         }
4810 }
4811
4812 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4813 {
4814         struct drm_device *dev = crtc->dev;
4815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4816         struct drm_plane *p;
4817         int pipe = intel_crtc->pipe;
4818
4819         intel_crtc_dpms_overlay_disable(intel_crtc);
4820
4821         drm_for_each_plane_mask(p, dev, plane_mask)
4822                 to_intel_plane(p)->disable_plane(p, crtc);
4823
4824         /*
4825          * FIXME: Once we grow proper nuclear flip support out of this we need
4826          * to compute the mask of flip planes precisely. For the time being
4827          * consider this a flip to a NULL plane.
4828          */
4829         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4830 }
4831
4832 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4833 {
4834         struct drm_device *dev = crtc->dev;
4835         struct drm_i915_private *dev_priv = dev->dev_private;
4836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4837         struct intel_encoder *encoder;
4838         int pipe = intel_crtc->pipe;
4839
4840         if (WARN_ON(intel_crtc->active))
4841                 return;
4842
4843         if (intel_crtc->config->has_pch_encoder)
4844                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4845
4846         if (intel_crtc->config->has_pch_encoder)
4847                 intel_prepare_shared_dpll(intel_crtc);
4848
4849         if (intel_crtc->config->has_dp_encoder)
4850                 intel_dp_set_m_n(intel_crtc, M1_N1);
4851
4852         intel_set_pipe_timings(intel_crtc);
4853
4854         if (intel_crtc->config->has_pch_encoder) {
4855                 intel_cpu_transcoder_set_m_n(intel_crtc,
4856                                      &intel_crtc->config->fdi_m_n, NULL);
4857         }
4858
4859         ironlake_set_pipeconf(crtc);
4860
4861         intel_crtc->active = true;
4862
4863         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4864
4865         for_each_encoder_on_crtc(dev, crtc, encoder)
4866                 if (encoder->pre_enable)
4867                         encoder->pre_enable(encoder);
4868
4869         if (intel_crtc->config->has_pch_encoder) {
4870                 /* Note: FDI PLL enabling _must_ be done before we enable the
4871                  * cpu pipes, hence this is separate from all the other fdi/pch
4872                  * enabling. */
4873                 ironlake_fdi_pll_enable(intel_crtc);
4874         } else {
4875                 assert_fdi_tx_disabled(dev_priv, pipe);
4876                 assert_fdi_rx_disabled(dev_priv, pipe);
4877         }
4878
4879         ironlake_pfit_enable(intel_crtc);
4880
4881         /*
4882          * On ILK+ LUT must be loaded before the pipe is running but with
4883          * clocks enabled
4884          */
4885         intel_crtc_load_lut(crtc);
4886
4887         intel_update_watermarks(crtc);
4888         intel_enable_pipe(intel_crtc);
4889
4890         if (intel_crtc->config->has_pch_encoder)
4891                 ironlake_pch_enable(crtc);
4892
4893         assert_vblank_disabled(crtc);
4894         drm_crtc_vblank_on(crtc);
4895
4896         for_each_encoder_on_crtc(dev, crtc, encoder)
4897                 encoder->enable(encoder);
4898
4899         if (HAS_PCH_CPT(dev))
4900                 cpt_verify_modeset(dev, intel_crtc->pipe);
4901
4902         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4903         if (intel_crtc->config->has_pch_encoder)
4904                 intel_wait_for_vblank(dev, pipe);
4905         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4906 }
4907
4908 /* IPS only exists on ULT machines and is tied to pipe A. */
4909 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4910 {
4911         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4912 }
4913
4914 static void haswell_crtc_enable(struct drm_crtc *crtc)
4915 {
4916         struct drm_device *dev = crtc->dev;
4917         struct drm_i915_private *dev_priv = dev->dev_private;
4918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4919         struct intel_encoder *encoder;
4920         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4921         struct intel_crtc_state *pipe_config =
4922                 to_intel_crtc_state(crtc->state);
4923         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4924
4925         if (WARN_ON(intel_crtc->active))
4926                 return;
4927
4928         if (intel_crtc->config->has_pch_encoder)
4929                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4930                                                       false);
4931
4932         if (intel_crtc_to_shared_dpll(intel_crtc))
4933                 intel_enable_shared_dpll(intel_crtc);
4934
4935         if (intel_crtc->config->has_dp_encoder)
4936                 intel_dp_set_m_n(intel_crtc, M1_N1);
4937
4938         intel_set_pipe_timings(intel_crtc);
4939
4940         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4941                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4942                            intel_crtc->config->pixel_multiplier - 1);
4943         }
4944
4945         if (intel_crtc->config->has_pch_encoder) {
4946                 intel_cpu_transcoder_set_m_n(intel_crtc,
4947                                      &intel_crtc->config->fdi_m_n, NULL);
4948         }
4949
4950         haswell_set_pipeconf(crtc);
4951
4952         intel_set_pipe_csc(crtc);
4953
4954         intel_crtc->active = true;
4955
4956         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957         for_each_encoder_on_crtc(dev, crtc, encoder) {
4958                 if (encoder->pre_pll_enable)
4959                         encoder->pre_pll_enable(encoder);
4960                 if (encoder->pre_enable)
4961                         encoder->pre_enable(encoder);
4962         }
4963
4964         if (intel_crtc->config->has_pch_encoder)
4965                 dev_priv->display.fdi_link_train(crtc);
4966
4967         if (!is_dsi)
4968                 intel_ddi_enable_pipe_clock(intel_crtc);
4969
4970         if (INTEL_INFO(dev)->gen >= 9)
4971                 skylake_pfit_enable(intel_crtc);
4972         else
4973                 ironlake_pfit_enable(intel_crtc);
4974
4975         /*
4976          * On ILK+ LUT must be loaded before the pipe is running but with
4977          * clocks enabled
4978          */
4979         intel_crtc_load_lut(crtc);
4980
4981         intel_ddi_set_pipe_settings(crtc);
4982         if (!is_dsi)
4983                 intel_ddi_enable_transcoder_func(crtc);
4984
4985         intel_update_watermarks(crtc);
4986         intel_enable_pipe(intel_crtc);
4987
4988         if (intel_crtc->config->has_pch_encoder)
4989                 lpt_pch_enable(crtc);
4990
4991         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
4992                 intel_ddi_set_vc_payload_alloc(crtc, true);
4993
4994         assert_vblank_disabled(crtc);
4995         drm_crtc_vblank_on(crtc);
4996
4997         for_each_encoder_on_crtc(dev, crtc, encoder) {
4998                 encoder->enable(encoder);
4999                 intel_opregion_notify_encoder(encoder, true);
5000         }
5001
5002         if (intel_crtc->config->has_pch_encoder)
5003                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5004                                                       true);
5005
5006         /* If we change the relative order between pipe/planes enabling, we need
5007          * to change the workaround. */
5008         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5009         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5010                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5011                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5012         }
5013 }
5014
5015 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5016 {
5017         struct drm_device *dev = crtc->base.dev;
5018         struct drm_i915_private *dev_priv = dev->dev_private;
5019         int pipe = crtc->pipe;
5020
5021         /* To avoid upsetting the power well on haswell only disable the pfit if
5022          * it's in use. The hw state code will make sure we get this right. */
5023         if (force || crtc->config->pch_pfit.enabled) {
5024                 I915_WRITE(PF_CTL(pipe), 0);
5025                 I915_WRITE(PF_WIN_POS(pipe), 0);
5026                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5027         }
5028 }
5029
5030 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5031 {
5032         struct drm_device *dev = crtc->dev;
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5035         struct intel_encoder *encoder;
5036         int pipe = intel_crtc->pipe;
5037
5038         if (intel_crtc->config->has_pch_encoder)
5039                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5040
5041         for_each_encoder_on_crtc(dev, crtc, encoder)
5042                 encoder->disable(encoder);
5043
5044         drm_crtc_vblank_off(crtc);
5045         assert_vblank_disabled(crtc);
5046
5047         intel_disable_pipe(intel_crtc);
5048
5049         ironlake_pfit_disable(intel_crtc, false);
5050
5051         if (intel_crtc->config->has_pch_encoder)
5052                 ironlake_fdi_disable(crtc);
5053
5054         for_each_encoder_on_crtc(dev, crtc, encoder)
5055                 if (encoder->post_disable)
5056                         encoder->post_disable(encoder);
5057
5058         if (intel_crtc->config->has_pch_encoder) {
5059                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5060
5061                 if (HAS_PCH_CPT(dev)) {
5062                         i915_reg_t reg;
5063                         u32 temp;
5064
5065                         /* disable TRANS_DP_CTL */
5066                         reg = TRANS_DP_CTL(pipe);
5067                         temp = I915_READ(reg);
5068                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5069                                   TRANS_DP_PORT_SEL_MASK);
5070                         temp |= TRANS_DP_PORT_SEL_NONE;
5071                         I915_WRITE(reg, temp);
5072
5073                         /* disable DPLL_SEL */
5074                         temp = I915_READ(PCH_DPLL_SEL);
5075                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5076                         I915_WRITE(PCH_DPLL_SEL, temp);
5077                 }
5078
5079                 ironlake_fdi_pll_disable(intel_crtc);
5080         }
5081
5082         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5083 }
5084
5085 static void haswell_crtc_disable(struct drm_crtc *crtc)
5086 {
5087         struct drm_device *dev = crtc->dev;
5088         struct drm_i915_private *dev_priv = dev->dev_private;
5089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5090         struct intel_encoder *encoder;
5091         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5092         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5093
5094         if (intel_crtc->config->has_pch_encoder)
5095                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5096                                                       false);
5097
5098         for_each_encoder_on_crtc(dev, crtc, encoder) {
5099                 intel_opregion_notify_encoder(encoder, false);
5100                 encoder->disable(encoder);
5101         }
5102
5103         drm_crtc_vblank_off(crtc);
5104         assert_vblank_disabled(crtc);
5105
5106         intel_disable_pipe(intel_crtc);
5107
5108         if (intel_crtc->config->dp_encoder_is_mst)
5109                 intel_ddi_set_vc_payload_alloc(crtc, false);
5110
5111         if (!is_dsi)
5112                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5113
5114         if (INTEL_INFO(dev)->gen >= 9)
5115                 skylake_scaler_disable(intel_crtc);
5116         else
5117                 ironlake_pfit_disable(intel_crtc, false);
5118
5119         if (!is_dsi)
5120                 intel_ddi_disable_pipe_clock(intel_crtc);
5121
5122         if (intel_crtc->config->has_pch_encoder) {
5123                 lpt_disable_pch_transcoder(dev_priv);
5124                 intel_ddi_fdi_disable(crtc);
5125         }
5126
5127         for_each_encoder_on_crtc(dev, crtc, encoder)
5128                 if (encoder->post_disable)
5129                         encoder->post_disable(encoder);
5130
5131         if (intel_crtc->config->has_pch_encoder)
5132                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5133                                                       true);
5134 }
5135
5136 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->base.dev;
5139         struct drm_i915_private *dev_priv = dev->dev_private;
5140         struct intel_crtc_state *pipe_config = crtc->config;
5141
5142         if (!pipe_config->gmch_pfit.control)
5143                 return;
5144
5145         /*
5146          * The panel fitter should only be adjusted whilst the pipe is disabled,
5147          * according to register description and PRM.
5148          */
5149         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5150         assert_pipe_disabled(dev_priv, crtc->pipe);
5151
5152         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5153         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5154
5155         /* Border color in case we don't scale up to the full screen. Black by
5156          * default, change to something else for debugging. */
5157         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5158 }
5159
5160 static enum intel_display_power_domain port_to_power_domain(enum port port)
5161 {
5162         switch (port) {
5163         case PORT_A:
5164                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5165         case PORT_B:
5166                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5167         case PORT_C:
5168                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5169         case PORT_D:
5170                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5171         case PORT_E:
5172                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5173         default:
5174                 MISSING_CASE(port);
5175                 return POWER_DOMAIN_PORT_OTHER;
5176         }
5177 }
5178
5179 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5180 {
5181         switch (port) {
5182         case PORT_A:
5183                 return POWER_DOMAIN_AUX_A;
5184         case PORT_B:
5185                 return POWER_DOMAIN_AUX_B;
5186         case PORT_C:
5187                 return POWER_DOMAIN_AUX_C;
5188         case PORT_D:
5189                 return POWER_DOMAIN_AUX_D;
5190         case PORT_E:
5191                 /* FIXME: Check VBT for actual wiring of PORT E */
5192                 return POWER_DOMAIN_AUX_D;
5193         default:
5194                 MISSING_CASE(port);
5195                 return POWER_DOMAIN_AUX_A;
5196         }
5197 }
5198
5199 #define for_each_power_domain(domain, mask)                             \
5200         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5201                 if ((1 << (domain)) & (mask))
5202
5203 enum intel_display_power_domain
5204 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5205 {
5206         struct drm_device *dev = intel_encoder->base.dev;
5207         struct intel_digital_port *intel_dig_port;
5208
5209         switch (intel_encoder->type) {
5210         case INTEL_OUTPUT_UNKNOWN:
5211                 /* Only DDI platforms should ever use this output type */
5212                 WARN_ON_ONCE(!HAS_DDI(dev));
5213         case INTEL_OUTPUT_DISPLAYPORT:
5214         case INTEL_OUTPUT_HDMI:
5215         case INTEL_OUTPUT_EDP:
5216                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5217                 return port_to_power_domain(intel_dig_port->port);
5218         case INTEL_OUTPUT_DP_MST:
5219                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5220                 return port_to_power_domain(intel_dig_port->port);
5221         case INTEL_OUTPUT_ANALOG:
5222                 return POWER_DOMAIN_PORT_CRT;
5223         case INTEL_OUTPUT_DSI:
5224                 return POWER_DOMAIN_PORT_DSI;
5225         default:
5226                 return POWER_DOMAIN_PORT_OTHER;
5227         }
5228 }
5229
5230 enum intel_display_power_domain
5231 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5232 {
5233         struct drm_device *dev = intel_encoder->base.dev;
5234         struct intel_digital_port *intel_dig_port;
5235
5236         switch (intel_encoder->type) {
5237         case INTEL_OUTPUT_UNKNOWN:
5238         case INTEL_OUTPUT_HDMI:
5239                 /*
5240                  * Only DDI platforms should ever use these output types.
5241                  * We can get here after the HDMI detect code has already set
5242                  * the type of the shared encoder. Since we can't be sure
5243                  * what's the status of the given connectors, play safe and
5244                  * run the DP detection too.
5245                  */
5246                 WARN_ON_ONCE(!HAS_DDI(dev));
5247         case INTEL_OUTPUT_DISPLAYPORT:
5248         case INTEL_OUTPUT_EDP:
5249                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5250                 return port_to_aux_power_domain(intel_dig_port->port);
5251         case INTEL_OUTPUT_DP_MST:
5252                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5253                 return port_to_aux_power_domain(intel_dig_port->port);
5254         default:
5255                 MISSING_CASE(intel_encoder->type);
5256                 return POWER_DOMAIN_AUX_A;
5257         }
5258 }
5259
5260 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5261 {
5262         struct drm_device *dev = crtc->dev;
5263         struct intel_encoder *intel_encoder;
5264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5265         enum pipe pipe = intel_crtc->pipe;
5266         unsigned long mask;
5267         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5268
5269         if (!crtc->state->active)
5270                 return 0;
5271
5272         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5273         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5274         if (intel_crtc->config->pch_pfit.enabled ||
5275             intel_crtc->config->pch_pfit.force_thru)
5276                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5277
5278         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5279                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5280
5281         return mask;
5282 }
5283
5284 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5285 {
5286         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288         enum intel_display_power_domain domain;
5289         unsigned long domains, new_domains, old_domains;
5290
5291         old_domains = intel_crtc->enabled_power_domains;
5292         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5293
5294         domains = new_domains & ~old_domains;
5295
5296         for_each_power_domain(domain, domains)
5297                 intel_display_power_get(dev_priv, domain);
5298
5299         return old_domains & ~new_domains;
5300 }
5301
5302 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5303                                       unsigned long domains)
5304 {
5305         enum intel_display_power_domain domain;
5306
5307         for_each_power_domain(domain, domains)
5308                 intel_display_power_put(dev_priv, domain);
5309 }
5310
5311 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5312 {
5313         struct drm_device *dev = state->dev;
5314         struct drm_i915_private *dev_priv = dev->dev_private;
5315         unsigned long put_domains[I915_MAX_PIPES] = {};
5316         struct drm_crtc_state *crtc_state;
5317         struct drm_crtc *crtc;
5318         int i;
5319
5320         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5321                 if (needs_modeset(crtc->state))
5322                         put_domains[to_intel_crtc(crtc)->pipe] =
5323                                 modeset_get_crtc_power_domains(crtc);
5324         }
5325
5326         if (dev_priv->display.modeset_commit_cdclk) {
5327                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5328
5329                 if (cdclk != dev_priv->cdclk_freq &&
5330                     !WARN_ON(!state->allow_modeset))
5331                         dev_priv->display.modeset_commit_cdclk(state);
5332         }
5333
5334         for (i = 0; i < I915_MAX_PIPES; i++)
5335                 if (put_domains[i])
5336                         modeset_put_power_domains(dev_priv, put_domains[i]);
5337 }
5338
5339 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5340 {
5341         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5342
5343         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5344             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5345                 return max_cdclk_freq;
5346         else if (IS_CHERRYVIEW(dev_priv))
5347                 return max_cdclk_freq*95/100;
5348         else if (INTEL_INFO(dev_priv)->gen < 4)
5349                 return 2*max_cdclk_freq*90/100;
5350         else
5351                 return max_cdclk_freq*90/100;
5352 }
5353
5354 static void intel_update_max_cdclk(struct drm_device *dev)
5355 {
5356         struct drm_i915_private *dev_priv = dev->dev_private;
5357
5358         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5359                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5360
5361                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5362                         dev_priv->max_cdclk_freq = 675000;
5363                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5364                         dev_priv->max_cdclk_freq = 540000;
5365                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5366                         dev_priv->max_cdclk_freq = 450000;
5367                 else
5368                         dev_priv->max_cdclk_freq = 337500;
5369         } else if (IS_BROADWELL(dev))  {
5370                 /*
5371                  * FIXME with extra cooling we can allow
5372                  * 540 MHz for ULX and 675 Mhz for ULT.
5373                  * How can we know if extra cooling is
5374                  * available? PCI ID, VTB, something else?
5375                  */
5376                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5377                         dev_priv->max_cdclk_freq = 450000;
5378                 else if (IS_BDW_ULX(dev))
5379                         dev_priv->max_cdclk_freq = 450000;
5380                 else if (IS_BDW_ULT(dev))
5381                         dev_priv->max_cdclk_freq = 540000;
5382                 else
5383                         dev_priv->max_cdclk_freq = 675000;
5384         } else if (IS_CHERRYVIEW(dev)) {
5385                 dev_priv->max_cdclk_freq = 320000;
5386         } else if (IS_VALLEYVIEW(dev)) {
5387                 dev_priv->max_cdclk_freq = 400000;
5388         } else {
5389                 /* otherwise assume cdclk is fixed */
5390                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5391         }
5392
5393         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5394
5395         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5396                          dev_priv->max_cdclk_freq);
5397
5398         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5399                          dev_priv->max_dotclk_freq);
5400 }
5401
5402 static void intel_update_cdclk(struct drm_device *dev)
5403 {
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405
5406         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5407         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5408                          dev_priv->cdclk_freq);
5409
5410         /*
5411          * Program the gmbus_freq based on the cdclk frequency.
5412          * BSpec erroneously claims we should aim for 4MHz, but
5413          * in fact 1MHz is the correct frequency.
5414          */
5415         if (IS_VALLEYVIEW(dev)) {
5416                 /*
5417                  * Program the gmbus_freq based on the cdclk frequency.
5418                  * BSpec erroneously claims we should aim for 4MHz, but
5419                  * in fact 1MHz is the correct frequency.
5420                  */
5421                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5422         }
5423
5424         if (dev_priv->max_cdclk_freq == 0)
5425                 intel_update_max_cdclk(dev);
5426 }
5427
5428 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5429 {
5430         struct drm_i915_private *dev_priv = dev->dev_private;
5431         uint32_t divider;
5432         uint32_t ratio;
5433         uint32_t current_freq;
5434         int ret;
5435
5436         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5437         switch (frequency) {
5438         case 144000:
5439                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5440                 ratio = BXT_DE_PLL_RATIO(60);
5441                 break;
5442         case 288000:
5443                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5444                 ratio = BXT_DE_PLL_RATIO(60);
5445                 break;
5446         case 384000:
5447                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5448                 ratio = BXT_DE_PLL_RATIO(60);
5449                 break;
5450         case 576000:
5451                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5452                 ratio = BXT_DE_PLL_RATIO(60);
5453                 break;
5454         case 624000:
5455                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5456                 ratio = BXT_DE_PLL_RATIO(65);
5457                 break;
5458         case 19200:
5459                 /*
5460                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5461                  * to suppress GCC warning.
5462                  */
5463                 ratio = 0;
5464                 divider = 0;
5465                 break;
5466         default:
5467                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5468
5469                 return;
5470         }
5471
5472         mutex_lock(&dev_priv->rps.hw_lock);
5473         /* Inform power controller of upcoming frequency change */
5474         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5475                                       0x80000000);
5476         mutex_unlock(&dev_priv->rps.hw_lock);
5477
5478         if (ret) {
5479                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5480                           ret, frequency);
5481                 return;
5482         }
5483
5484         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5485         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5486         current_freq = current_freq * 500 + 1000;
5487
5488         /*
5489          * DE PLL has to be disabled when
5490          * - setting to 19.2MHz (bypass, PLL isn't used)
5491          * - before setting to 624MHz (PLL needs toggling)
5492          * - before setting to any frequency from 624MHz (PLL needs toggling)
5493          */
5494         if (frequency == 19200 || frequency == 624000 ||
5495             current_freq == 624000) {
5496                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5497                 /* Timeout 200us */
5498                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5499                              1))
5500                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5501         }
5502
5503         if (frequency != 19200) {
5504                 uint32_t val;
5505
5506                 val = I915_READ(BXT_DE_PLL_CTL);
5507                 val &= ~BXT_DE_PLL_RATIO_MASK;
5508                 val |= ratio;
5509                 I915_WRITE(BXT_DE_PLL_CTL, val);
5510
5511                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5512                 /* Timeout 200us */
5513                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5514                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5515
5516                 val = I915_READ(CDCLK_CTL);
5517                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5518                 val |= divider;
5519                 /*
5520                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5521                  * enable otherwise.
5522                  */
5523                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5524                 if (frequency >= 500000)
5525                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5526
5527                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5528                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5529                 val |= (frequency - 1000) / 500;
5530                 I915_WRITE(CDCLK_CTL, val);
5531         }
5532
5533         mutex_lock(&dev_priv->rps.hw_lock);
5534         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5535                                       DIV_ROUND_UP(frequency, 25000));
5536         mutex_unlock(&dev_priv->rps.hw_lock);
5537
5538         if (ret) {
5539                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5540                           ret, frequency);
5541                 return;
5542         }
5543
5544         intel_update_cdclk(dev);
5545 }
5546
5547 void broxton_init_cdclk(struct drm_device *dev)
5548 {
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         uint32_t val;
5551
5552         /*
5553          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5554          * or else the reset will hang because there is no PCH to respond.
5555          * Move the handshake programming to initialization sequence.
5556          * Previously was left up to BIOS.
5557          */
5558         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5559         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5560         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5561
5562         /* Enable PG1 for cdclk */
5563         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5564
5565         /* check if cd clock is enabled */
5566         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5567                 DRM_DEBUG_KMS("Display already initialized\n");
5568                 return;
5569         }
5570
5571         /*
5572          * FIXME:
5573          * - The initial CDCLK needs to be read from VBT.
5574          *   Need to make this change after VBT has changes for BXT.
5575          * - check if setting the max (or any) cdclk freq is really necessary
5576          *   here, it belongs to modeset time
5577          */
5578         broxton_set_cdclk(dev, 624000);
5579
5580         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5581         POSTING_READ(DBUF_CTL);
5582
5583         udelay(10);
5584
5585         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5586                 DRM_ERROR("DBuf power enable timeout!\n");
5587 }
5588
5589 void broxton_uninit_cdclk(struct drm_device *dev)
5590 {
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592
5593         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5594         POSTING_READ(DBUF_CTL);
5595
5596         udelay(10);
5597
5598         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5599                 DRM_ERROR("DBuf power disable timeout!\n");
5600
5601         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5602         broxton_set_cdclk(dev, 19200);
5603
5604         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5605 }
5606
5607 static const struct skl_cdclk_entry {
5608         unsigned int freq;
5609         unsigned int vco;
5610 } skl_cdclk_frequencies[] = {
5611         { .freq = 308570, .vco = 8640 },
5612         { .freq = 337500, .vco = 8100 },
5613         { .freq = 432000, .vco = 8640 },
5614         { .freq = 450000, .vco = 8100 },
5615         { .freq = 540000, .vco = 8100 },
5616         { .freq = 617140, .vco = 8640 },
5617         { .freq = 675000, .vco = 8100 },
5618 };
5619
5620 static unsigned int skl_cdclk_decimal(unsigned int freq)
5621 {
5622         return (freq - 1000) / 500;
5623 }
5624
5625 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5626 {
5627         unsigned int i;
5628
5629         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5630                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5631
5632                 if (e->freq == freq)
5633                         return e->vco;
5634         }
5635
5636         return 8100;
5637 }
5638
5639 static void
5640 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5641 {
5642         unsigned int min_freq;
5643         u32 val;
5644
5645         /* select the minimum CDCLK before enabling DPLL 0 */
5646         val = I915_READ(CDCLK_CTL);
5647         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5648         val |= CDCLK_FREQ_337_308;
5649
5650         if (required_vco == 8640)
5651                 min_freq = 308570;
5652         else
5653                 min_freq = 337500;
5654
5655         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5656
5657         I915_WRITE(CDCLK_CTL, val);
5658         POSTING_READ(CDCLK_CTL);
5659
5660         /*
5661          * We always enable DPLL0 with the lowest link rate possible, but still
5662          * taking into account the VCO required to operate the eDP panel at the
5663          * desired frequency. The usual DP link rates operate with a VCO of
5664          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5665          * The modeset code is responsible for the selection of the exact link
5666          * rate later on, with the constraint of choosing a frequency that
5667          * works with required_vco.
5668          */
5669         val = I915_READ(DPLL_CTRL1);
5670
5671         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5672                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5673         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5674         if (required_vco == 8640)
5675                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5676                                             SKL_DPLL0);
5677         else
5678                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5679                                             SKL_DPLL0);
5680
5681         I915_WRITE(DPLL_CTRL1, val);
5682         POSTING_READ(DPLL_CTRL1);
5683
5684         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5685
5686         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5687                 DRM_ERROR("DPLL0 not locked\n");
5688 }
5689
5690 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5691 {
5692         int ret;
5693         u32 val;
5694
5695         /* inform PCU we want to change CDCLK */
5696         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5697         mutex_lock(&dev_priv->rps.hw_lock);
5698         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5699         mutex_unlock(&dev_priv->rps.hw_lock);
5700
5701         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5702 }
5703
5704 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5705 {
5706         unsigned int i;
5707
5708         for (i = 0; i < 15; i++) {
5709                 if (skl_cdclk_pcu_ready(dev_priv))
5710                         return true;
5711                 udelay(10);
5712         }
5713
5714         return false;
5715 }
5716
5717 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5718 {
5719         struct drm_device *dev = dev_priv->dev;
5720         u32 freq_select, pcu_ack;
5721
5722         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5723
5724         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5725                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5726                 return;
5727         }
5728
5729         /* set CDCLK_CTL */
5730         switch(freq) {
5731         case 450000:
5732         case 432000:
5733                 freq_select = CDCLK_FREQ_450_432;
5734                 pcu_ack = 1;
5735                 break;
5736         case 540000:
5737                 freq_select = CDCLK_FREQ_540;
5738                 pcu_ack = 2;
5739                 break;
5740         case 308570:
5741         case 337500:
5742         default:
5743                 freq_select = CDCLK_FREQ_337_308;
5744                 pcu_ack = 0;
5745                 break;
5746         case 617140:
5747         case 675000:
5748                 freq_select = CDCLK_FREQ_675_617;
5749                 pcu_ack = 3;
5750                 break;
5751         }
5752
5753         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5754         POSTING_READ(CDCLK_CTL);
5755
5756         /* inform PCU of the change */
5757         mutex_lock(&dev_priv->rps.hw_lock);
5758         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5759         mutex_unlock(&dev_priv->rps.hw_lock);
5760
5761         intel_update_cdclk(dev);
5762 }
5763
5764 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5765 {
5766         /* disable DBUF power */
5767         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5768         POSTING_READ(DBUF_CTL);
5769
5770         udelay(10);
5771
5772         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5773                 DRM_ERROR("DBuf power disable timeout\n");
5774
5775         /* disable DPLL0 */
5776         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5777         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5778                 DRM_ERROR("Couldn't disable DPLL0\n");
5779 }
5780
5781 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5782 {
5783         unsigned int required_vco;
5784
5785         /* DPLL0 not enabled (happens on early BIOS versions) */
5786         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5787                 /* enable DPLL0 */
5788                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5789                 skl_dpll0_enable(dev_priv, required_vco);
5790         }
5791
5792         /* set CDCLK to the frequency the BIOS chose */
5793         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5794
5795         /* enable DBUF power */
5796         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5797         POSTING_READ(DBUF_CTL);
5798
5799         udelay(10);
5800
5801         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5802                 DRM_ERROR("DBuf power enable timeout\n");
5803 }
5804
5805 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5806 {
5807         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5808         uint32_t cdctl = I915_READ(CDCLK_CTL);
5809         int freq = dev_priv->skl_boot_cdclk;
5810
5811         /*
5812          * check if the pre-os intialized the display
5813          * There is SWF18 scratchpad register defined which is set by the
5814          * pre-os which can be used by the OS drivers to check the status
5815          */
5816         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5817                 goto sanitize;
5818
5819         /* Is PLL enabled and locked ? */
5820         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5821                 goto sanitize;
5822
5823         /* DPLL okay; verify the cdclock
5824          *
5825          * Noticed in some instances that the freq selection is correct but
5826          * decimal part is programmed wrong from BIOS where pre-os does not
5827          * enable display. Verify the same as well.
5828          */
5829         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5830                 /* All well; nothing to sanitize */
5831                 return false;
5832 sanitize:
5833         /*
5834          * As of now initialize with max cdclk till
5835          * we get dynamic cdclk support
5836          * */
5837         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5838         skl_init_cdclk(dev_priv);
5839
5840         /* we did have to sanitize */
5841         return true;
5842 }
5843
5844 /* Adjust CDclk dividers to allow high res or save power if possible */
5845 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5846 {
5847         struct drm_i915_private *dev_priv = dev->dev_private;
5848         u32 val, cmd;
5849
5850         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5851                                         != dev_priv->cdclk_freq);
5852
5853         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5854                 cmd = 2;
5855         else if (cdclk == 266667)
5856                 cmd = 1;
5857         else
5858                 cmd = 0;
5859
5860         mutex_lock(&dev_priv->rps.hw_lock);
5861         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5862         val &= ~DSPFREQGUAR_MASK;
5863         val |= (cmd << DSPFREQGUAR_SHIFT);
5864         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5865         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5866                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5867                      50)) {
5868                 DRM_ERROR("timed out waiting for CDclk change\n");
5869         }
5870         mutex_unlock(&dev_priv->rps.hw_lock);
5871
5872         mutex_lock(&dev_priv->sb_lock);
5873
5874         if (cdclk == 400000) {
5875                 u32 divider;
5876
5877                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5878
5879                 /* adjust cdclk divider */
5880                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5881                 val &= ~CCK_FREQUENCY_VALUES;
5882                 val |= divider;
5883                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5884
5885                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5886                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5887                              50))
5888                         DRM_ERROR("timed out waiting for CDclk change\n");
5889         }
5890
5891         /* adjust self-refresh exit latency value */
5892         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5893         val &= ~0x7f;
5894
5895         /*
5896          * For high bandwidth configs, we set a higher latency in the bunit
5897          * so that the core display fetch happens in time to avoid underruns.
5898          */
5899         if (cdclk == 400000)
5900                 val |= 4500 / 250; /* 4.5 usec */
5901         else
5902                 val |= 3000 / 250; /* 3.0 usec */
5903         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5904
5905         mutex_unlock(&dev_priv->sb_lock);
5906
5907         intel_update_cdclk(dev);
5908 }
5909
5910 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5911 {
5912         struct drm_i915_private *dev_priv = dev->dev_private;
5913         u32 val, cmd;
5914
5915         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5916                                                 != dev_priv->cdclk_freq);
5917
5918         switch (cdclk) {
5919         case 333333:
5920         case 320000:
5921         case 266667:
5922         case 200000:
5923                 break;
5924         default:
5925                 MISSING_CASE(cdclk);
5926                 return;
5927         }
5928
5929         /*
5930          * Specs are full of misinformation, but testing on actual
5931          * hardware has shown that we just need to write the desired
5932          * CCK divider into the Punit register.
5933          */
5934         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5935
5936         mutex_lock(&dev_priv->rps.hw_lock);
5937         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5938         val &= ~DSPFREQGUAR_MASK_CHV;
5939         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5940         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5941         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5942                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5943                      50)) {
5944                 DRM_ERROR("timed out waiting for CDclk change\n");
5945         }
5946         mutex_unlock(&dev_priv->rps.hw_lock);
5947
5948         intel_update_cdclk(dev);
5949 }
5950
5951 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5952                                  int max_pixclk)
5953 {
5954         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5955         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5956
5957         /*
5958          * Really only a few cases to deal with, as only 4 CDclks are supported:
5959          *   200MHz
5960          *   267MHz
5961          *   320/333MHz (depends on HPLL freq)
5962          *   400MHz (VLV only)
5963          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5964          * of the lower bin and adjust if needed.
5965          *
5966          * We seem to get an unstable or solid color picture at 200MHz.
5967          * Not sure what's wrong. For now use 200MHz only when all pipes
5968          * are off.
5969          */
5970         if (!IS_CHERRYVIEW(dev_priv) &&
5971             max_pixclk > freq_320*limit/100)
5972                 return 400000;
5973         else if (max_pixclk > 266667*limit/100)
5974                 return freq_320;
5975         else if (max_pixclk > 0)
5976                 return 266667;
5977         else
5978                 return 200000;
5979 }
5980
5981 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5982                               int max_pixclk)
5983 {
5984         /*
5985          * FIXME:
5986          * - remove the guardband, it's not needed on BXT
5987          * - set 19.2MHz bypass frequency if there are no active pipes
5988          */
5989         if (max_pixclk > 576000*9/10)
5990                 return 624000;
5991         else if (max_pixclk > 384000*9/10)
5992                 return 576000;
5993         else if (max_pixclk > 288000*9/10)
5994                 return 384000;
5995         else if (max_pixclk > 144000*9/10)
5996                 return 288000;
5997         else
5998                 return 144000;
5999 }
6000
6001 /* Compute the max pixel clock for new configuration. Uses atomic state if
6002  * that's non-NULL, look at current state otherwise. */
6003 static int intel_mode_max_pixclk(struct drm_device *dev,
6004                                  struct drm_atomic_state *state)
6005 {
6006         struct intel_crtc *intel_crtc;
6007         struct intel_crtc_state *crtc_state;
6008         int max_pixclk = 0;
6009
6010         for_each_intel_crtc(dev, intel_crtc) {
6011                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6012                 if (IS_ERR(crtc_state))
6013                         return PTR_ERR(crtc_state);
6014
6015                 if (!crtc_state->base.enable)
6016                         continue;
6017
6018                 max_pixclk = max(max_pixclk,
6019                                  crtc_state->base.adjusted_mode.crtc_clock);
6020         }
6021
6022         return max_pixclk;
6023 }
6024
6025 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6026 {
6027         struct drm_device *dev = state->dev;
6028         struct drm_i915_private *dev_priv = dev->dev_private;
6029         int max_pixclk = intel_mode_max_pixclk(dev, state);
6030
6031         if (max_pixclk < 0)
6032                 return max_pixclk;
6033
6034         to_intel_atomic_state(state)->cdclk =
6035                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6036
6037         return 0;
6038 }
6039
6040 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6041 {
6042         struct drm_device *dev = state->dev;
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044         int max_pixclk = intel_mode_max_pixclk(dev, state);
6045
6046         if (max_pixclk < 0)
6047                 return max_pixclk;
6048
6049         to_intel_atomic_state(state)->cdclk =
6050                 broxton_calc_cdclk(dev_priv, max_pixclk);
6051
6052         return 0;
6053 }
6054
6055 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6056 {
6057         unsigned int credits, default_credits;
6058
6059         if (IS_CHERRYVIEW(dev_priv))
6060                 default_credits = PFI_CREDIT(12);
6061         else
6062                 default_credits = PFI_CREDIT(8);
6063
6064         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6065                 /* CHV suggested value is 31 or 63 */
6066                 if (IS_CHERRYVIEW(dev_priv))
6067                         credits = PFI_CREDIT_63;
6068                 else
6069                         credits = PFI_CREDIT(15);
6070         } else {
6071                 credits = default_credits;
6072         }
6073
6074         /*
6075          * WA - write default credits before re-programming
6076          * FIXME: should we also set the resend bit here?
6077          */
6078         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6079                    default_credits);
6080
6081         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6082                    credits | PFI_CREDIT_RESEND);
6083
6084         /*
6085          * FIXME is this guaranteed to clear
6086          * immediately or should we poll for it?
6087          */
6088         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6089 }
6090
6091 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6092 {
6093         struct drm_device *dev = old_state->dev;
6094         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096
6097         /*
6098          * FIXME: We can end up here with all power domains off, yet
6099          * with a CDCLK frequency other than the minimum. To account
6100          * for this take the PIPE-A power domain, which covers the HW
6101          * blocks needed for the following programming. This can be
6102          * removed once it's guaranteed that we get here either with
6103          * the minimum CDCLK set, or the required power domains
6104          * enabled.
6105          */
6106         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6107
6108         if (IS_CHERRYVIEW(dev))
6109                 cherryview_set_cdclk(dev, req_cdclk);
6110         else
6111                 valleyview_set_cdclk(dev, req_cdclk);
6112
6113         vlv_program_pfi_credits(dev_priv);
6114
6115         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6116 }
6117
6118 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6119 {
6120         struct drm_device *dev = crtc->dev;
6121         struct drm_i915_private *dev_priv = to_i915(dev);
6122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6123         struct intel_encoder *encoder;
6124         int pipe = intel_crtc->pipe;
6125         bool is_dsi;
6126
6127         if (WARN_ON(intel_crtc->active))
6128                 return;
6129
6130         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6131
6132         if (intel_crtc->config->has_dp_encoder)
6133                 intel_dp_set_m_n(intel_crtc, M1_N1);
6134
6135         intel_set_pipe_timings(intel_crtc);
6136
6137         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6138                 struct drm_i915_private *dev_priv = dev->dev_private;
6139
6140                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6141                 I915_WRITE(CHV_CANVAS(pipe), 0);
6142         }
6143
6144         i9xx_set_pipeconf(intel_crtc);
6145
6146         intel_crtc->active = true;
6147
6148         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6149
6150         for_each_encoder_on_crtc(dev, crtc, encoder)
6151                 if (encoder->pre_pll_enable)
6152                         encoder->pre_pll_enable(encoder);
6153
6154         if (!is_dsi) {
6155                 if (IS_CHERRYVIEW(dev)) {
6156                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6157                         chv_enable_pll(intel_crtc, intel_crtc->config);
6158                 } else {
6159                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6160                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6161                 }
6162         }
6163
6164         for_each_encoder_on_crtc(dev, crtc, encoder)
6165                 if (encoder->pre_enable)
6166                         encoder->pre_enable(encoder);
6167
6168         i9xx_pfit_enable(intel_crtc);
6169
6170         intel_crtc_load_lut(crtc);
6171
6172         intel_enable_pipe(intel_crtc);
6173
6174         assert_vblank_disabled(crtc);
6175         drm_crtc_vblank_on(crtc);
6176
6177         for_each_encoder_on_crtc(dev, crtc, encoder)
6178                 encoder->enable(encoder);
6179 }
6180
6181 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6182 {
6183         struct drm_device *dev = crtc->base.dev;
6184         struct drm_i915_private *dev_priv = dev->dev_private;
6185
6186         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6187         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6188 }
6189
6190 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6191 {
6192         struct drm_device *dev = crtc->dev;
6193         struct drm_i915_private *dev_priv = to_i915(dev);
6194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195         struct intel_encoder *encoder;
6196         int pipe = intel_crtc->pipe;
6197
6198         if (WARN_ON(intel_crtc->active))
6199                 return;
6200
6201         i9xx_set_pll_dividers(intel_crtc);
6202
6203         if (intel_crtc->config->has_dp_encoder)
6204                 intel_dp_set_m_n(intel_crtc, M1_N1);
6205
6206         intel_set_pipe_timings(intel_crtc);
6207
6208         i9xx_set_pipeconf(intel_crtc);
6209
6210         intel_crtc->active = true;
6211
6212         if (!IS_GEN2(dev))
6213                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6214
6215         for_each_encoder_on_crtc(dev, crtc, encoder)
6216                 if (encoder->pre_enable)
6217                         encoder->pre_enable(encoder);
6218
6219         i9xx_enable_pll(intel_crtc);
6220
6221         i9xx_pfit_enable(intel_crtc);
6222
6223         intel_crtc_load_lut(crtc);
6224
6225         intel_update_watermarks(crtc);
6226         intel_enable_pipe(intel_crtc);
6227
6228         assert_vblank_disabled(crtc);
6229         drm_crtc_vblank_on(crtc);
6230
6231         for_each_encoder_on_crtc(dev, crtc, encoder)
6232                 encoder->enable(encoder);
6233 }
6234
6235 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6236 {
6237         struct drm_device *dev = crtc->base.dev;
6238         struct drm_i915_private *dev_priv = dev->dev_private;
6239
6240         if (!crtc->config->gmch_pfit.control)
6241                 return;
6242
6243         assert_pipe_disabled(dev_priv, crtc->pipe);
6244
6245         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6246                          I915_READ(PFIT_CONTROL));
6247         I915_WRITE(PFIT_CONTROL, 0);
6248 }
6249
6250 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6251 {
6252         struct drm_device *dev = crtc->dev;
6253         struct drm_i915_private *dev_priv = dev->dev_private;
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255         struct intel_encoder *encoder;
6256         int pipe = intel_crtc->pipe;
6257
6258         /*
6259          * On gen2 planes are double buffered but the pipe isn't, so we must
6260          * wait for planes to fully turn off before disabling the pipe.
6261          * We also need to wait on all gmch platforms because of the
6262          * self-refresh mode constraint explained above.
6263          */
6264         intel_wait_for_vblank(dev, pipe);
6265
6266         for_each_encoder_on_crtc(dev, crtc, encoder)
6267                 encoder->disable(encoder);
6268
6269         drm_crtc_vblank_off(crtc);
6270         assert_vblank_disabled(crtc);
6271
6272         intel_disable_pipe(intel_crtc);
6273
6274         i9xx_pfit_disable(intel_crtc);
6275
6276         for_each_encoder_on_crtc(dev, crtc, encoder)
6277                 if (encoder->post_disable)
6278                         encoder->post_disable(encoder);
6279
6280         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6281                 if (IS_CHERRYVIEW(dev))
6282                         chv_disable_pll(dev_priv, pipe);
6283                 else if (IS_VALLEYVIEW(dev))
6284                         vlv_disable_pll(dev_priv, pipe);
6285                 else
6286                         i9xx_disable_pll(intel_crtc);
6287         }
6288
6289         for_each_encoder_on_crtc(dev, crtc, encoder)
6290                 if (encoder->post_pll_disable)
6291                         encoder->post_pll_disable(encoder);
6292
6293         if (!IS_GEN2(dev))
6294                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6295 }
6296
6297 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6298 {
6299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6301         enum intel_display_power_domain domain;
6302         unsigned long domains;
6303
6304         if (!intel_crtc->active)
6305                 return;
6306
6307         if (to_intel_plane_state(crtc->primary->state)->visible) {
6308                 WARN_ON(intel_crtc->unpin_work);
6309
6310                 intel_pre_disable_primary(crtc);
6311         }
6312
6313         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6314         dev_priv->display.crtc_disable(crtc);
6315         intel_crtc->active = false;
6316         intel_update_watermarks(crtc);
6317         intel_disable_shared_dpll(intel_crtc);
6318
6319         domains = intel_crtc->enabled_power_domains;
6320         for_each_power_domain(domain, domains)
6321                 intel_display_power_put(dev_priv, domain);
6322         intel_crtc->enabled_power_domains = 0;
6323 }
6324
6325 /*
6326  * turn all crtc's off, but do not adjust state
6327  * This has to be paired with a call to intel_modeset_setup_hw_state.
6328  */
6329 int intel_display_suspend(struct drm_device *dev)
6330 {
6331         struct drm_mode_config *config = &dev->mode_config;
6332         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6333         struct drm_atomic_state *state;
6334         struct drm_crtc *crtc;
6335         unsigned crtc_mask = 0;
6336         int ret = 0;
6337
6338         if (WARN_ON(!ctx))
6339                 return 0;
6340
6341         lockdep_assert_held(&ctx->ww_ctx);
6342         state = drm_atomic_state_alloc(dev);
6343         if (WARN_ON(!state))
6344                 return -ENOMEM;
6345
6346         state->acquire_ctx = ctx;
6347         state->allow_modeset = true;
6348
6349         for_each_crtc(dev, crtc) {
6350                 struct drm_crtc_state *crtc_state =
6351                         drm_atomic_get_crtc_state(state, crtc);
6352
6353                 ret = PTR_ERR_OR_ZERO(crtc_state);
6354                 if (ret)
6355                         goto free;
6356
6357                 if (!crtc_state->active)
6358                         continue;
6359
6360                 crtc_state->active = false;
6361                 crtc_mask |= 1 << drm_crtc_index(crtc);
6362         }
6363
6364         if (crtc_mask) {
6365                 ret = drm_atomic_commit(state);
6366
6367                 if (!ret) {
6368                         for_each_crtc(dev, crtc)
6369                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6370                                         crtc->state->active = true;
6371
6372                         return ret;
6373                 }
6374         }
6375
6376 free:
6377         if (ret)
6378                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6379         drm_atomic_state_free(state);
6380         return ret;
6381 }
6382
6383 void intel_encoder_destroy(struct drm_encoder *encoder)
6384 {
6385         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6386
6387         drm_encoder_cleanup(encoder);
6388         kfree(intel_encoder);
6389 }
6390
6391 /* Cross check the actual hw state with our own modeset state tracking (and it's
6392  * internal consistency). */
6393 static void intel_connector_check_state(struct intel_connector *connector)
6394 {
6395         struct drm_crtc *crtc = connector->base.state->crtc;
6396
6397         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6398                       connector->base.base.id,
6399                       connector->base.name);
6400
6401         if (connector->get_hw_state(connector)) {
6402                 struct intel_encoder *encoder = connector->encoder;
6403                 struct drm_connector_state *conn_state = connector->base.state;
6404
6405                 I915_STATE_WARN(!crtc,
6406                          "connector enabled without attached crtc\n");
6407
6408                 if (!crtc)
6409                         return;
6410
6411                 I915_STATE_WARN(!crtc->state->active,
6412                       "connector is active, but attached crtc isn't\n");
6413
6414                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6415                         return;
6416
6417                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6418                         "atomic encoder doesn't match attached encoder\n");
6419
6420                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6421                         "attached encoder crtc differs from connector crtc\n");
6422         } else {
6423                 I915_STATE_WARN(crtc && crtc->state->active,
6424                         "attached crtc is active, but connector isn't\n");
6425                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6426                         "best encoder set without crtc!\n");
6427         }
6428 }
6429
6430 int intel_connector_init(struct intel_connector *connector)
6431 {
6432         struct drm_connector_state *connector_state;
6433
6434         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6435         if (!connector_state)
6436                 return -ENOMEM;
6437
6438         connector->base.state = connector_state;
6439         return 0;
6440 }
6441
6442 struct intel_connector *intel_connector_alloc(void)
6443 {
6444         struct intel_connector *connector;
6445
6446         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6447         if (!connector)
6448                 return NULL;
6449
6450         if (intel_connector_init(connector) < 0) {
6451                 kfree(connector);
6452                 return NULL;
6453         }
6454
6455         return connector;
6456 }
6457
6458 /* Simple connector->get_hw_state implementation for encoders that support only
6459  * one connector and no cloning and hence the encoder state determines the state
6460  * of the connector. */
6461 bool intel_connector_get_hw_state(struct intel_connector *connector)
6462 {
6463         enum pipe pipe = 0;
6464         struct intel_encoder *encoder = connector->encoder;
6465
6466         return encoder->get_hw_state(encoder, &pipe);
6467 }
6468
6469 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6470 {
6471         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6472                 return crtc_state->fdi_lanes;
6473
6474         return 0;
6475 }
6476
6477 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6478                                      struct intel_crtc_state *pipe_config)
6479 {
6480         struct drm_atomic_state *state = pipe_config->base.state;
6481         struct intel_crtc *other_crtc;
6482         struct intel_crtc_state *other_crtc_state;
6483
6484         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6485                       pipe_name(pipe), pipe_config->fdi_lanes);
6486         if (pipe_config->fdi_lanes > 4) {
6487                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6488                               pipe_name(pipe), pipe_config->fdi_lanes);
6489                 return -EINVAL;
6490         }
6491
6492         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6493                 if (pipe_config->fdi_lanes > 2) {
6494                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6495                                       pipe_config->fdi_lanes);
6496                         return -EINVAL;
6497                 } else {
6498                         return 0;
6499                 }
6500         }
6501
6502         if (INTEL_INFO(dev)->num_pipes == 2)
6503                 return 0;
6504
6505         /* Ivybridge 3 pipe is really complicated */
6506         switch (pipe) {
6507         case PIPE_A:
6508                 return 0;
6509         case PIPE_B:
6510                 if (pipe_config->fdi_lanes <= 2)
6511                         return 0;
6512
6513                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6514                 other_crtc_state =
6515                         intel_atomic_get_crtc_state(state, other_crtc);
6516                 if (IS_ERR(other_crtc_state))
6517                         return PTR_ERR(other_crtc_state);
6518
6519                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6520                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6521                                       pipe_name(pipe), pipe_config->fdi_lanes);
6522                         return -EINVAL;
6523                 }
6524                 return 0;
6525         case PIPE_C:
6526                 if (pipe_config->fdi_lanes > 2) {
6527                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6528                                       pipe_name(pipe), pipe_config->fdi_lanes);
6529                         return -EINVAL;
6530                 }
6531
6532                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6533                 other_crtc_state =
6534                         intel_atomic_get_crtc_state(state, other_crtc);
6535                 if (IS_ERR(other_crtc_state))
6536                         return PTR_ERR(other_crtc_state);
6537
6538                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6539                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6540                         return -EINVAL;
6541                 }
6542                 return 0;
6543         default:
6544                 BUG();
6545         }
6546 }
6547
6548 #define RETRY 1
6549 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6550                                        struct intel_crtc_state *pipe_config)
6551 {
6552         struct drm_device *dev = intel_crtc->base.dev;
6553         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6554         int lane, link_bw, fdi_dotclock, ret;
6555         bool needs_recompute = false;
6556
6557 retry:
6558         /* FDI is a binary signal running at ~2.7GHz, encoding
6559          * each output octet as 10 bits. The actual frequency
6560          * is stored as a divider into a 100MHz clock, and the
6561          * mode pixel clock is stored in units of 1KHz.
6562          * Hence the bw of each lane in terms of the mode signal
6563          * is:
6564          */
6565         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6566
6567         fdi_dotclock = adjusted_mode->crtc_clock;
6568
6569         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6570                                            pipe_config->pipe_bpp);
6571
6572         pipe_config->fdi_lanes = lane;
6573
6574         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6575                                link_bw, &pipe_config->fdi_m_n);
6576
6577         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6578                                        intel_crtc->pipe, pipe_config);
6579         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6580                 pipe_config->pipe_bpp -= 2*3;
6581                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6582                               pipe_config->pipe_bpp);
6583                 needs_recompute = true;
6584                 pipe_config->bw_constrained = true;
6585
6586                 goto retry;
6587         }
6588
6589         if (needs_recompute)
6590                 return RETRY;
6591
6592         return ret;
6593 }
6594
6595 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6596                                      struct intel_crtc_state *pipe_config)
6597 {
6598         if (pipe_config->pipe_bpp > 24)
6599                 return false;
6600
6601         /* HSW can handle pixel rate up to cdclk? */
6602         if (IS_HASWELL(dev_priv->dev))
6603                 return true;
6604
6605         /*
6606          * We compare against max which means we must take
6607          * the increased cdclk requirement into account when
6608          * calculating the new cdclk.
6609          *
6610          * Should measure whether using a lower cdclk w/o IPS
6611          */
6612         return ilk_pipe_pixel_rate(pipe_config) <=
6613                 dev_priv->max_cdclk_freq * 95 / 100;
6614 }
6615
6616 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6617                                    struct intel_crtc_state *pipe_config)
6618 {
6619         struct drm_device *dev = crtc->base.dev;
6620         struct drm_i915_private *dev_priv = dev->dev_private;
6621
6622         pipe_config->ips_enabled = i915.enable_ips &&
6623                 hsw_crtc_supports_ips(crtc) &&
6624                 pipe_config_supports_ips(dev_priv, pipe_config);
6625 }
6626
6627 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6628 {
6629         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6630
6631         /* GDG double wide on either pipe, otherwise pipe A only */
6632         return INTEL_INFO(dev_priv)->gen < 4 &&
6633                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6634 }
6635
6636 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6637                                      struct intel_crtc_state *pipe_config)
6638 {
6639         struct drm_device *dev = crtc->base.dev;
6640         struct drm_i915_private *dev_priv = dev->dev_private;
6641         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6642
6643         /* FIXME should check pixel clock limits on all platforms */
6644         if (INTEL_INFO(dev)->gen < 4) {
6645                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6646
6647                 /*
6648                  * Enable double wide mode when the dot clock
6649                  * is > 90% of the (display) core speed.
6650                  */
6651                 if (intel_crtc_supports_double_wide(crtc) &&
6652                     adjusted_mode->crtc_clock > clock_limit) {
6653                         clock_limit *= 2;
6654                         pipe_config->double_wide = true;
6655                 }
6656
6657                 if (adjusted_mode->crtc_clock > clock_limit) {
6658                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6659                                       adjusted_mode->crtc_clock, clock_limit,
6660                                       yesno(pipe_config->double_wide));
6661                         return -EINVAL;
6662                 }
6663         }
6664
6665         /*
6666          * Pipe horizontal size must be even in:
6667          * - DVO ganged mode
6668          * - LVDS dual channel mode
6669          * - Double wide pipe
6670          */
6671         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6672              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6673                 pipe_config->pipe_src_w &= ~1;
6674
6675         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6676          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6677          */
6678         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6679                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6680                 return -EINVAL;
6681
6682         if (HAS_IPS(dev))
6683                 hsw_compute_ips_config(crtc, pipe_config);
6684
6685         if (pipe_config->has_pch_encoder)
6686                 return ironlake_fdi_compute_config(crtc, pipe_config);
6687
6688         return 0;
6689 }
6690
6691 static int skylake_get_display_clock_speed(struct drm_device *dev)
6692 {
6693         struct drm_i915_private *dev_priv = to_i915(dev);
6694         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6695         uint32_t cdctl = I915_READ(CDCLK_CTL);
6696         uint32_t linkrate;
6697
6698         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6699                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6700
6701         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6702                 return 540000;
6703
6704         linkrate = (I915_READ(DPLL_CTRL1) &
6705                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6706
6707         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6708             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6709                 /* vco 8640 */
6710                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6711                 case CDCLK_FREQ_450_432:
6712                         return 432000;
6713                 case CDCLK_FREQ_337_308:
6714                         return 308570;
6715                 case CDCLK_FREQ_675_617:
6716                         return 617140;
6717                 default:
6718                         WARN(1, "Unknown cd freq selection\n");
6719                 }
6720         } else {
6721                 /* vco 8100 */
6722                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6723                 case CDCLK_FREQ_450_432:
6724                         return 450000;
6725                 case CDCLK_FREQ_337_308:
6726                         return 337500;
6727                 case CDCLK_FREQ_675_617:
6728                         return 675000;
6729                 default:
6730                         WARN(1, "Unknown cd freq selection\n");
6731                 }
6732         }
6733
6734         /* error case, do as if DPLL0 isn't enabled */
6735         return 24000;
6736 }
6737
6738 static int broxton_get_display_clock_speed(struct drm_device *dev)
6739 {
6740         struct drm_i915_private *dev_priv = to_i915(dev);
6741         uint32_t cdctl = I915_READ(CDCLK_CTL);
6742         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6743         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6744         int cdclk;
6745
6746         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6747                 return 19200;
6748
6749         cdclk = 19200 * pll_ratio / 2;
6750
6751         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6752         case BXT_CDCLK_CD2X_DIV_SEL_1:
6753                 return cdclk;  /* 576MHz or 624MHz */
6754         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6755                 return cdclk * 2 / 3; /* 384MHz */
6756         case BXT_CDCLK_CD2X_DIV_SEL_2:
6757                 return cdclk / 2; /* 288MHz */
6758         case BXT_CDCLK_CD2X_DIV_SEL_4:
6759                 return cdclk / 4; /* 144MHz */
6760         }
6761
6762         /* error case, do as if DE PLL isn't enabled */
6763         return 19200;
6764 }
6765
6766 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769         uint32_t lcpll = I915_READ(LCPLL_CTL);
6770         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6771
6772         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6773                 return 800000;
6774         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6775                 return 450000;
6776         else if (freq == LCPLL_CLK_FREQ_450)
6777                 return 450000;
6778         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6779                 return 540000;
6780         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6781                 return 337500;
6782         else
6783                 return 675000;
6784 }
6785
6786 static int haswell_get_display_clock_speed(struct drm_device *dev)
6787 {
6788         struct drm_i915_private *dev_priv = dev->dev_private;
6789         uint32_t lcpll = I915_READ(LCPLL_CTL);
6790         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6791
6792         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6793                 return 800000;
6794         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6795                 return 450000;
6796         else if (freq == LCPLL_CLK_FREQ_450)
6797                 return 450000;
6798         else if (IS_HSW_ULT(dev))
6799                 return 337500;
6800         else
6801                 return 540000;
6802 }
6803
6804 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6805 {
6806         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6807                                       CCK_DISPLAY_CLOCK_CONTROL);
6808 }
6809
6810 static int ilk_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         return 450000;
6813 }
6814
6815 static int i945_get_display_clock_speed(struct drm_device *dev)
6816 {
6817         return 400000;
6818 }
6819
6820 static int i915_get_display_clock_speed(struct drm_device *dev)
6821 {
6822         return 333333;
6823 }
6824
6825 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6826 {
6827         return 200000;
6828 }
6829
6830 static int pnv_get_display_clock_speed(struct drm_device *dev)
6831 {
6832         u16 gcfgc = 0;
6833
6834         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6835
6836         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6837         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6838                 return 266667;
6839         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6840                 return 333333;
6841         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6842                 return 444444;
6843         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6844                 return 200000;
6845         default:
6846                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6847         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6848                 return 133333;
6849         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6850                 return 166667;
6851         }
6852 }
6853
6854 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6855 {
6856         u16 gcfgc = 0;
6857
6858         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6859
6860         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6861                 return 133333;
6862         else {
6863                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6864                 case GC_DISPLAY_CLOCK_333_MHZ:
6865                         return 333333;
6866                 default:
6867                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6868                         return 190000;
6869                 }
6870         }
6871 }
6872
6873 static int i865_get_display_clock_speed(struct drm_device *dev)
6874 {
6875         return 266667;
6876 }
6877
6878 static int i85x_get_display_clock_speed(struct drm_device *dev)
6879 {
6880         u16 hpllcc = 0;
6881
6882         /*
6883          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6884          * encoding is different :(
6885          * FIXME is this the right way to detect 852GM/852GMV?
6886          */
6887         if (dev->pdev->revision == 0x1)
6888                 return 133333;
6889
6890         pci_bus_read_config_word(dev->pdev->bus,
6891                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6892
6893         /* Assume that the hardware is in the high speed state.  This
6894          * should be the default.
6895          */
6896         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6897         case GC_CLOCK_133_200:
6898         case GC_CLOCK_133_200_2:
6899         case GC_CLOCK_100_200:
6900                 return 200000;
6901         case GC_CLOCK_166_250:
6902                 return 250000;
6903         case GC_CLOCK_100_133:
6904                 return 133333;
6905         case GC_CLOCK_133_266:
6906         case GC_CLOCK_133_266_2:
6907         case GC_CLOCK_166_266:
6908                 return 266667;
6909         }
6910
6911         /* Shouldn't happen */
6912         return 0;
6913 }
6914
6915 static int i830_get_display_clock_speed(struct drm_device *dev)
6916 {
6917         return 133333;
6918 }
6919
6920 static unsigned int intel_hpll_vco(struct drm_device *dev)
6921 {
6922         struct drm_i915_private *dev_priv = dev->dev_private;
6923         static const unsigned int blb_vco[8] = {
6924                 [0] = 3200000,
6925                 [1] = 4000000,
6926                 [2] = 5333333,
6927                 [3] = 4800000,
6928                 [4] = 6400000,
6929         };
6930         static const unsigned int pnv_vco[8] = {
6931                 [0] = 3200000,
6932                 [1] = 4000000,
6933                 [2] = 5333333,
6934                 [3] = 4800000,
6935                 [4] = 2666667,
6936         };
6937         static const unsigned int cl_vco[8] = {
6938                 [0] = 3200000,
6939                 [1] = 4000000,
6940                 [2] = 5333333,
6941                 [3] = 6400000,
6942                 [4] = 3333333,
6943                 [5] = 3566667,
6944                 [6] = 4266667,
6945         };
6946         static const unsigned int elk_vco[8] = {
6947                 [0] = 3200000,
6948                 [1] = 4000000,
6949                 [2] = 5333333,
6950                 [3] = 4800000,
6951         };
6952         static const unsigned int ctg_vco[8] = {
6953                 [0] = 3200000,
6954                 [1] = 4000000,
6955                 [2] = 5333333,
6956                 [3] = 6400000,
6957                 [4] = 2666667,
6958                 [5] = 4266667,
6959         };
6960         const unsigned int *vco_table;
6961         unsigned int vco;
6962         uint8_t tmp = 0;
6963
6964         /* FIXME other chipsets? */
6965         if (IS_GM45(dev))
6966                 vco_table = ctg_vco;
6967         else if (IS_G4X(dev))
6968                 vco_table = elk_vco;
6969         else if (IS_CRESTLINE(dev))
6970                 vco_table = cl_vco;
6971         else if (IS_PINEVIEW(dev))
6972                 vco_table = pnv_vco;
6973         else if (IS_G33(dev))
6974                 vco_table = blb_vco;
6975         else
6976                 return 0;
6977
6978         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6979
6980         vco = vco_table[tmp & 0x7];
6981         if (vco == 0)
6982                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6983         else
6984                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6985
6986         return vco;
6987 }
6988
6989 static int gm45_get_display_clock_speed(struct drm_device *dev)
6990 {
6991         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6992         uint16_t tmp = 0;
6993
6994         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6995
6996         cdclk_sel = (tmp >> 12) & 0x1;
6997
6998         switch (vco) {
6999         case 2666667:
7000         case 4000000:
7001         case 5333333:
7002                 return cdclk_sel ? 333333 : 222222;
7003         case 3200000:
7004                 return cdclk_sel ? 320000 : 228571;
7005         default:
7006                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7007                 return 222222;
7008         }
7009 }
7010
7011 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7012 {
7013         static const uint8_t div_3200[] = { 16, 10,  8 };
7014         static const uint8_t div_4000[] = { 20, 12, 10 };
7015         static const uint8_t div_5333[] = { 24, 16, 14 };
7016         const uint8_t *div_table;
7017         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7018         uint16_t tmp = 0;
7019
7020         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7021
7022         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7023
7024         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7025                 goto fail;
7026
7027         switch (vco) {
7028         case 3200000:
7029                 div_table = div_3200;
7030                 break;
7031         case 4000000:
7032                 div_table = div_4000;
7033                 break;
7034         case 5333333:
7035                 div_table = div_5333;
7036                 break;
7037         default:
7038                 goto fail;
7039         }
7040
7041         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7042
7043 fail:
7044         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7045         return 200000;
7046 }
7047
7048 static int g33_get_display_clock_speed(struct drm_device *dev)
7049 {
7050         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7051         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7052         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7053         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7054         const uint8_t *div_table;
7055         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7056         uint16_t tmp = 0;
7057
7058         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7059
7060         cdclk_sel = (tmp >> 4) & 0x7;
7061
7062         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7063                 goto fail;
7064
7065         switch (vco) {
7066         case 3200000:
7067                 div_table = div_3200;
7068                 break;
7069         case 4000000:
7070                 div_table = div_4000;
7071                 break;
7072         case 4800000:
7073                 div_table = div_4800;
7074                 break;
7075         case 5333333:
7076                 div_table = div_5333;
7077                 break;
7078         default:
7079                 goto fail;
7080         }
7081
7082         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7083
7084 fail:
7085         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7086         return 190476;
7087 }
7088
7089 static void
7090 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7091 {
7092         while (*num > DATA_LINK_M_N_MASK ||
7093                *den > DATA_LINK_M_N_MASK) {
7094                 *num >>= 1;
7095                 *den >>= 1;
7096         }
7097 }
7098
7099 static void compute_m_n(unsigned int m, unsigned int n,
7100                         uint32_t *ret_m, uint32_t *ret_n)
7101 {
7102         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7103         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7104         intel_reduce_m_n_ratio(ret_m, ret_n);
7105 }
7106
7107 void
7108 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7109                        int pixel_clock, int link_clock,
7110                        struct intel_link_m_n *m_n)
7111 {
7112         m_n->tu = 64;
7113
7114         compute_m_n(bits_per_pixel * pixel_clock,
7115                     link_clock * nlanes * 8,
7116                     &m_n->gmch_m, &m_n->gmch_n);
7117
7118         compute_m_n(pixel_clock, link_clock,
7119                     &m_n->link_m, &m_n->link_n);
7120 }
7121
7122 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7123 {
7124         if (i915.panel_use_ssc >= 0)
7125                 return i915.panel_use_ssc != 0;
7126         return dev_priv->vbt.lvds_use_ssc
7127                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7128 }
7129
7130 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7131                            int num_connectors)
7132 {
7133         struct drm_device *dev = crtc_state->base.crtc->dev;
7134         struct drm_i915_private *dev_priv = dev->dev_private;
7135         int refclk;
7136
7137         WARN_ON(!crtc_state->base.state);
7138
7139         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7140                 refclk = 100000;
7141         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7142             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7143                 refclk = dev_priv->vbt.lvds_ssc_freq;
7144                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7145         } else if (!IS_GEN2(dev)) {
7146                 refclk = 96000;
7147         } else {
7148                 refclk = 48000;
7149         }
7150
7151         return refclk;
7152 }
7153
7154 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7155 {
7156         return (1 << dpll->n) << 16 | dpll->m2;
7157 }
7158
7159 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7160 {
7161         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7162 }
7163
7164 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7165                                      struct intel_crtc_state *crtc_state,
7166                                      intel_clock_t *reduced_clock)
7167 {
7168         struct drm_device *dev = crtc->base.dev;
7169         u32 fp, fp2 = 0;
7170
7171         if (IS_PINEVIEW(dev)) {
7172                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7173                 if (reduced_clock)
7174                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7175         } else {
7176                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7177                 if (reduced_clock)
7178                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7179         }
7180
7181         crtc_state->dpll_hw_state.fp0 = fp;
7182
7183         crtc->lowfreq_avail = false;
7184         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7185             reduced_clock) {
7186                 crtc_state->dpll_hw_state.fp1 = fp2;
7187                 crtc->lowfreq_avail = true;
7188         } else {
7189                 crtc_state->dpll_hw_state.fp1 = fp;
7190         }
7191 }
7192
7193 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7194                 pipe)
7195 {
7196         u32 reg_val;
7197
7198         /*
7199          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7200          * and set it to a reasonable value instead.
7201          */
7202         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7203         reg_val &= 0xffffff00;
7204         reg_val |= 0x00000030;
7205         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7206
7207         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7208         reg_val &= 0x8cffffff;
7209         reg_val = 0x8c000000;
7210         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7211
7212         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7213         reg_val &= 0xffffff00;
7214         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7215
7216         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7217         reg_val &= 0x00ffffff;
7218         reg_val |= 0xb0000000;
7219         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7220 }
7221
7222 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7223                                          struct intel_link_m_n *m_n)
7224 {
7225         struct drm_device *dev = crtc->base.dev;
7226         struct drm_i915_private *dev_priv = dev->dev_private;
7227         int pipe = crtc->pipe;
7228
7229         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7230         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7231         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7232         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7233 }
7234
7235 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7236                                          struct intel_link_m_n *m_n,
7237                                          struct intel_link_m_n *m2_n2)
7238 {
7239         struct drm_device *dev = crtc->base.dev;
7240         struct drm_i915_private *dev_priv = dev->dev_private;
7241         int pipe = crtc->pipe;
7242         enum transcoder transcoder = crtc->config->cpu_transcoder;
7243
7244         if (INTEL_INFO(dev)->gen >= 5) {
7245                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7246                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7247                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7248                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7249                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7250                  * for gen < 8) and if DRRS is supported (to make sure the
7251                  * registers are not unnecessarily accessed).
7252                  */
7253                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7254                         crtc->config->has_drrs) {
7255                         I915_WRITE(PIPE_DATA_M2(transcoder),
7256                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7257                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7258                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7259                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7260                 }
7261         } else {
7262                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7263                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7264                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7265                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7266         }
7267 }
7268
7269 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7270 {
7271         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7272
7273         if (m_n == M1_N1) {
7274                 dp_m_n = &crtc->config->dp_m_n;
7275                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7276         } else if (m_n == M2_N2) {
7277
7278                 /*
7279                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7280                  * needs to be programmed into M1_N1.
7281                  */
7282                 dp_m_n = &crtc->config->dp_m2_n2;
7283         } else {
7284                 DRM_ERROR("Unsupported divider value\n");
7285                 return;
7286         }
7287
7288         if (crtc->config->has_pch_encoder)
7289                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7290         else
7291                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7292 }
7293
7294 static void vlv_compute_dpll(struct intel_crtc *crtc,
7295                              struct intel_crtc_state *pipe_config)
7296 {
7297         u32 dpll, dpll_md;
7298
7299         /*
7300          * Enable DPIO clock input. We should never disable the reference
7301          * clock for pipe B, since VGA hotplug / manual detection depends
7302          * on it.
7303          */
7304         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7305                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7306         /* We should never disable this, set it here for state tracking */
7307         if (crtc->pipe == PIPE_B)
7308                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7309         dpll |= DPLL_VCO_ENABLE;
7310         pipe_config->dpll_hw_state.dpll = dpll;
7311
7312         dpll_md = (pipe_config->pixel_multiplier - 1)
7313                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7314         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7315 }
7316
7317 static void vlv_prepare_pll(struct intel_crtc *crtc,
7318                             const struct intel_crtc_state *pipe_config)
7319 {
7320         struct drm_device *dev = crtc->base.dev;
7321         struct drm_i915_private *dev_priv = dev->dev_private;
7322         int pipe = crtc->pipe;
7323         u32 mdiv;
7324         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7325         u32 coreclk, reg_val;
7326
7327         mutex_lock(&dev_priv->sb_lock);
7328
7329         bestn = pipe_config->dpll.n;
7330         bestm1 = pipe_config->dpll.m1;
7331         bestm2 = pipe_config->dpll.m2;
7332         bestp1 = pipe_config->dpll.p1;
7333         bestp2 = pipe_config->dpll.p2;
7334
7335         /* See eDP HDMI DPIO driver vbios notes doc */
7336
7337         /* PLL B needs special handling */
7338         if (pipe == PIPE_B)
7339                 vlv_pllb_recal_opamp(dev_priv, pipe);
7340
7341         /* Set up Tx target for periodic Rcomp update */
7342         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7343
7344         /* Disable target IRef on PLL */
7345         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7346         reg_val &= 0x00ffffff;
7347         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7348
7349         /* Disable fast lock */
7350         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7351
7352         /* Set idtafcrecal before PLL is enabled */
7353         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7354         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7355         mdiv |= ((bestn << DPIO_N_SHIFT));
7356         mdiv |= (1 << DPIO_K_SHIFT);
7357
7358         /*
7359          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7360          * but we don't support that).
7361          * Note: don't use the DAC post divider as it seems unstable.
7362          */
7363         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7364         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7365
7366         mdiv |= DPIO_ENABLE_CALIBRATION;
7367         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7368
7369         /* Set HBR and RBR LPF coefficients */
7370         if (pipe_config->port_clock == 162000 ||
7371             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7372             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7373                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7374                                  0x009f0003);
7375         else
7376                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7377                                  0x00d0000f);
7378
7379         if (pipe_config->has_dp_encoder) {
7380                 /* Use SSC source */
7381                 if (pipe == PIPE_A)
7382                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7383                                          0x0df40000);
7384                 else
7385                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7386                                          0x0df70000);
7387         } else { /* HDMI or VGA */
7388                 /* Use bend source */
7389                 if (pipe == PIPE_A)
7390                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7391                                          0x0df70000);
7392                 else
7393                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7394                                          0x0df40000);
7395         }
7396
7397         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7398         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7400             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7401                 coreclk |= 0x01000000;
7402         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7403
7404         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7405         mutex_unlock(&dev_priv->sb_lock);
7406 }
7407
7408 static void chv_compute_dpll(struct intel_crtc *crtc,
7409                              struct intel_crtc_state *pipe_config)
7410 {
7411         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7412                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7413                 DPLL_VCO_ENABLE;
7414         if (crtc->pipe != PIPE_A)
7415                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7416
7417         pipe_config->dpll_hw_state.dpll_md =
7418                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7419 }
7420
7421 static void chv_prepare_pll(struct intel_crtc *crtc,
7422                             const struct intel_crtc_state *pipe_config)
7423 {
7424         struct drm_device *dev = crtc->base.dev;
7425         struct drm_i915_private *dev_priv = dev->dev_private;
7426         int pipe = crtc->pipe;
7427         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7428         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7429         u32 loopfilter, tribuf_calcntr;
7430         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7431         u32 dpio_val;
7432         int vco;
7433
7434         bestn = pipe_config->dpll.n;
7435         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7436         bestm1 = pipe_config->dpll.m1;
7437         bestm2 = pipe_config->dpll.m2 >> 22;
7438         bestp1 = pipe_config->dpll.p1;
7439         bestp2 = pipe_config->dpll.p2;
7440         vco = pipe_config->dpll.vco;
7441         dpio_val = 0;
7442         loopfilter = 0;
7443
7444         /*
7445          * Enable Refclk and SSC
7446          */
7447         I915_WRITE(dpll_reg,
7448                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7449
7450         mutex_lock(&dev_priv->sb_lock);
7451
7452         /* p1 and p2 divider */
7453         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7454                         5 << DPIO_CHV_S1_DIV_SHIFT |
7455                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7456                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7457                         1 << DPIO_CHV_K_DIV_SHIFT);
7458
7459         /* Feedback post-divider - m2 */
7460         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7461
7462         /* Feedback refclk divider - n and m1 */
7463         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7464                         DPIO_CHV_M1_DIV_BY_2 |
7465                         1 << DPIO_CHV_N_DIV_SHIFT);
7466
7467         /* M2 fraction division */
7468         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7469
7470         /* M2 fraction division enable */
7471         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7472         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7473         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7474         if (bestm2_frac)
7475                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7476         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7477
7478         /* Program digital lock detect threshold */
7479         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7480         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7481                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7482         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7483         if (!bestm2_frac)
7484                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7485         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7486
7487         /* Loop filter */
7488         if (vco == 5400000) {
7489                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7490                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7491                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7492                 tribuf_calcntr = 0x9;
7493         } else if (vco <= 6200000) {
7494                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7495                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7496                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7497                 tribuf_calcntr = 0x9;
7498         } else if (vco <= 6480000) {
7499                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7500                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7501                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7502                 tribuf_calcntr = 0x8;
7503         } else {
7504                 /* Not supported. Apply the same limits as in the max case */
7505                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7506                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7507                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7508                 tribuf_calcntr = 0;
7509         }
7510         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7511
7512         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7513         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7514         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7515         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7516
7517         /* AFC Recal */
7518         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7519                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7520                         DPIO_AFC_RECAL);
7521
7522         mutex_unlock(&dev_priv->sb_lock);
7523 }
7524
7525 /**
7526  * vlv_force_pll_on - forcibly enable just the PLL
7527  * @dev_priv: i915 private structure
7528  * @pipe: pipe PLL to enable
7529  * @dpll: PLL configuration
7530  *
7531  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7532  * in cases where we need the PLL enabled even when @pipe is not going to
7533  * be enabled.
7534  */
7535 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7536                       const struct dpll *dpll)
7537 {
7538         struct intel_crtc *crtc =
7539                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7540         struct intel_crtc_state pipe_config = {
7541                 .base.crtc = &crtc->base,
7542                 .pixel_multiplier = 1,
7543                 .dpll = *dpll,
7544         };
7545
7546         if (IS_CHERRYVIEW(dev)) {
7547                 chv_compute_dpll(crtc, &pipe_config);
7548                 chv_prepare_pll(crtc, &pipe_config);
7549                 chv_enable_pll(crtc, &pipe_config);
7550         } else {
7551                 vlv_compute_dpll(crtc, &pipe_config);
7552                 vlv_prepare_pll(crtc, &pipe_config);
7553                 vlv_enable_pll(crtc, &pipe_config);
7554         }
7555 }
7556
7557 /**
7558  * vlv_force_pll_off - forcibly disable just the PLL
7559  * @dev_priv: i915 private structure
7560  * @pipe: pipe PLL to disable
7561  *
7562  * Disable the PLL for @pipe. To be used in cases where we need
7563  * the PLL enabled even when @pipe is not going to be enabled.
7564  */
7565 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7566 {
7567         if (IS_CHERRYVIEW(dev))
7568                 chv_disable_pll(to_i915(dev), pipe);
7569         else
7570                 vlv_disable_pll(to_i915(dev), pipe);
7571 }
7572
7573 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7574                               struct intel_crtc_state *crtc_state,
7575                               intel_clock_t *reduced_clock,
7576                               int num_connectors)
7577 {
7578         struct drm_device *dev = crtc->base.dev;
7579         struct drm_i915_private *dev_priv = dev->dev_private;
7580         u32 dpll;
7581         bool is_sdvo;
7582         struct dpll *clock = &crtc_state->dpll;
7583
7584         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7585
7586         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7587                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7588
7589         dpll = DPLL_VGA_MODE_DIS;
7590
7591         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7592                 dpll |= DPLLB_MODE_LVDS;
7593         else
7594                 dpll |= DPLLB_MODE_DAC_SERIAL;
7595
7596         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7597                 dpll |= (crtc_state->pixel_multiplier - 1)
7598                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7599         }
7600
7601         if (is_sdvo)
7602                 dpll |= DPLL_SDVO_HIGH_SPEED;
7603
7604         if (crtc_state->has_dp_encoder)
7605                 dpll |= DPLL_SDVO_HIGH_SPEED;
7606
7607         /* compute bitmask from p1 value */
7608         if (IS_PINEVIEW(dev))
7609                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7610         else {
7611                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612                 if (IS_G4X(dev) && reduced_clock)
7613                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7614         }
7615         switch (clock->p2) {
7616         case 5:
7617                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7618                 break;
7619         case 7:
7620                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7621                 break;
7622         case 10:
7623                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7624                 break;
7625         case 14:
7626                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7627                 break;
7628         }
7629         if (INTEL_INFO(dev)->gen >= 4)
7630                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7631
7632         if (crtc_state->sdvo_tv_clock)
7633                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7634         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7635                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7636                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7637         else
7638                 dpll |= PLL_REF_INPUT_DREFCLK;
7639
7640         dpll |= DPLL_VCO_ENABLE;
7641         crtc_state->dpll_hw_state.dpll = dpll;
7642
7643         if (INTEL_INFO(dev)->gen >= 4) {
7644                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7645                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7646                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7647         }
7648 }
7649
7650 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7651                               struct intel_crtc_state *crtc_state,
7652                               intel_clock_t *reduced_clock,
7653                               int num_connectors)
7654 {
7655         struct drm_device *dev = crtc->base.dev;
7656         struct drm_i915_private *dev_priv = dev->dev_private;
7657         u32 dpll;
7658         struct dpll *clock = &crtc_state->dpll;
7659
7660         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7661
7662         dpll = DPLL_VGA_MODE_DIS;
7663
7664         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7665                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7666         } else {
7667                 if (clock->p1 == 2)
7668                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7669                 else
7670                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7671                 if (clock->p2 == 4)
7672                         dpll |= PLL_P2_DIVIDE_BY_4;
7673         }
7674
7675         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7676                 dpll |= DPLL_DVO_2X_MODE;
7677
7678         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7679                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7680                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7681         else
7682                 dpll |= PLL_REF_INPUT_DREFCLK;
7683
7684         dpll |= DPLL_VCO_ENABLE;
7685         crtc_state->dpll_hw_state.dpll = dpll;
7686 }
7687
7688 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7689 {
7690         struct drm_device *dev = intel_crtc->base.dev;
7691         struct drm_i915_private *dev_priv = dev->dev_private;
7692         enum pipe pipe = intel_crtc->pipe;
7693         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7694         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7695         uint32_t crtc_vtotal, crtc_vblank_end;
7696         int vsyncshift = 0;
7697
7698         /* We need to be careful not to changed the adjusted mode, for otherwise
7699          * the hw state checker will get angry at the mismatch. */
7700         crtc_vtotal = adjusted_mode->crtc_vtotal;
7701         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7702
7703         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7704                 /* the chip adds 2 halflines automatically */
7705                 crtc_vtotal -= 1;
7706                 crtc_vblank_end -= 1;
7707
7708                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7709                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7710                 else
7711                         vsyncshift = adjusted_mode->crtc_hsync_start -
7712                                 adjusted_mode->crtc_htotal / 2;
7713                 if (vsyncshift < 0)
7714                         vsyncshift += adjusted_mode->crtc_htotal;
7715         }
7716
7717         if (INTEL_INFO(dev)->gen > 3)
7718                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7719
7720         I915_WRITE(HTOTAL(cpu_transcoder),
7721                    (adjusted_mode->crtc_hdisplay - 1) |
7722                    ((adjusted_mode->crtc_htotal - 1) << 16));
7723         I915_WRITE(HBLANK(cpu_transcoder),
7724                    (adjusted_mode->crtc_hblank_start - 1) |
7725                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7726         I915_WRITE(HSYNC(cpu_transcoder),
7727                    (adjusted_mode->crtc_hsync_start - 1) |
7728                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7729
7730         I915_WRITE(VTOTAL(cpu_transcoder),
7731                    (adjusted_mode->crtc_vdisplay - 1) |
7732                    ((crtc_vtotal - 1) << 16));
7733         I915_WRITE(VBLANK(cpu_transcoder),
7734                    (adjusted_mode->crtc_vblank_start - 1) |
7735                    ((crtc_vblank_end - 1) << 16));
7736         I915_WRITE(VSYNC(cpu_transcoder),
7737                    (adjusted_mode->crtc_vsync_start - 1) |
7738                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7739
7740         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7741          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7742          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7743          * bits. */
7744         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7745             (pipe == PIPE_B || pipe == PIPE_C))
7746                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7747
7748         /* pipesrc controls the size that is scaled from, which should
7749          * always be the user's requested size.
7750          */
7751         I915_WRITE(PIPESRC(pipe),
7752                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7753                    (intel_crtc->config->pipe_src_h - 1));
7754 }
7755
7756 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7757                                    struct intel_crtc_state *pipe_config)
7758 {
7759         struct drm_device *dev = crtc->base.dev;
7760         struct drm_i915_private *dev_priv = dev->dev_private;
7761         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7762         uint32_t tmp;
7763
7764         tmp = I915_READ(HTOTAL(cpu_transcoder));
7765         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7766         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7767         tmp = I915_READ(HBLANK(cpu_transcoder));
7768         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7769         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7770         tmp = I915_READ(HSYNC(cpu_transcoder));
7771         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7772         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7773
7774         tmp = I915_READ(VTOTAL(cpu_transcoder));
7775         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7776         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7777         tmp = I915_READ(VBLANK(cpu_transcoder));
7778         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7779         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7780         tmp = I915_READ(VSYNC(cpu_transcoder));
7781         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7782         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7783
7784         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7785                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7786                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7787                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7788         }
7789
7790         tmp = I915_READ(PIPESRC(crtc->pipe));
7791         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7792         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7793
7794         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7795         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7796 }
7797
7798 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7799                                  struct intel_crtc_state *pipe_config)
7800 {
7801         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7802         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7803         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7804         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7805
7806         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7807         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7808         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7809         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7810
7811         mode->flags = pipe_config->base.adjusted_mode.flags;
7812         mode->type = DRM_MODE_TYPE_DRIVER;
7813
7814         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7815         mode->flags |= pipe_config->base.adjusted_mode.flags;
7816
7817         mode->hsync = drm_mode_hsync(mode);
7818         mode->vrefresh = drm_mode_vrefresh(mode);
7819         drm_mode_set_name(mode);
7820 }
7821
7822 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7823 {
7824         struct drm_device *dev = intel_crtc->base.dev;
7825         struct drm_i915_private *dev_priv = dev->dev_private;
7826         uint32_t pipeconf;
7827
7828         pipeconf = 0;
7829
7830         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7831             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7832                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7833
7834         if (intel_crtc->config->double_wide)
7835                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7836
7837         /* only g4x and later have fancy bpc/dither controls */
7838         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7839                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7840                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7841                         pipeconf |= PIPECONF_DITHER_EN |
7842                                     PIPECONF_DITHER_TYPE_SP;
7843
7844                 switch (intel_crtc->config->pipe_bpp) {
7845                 case 18:
7846                         pipeconf |= PIPECONF_6BPC;
7847                         break;
7848                 case 24:
7849                         pipeconf |= PIPECONF_8BPC;
7850                         break;
7851                 case 30:
7852                         pipeconf |= PIPECONF_10BPC;
7853                         break;
7854                 default:
7855                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7856                         BUG();
7857                 }
7858         }
7859
7860         if (HAS_PIPE_CXSR(dev)) {
7861                 if (intel_crtc->lowfreq_avail) {
7862                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7863                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7864                 } else {
7865                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7866                 }
7867         }
7868
7869         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7870                 if (INTEL_INFO(dev)->gen < 4 ||
7871                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7872                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7873                 else
7874                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7875         } else
7876                 pipeconf |= PIPECONF_PROGRESSIVE;
7877
7878         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7879                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7880
7881         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7882         POSTING_READ(PIPECONF(intel_crtc->pipe));
7883 }
7884
7885 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7886                                    struct intel_crtc_state *crtc_state)
7887 {
7888         struct drm_device *dev = crtc->base.dev;
7889         struct drm_i915_private *dev_priv = dev->dev_private;
7890         int refclk, num_connectors = 0;
7891         intel_clock_t clock;
7892         bool ok;
7893         bool is_dsi = false;
7894         struct intel_encoder *encoder;
7895         const intel_limit_t *limit;
7896         struct drm_atomic_state *state = crtc_state->base.state;
7897         struct drm_connector *connector;
7898         struct drm_connector_state *connector_state;
7899         int i;
7900
7901         memset(&crtc_state->dpll_hw_state, 0,
7902                sizeof(crtc_state->dpll_hw_state));
7903
7904         for_each_connector_in_state(state, connector, connector_state, i) {
7905                 if (connector_state->crtc != &crtc->base)
7906                         continue;
7907
7908                 encoder = to_intel_encoder(connector_state->best_encoder);
7909
7910                 switch (encoder->type) {
7911                 case INTEL_OUTPUT_DSI:
7912                         is_dsi = true;
7913                         break;
7914                 default:
7915                         break;
7916                 }
7917
7918                 num_connectors++;
7919         }
7920
7921         if (is_dsi)
7922                 return 0;
7923
7924         if (!crtc_state->clock_set) {
7925                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7926
7927                 /*
7928                  * Returns a set of divisors for the desired target clock with
7929                  * the given refclk, or FALSE.  The returned values represent
7930                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7931                  * 2) / p1 / p2.
7932                  */
7933                 limit = intel_limit(crtc_state, refclk);
7934                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7935                                                  crtc_state->port_clock,
7936                                                  refclk, NULL, &clock);
7937                 if (!ok) {
7938                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939                         return -EINVAL;
7940                 }
7941
7942                 /* Compat-code for transition, will disappear. */
7943                 crtc_state->dpll.n = clock.n;
7944                 crtc_state->dpll.m1 = clock.m1;
7945                 crtc_state->dpll.m2 = clock.m2;
7946                 crtc_state->dpll.p1 = clock.p1;
7947                 crtc_state->dpll.p2 = clock.p2;
7948         }
7949
7950         if (IS_GEN2(dev)) {
7951                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7952                                   num_connectors);
7953         } else if (IS_CHERRYVIEW(dev)) {
7954                 chv_compute_dpll(crtc, crtc_state);
7955         } else if (IS_VALLEYVIEW(dev)) {
7956                 vlv_compute_dpll(crtc, crtc_state);
7957         } else {
7958                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7959                                   num_connectors);
7960         }
7961
7962         return 0;
7963 }
7964
7965 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7966                                  struct intel_crtc_state *pipe_config)
7967 {
7968         struct drm_device *dev = crtc->base.dev;
7969         struct drm_i915_private *dev_priv = dev->dev_private;
7970         uint32_t tmp;
7971
7972         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7973                 return;
7974
7975         tmp = I915_READ(PFIT_CONTROL);
7976         if (!(tmp & PFIT_ENABLE))
7977                 return;
7978
7979         /* Check whether the pfit is attached to our pipe. */
7980         if (INTEL_INFO(dev)->gen < 4) {
7981                 if (crtc->pipe != PIPE_B)
7982                         return;
7983         } else {
7984                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7985                         return;
7986         }
7987
7988         pipe_config->gmch_pfit.control = tmp;
7989         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7990         if (INTEL_INFO(dev)->gen < 5)
7991                 pipe_config->gmch_pfit.lvds_border_bits =
7992                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7993 }
7994
7995 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7996                                struct intel_crtc_state *pipe_config)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         int pipe = pipe_config->cpu_transcoder;
8001         intel_clock_t clock;
8002         u32 mdiv;
8003         int refclk = 100000;
8004
8005         /* In case of MIPI DPLL will not even be used */
8006         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8007                 return;
8008
8009         mutex_lock(&dev_priv->sb_lock);
8010         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8011         mutex_unlock(&dev_priv->sb_lock);
8012
8013         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8014         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8015         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8016         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8017         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8018
8019         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8020 }
8021
8022 static void
8023 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024                               struct intel_initial_plane_config *plane_config)
8025 {
8026         struct drm_device *dev = crtc->base.dev;
8027         struct drm_i915_private *dev_priv = dev->dev_private;
8028         u32 val, base, offset;
8029         int pipe = crtc->pipe, plane = crtc->plane;
8030         int fourcc, pixel_format;
8031         unsigned int aligned_height;
8032         struct drm_framebuffer *fb;
8033         struct intel_framebuffer *intel_fb;
8034
8035         val = I915_READ(DSPCNTR(plane));
8036         if (!(val & DISPLAY_PLANE_ENABLE))
8037                 return;
8038
8039         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8040         if (!intel_fb) {
8041                 DRM_DEBUG_KMS("failed to alloc fb\n");
8042                 return;
8043         }
8044
8045         fb = &intel_fb->base;
8046
8047         if (INTEL_INFO(dev)->gen >= 4) {
8048                 if (val & DISPPLANE_TILED) {
8049                         plane_config->tiling = I915_TILING_X;
8050                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8051                 }
8052         }
8053
8054         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8055         fourcc = i9xx_format_to_fourcc(pixel_format);
8056         fb->pixel_format = fourcc;
8057         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8058
8059         if (INTEL_INFO(dev)->gen >= 4) {
8060                 if (plane_config->tiling)
8061                         offset = I915_READ(DSPTILEOFF(plane));
8062                 else
8063                         offset = I915_READ(DSPLINOFF(plane));
8064                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8065         } else {
8066                 base = I915_READ(DSPADDR(plane));
8067         }
8068         plane_config->base = base;
8069
8070         val = I915_READ(PIPESRC(pipe));
8071         fb->width = ((val >> 16) & 0xfff) + 1;
8072         fb->height = ((val >> 0) & 0xfff) + 1;
8073
8074         val = I915_READ(DSPSTRIDE(pipe));
8075         fb->pitches[0] = val & 0xffffffc0;
8076
8077         aligned_height = intel_fb_align_height(dev, fb->height,
8078                                                fb->pixel_format,
8079                                                fb->modifier[0]);
8080
8081         plane_config->size = fb->pitches[0] * aligned_height;
8082
8083         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084                       pipe_name(pipe), plane, fb->width, fb->height,
8085                       fb->bits_per_pixel, base, fb->pitches[0],
8086                       plane_config->size);
8087
8088         plane_config->fb = intel_fb;
8089 }
8090
8091 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8092                                struct intel_crtc_state *pipe_config)
8093 {
8094         struct drm_device *dev = crtc->base.dev;
8095         struct drm_i915_private *dev_priv = dev->dev_private;
8096         int pipe = pipe_config->cpu_transcoder;
8097         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098         intel_clock_t clock;
8099         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8100         int refclk = 100000;
8101
8102         mutex_lock(&dev_priv->sb_lock);
8103         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8104         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8105         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8106         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8107         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8108         mutex_unlock(&dev_priv->sb_lock);
8109
8110         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8111         clock.m2 = (pll_dw0 & 0xff) << 22;
8112         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8113                 clock.m2 |= pll_dw2 & 0x3fffff;
8114         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8115         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8116         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8117
8118         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8119 }
8120
8121 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8122                                  struct intel_crtc_state *pipe_config)
8123 {
8124         struct drm_device *dev = crtc->base.dev;
8125         struct drm_i915_private *dev_priv = dev->dev_private;
8126         uint32_t tmp;
8127
8128         if (!intel_display_power_is_enabled(dev_priv,
8129                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8130                 return false;
8131
8132         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8133         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8134
8135         tmp = I915_READ(PIPECONF(crtc->pipe));
8136         if (!(tmp & PIPECONF_ENABLE))
8137                 return false;
8138
8139         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8140                 switch (tmp & PIPECONF_BPC_MASK) {
8141                 case PIPECONF_6BPC:
8142                         pipe_config->pipe_bpp = 18;
8143                         break;
8144                 case PIPECONF_8BPC:
8145                         pipe_config->pipe_bpp = 24;
8146                         break;
8147                 case PIPECONF_10BPC:
8148                         pipe_config->pipe_bpp = 30;
8149                         break;
8150                 default:
8151                         break;
8152                 }
8153         }
8154
8155         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8156                 pipe_config->limited_color_range = true;
8157
8158         if (INTEL_INFO(dev)->gen < 4)
8159                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8160
8161         intel_get_pipe_timings(crtc, pipe_config);
8162
8163         i9xx_get_pfit_config(crtc, pipe_config);
8164
8165         if (INTEL_INFO(dev)->gen >= 4) {
8166                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8167                 pipe_config->pixel_multiplier =
8168                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8169                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8170                 pipe_config->dpll_hw_state.dpll_md = tmp;
8171         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8172                 tmp = I915_READ(DPLL(crtc->pipe));
8173                 pipe_config->pixel_multiplier =
8174                         ((tmp & SDVO_MULTIPLIER_MASK)
8175                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8176         } else {
8177                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8178                  * port and will be fixed up in the encoder->get_config
8179                  * function. */
8180                 pipe_config->pixel_multiplier = 1;
8181         }
8182         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8183         if (!IS_VALLEYVIEW(dev)) {
8184                 /*
8185                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8186                  * on 830. Filter it out here so that we don't
8187                  * report errors due to that.
8188                  */
8189                 if (IS_I830(dev))
8190                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8191
8192                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8193                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8194         } else {
8195                 /* Mask out read-only status bits. */
8196                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8197                                                      DPLL_PORTC_READY_MASK |
8198                                                      DPLL_PORTB_READY_MASK);
8199         }
8200
8201         if (IS_CHERRYVIEW(dev))
8202                 chv_crtc_clock_get(crtc, pipe_config);
8203         else if (IS_VALLEYVIEW(dev))
8204                 vlv_crtc_clock_get(crtc, pipe_config);
8205         else
8206                 i9xx_crtc_clock_get(crtc, pipe_config);
8207
8208         /*
8209          * Normally the dotclock is filled in by the encoder .get_config()
8210          * but in case the pipe is enabled w/o any ports we need a sane
8211          * default.
8212          */
8213         pipe_config->base.adjusted_mode.crtc_clock =
8214                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8215
8216         return true;
8217 }
8218
8219 static void ironlake_init_pch_refclk(struct drm_device *dev)
8220 {
8221         struct drm_i915_private *dev_priv = dev->dev_private;
8222         struct intel_encoder *encoder;
8223         u32 val, final;
8224         bool has_lvds = false;
8225         bool has_cpu_edp = false;
8226         bool has_panel = false;
8227         bool has_ck505 = false;
8228         bool can_ssc = false;
8229
8230         /* We need to take the global config into account */
8231         for_each_intel_encoder(dev, encoder) {
8232                 switch (encoder->type) {
8233                 case INTEL_OUTPUT_LVDS:
8234                         has_panel = true;
8235                         has_lvds = true;
8236                         break;
8237                 case INTEL_OUTPUT_EDP:
8238                         has_panel = true;
8239                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8240                                 has_cpu_edp = true;
8241                         break;
8242                 default:
8243                         break;
8244                 }
8245         }
8246
8247         if (HAS_PCH_IBX(dev)) {
8248                 has_ck505 = dev_priv->vbt.display_clock_mode;
8249                 can_ssc = has_ck505;
8250         } else {
8251                 has_ck505 = false;
8252                 can_ssc = true;
8253         }
8254
8255         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8256                       has_panel, has_lvds, has_ck505);
8257
8258         /* Ironlake: try to setup display ref clock before DPLL
8259          * enabling. This is only under driver's control after
8260          * PCH B stepping, previous chipset stepping should be
8261          * ignoring this setting.
8262          */
8263         val = I915_READ(PCH_DREF_CONTROL);
8264
8265         /* As we must carefully and slowly disable/enable each source in turn,
8266          * compute the final state we want first and check if we need to
8267          * make any changes at all.
8268          */
8269         final = val;
8270         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8271         if (has_ck505)
8272                 final |= DREF_NONSPREAD_CK505_ENABLE;
8273         else
8274                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8275
8276         final &= ~DREF_SSC_SOURCE_MASK;
8277         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8278         final &= ~DREF_SSC1_ENABLE;
8279
8280         if (has_panel) {
8281                 final |= DREF_SSC_SOURCE_ENABLE;
8282
8283                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8284                         final |= DREF_SSC1_ENABLE;
8285
8286                 if (has_cpu_edp) {
8287                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8288                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8289                         else
8290                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8291                 } else
8292                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8293         } else {
8294                 final |= DREF_SSC_SOURCE_DISABLE;
8295                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8296         }
8297
8298         if (final == val)
8299                 return;
8300
8301         /* Always enable nonspread source */
8302         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8303
8304         if (has_ck505)
8305                 val |= DREF_NONSPREAD_CK505_ENABLE;
8306         else
8307                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8308
8309         if (has_panel) {
8310                 val &= ~DREF_SSC_SOURCE_MASK;
8311                 val |= DREF_SSC_SOURCE_ENABLE;
8312
8313                 /* SSC must be turned on before enabling the CPU output  */
8314                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8315                         DRM_DEBUG_KMS("Using SSC on panel\n");
8316                         val |= DREF_SSC1_ENABLE;
8317                 } else
8318                         val &= ~DREF_SSC1_ENABLE;
8319
8320                 /* Get SSC going before enabling the outputs */
8321                 I915_WRITE(PCH_DREF_CONTROL, val);
8322                 POSTING_READ(PCH_DREF_CONTROL);
8323                 udelay(200);
8324
8325                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8326
8327                 /* Enable CPU source on CPU attached eDP */
8328                 if (has_cpu_edp) {
8329                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8330                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8331                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8332                         } else
8333                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8334                 } else
8335                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8336
8337                 I915_WRITE(PCH_DREF_CONTROL, val);
8338                 POSTING_READ(PCH_DREF_CONTROL);
8339                 udelay(200);
8340         } else {
8341                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8342
8343                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8344
8345                 /* Turn off CPU output */
8346                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8347
8348                 I915_WRITE(PCH_DREF_CONTROL, val);
8349                 POSTING_READ(PCH_DREF_CONTROL);
8350                 udelay(200);
8351
8352                 /* Turn off the SSC source */
8353                 val &= ~DREF_SSC_SOURCE_MASK;
8354                 val |= DREF_SSC_SOURCE_DISABLE;
8355
8356                 /* Turn off SSC1 */
8357                 val &= ~DREF_SSC1_ENABLE;
8358
8359                 I915_WRITE(PCH_DREF_CONTROL, val);
8360                 POSTING_READ(PCH_DREF_CONTROL);
8361                 udelay(200);
8362         }
8363
8364         BUG_ON(val != final);
8365 }
8366
8367 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8368 {
8369         uint32_t tmp;
8370
8371         tmp = I915_READ(SOUTH_CHICKEN2);
8372         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8373         I915_WRITE(SOUTH_CHICKEN2, tmp);
8374
8375         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8376                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8377                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8378
8379         tmp = I915_READ(SOUTH_CHICKEN2);
8380         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8381         I915_WRITE(SOUTH_CHICKEN2, tmp);
8382
8383         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8384                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8385                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8386 }
8387
8388 /* WaMPhyProgramming:hsw */
8389 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8390 {
8391         uint32_t tmp;
8392
8393         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8394         tmp &= ~(0xFF << 24);
8395         tmp |= (0x12 << 24);
8396         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8397
8398         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8399         tmp |= (1 << 11);
8400         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8403         tmp |= (1 << 11);
8404         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8405
8406         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8407         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8408         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8409
8410         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8411         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8412         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8413
8414         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8415         tmp &= ~(7 << 13);
8416         tmp |= (5 << 13);
8417         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8418
8419         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8420         tmp &= ~(7 << 13);
8421         tmp |= (5 << 13);
8422         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8423
8424         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8425         tmp &= ~0xFF;
8426         tmp |= 0x1C;
8427         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8428
8429         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8430         tmp &= ~0xFF;
8431         tmp |= 0x1C;
8432         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8435         tmp &= ~(0xFF << 16);
8436         tmp |= (0x1C << 16);
8437         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8438
8439         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8440         tmp &= ~(0xFF << 16);
8441         tmp |= (0x1C << 16);
8442         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8443
8444         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8445         tmp |= (1 << 27);
8446         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8449         tmp |= (1 << 27);
8450         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8451
8452         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8453         tmp &= ~(0xF << 28);
8454         tmp |= (4 << 28);
8455         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8456
8457         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8458         tmp &= ~(0xF << 28);
8459         tmp |= (4 << 28);
8460         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8461 }
8462
8463 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8464  * Programming" based on the parameters passed:
8465  * - Sequence to enable CLKOUT_DP
8466  * - Sequence to enable CLKOUT_DP without spread
8467  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8468  */
8469 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8470                                  bool with_fdi)
8471 {
8472         struct drm_i915_private *dev_priv = dev->dev_private;
8473         uint32_t reg, tmp;
8474
8475         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8476                 with_spread = true;
8477         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8478                 with_fdi = false;
8479
8480         mutex_lock(&dev_priv->sb_lock);
8481
8482         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8483         tmp &= ~SBI_SSCCTL_DISABLE;
8484         tmp |= SBI_SSCCTL_PATHALT;
8485         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8486
8487         udelay(24);
8488
8489         if (with_spread) {
8490                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8491                 tmp &= ~SBI_SSCCTL_PATHALT;
8492                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8493
8494                 if (with_fdi) {
8495                         lpt_reset_fdi_mphy(dev_priv);
8496                         lpt_program_fdi_mphy(dev_priv);
8497                 }
8498         }
8499
8500         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8501         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8502         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8503         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8504
8505         mutex_unlock(&dev_priv->sb_lock);
8506 }
8507
8508 /* Sequence to disable CLKOUT_DP */
8509 static void lpt_disable_clkout_dp(struct drm_device *dev)
8510 {
8511         struct drm_i915_private *dev_priv = dev->dev_private;
8512         uint32_t reg, tmp;
8513
8514         mutex_lock(&dev_priv->sb_lock);
8515
8516         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8517         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8518         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8519         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8520
8521         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8522         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8523                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8524                         tmp |= SBI_SSCCTL_PATHALT;
8525                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8526                         udelay(32);
8527                 }
8528                 tmp |= SBI_SSCCTL_DISABLE;
8529                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8530         }
8531
8532         mutex_unlock(&dev_priv->sb_lock);
8533 }
8534
8535 static void lpt_init_pch_refclk(struct drm_device *dev)
8536 {
8537         struct intel_encoder *encoder;
8538         bool has_vga = false;
8539
8540         for_each_intel_encoder(dev, encoder) {
8541                 switch (encoder->type) {
8542                 case INTEL_OUTPUT_ANALOG:
8543                         has_vga = true;
8544                         break;
8545                 default:
8546                         break;
8547                 }
8548         }
8549
8550         if (has_vga)
8551                 lpt_enable_clkout_dp(dev, true, true);
8552         else
8553                 lpt_disable_clkout_dp(dev);
8554 }
8555
8556 /*
8557  * Initialize reference clocks when the driver loads
8558  */
8559 void intel_init_pch_refclk(struct drm_device *dev)
8560 {
8561         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8562                 ironlake_init_pch_refclk(dev);
8563         else if (HAS_PCH_LPT(dev))
8564                 lpt_init_pch_refclk(dev);
8565 }
8566
8567 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8568 {
8569         struct drm_device *dev = crtc_state->base.crtc->dev;
8570         struct drm_i915_private *dev_priv = dev->dev_private;
8571         struct drm_atomic_state *state = crtc_state->base.state;
8572         struct drm_connector *connector;
8573         struct drm_connector_state *connector_state;
8574         struct intel_encoder *encoder;
8575         int num_connectors = 0, i;
8576         bool is_lvds = false;
8577
8578         for_each_connector_in_state(state, connector, connector_state, i) {
8579                 if (connector_state->crtc != crtc_state->base.crtc)
8580                         continue;
8581
8582                 encoder = to_intel_encoder(connector_state->best_encoder);
8583
8584                 switch (encoder->type) {
8585                 case INTEL_OUTPUT_LVDS:
8586                         is_lvds = true;
8587                         break;
8588                 default:
8589                         break;
8590                 }
8591                 num_connectors++;
8592         }
8593
8594         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8595                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8596                               dev_priv->vbt.lvds_ssc_freq);
8597                 return dev_priv->vbt.lvds_ssc_freq;
8598         }
8599
8600         return 120000;
8601 }
8602
8603 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8604 {
8605         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8607         int pipe = intel_crtc->pipe;
8608         uint32_t val;
8609
8610         val = 0;
8611
8612         switch (intel_crtc->config->pipe_bpp) {
8613         case 18:
8614                 val |= PIPECONF_6BPC;
8615                 break;
8616         case 24:
8617                 val |= PIPECONF_8BPC;
8618                 break;
8619         case 30:
8620                 val |= PIPECONF_10BPC;
8621                 break;
8622         case 36:
8623                 val |= PIPECONF_12BPC;
8624                 break;
8625         default:
8626                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8627                 BUG();
8628         }
8629
8630         if (intel_crtc->config->dither)
8631                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8632
8633         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8634                 val |= PIPECONF_INTERLACED_ILK;
8635         else
8636                 val |= PIPECONF_PROGRESSIVE;
8637
8638         if (intel_crtc->config->limited_color_range)
8639                 val |= PIPECONF_COLOR_RANGE_SELECT;
8640
8641         I915_WRITE(PIPECONF(pipe), val);
8642         POSTING_READ(PIPECONF(pipe));
8643 }
8644
8645 /*
8646  * Set up the pipe CSC unit.
8647  *
8648  * Currently only full range RGB to limited range RGB conversion
8649  * is supported, but eventually this should handle various
8650  * RGB<->YCbCr scenarios as well.
8651  */
8652 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8653 {
8654         struct drm_device *dev = crtc->dev;
8655         struct drm_i915_private *dev_priv = dev->dev_private;
8656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8657         int pipe = intel_crtc->pipe;
8658         uint16_t coeff = 0x7800; /* 1.0 */
8659
8660         /*
8661          * TODO: Check what kind of values actually come out of the pipe
8662          * with these coeff/postoff values and adjust to get the best
8663          * accuracy. Perhaps we even need to take the bpc value into
8664          * consideration.
8665          */
8666
8667         if (intel_crtc->config->limited_color_range)
8668                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8669
8670         /*
8671          * GY/GU and RY/RU should be the other way around according
8672          * to BSpec, but reality doesn't agree. Just set them up in
8673          * a way that results in the correct picture.
8674          */
8675         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8676         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8677
8678         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8679         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8680
8681         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8682         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8683
8684         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8685         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8686         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8687
8688         if (INTEL_INFO(dev)->gen > 6) {
8689                 uint16_t postoff = 0;
8690
8691                 if (intel_crtc->config->limited_color_range)
8692                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8693
8694                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8695                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8696                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8697
8698                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8699         } else {
8700                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8701
8702                 if (intel_crtc->config->limited_color_range)
8703                         mode |= CSC_BLACK_SCREEN_OFFSET;
8704
8705                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8706         }
8707 }
8708
8709 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8710 {
8711         struct drm_device *dev = crtc->dev;
8712         struct drm_i915_private *dev_priv = dev->dev_private;
8713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8714         enum pipe pipe = intel_crtc->pipe;
8715         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8716         uint32_t val;
8717
8718         val = 0;
8719
8720         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8721                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8722
8723         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8724                 val |= PIPECONF_INTERLACED_ILK;
8725         else
8726                 val |= PIPECONF_PROGRESSIVE;
8727
8728         I915_WRITE(PIPECONF(cpu_transcoder), val);
8729         POSTING_READ(PIPECONF(cpu_transcoder));
8730
8731         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8732         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8733
8734         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8735                 val = 0;
8736
8737                 switch (intel_crtc->config->pipe_bpp) {
8738                 case 18:
8739                         val |= PIPEMISC_DITHER_6_BPC;
8740                         break;
8741                 case 24:
8742                         val |= PIPEMISC_DITHER_8_BPC;
8743                         break;
8744                 case 30:
8745                         val |= PIPEMISC_DITHER_10_BPC;
8746                         break;
8747                 case 36:
8748                         val |= PIPEMISC_DITHER_12_BPC;
8749                         break;
8750                 default:
8751                         /* Case prevented by pipe_config_set_bpp. */
8752                         BUG();
8753                 }
8754
8755                 if (intel_crtc->config->dither)
8756                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8757
8758                 I915_WRITE(PIPEMISC(pipe), val);
8759         }
8760 }
8761
8762 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8763                                     struct intel_crtc_state *crtc_state,
8764                                     intel_clock_t *clock,
8765                                     bool *has_reduced_clock,
8766                                     intel_clock_t *reduced_clock)
8767 {
8768         struct drm_device *dev = crtc->dev;
8769         struct drm_i915_private *dev_priv = dev->dev_private;
8770         int refclk;
8771         const intel_limit_t *limit;
8772         bool ret;
8773
8774         refclk = ironlake_get_refclk(crtc_state);
8775
8776         /*
8777          * Returns a set of divisors for the desired target clock with the given
8778          * refclk, or FALSE.  The returned values represent the clock equation:
8779          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8780          */
8781         limit = intel_limit(crtc_state, refclk);
8782         ret = dev_priv->display.find_dpll(limit, crtc_state,
8783                                           crtc_state->port_clock,
8784                                           refclk, NULL, clock);
8785         if (!ret)
8786                 return false;
8787
8788         return true;
8789 }
8790
8791 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8792 {
8793         /*
8794          * Account for spread spectrum to avoid
8795          * oversubscribing the link. Max center spread
8796          * is 2.5%; use 5% for safety's sake.
8797          */
8798         u32 bps = target_clock * bpp * 21 / 20;
8799         return DIV_ROUND_UP(bps, link_bw * 8);
8800 }
8801
8802 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8803 {
8804         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8805 }
8806
8807 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8808                                       struct intel_crtc_state *crtc_state,
8809                                       u32 *fp,
8810                                       intel_clock_t *reduced_clock, u32 *fp2)
8811 {
8812         struct drm_crtc *crtc = &intel_crtc->base;
8813         struct drm_device *dev = crtc->dev;
8814         struct drm_i915_private *dev_priv = dev->dev_private;
8815         struct drm_atomic_state *state = crtc_state->base.state;
8816         struct drm_connector *connector;
8817         struct drm_connector_state *connector_state;
8818         struct intel_encoder *encoder;
8819         uint32_t dpll;
8820         int factor, num_connectors = 0, i;
8821         bool is_lvds = false, is_sdvo = false;
8822
8823         for_each_connector_in_state(state, connector, connector_state, i) {
8824                 if (connector_state->crtc != crtc_state->base.crtc)
8825                         continue;
8826
8827                 encoder = to_intel_encoder(connector_state->best_encoder);
8828
8829                 switch (encoder->type) {
8830                 case INTEL_OUTPUT_LVDS:
8831                         is_lvds = true;
8832                         break;
8833                 case INTEL_OUTPUT_SDVO:
8834                 case INTEL_OUTPUT_HDMI:
8835                         is_sdvo = true;
8836                         break;
8837                 default:
8838                         break;
8839                 }
8840
8841                 num_connectors++;
8842         }
8843
8844         /* Enable autotuning of the PLL clock (if permissible) */
8845         factor = 21;
8846         if (is_lvds) {
8847                 if ((intel_panel_use_ssc(dev_priv) &&
8848                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8849                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8850                         factor = 25;
8851         } else if (crtc_state->sdvo_tv_clock)
8852                 factor = 20;
8853
8854         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8855                 *fp |= FP_CB_TUNE;
8856
8857         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8858                 *fp2 |= FP_CB_TUNE;
8859
8860         dpll = 0;
8861
8862         if (is_lvds)
8863                 dpll |= DPLLB_MODE_LVDS;
8864         else
8865                 dpll |= DPLLB_MODE_DAC_SERIAL;
8866
8867         dpll |= (crtc_state->pixel_multiplier - 1)
8868                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8869
8870         if (is_sdvo)
8871                 dpll |= DPLL_SDVO_HIGH_SPEED;
8872         if (crtc_state->has_dp_encoder)
8873                 dpll |= DPLL_SDVO_HIGH_SPEED;
8874
8875         /* compute bitmask from p1 value */
8876         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8877         /* also FPA1 */
8878         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8879
8880         switch (crtc_state->dpll.p2) {
8881         case 5:
8882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8883                 break;
8884         case 7:
8885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8886                 break;
8887         case 10:
8888                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8889                 break;
8890         case 14:
8891                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8892                 break;
8893         }
8894
8895         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8896                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8897         else
8898                 dpll |= PLL_REF_INPUT_DREFCLK;
8899
8900         return dpll | DPLL_VCO_ENABLE;
8901 }
8902
8903 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8904                                        struct intel_crtc_state *crtc_state)
8905 {
8906         struct drm_device *dev = crtc->base.dev;
8907         intel_clock_t clock, reduced_clock;
8908         u32 dpll = 0, fp = 0, fp2 = 0;
8909         bool ok, has_reduced_clock = false;
8910         bool is_lvds = false;
8911         struct intel_shared_dpll *pll;
8912
8913         memset(&crtc_state->dpll_hw_state, 0,
8914                sizeof(crtc_state->dpll_hw_state));
8915
8916         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8917
8918         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8919              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8920
8921         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8922                                      &has_reduced_clock, &reduced_clock);
8923         if (!ok && !crtc_state->clock_set) {
8924                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8925                 return -EINVAL;
8926         }
8927         /* Compat-code for transition, will disappear. */
8928         if (!crtc_state->clock_set) {
8929                 crtc_state->dpll.n = clock.n;
8930                 crtc_state->dpll.m1 = clock.m1;
8931                 crtc_state->dpll.m2 = clock.m2;
8932                 crtc_state->dpll.p1 = clock.p1;
8933                 crtc_state->dpll.p2 = clock.p2;
8934         }
8935
8936         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8937         if (crtc_state->has_pch_encoder) {
8938                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8939                 if (has_reduced_clock)
8940                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8941
8942                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8943                                              &fp, &reduced_clock,
8944                                              has_reduced_clock ? &fp2 : NULL);
8945
8946                 crtc_state->dpll_hw_state.dpll = dpll;
8947                 crtc_state->dpll_hw_state.fp0 = fp;
8948                 if (has_reduced_clock)
8949                         crtc_state->dpll_hw_state.fp1 = fp2;
8950                 else
8951                         crtc_state->dpll_hw_state.fp1 = fp;
8952
8953                 pll = intel_get_shared_dpll(crtc, crtc_state);
8954                 if (pll == NULL) {
8955                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8956                                          pipe_name(crtc->pipe));
8957                         return -EINVAL;
8958                 }
8959         }
8960
8961         if (is_lvds && has_reduced_clock)
8962                 crtc->lowfreq_avail = true;
8963         else
8964                 crtc->lowfreq_avail = false;
8965
8966         return 0;
8967 }
8968
8969 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8970                                          struct intel_link_m_n *m_n)
8971 {
8972         struct drm_device *dev = crtc->base.dev;
8973         struct drm_i915_private *dev_priv = dev->dev_private;
8974         enum pipe pipe = crtc->pipe;
8975
8976         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8977         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8978         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8979                 & ~TU_SIZE_MASK;
8980         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8981         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8982                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8983 }
8984
8985 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8986                                          enum transcoder transcoder,
8987                                          struct intel_link_m_n *m_n,
8988                                          struct intel_link_m_n *m2_n2)
8989 {
8990         struct drm_device *dev = crtc->base.dev;
8991         struct drm_i915_private *dev_priv = dev->dev_private;
8992         enum pipe pipe = crtc->pipe;
8993
8994         if (INTEL_INFO(dev)->gen >= 5) {
8995                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8996                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8997                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8998                         & ~TU_SIZE_MASK;
8999                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9000                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9001                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9002                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9003                  * gen < 8) and if DRRS is supported (to make sure the
9004                  * registers are not unnecessarily read).
9005                  */
9006                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9007                         crtc->config->has_drrs) {
9008                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9009                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9010                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9011                                         & ~TU_SIZE_MASK;
9012                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9013                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9014                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9015                 }
9016         } else {
9017                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9018                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9019                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9020                         & ~TU_SIZE_MASK;
9021                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9022                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9023                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9024         }
9025 }
9026
9027 void intel_dp_get_m_n(struct intel_crtc *crtc,
9028                       struct intel_crtc_state *pipe_config)
9029 {
9030         if (pipe_config->has_pch_encoder)
9031                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9032         else
9033                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9034                                              &pipe_config->dp_m_n,
9035                                              &pipe_config->dp_m2_n2);
9036 }
9037
9038 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9039                                         struct intel_crtc_state *pipe_config)
9040 {
9041         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9042                                      &pipe_config->fdi_m_n, NULL);
9043 }
9044
9045 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9046                                     struct intel_crtc_state *pipe_config)
9047 {
9048         struct drm_device *dev = crtc->base.dev;
9049         struct drm_i915_private *dev_priv = dev->dev_private;
9050         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9051         uint32_t ps_ctrl = 0;
9052         int id = -1;
9053         int i;
9054
9055         /* find scaler attached to this pipe */
9056         for (i = 0; i < crtc->num_scalers; i++) {
9057                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9058                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9059                         id = i;
9060                         pipe_config->pch_pfit.enabled = true;
9061                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9062                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9063                         break;
9064                 }
9065         }
9066
9067         scaler_state->scaler_id = id;
9068         if (id >= 0) {
9069                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9070         } else {
9071                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9072         }
9073 }
9074
9075 static void
9076 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9077                                  struct intel_initial_plane_config *plane_config)
9078 {
9079         struct drm_device *dev = crtc->base.dev;
9080         struct drm_i915_private *dev_priv = dev->dev_private;
9081         u32 val, base, offset, stride_mult, tiling;
9082         int pipe = crtc->pipe;
9083         int fourcc, pixel_format;
9084         unsigned int aligned_height;
9085         struct drm_framebuffer *fb;
9086         struct intel_framebuffer *intel_fb;
9087
9088         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9089         if (!intel_fb) {
9090                 DRM_DEBUG_KMS("failed to alloc fb\n");
9091                 return;
9092         }
9093
9094         fb = &intel_fb->base;
9095
9096         val = I915_READ(PLANE_CTL(pipe, 0));
9097         if (!(val & PLANE_CTL_ENABLE))
9098                 goto error;
9099
9100         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9101         fourcc = skl_format_to_fourcc(pixel_format,
9102                                       val & PLANE_CTL_ORDER_RGBX,
9103                                       val & PLANE_CTL_ALPHA_MASK);
9104         fb->pixel_format = fourcc;
9105         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9106
9107         tiling = val & PLANE_CTL_TILED_MASK;
9108         switch (tiling) {
9109         case PLANE_CTL_TILED_LINEAR:
9110                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9111                 break;
9112         case PLANE_CTL_TILED_X:
9113                 plane_config->tiling = I915_TILING_X;
9114                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9115                 break;
9116         case PLANE_CTL_TILED_Y:
9117                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9118                 break;
9119         case PLANE_CTL_TILED_YF:
9120                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9121                 break;
9122         default:
9123                 MISSING_CASE(tiling);
9124                 goto error;
9125         }
9126
9127         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9128         plane_config->base = base;
9129
9130         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9131
9132         val = I915_READ(PLANE_SIZE(pipe, 0));
9133         fb->height = ((val >> 16) & 0xfff) + 1;
9134         fb->width = ((val >> 0) & 0x1fff) + 1;
9135
9136         val = I915_READ(PLANE_STRIDE(pipe, 0));
9137         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9138                                                 fb->pixel_format);
9139         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9140
9141         aligned_height = intel_fb_align_height(dev, fb->height,
9142                                                fb->pixel_format,
9143                                                fb->modifier[0]);
9144
9145         plane_config->size = fb->pitches[0] * aligned_height;
9146
9147         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9148                       pipe_name(pipe), fb->width, fb->height,
9149                       fb->bits_per_pixel, base, fb->pitches[0],
9150                       plane_config->size);
9151
9152         plane_config->fb = intel_fb;
9153         return;
9154
9155 error:
9156         kfree(fb);
9157 }
9158
9159 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9160                                      struct intel_crtc_state *pipe_config)
9161 {
9162         struct drm_device *dev = crtc->base.dev;
9163         struct drm_i915_private *dev_priv = dev->dev_private;
9164         uint32_t tmp;
9165
9166         tmp = I915_READ(PF_CTL(crtc->pipe));
9167
9168         if (tmp & PF_ENABLE) {
9169                 pipe_config->pch_pfit.enabled = true;
9170                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9171                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9172
9173                 /* We currently do not free assignements of panel fitters on
9174                  * ivb/hsw (since we don't use the higher upscaling modes which
9175                  * differentiates them) so just WARN about this case for now. */
9176                 if (IS_GEN7(dev)) {
9177                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9178                                 PF_PIPE_SEL_IVB(crtc->pipe));
9179                 }
9180         }
9181 }
9182
9183 static void
9184 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9185                                   struct intel_initial_plane_config *plane_config)
9186 {
9187         struct drm_device *dev = crtc->base.dev;
9188         struct drm_i915_private *dev_priv = dev->dev_private;
9189         u32 val, base, offset;
9190         int pipe = crtc->pipe;
9191         int fourcc, pixel_format;
9192         unsigned int aligned_height;
9193         struct drm_framebuffer *fb;
9194         struct intel_framebuffer *intel_fb;
9195
9196         val = I915_READ(DSPCNTR(pipe));
9197         if (!(val & DISPLAY_PLANE_ENABLE))
9198                 return;
9199
9200         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9201         if (!intel_fb) {
9202                 DRM_DEBUG_KMS("failed to alloc fb\n");
9203                 return;
9204         }
9205
9206         fb = &intel_fb->base;
9207
9208         if (INTEL_INFO(dev)->gen >= 4) {
9209                 if (val & DISPPLANE_TILED) {
9210                         plane_config->tiling = I915_TILING_X;
9211                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9212                 }
9213         }
9214
9215         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9216         fourcc = i9xx_format_to_fourcc(pixel_format);
9217         fb->pixel_format = fourcc;
9218         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9219
9220         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9221         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9222                 offset = I915_READ(DSPOFFSET(pipe));
9223         } else {
9224                 if (plane_config->tiling)
9225                         offset = I915_READ(DSPTILEOFF(pipe));
9226                 else
9227                         offset = I915_READ(DSPLINOFF(pipe));
9228         }
9229         plane_config->base = base;
9230
9231         val = I915_READ(PIPESRC(pipe));
9232         fb->width = ((val >> 16) & 0xfff) + 1;
9233         fb->height = ((val >> 0) & 0xfff) + 1;
9234
9235         val = I915_READ(DSPSTRIDE(pipe));
9236         fb->pitches[0] = val & 0xffffffc0;
9237
9238         aligned_height = intel_fb_align_height(dev, fb->height,
9239                                                fb->pixel_format,
9240                                                fb->modifier[0]);
9241
9242         plane_config->size = fb->pitches[0] * aligned_height;
9243
9244         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9245                       pipe_name(pipe), fb->width, fb->height,
9246                       fb->bits_per_pixel, base, fb->pitches[0],
9247                       plane_config->size);
9248
9249         plane_config->fb = intel_fb;
9250 }
9251
9252 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9253                                      struct intel_crtc_state *pipe_config)
9254 {
9255         struct drm_device *dev = crtc->base.dev;
9256         struct drm_i915_private *dev_priv = dev->dev_private;
9257         uint32_t tmp;
9258
9259         if (!intel_display_power_is_enabled(dev_priv,
9260                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9261                 return false;
9262
9263         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9264         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9265
9266         tmp = I915_READ(PIPECONF(crtc->pipe));
9267         if (!(tmp & PIPECONF_ENABLE))
9268                 return false;
9269
9270         switch (tmp & PIPECONF_BPC_MASK) {
9271         case PIPECONF_6BPC:
9272                 pipe_config->pipe_bpp = 18;
9273                 break;
9274         case PIPECONF_8BPC:
9275                 pipe_config->pipe_bpp = 24;
9276                 break;
9277         case PIPECONF_10BPC:
9278                 pipe_config->pipe_bpp = 30;
9279                 break;
9280         case PIPECONF_12BPC:
9281                 pipe_config->pipe_bpp = 36;
9282                 break;
9283         default:
9284                 break;
9285         }
9286
9287         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9288                 pipe_config->limited_color_range = true;
9289
9290         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9291                 struct intel_shared_dpll *pll;
9292
9293                 pipe_config->has_pch_encoder = true;
9294
9295                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9296                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9297                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9298
9299                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9300
9301                 if (HAS_PCH_IBX(dev_priv->dev)) {
9302                         pipe_config->shared_dpll =
9303                                 (enum intel_dpll_id) crtc->pipe;
9304                 } else {
9305                         tmp = I915_READ(PCH_DPLL_SEL);
9306                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9307                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9308                         else
9309                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9310                 }
9311
9312                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9313
9314                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9315                                            &pipe_config->dpll_hw_state));
9316
9317                 tmp = pipe_config->dpll_hw_state.dpll;
9318                 pipe_config->pixel_multiplier =
9319                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9320                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9321
9322                 ironlake_pch_clock_get(crtc, pipe_config);
9323         } else {
9324                 pipe_config->pixel_multiplier = 1;
9325         }
9326
9327         intel_get_pipe_timings(crtc, pipe_config);
9328
9329         ironlake_get_pfit_config(crtc, pipe_config);
9330
9331         return true;
9332 }
9333
9334 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9335 {
9336         struct drm_device *dev = dev_priv->dev;
9337         struct intel_crtc *crtc;
9338
9339         for_each_intel_crtc(dev, crtc)
9340                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9341                      pipe_name(crtc->pipe));
9342
9343         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9344         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9345         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9346         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9347         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9348         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9349              "CPU PWM1 enabled\n");
9350         if (IS_HASWELL(dev))
9351                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9352                      "CPU PWM2 enabled\n");
9353         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9354              "PCH PWM1 enabled\n");
9355         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9356              "Utility pin enabled\n");
9357         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9358
9359         /*
9360          * In theory we can still leave IRQs enabled, as long as only the HPD
9361          * interrupts remain enabled. We used to check for that, but since it's
9362          * gen-specific and since we only disable LCPLL after we fully disable
9363          * the interrupts, the check below should be enough.
9364          */
9365         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9366 }
9367
9368 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9369 {
9370         struct drm_device *dev = dev_priv->dev;
9371
9372         if (IS_HASWELL(dev))
9373                 return I915_READ(D_COMP_HSW);
9374         else
9375                 return I915_READ(D_COMP_BDW);
9376 }
9377
9378 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9379 {
9380         struct drm_device *dev = dev_priv->dev;
9381
9382         if (IS_HASWELL(dev)) {
9383                 mutex_lock(&dev_priv->rps.hw_lock);
9384                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9385                                             val))
9386                         DRM_ERROR("Failed to write to D_COMP\n");
9387                 mutex_unlock(&dev_priv->rps.hw_lock);
9388         } else {
9389                 I915_WRITE(D_COMP_BDW, val);
9390                 POSTING_READ(D_COMP_BDW);
9391         }
9392 }
9393
9394 /*
9395  * This function implements pieces of two sequences from BSpec:
9396  * - Sequence for display software to disable LCPLL
9397  * - Sequence for display software to allow package C8+
9398  * The steps implemented here are just the steps that actually touch the LCPLL
9399  * register. Callers should take care of disabling all the display engine
9400  * functions, doing the mode unset, fixing interrupts, etc.
9401  */
9402 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9403                               bool switch_to_fclk, bool allow_power_down)
9404 {
9405         uint32_t val;
9406
9407         assert_can_disable_lcpll(dev_priv);
9408
9409         val = I915_READ(LCPLL_CTL);
9410
9411         if (switch_to_fclk) {
9412                 val |= LCPLL_CD_SOURCE_FCLK;
9413                 I915_WRITE(LCPLL_CTL, val);
9414
9415                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9416                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9417                         DRM_ERROR("Switching to FCLK failed\n");
9418
9419                 val = I915_READ(LCPLL_CTL);
9420         }
9421
9422         val |= LCPLL_PLL_DISABLE;
9423         I915_WRITE(LCPLL_CTL, val);
9424         POSTING_READ(LCPLL_CTL);
9425
9426         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9427                 DRM_ERROR("LCPLL still locked\n");
9428
9429         val = hsw_read_dcomp(dev_priv);
9430         val |= D_COMP_COMP_DISABLE;
9431         hsw_write_dcomp(dev_priv, val);
9432         ndelay(100);
9433
9434         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9435                      1))
9436                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9437
9438         if (allow_power_down) {
9439                 val = I915_READ(LCPLL_CTL);
9440                 val |= LCPLL_POWER_DOWN_ALLOW;
9441                 I915_WRITE(LCPLL_CTL, val);
9442                 POSTING_READ(LCPLL_CTL);
9443         }
9444 }
9445
9446 /*
9447  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9448  * source.
9449  */
9450 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9451 {
9452         uint32_t val;
9453
9454         val = I915_READ(LCPLL_CTL);
9455
9456         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9457                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9458                 return;
9459
9460         /*
9461          * Make sure we're not on PC8 state before disabling PC8, otherwise
9462          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9463          */
9464         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9465
9466         if (val & LCPLL_POWER_DOWN_ALLOW) {
9467                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9468                 I915_WRITE(LCPLL_CTL, val);
9469                 POSTING_READ(LCPLL_CTL);
9470         }
9471
9472         val = hsw_read_dcomp(dev_priv);
9473         val |= D_COMP_COMP_FORCE;
9474         val &= ~D_COMP_COMP_DISABLE;
9475         hsw_write_dcomp(dev_priv, val);
9476
9477         val = I915_READ(LCPLL_CTL);
9478         val &= ~LCPLL_PLL_DISABLE;
9479         I915_WRITE(LCPLL_CTL, val);
9480
9481         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9482                 DRM_ERROR("LCPLL not locked yet\n");
9483
9484         if (val & LCPLL_CD_SOURCE_FCLK) {
9485                 val = I915_READ(LCPLL_CTL);
9486                 val &= ~LCPLL_CD_SOURCE_FCLK;
9487                 I915_WRITE(LCPLL_CTL, val);
9488
9489                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9490                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9491                         DRM_ERROR("Switching back to LCPLL failed\n");
9492         }
9493
9494         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9495         intel_update_cdclk(dev_priv->dev);
9496 }
9497
9498 /*
9499  * Package states C8 and deeper are really deep PC states that can only be
9500  * reached when all the devices on the system allow it, so even if the graphics
9501  * device allows PC8+, it doesn't mean the system will actually get to these
9502  * states. Our driver only allows PC8+ when going into runtime PM.
9503  *
9504  * The requirements for PC8+ are that all the outputs are disabled, the power
9505  * well is disabled and most interrupts are disabled, and these are also
9506  * requirements for runtime PM. When these conditions are met, we manually do
9507  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9508  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9509  * hang the machine.
9510  *
9511  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9512  * the state of some registers, so when we come back from PC8+ we need to
9513  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9514  * need to take care of the registers kept by RC6. Notice that this happens even
9515  * if we don't put the device in PCI D3 state (which is what currently happens
9516  * because of the runtime PM support).
9517  *
9518  * For more, read "Display Sequences for Package C8" on the hardware
9519  * documentation.
9520  */
9521 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9522 {
9523         struct drm_device *dev = dev_priv->dev;
9524         uint32_t val;
9525
9526         DRM_DEBUG_KMS("Enabling package C8+\n");
9527
9528         if (HAS_PCH_LPT_LP(dev)) {
9529                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9530                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9531                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9532         }
9533
9534         lpt_disable_clkout_dp(dev);
9535         hsw_disable_lcpll(dev_priv, true, true);
9536 }
9537
9538 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9539 {
9540         struct drm_device *dev = dev_priv->dev;
9541         uint32_t val;
9542
9543         DRM_DEBUG_KMS("Disabling package C8+\n");
9544
9545         hsw_restore_lcpll(dev_priv);
9546         lpt_init_pch_refclk(dev);
9547
9548         if (HAS_PCH_LPT_LP(dev)) {
9549                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9550                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9551                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9552         }
9553
9554         intel_prepare_ddi(dev);
9555 }
9556
9557 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9558 {
9559         struct drm_device *dev = old_state->dev;
9560         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9561
9562         broxton_set_cdclk(dev, req_cdclk);
9563 }
9564
9565 /* compute the max rate for new configuration */
9566 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9567 {
9568         struct intel_crtc *intel_crtc;
9569         struct intel_crtc_state *crtc_state;
9570         int max_pixel_rate = 0;
9571
9572         for_each_intel_crtc(state->dev, intel_crtc) {
9573                 int pixel_rate;
9574
9575                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9576                 if (IS_ERR(crtc_state))
9577                         return PTR_ERR(crtc_state);
9578
9579                 if (!crtc_state->base.enable)
9580                         continue;
9581
9582                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9583
9584                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9585                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9586                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9587
9588                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9589         }
9590
9591         return max_pixel_rate;
9592 }
9593
9594 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9595 {
9596         struct drm_i915_private *dev_priv = dev->dev_private;
9597         uint32_t val, data;
9598         int ret;
9599
9600         if (WARN((I915_READ(LCPLL_CTL) &
9601                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9602                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9603                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9604                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9605                  "trying to change cdclk frequency with cdclk not enabled\n"))
9606                 return;
9607
9608         mutex_lock(&dev_priv->rps.hw_lock);
9609         ret = sandybridge_pcode_write(dev_priv,
9610                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9611         mutex_unlock(&dev_priv->rps.hw_lock);
9612         if (ret) {
9613                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9614                 return;
9615         }
9616
9617         val = I915_READ(LCPLL_CTL);
9618         val |= LCPLL_CD_SOURCE_FCLK;
9619         I915_WRITE(LCPLL_CTL, val);
9620
9621         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9622                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9623                 DRM_ERROR("Switching to FCLK failed\n");
9624
9625         val = I915_READ(LCPLL_CTL);
9626         val &= ~LCPLL_CLK_FREQ_MASK;
9627
9628         switch (cdclk) {
9629         case 450000:
9630                 val |= LCPLL_CLK_FREQ_450;
9631                 data = 0;
9632                 break;
9633         case 540000:
9634                 val |= LCPLL_CLK_FREQ_54O_BDW;
9635                 data = 1;
9636                 break;
9637         case 337500:
9638                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9639                 data = 2;
9640                 break;
9641         case 675000:
9642                 val |= LCPLL_CLK_FREQ_675_BDW;
9643                 data = 3;
9644                 break;
9645         default:
9646                 WARN(1, "invalid cdclk frequency\n");
9647                 return;
9648         }
9649
9650         I915_WRITE(LCPLL_CTL, val);
9651
9652         val = I915_READ(LCPLL_CTL);
9653         val &= ~LCPLL_CD_SOURCE_FCLK;
9654         I915_WRITE(LCPLL_CTL, val);
9655
9656         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9657                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9658                 DRM_ERROR("Switching back to LCPLL failed\n");
9659
9660         mutex_lock(&dev_priv->rps.hw_lock);
9661         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9662         mutex_unlock(&dev_priv->rps.hw_lock);
9663
9664         intel_update_cdclk(dev);
9665
9666         WARN(cdclk != dev_priv->cdclk_freq,
9667              "cdclk requested %d kHz but got %d kHz\n",
9668              cdclk, dev_priv->cdclk_freq);
9669 }
9670
9671 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9672 {
9673         struct drm_i915_private *dev_priv = to_i915(state->dev);
9674         int max_pixclk = ilk_max_pixel_rate(state);
9675         int cdclk;
9676
9677         /*
9678          * FIXME should also account for plane ratio
9679          * once 64bpp pixel formats are supported.
9680          */
9681         if (max_pixclk > 540000)
9682                 cdclk = 675000;
9683         else if (max_pixclk > 450000)
9684                 cdclk = 540000;
9685         else if (max_pixclk > 337500)
9686                 cdclk = 450000;
9687         else
9688                 cdclk = 337500;
9689
9690         /*
9691          * FIXME move the cdclk caclulation to
9692          * compute_config() so we can fail gracegully.
9693          */
9694         if (cdclk > dev_priv->max_cdclk_freq) {
9695                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9696                           cdclk, dev_priv->max_cdclk_freq);
9697                 cdclk = dev_priv->max_cdclk_freq;
9698         }
9699
9700         to_intel_atomic_state(state)->cdclk = cdclk;
9701
9702         return 0;
9703 }
9704
9705 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9706 {
9707         struct drm_device *dev = old_state->dev;
9708         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9709
9710         broadwell_set_cdclk(dev, req_cdclk);
9711 }
9712
9713 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9714                                       struct intel_crtc_state *crtc_state)
9715 {
9716         if (!intel_ddi_pll_select(crtc, crtc_state))
9717                 return -EINVAL;
9718
9719         crtc->lowfreq_avail = false;
9720
9721         return 0;
9722 }
9723
9724 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9725                                 enum port port,
9726                                 struct intel_crtc_state *pipe_config)
9727 {
9728         switch (port) {
9729         case PORT_A:
9730                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9731                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9732                 break;
9733         case PORT_B:
9734                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9735                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9736                 break;
9737         case PORT_C:
9738                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9739                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9740                 break;
9741         default:
9742                 DRM_ERROR("Incorrect port type\n");
9743         }
9744 }
9745
9746 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9747                                 enum port port,
9748                                 struct intel_crtc_state *pipe_config)
9749 {
9750         u32 temp, dpll_ctl1;
9751
9752         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9753         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9754
9755         switch (pipe_config->ddi_pll_sel) {
9756         case SKL_DPLL0:
9757                 /*
9758                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9759                  * of the shared DPLL framework and thus needs to be read out
9760                  * separately
9761                  */
9762                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9763                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9764                 break;
9765         case SKL_DPLL1:
9766                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9767                 break;
9768         case SKL_DPLL2:
9769                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9770                 break;
9771         case SKL_DPLL3:
9772                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9773                 break;
9774         }
9775 }
9776
9777 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9778                                 enum port port,
9779                                 struct intel_crtc_state *pipe_config)
9780 {
9781         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9782
9783         switch (pipe_config->ddi_pll_sel) {
9784         case PORT_CLK_SEL_WRPLL1:
9785                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9786                 break;
9787         case PORT_CLK_SEL_WRPLL2:
9788                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9789                 break;
9790         }
9791 }
9792
9793 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9794                                        struct intel_crtc_state *pipe_config)
9795 {
9796         struct drm_device *dev = crtc->base.dev;
9797         struct drm_i915_private *dev_priv = dev->dev_private;
9798         struct intel_shared_dpll *pll;
9799         enum port port;
9800         uint32_t tmp;
9801
9802         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9803
9804         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9805
9806         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9807                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9808         else if (IS_BROXTON(dev))
9809                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9810         else
9811                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9812
9813         if (pipe_config->shared_dpll >= 0) {
9814                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9815
9816                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9817                                            &pipe_config->dpll_hw_state));
9818         }
9819
9820         /*
9821          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9822          * DDI E. So just check whether this pipe is wired to DDI E and whether
9823          * the PCH transcoder is on.
9824          */
9825         if (INTEL_INFO(dev)->gen < 9 &&
9826             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9827                 pipe_config->has_pch_encoder = true;
9828
9829                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9830                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9831                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9832
9833                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9834         }
9835 }
9836
9837 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9838                                     struct intel_crtc_state *pipe_config)
9839 {
9840         struct drm_device *dev = crtc->base.dev;
9841         struct drm_i915_private *dev_priv = dev->dev_private;
9842         enum intel_display_power_domain pfit_domain;
9843         uint32_t tmp;
9844
9845         if (!intel_display_power_is_enabled(dev_priv,
9846                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9847                 return false;
9848
9849         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9850         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9851
9852         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9853         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9854                 enum pipe trans_edp_pipe;
9855                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9856                 default:
9857                         WARN(1, "unknown pipe linked to edp transcoder\n");
9858                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9859                 case TRANS_DDI_EDP_INPUT_A_ON:
9860                         trans_edp_pipe = PIPE_A;
9861                         break;
9862                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9863                         trans_edp_pipe = PIPE_B;
9864                         break;
9865                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9866                         trans_edp_pipe = PIPE_C;
9867                         break;
9868                 }
9869
9870                 if (trans_edp_pipe == crtc->pipe)
9871                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9872         }
9873
9874         if (!intel_display_power_is_enabled(dev_priv,
9875                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9876                 return false;
9877
9878         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9879         if (!(tmp & PIPECONF_ENABLE))
9880                 return false;
9881
9882         haswell_get_ddi_port_state(crtc, pipe_config);
9883
9884         intel_get_pipe_timings(crtc, pipe_config);
9885
9886         if (INTEL_INFO(dev)->gen >= 9) {
9887                 skl_init_scalers(dev, crtc, pipe_config);
9888         }
9889
9890         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9891
9892         if (INTEL_INFO(dev)->gen >= 9) {
9893                 pipe_config->scaler_state.scaler_id = -1;
9894                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9895         }
9896
9897         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9898                 if (INTEL_INFO(dev)->gen >= 9)
9899                         skylake_get_pfit_config(crtc, pipe_config);
9900                 else
9901                         ironlake_get_pfit_config(crtc, pipe_config);
9902         }
9903
9904         if (IS_HASWELL(dev))
9905                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9906                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9907
9908         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9909                 pipe_config->pixel_multiplier =
9910                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9911         } else {
9912                 pipe_config->pixel_multiplier = 1;
9913         }
9914
9915         return true;
9916 }
9917
9918 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9919 {
9920         struct drm_device *dev = crtc->dev;
9921         struct drm_i915_private *dev_priv = dev->dev_private;
9922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9923         uint32_t cntl = 0, size = 0;
9924
9925         if (base) {
9926                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9927                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9928                 unsigned int stride = roundup_pow_of_two(width) * 4;
9929
9930                 switch (stride) {
9931                 default:
9932                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9933                                   width, stride);
9934                         stride = 256;
9935                         /* fallthrough */
9936                 case 256:
9937                 case 512:
9938                 case 1024:
9939                 case 2048:
9940                         break;
9941                 }
9942
9943                 cntl |= CURSOR_ENABLE |
9944                         CURSOR_GAMMA_ENABLE |
9945                         CURSOR_FORMAT_ARGB |
9946                         CURSOR_STRIDE(stride);
9947
9948                 size = (height << 12) | width;
9949         }
9950
9951         if (intel_crtc->cursor_cntl != 0 &&
9952             (intel_crtc->cursor_base != base ||
9953              intel_crtc->cursor_size != size ||
9954              intel_crtc->cursor_cntl != cntl)) {
9955                 /* On these chipsets we can only modify the base/size/stride
9956                  * whilst the cursor is disabled.
9957                  */
9958                 I915_WRITE(CURCNTR(PIPE_A), 0);
9959                 POSTING_READ(CURCNTR(PIPE_A));
9960                 intel_crtc->cursor_cntl = 0;
9961         }
9962
9963         if (intel_crtc->cursor_base != base) {
9964                 I915_WRITE(CURBASE(PIPE_A), base);
9965                 intel_crtc->cursor_base = base;
9966         }
9967
9968         if (intel_crtc->cursor_size != size) {
9969                 I915_WRITE(CURSIZE, size);
9970                 intel_crtc->cursor_size = size;
9971         }
9972
9973         if (intel_crtc->cursor_cntl != cntl) {
9974                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9975                 POSTING_READ(CURCNTR(PIPE_A));
9976                 intel_crtc->cursor_cntl = cntl;
9977         }
9978 }
9979
9980 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9981 {
9982         struct drm_device *dev = crtc->dev;
9983         struct drm_i915_private *dev_priv = dev->dev_private;
9984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9985         int pipe = intel_crtc->pipe;
9986         uint32_t cntl;
9987
9988         cntl = 0;
9989         if (base) {
9990                 cntl = MCURSOR_GAMMA_ENABLE;
9991                 switch (intel_crtc->base.cursor->state->crtc_w) {
9992                         case 64:
9993                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9994                                 break;
9995                         case 128:
9996                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9997                                 break;
9998                         case 256:
9999                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10000                                 break;
10001                         default:
10002                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10003                                 return;
10004                 }
10005                 cntl |= pipe << 28; /* Connect to correct pipe */
10006
10007                 if (HAS_DDI(dev))
10008                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10009         }
10010
10011         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10012                 cntl |= CURSOR_ROTATE_180;
10013
10014         if (intel_crtc->cursor_cntl != cntl) {
10015                 I915_WRITE(CURCNTR(pipe), cntl);
10016                 POSTING_READ(CURCNTR(pipe));
10017                 intel_crtc->cursor_cntl = cntl;
10018         }
10019
10020         /* and commit changes on next vblank */
10021         I915_WRITE(CURBASE(pipe), base);
10022         POSTING_READ(CURBASE(pipe));
10023
10024         intel_crtc->cursor_base = base;
10025 }
10026
10027 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10028 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10029                                      bool on)
10030 {
10031         struct drm_device *dev = crtc->dev;
10032         struct drm_i915_private *dev_priv = dev->dev_private;
10033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10034         int pipe = intel_crtc->pipe;
10035         struct drm_plane_state *cursor_state = crtc->cursor->state;
10036         int x = cursor_state->crtc_x;
10037         int y = cursor_state->crtc_y;
10038         u32 base = 0, pos = 0;
10039
10040         if (on)
10041                 base = intel_crtc->cursor_addr;
10042
10043         if (x >= intel_crtc->config->pipe_src_w)
10044                 base = 0;
10045
10046         if (y >= intel_crtc->config->pipe_src_h)
10047                 base = 0;
10048
10049         if (x < 0) {
10050                 if (x + cursor_state->crtc_w <= 0)
10051                         base = 0;
10052
10053                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10054                 x = -x;
10055         }
10056         pos |= x << CURSOR_X_SHIFT;
10057
10058         if (y < 0) {
10059                 if (y + cursor_state->crtc_h <= 0)
10060                         base = 0;
10061
10062                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10063                 y = -y;
10064         }
10065         pos |= y << CURSOR_Y_SHIFT;
10066
10067         if (base == 0 && intel_crtc->cursor_base == 0)
10068                 return;
10069
10070         I915_WRITE(CURPOS(pipe), pos);
10071
10072         /* ILK+ do this automagically */
10073         if (HAS_GMCH_DISPLAY(dev) &&
10074             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10075                 base += (cursor_state->crtc_h *
10076                          cursor_state->crtc_w - 1) * 4;
10077         }
10078
10079         if (IS_845G(dev) || IS_I865G(dev))
10080                 i845_update_cursor(crtc, base);
10081         else
10082                 i9xx_update_cursor(crtc, base);
10083 }
10084
10085 static bool cursor_size_ok(struct drm_device *dev,
10086                            uint32_t width, uint32_t height)
10087 {
10088         if (width == 0 || height == 0)
10089                 return false;
10090
10091         /*
10092          * 845g/865g are special in that they are only limited by
10093          * the width of their cursors, the height is arbitrary up to
10094          * the precision of the register. Everything else requires
10095          * square cursors, limited to a few power-of-two sizes.
10096          */
10097         if (IS_845G(dev) || IS_I865G(dev)) {
10098                 if ((width & 63) != 0)
10099                         return false;
10100
10101                 if (width > (IS_845G(dev) ? 64 : 512))
10102                         return false;
10103
10104                 if (height > 1023)
10105                         return false;
10106         } else {
10107                 switch (width | height) {
10108                 case 256:
10109                 case 128:
10110                         if (IS_GEN2(dev))
10111                                 return false;
10112                 case 64:
10113                         break;
10114                 default:
10115                         return false;
10116                 }
10117         }
10118
10119         return true;
10120 }
10121
10122 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10123                                  u16 *blue, uint32_t start, uint32_t size)
10124 {
10125         int end = (start + size > 256) ? 256 : start + size, i;
10126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10127
10128         for (i = start; i < end; i++) {
10129                 intel_crtc->lut_r[i] = red[i] >> 8;
10130                 intel_crtc->lut_g[i] = green[i] >> 8;
10131                 intel_crtc->lut_b[i] = blue[i] >> 8;
10132         }
10133
10134         intel_crtc_load_lut(crtc);
10135 }
10136
10137 /* VESA 640x480x72Hz mode to set on the pipe */
10138 static struct drm_display_mode load_detect_mode = {
10139         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10140                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10141 };
10142
10143 struct drm_framebuffer *
10144 __intel_framebuffer_create(struct drm_device *dev,
10145                            struct drm_mode_fb_cmd2 *mode_cmd,
10146                            struct drm_i915_gem_object *obj)
10147 {
10148         struct intel_framebuffer *intel_fb;
10149         int ret;
10150
10151         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10152         if (!intel_fb)
10153                 return ERR_PTR(-ENOMEM);
10154
10155         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10156         if (ret)
10157                 goto err;
10158
10159         return &intel_fb->base;
10160
10161 err:
10162         kfree(intel_fb);
10163         return ERR_PTR(ret);
10164 }
10165
10166 static struct drm_framebuffer *
10167 intel_framebuffer_create(struct drm_device *dev,
10168                          struct drm_mode_fb_cmd2 *mode_cmd,
10169                          struct drm_i915_gem_object *obj)
10170 {
10171         struct drm_framebuffer *fb;
10172         int ret;
10173
10174         ret = i915_mutex_lock_interruptible(dev);
10175         if (ret)
10176                 return ERR_PTR(ret);
10177         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10178         mutex_unlock(&dev->struct_mutex);
10179
10180         return fb;
10181 }
10182
10183 static u32
10184 intel_framebuffer_pitch_for_width(int width, int bpp)
10185 {
10186         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10187         return ALIGN(pitch, 64);
10188 }
10189
10190 static u32
10191 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10192 {
10193         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10194         return PAGE_ALIGN(pitch * mode->vdisplay);
10195 }
10196
10197 static struct drm_framebuffer *
10198 intel_framebuffer_create_for_mode(struct drm_device *dev,
10199                                   struct drm_display_mode *mode,
10200                                   int depth, int bpp)
10201 {
10202         struct drm_framebuffer *fb;
10203         struct drm_i915_gem_object *obj;
10204         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10205
10206         obj = i915_gem_alloc_object(dev,
10207                                     intel_framebuffer_size_for_mode(mode, bpp));
10208         if (obj == NULL)
10209                 return ERR_PTR(-ENOMEM);
10210
10211         mode_cmd.width = mode->hdisplay;
10212         mode_cmd.height = mode->vdisplay;
10213         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10214                                                                 bpp);
10215         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10216
10217         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10218         if (IS_ERR(fb))
10219                 drm_gem_object_unreference_unlocked(&obj->base);
10220
10221         return fb;
10222 }
10223
10224 static struct drm_framebuffer *
10225 mode_fits_in_fbdev(struct drm_device *dev,
10226                    struct drm_display_mode *mode)
10227 {
10228 #ifdef CONFIG_DRM_FBDEV_EMULATION
10229         struct drm_i915_private *dev_priv = dev->dev_private;
10230         struct drm_i915_gem_object *obj;
10231         struct drm_framebuffer *fb;
10232
10233         if (!dev_priv->fbdev)
10234                 return NULL;
10235
10236         if (!dev_priv->fbdev->fb)
10237                 return NULL;
10238
10239         obj = dev_priv->fbdev->fb->obj;
10240         BUG_ON(!obj);
10241
10242         fb = &dev_priv->fbdev->fb->base;
10243         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10244                                                                fb->bits_per_pixel))
10245                 return NULL;
10246
10247         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10248                 return NULL;
10249
10250         return fb;
10251 #else
10252         return NULL;
10253 #endif
10254 }
10255
10256 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10257                                            struct drm_crtc *crtc,
10258                                            struct drm_display_mode *mode,
10259                                            struct drm_framebuffer *fb,
10260                                            int x, int y)
10261 {
10262         struct drm_plane_state *plane_state;
10263         int hdisplay, vdisplay;
10264         int ret;
10265
10266         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10267         if (IS_ERR(plane_state))
10268                 return PTR_ERR(plane_state);
10269
10270         if (mode)
10271                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10272         else
10273                 hdisplay = vdisplay = 0;
10274
10275         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10276         if (ret)
10277                 return ret;
10278         drm_atomic_set_fb_for_plane(plane_state, fb);
10279         plane_state->crtc_x = 0;
10280         plane_state->crtc_y = 0;
10281         plane_state->crtc_w = hdisplay;
10282         plane_state->crtc_h = vdisplay;
10283         plane_state->src_x = x << 16;
10284         plane_state->src_y = y << 16;
10285         plane_state->src_w = hdisplay << 16;
10286         plane_state->src_h = vdisplay << 16;
10287
10288         return 0;
10289 }
10290
10291 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10292                                 struct drm_display_mode *mode,
10293                                 struct intel_load_detect_pipe *old,
10294                                 struct drm_modeset_acquire_ctx *ctx)
10295 {
10296         struct intel_crtc *intel_crtc;
10297         struct intel_encoder *intel_encoder =
10298                 intel_attached_encoder(connector);
10299         struct drm_crtc *possible_crtc;
10300         struct drm_encoder *encoder = &intel_encoder->base;
10301         struct drm_crtc *crtc = NULL;
10302         struct drm_device *dev = encoder->dev;
10303         struct drm_framebuffer *fb;
10304         struct drm_mode_config *config = &dev->mode_config;
10305         struct drm_atomic_state *state = NULL;
10306         struct drm_connector_state *connector_state;
10307         struct intel_crtc_state *crtc_state;
10308         int ret, i = -1;
10309
10310         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10311                       connector->base.id, connector->name,
10312                       encoder->base.id, encoder->name);
10313
10314 retry:
10315         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10316         if (ret)
10317                 goto fail;
10318
10319         /*
10320          * Algorithm gets a little messy:
10321          *
10322          *   - if the connector already has an assigned crtc, use it (but make
10323          *     sure it's on first)
10324          *
10325          *   - try to find the first unused crtc that can drive this connector,
10326          *     and use that if we find one
10327          */
10328
10329         /* See if we already have a CRTC for this connector */
10330         if (encoder->crtc) {
10331                 crtc = encoder->crtc;
10332
10333                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10334                 if (ret)
10335                         goto fail;
10336                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10337                 if (ret)
10338                         goto fail;
10339
10340                 old->dpms_mode = connector->dpms;
10341                 old->load_detect_temp = false;
10342
10343                 /* Make sure the crtc and connector are running */
10344                 if (connector->dpms != DRM_MODE_DPMS_ON)
10345                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10346
10347                 return true;
10348         }
10349
10350         /* Find an unused one (if possible) */
10351         for_each_crtc(dev, possible_crtc) {
10352                 i++;
10353                 if (!(encoder->possible_crtcs & (1 << i)))
10354                         continue;
10355                 if (possible_crtc->state->enable)
10356                         continue;
10357
10358                 crtc = possible_crtc;
10359                 break;
10360         }
10361
10362         /*
10363          * If we didn't find an unused CRTC, don't use any.
10364          */
10365         if (!crtc) {
10366                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10367                 goto fail;
10368         }
10369
10370         ret = drm_modeset_lock(&crtc->mutex, ctx);
10371         if (ret)
10372                 goto fail;
10373         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10374         if (ret)
10375                 goto fail;
10376
10377         intel_crtc = to_intel_crtc(crtc);
10378         old->dpms_mode = connector->dpms;
10379         old->load_detect_temp = true;
10380         old->release_fb = NULL;
10381
10382         state = drm_atomic_state_alloc(dev);
10383         if (!state)
10384                 return false;
10385
10386         state->acquire_ctx = ctx;
10387
10388         connector_state = drm_atomic_get_connector_state(state, connector);
10389         if (IS_ERR(connector_state)) {
10390                 ret = PTR_ERR(connector_state);
10391                 goto fail;
10392         }
10393
10394         connector_state->crtc = crtc;
10395         connector_state->best_encoder = &intel_encoder->base;
10396
10397         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10398         if (IS_ERR(crtc_state)) {
10399                 ret = PTR_ERR(crtc_state);
10400                 goto fail;
10401         }
10402
10403         crtc_state->base.active = crtc_state->base.enable = true;
10404
10405         if (!mode)
10406                 mode = &load_detect_mode;
10407
10408         /* We need a framebuffer large enough to accommodate all accesses
10409          * that the plane may generate whilst we perform load detection.
10410          * We can not rely on the fbcon either being present (we get called
10411          * during its initialisation to detect all boot displays, or it may
10412          * not even exist) or that it is large enough to satisfy the
10413          * requested mode.
10414          */
10415         fb = mode_fits_in_fbdev(dev, mode);
10416         if (fb == NULL) {
10417                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10418                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10419                 old->release_fb = fb;
10420         } else
10421                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10422         if (IS_ERR(fb)) {
10423                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10424                 goto fail;
10425         }
10426
10427         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10428         if (ret)
10429                 goto fail;
10430
10431         drm_mode_copy(&crtc_state->base.mode, mode);
10432
10433         if (drm_atomic_commit(state)) {
10434                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10435                 if (old->release_fb)
10436                         old->release_fb->funcs->destroy(old->release_fb);
10437                 goto fail;
10438         }
10439         crtc->primary->crtc = crtc;
10440
10441         /* let the connector get through one full cycle before testing */
10442         intel_wait_for_vblank(dev, intel_crtc->pipe);
10443         return true;
10444
10445 fail:
10446         drm_atomic_state_free(state);
10447         state = NULL;
10448
10449         if (ret == -EDEADLK) {
10450                 drm_modeset_backoff(ctx);
10451                 goto retry;
10452         }
10453
10454         return false;
10455 }
10456
10457 void intel_release_load_detect_pipe(struct drm_connector *connector,
10458                                     struct intel_load_detect_pipe *old,
10459                                     struct drm_modeset_acquire_ctx *ctx)
10460 {
10461         struct drm_device *dev = connector->dev;
10462         struct intel_encoder *intel_encoder =
10463                 intel_attached_encoder(connector);
10464         struct drm_encoder *encoder = &intel_encoder->base;
10465         struct drm_crtc *crtc = encoder->crtc;
10466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10467         struct drm_atomic_state *state;
10468         struct drm_connector_state *connector_state;
10469         struct intel_crtc_state *crtc_state;
10470         int ret;
10471
10472         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10473                       connector->base.id, connector->name,
10474                       encoder->base.id, encoder->name);
10475
10476         if (old->load_detect_temp) {
10477                 state = drm_atomic_state_alloc(dev);
10478                 if (!state)
10479                         goto fail;
10480
10481                 state->acquire_ctx = ctx;
10482
10483                 connector_state = drm_atomic_get_connector_state(state, connector);
10484                 if (IS_ERR(connector_state))
10485                         goto fail;
10486
10487                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10488                 if (IS_ERR(crtc_state))
10489                         goto fail;
10490
10491                 connector_state->best_encoder = NULL;
10492                 connector_state->crtc = NULL;
10493
10494                 crtc_state->base.enable = crtc_state->base.active = false;
10495
10496                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10497                                                       0, 0);
10498                 if (ret)
10499                         goto fail;
10500
10501                 ret = drm_atomic_commit(state);
10502                 if (ret)
10503                         goto fail;
10504
10505                 if (old->release_fb) {
10506                         drm_framebuffer_unregister_private(old->release_fb);
10507                         drm_framebuffer_unreference(old->release_fb);
10508                 }
10509
10510                 return;
10511         }
10512
10513         /* Switch crtc and encoder back off if necessary */
10514         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10515                 connector->funcs->dpms(connector, old->dpms_mode);
10516
10517         return;
10518 fail:
10519         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10520         drm_atomic_state_free(state);
10521 }
10522
10523 static int i9xx_pll_refclk(struct drm_device *dev,
10524                            const struct intel_crtc_state *pipe_config)
10525 {
10526         struct drm_i915_private *dev_priv = dev->dev_private;
10527         u32 dpll = pipe_config->dpll_hw_state.dpll;
10528
10529         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10530                 return dev_priv->vbt.lvds_ssc_freq;
10531         else if (HAS_PCH_SPLIT(dev))
10532                 return 120000;
10533         else if (!IS_GEN2(dev))
10534                 return 96000;
10535         else
10536                 return 48000;
10537 }
10538
10539 /* Returns the clock of the currently programmed mode of the given pipe. */
10540 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10541                                 struct intel_crtc_state *pipe_config)
10542 {
10543         struct drm_device *dev = crtc->base.dev;
10544         struct drm_i915_private *dev_priv = dev->dev_private;
10545         int pipe = pipe_config->cpu_transcoder;
10546         u32 dpll = pipe_config->dpll_hw_state.dpll;
10547         u32 fp;
10548         intel_clock_t clock;
10549         int port_clock;
10550         int refclk = i9xx_pll_refclk(dev, pipe_config);
10551
10552         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10553                 fp = pipe_config->dpll_hw_state.fp0;
10554         else
10555                 fp = pipe_config->dpll_hw_state.fp1;
10556
10557         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10558         if (IS_PINEVIEW(dev)) {
10559                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10560                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10561         } else {
10562                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10563                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10564         }
10565
10566         if (!IS_GEN2(dev)) {
10567                 if (IS_PINEVIEW(dev))
10568                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10569                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10570                 else
10571                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10572                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10573
10574                 switch (dpll & DPLL_MODE_MASK) {
10575                 case DPLLB_MODE_DAC_SERIAL:
10576                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10577                                 5 : 10;
10578                         break;
10579                 case DPLLB_MODE_LVDS:
10580                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10581                                 7 : 14;
10582                         break;
10583                 default:
10584                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10585                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10586                         return;
10587                 }
10588
10589                 if (IS_PINEVIEW(dev))
10590                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10591                 else
10592                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10593         } else {
10594                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10595                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10596
10597                 if (is_lvds) {
10598                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10599                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10600
10601                         if (lvds & LVDS_CLKB_POWER_UP)
10602                                 clock.p2 = 7;
10603                         else
10604                                 clock.p2 = 14;
10605                 } else {
10606                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10607                                 clock.p1 = 2;
10608                         else {
10609                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10610                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10611                         }
10612                         if (dpll & PLL_P2_DIVIDE_BY_4)
10613                                 clock.p2 = 4;
10614                         else
10615                                 clock.p2 = 2;
10616                 }
10617
10618                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10619         }
10620
10621         /*
10622          * This value includes pixel_multiplier. We will use
10623          * port_clock to compute adjusted_mode.crtc_clock in the
10624          * encoder's get_config() function.
10625          */
10626         pipe_config->port_clock = port_clock;
10627 }
10628
10629 int intel_dotclock_calculate(int link_freq,
10630                              const struct intel_link_m_n *m_n)
10631 {
10632         /*
10633          * The calculation for the data clock is:
10634          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10635          * But we want to avoid losing precison if possible, so:
10636          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10637          *
10638          * and the link clock is simpler:
10639          * link_clock = (m * link_clock) / n
10640          */
10641
10642         if (!m_n->link_n)
10643                 return 0;
10644
10645         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10646 }
10647
10648 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10649                                    struct intel_crtc_state *pipe_config)
10650 {
10651         struct drm_device *dev = crtc->base.dev;
10652
10653         /* read out port_clock from the DPLL */
10654         i9xx_crtc_clock_get(crtc, pipe_config);
10655
10656         /*
10657          * This value does not include pixel_multiplier.
10658          * We will check that port_clock and adjusted_mode.crtc_clock
10659          * agree once we know their relationship in the encoder's
10660          * get_config() function.
10661          */
10662         pipe_config->base.adjusted_mode.crtc_clock =
10663                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10664                                          &pipe_config->fdi_m_n);
10665 }
10666
10667 /** Returns the currently programmed mode of the given pipe. */
10668 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10669                                              struct drm_crtc *crtc)
10670 {
10671         struct drm_i915_private *dev_priv = dev->dev_private;
10672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10673         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10674         struct drm_display_mode *mode;
10675         struct intel_crtc_state pipe_config;
10676         int htot = I915_READ(HTOTAL(cpu_transcoder));
10677         int hsync = I915_READ(HSYNC(cpu_transcoder));
10678         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10679         int vsync = I915_READ(VSYNC(cpu_transcoder));
10680         enum pipe pipe = intel_crtc->pipe;
10681
10682         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10683         if (!mode)
10684                 return NULL;
10685
10686         /*
10687          * Construct a pipe_config sufficient for getting the clock info
10688          * back out of crtc_clock_get.
10689          *
10690          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10691          * to use a real value here instead.
10692          */
10693         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10694         pipe_config.pixel_multiplier = 1;
10695         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10696         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10697         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10698         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10699
10700         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10701         mode->hdisplay = (htot & 0xffff) + 1;
10702         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10703         mode->hsync_start = (hsync & 0xffff) + 1;
10704         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10705         mode->vdisplay = (vtot & 0xffff) + 1;
10706         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10707         mode->vsync_start = (vsync & 0xffff) + 1;
10708         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10709
10710         drm_mode_set_name(mode);
10711
10712         return mode;
10713 }
10714
10715 void intel_mark_busy(struct drm_device *dev)
10716 {
10717         struct drm_i915_private *dev_priv = dev->dev_private;
10718
10719         if (dev_priv->mm.busy)
10720                 return;
10721
10722         intel_runtime_pm_get(dev_priv);
10723         i915_update_gfx_val(dev_priv);
10724         if (INTEL_INFO(dev)->gen >= 6)
10725                 gen6_rps_busy(dev_priv);
10726         dev_priv->mm.busy = true;
10727 }
10728
10729 void intel_mark_idle(struct drm_device *dev)
10730 {
10731         struct drm_i915_private *dev_priv = dev->dev_private;
10732
10733         if (!dev_priv->mm.busy)
10734                 return;
10735
10736         dev_priv->mm.busy = false;
10737
10738         if (INTEL_INFO(dev)->gen >= 6)
10739                 gen6_rps_idle(dev->dev_private);
10740
10741         intel_runtime_pm_put(dev_priv);
10742 }
10743
10744 static void intel_crtc_destroy(struct drm_crtc *crtc)
10745 {
10746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747         struct drm_device *dev = crtc->dev;
10748         struct intel_unpin_work *work;
10749
10750         spin_lock_irq(&dev->event_lock);
10751         work = intel_crtc->unpin_work;
10752         intel_crtc->unpin_work = NULL;
10753         spin_unlock_irq(&dev->event_lock);
10754
10755         if (work) {
10756                 cancel_work_sync(&work->work);
10757                 kfree(work);
10758         }
10759
10760         drm_crtc_cleanup(crtc);
10761
10762         kfree(intel_crtc);
10763 }
10764
10765 static void intel_unpin_work_fn(struct work_struct *__work)
10766 {
10767         struct intel_unpin_work *work =
10768                 container_of(__work, struct intel_unpin_work, work);
10769         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10770         struct drm_device *dev = crtc->base.dev;
10771         struct drm_plane *primary = crtc->base.primary;
10772
10773         mutex_lock(&dev->struct_mutex);
10774         intel_unpin_fb_obj(work->old_fb, primary->state);
10775         drm_gem_object_unreference(&work->pending_flip_obj->base);
10776
10777         if (work->flip_queued_req)
10778                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10779         mutex_unlock(&dev->struct_mutex);
10780
10781         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10782         drm_framebuffer_unreference(work->old_fb);
10783
10784         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10785         atomic_dec(&crtc->unpin_work_count);
10786
10787         kfree(work);
10788 }
10789
10790 static void do_intel_finish_page_flip(struct drm_device *dev,
10791                                       struct drm_crtc *crtc)
10792 {
10793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10794         struct intel_unpin_work *work;
10795         unsigned long flags;
10796
10797         /* Ignore early vblank irqs */
10798         if (intel_crtc == NULL)
10799                 return;
10800
10801         /*
10802          * This is called both by irq handlers and the reset code (to complete
10803          * lost pageflips) so needs the full irqsave spinlocks.
10804          */
10805         spin_lock_irqsave(&dev->event_lock, flags);
10806         work = intel_crtc->unpin_work;
10807
10808         /* Ensure we don't miss a work->pending update ... */
10809         smp_rmb();
10810
10811         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10812                 spin_unlock_irqrestore(&dev->event_lock, flags);
10813                 return;
10814         }
10815
10816         page_flip_completed(intel_crtc);
10817
10818         spin_unlock_irqrestore(&dev->event_lock, flags);
10819 }
10820
10821 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10822 {
10823         struct drm_i915_private *dev_priv = dev->dev_private;
10824         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10825
10826         do_intel_finish_page_flip(dev, crtc);
10827 }
10828
10829 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10830 {
10831         struct drm_i915_private *dev_priv = dev->dev_private;
10832         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10833
10834         do_intel_finish_page_flip(dev, crtc);
10835 }
10836
10837 /* Is 'a' after or equal to 'b'? */
10838 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10839 {
10840         return !((a - b) & 0x80000000);
10841 }
10842
10843 static bool page_flip_finished(struct intel_crtc *crtc)
10844 {
10845         struct drm_device *dev = crtc->base.dev;
10846         struct drm_i915_private *dev_priv = dev->dev_private;
10847
10848         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10849             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10850                 return true;
10851
10852         /*
10853          * The relevant registers doen't exist on pre-ctg.
10854          * As the flip done interrupt doesn't trigger for mmio
10855          * flips on gmch platforms, a flip count check isn't
10856          * really needed there. But since ctg has the registers,
10857          * include it in the check anyway.
10858          */
10859         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10860                 return true;
10861
10862         /*
10863          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10864          * used the same base address. In that case the mmio flip might
10865          * have completed, but the CS hasn't even executed the flip yet.
10866          *
10867          * A flip count check isn't enough as the CS might have updated
10868          * the base address just after start of vblank, but before we
10869          * managed to process the interrupt. This means we'd complete the
10870          * CS flip too soon.
10871          *
10872          * Combining both checks should get us a good enough result. It may
10873          * still happen that the CS flip has been executed, but has not
10874          * yet actually completed. But in case the base address is the same
10875          * anyway, we don't really care.
10876          */
10877         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10878                 crtc->unpin_work->gtt_offset &&
10879                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10880                                     crtc->unpin_work->flip_count);
10881 }
10882
10883 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10884 {
10885         struct drm_i915_private *dev_priv = dev->dev_private;
10886         struct intel_crtc *intel_crtc =
10887                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10888         unsigned long flags;
10889
10890
10891         /*
10892          * This is called both by irq handlers and the reset code (to complete
10893          * lost pageflips) so needs the full irqsave spinlocks.
10894          *
10895          * NB: An MMIO update of the plane base pointer will also
10896          * generate a page-flip completion irq, i.e. every modeset
10897          * is also accompanied by a spurious intel_prepare_page_flip().
10898          */
10899         spin_lock_irqsave(&dev->event_lock, flags);
10900         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10901                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10902         spin_unlock_irqrestore(&dev->event_lock, flags);
10903 }
10904
10905 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10906 {
10907         /* Ensure that the work item is consistent when activating it ... */
10908         smp_wmb();
10909         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10910         /* and that it is marked active as soon as the irq could fire. */
10911         smp_wmb();
10912 }
10913
10914 static int intel_gen2_queue_flip(struct drm_device *dev,
10915                                  struct drm_crtc *crtc,
10916                                  struct drm_framebuffer *fb,
10917                                  struct drm_i915_gem_object *obj,
10918                                  struct drm_i915_gem_request *req,
10919                                  uint32_t flags)
10920 {
10921         struct intel_engine_cs *ring = req->ring;
10922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10923         u32 flip_mask;
10924         int ret;
10925
10926         ret = intel_ring_begin(req, 6);
10927         if (ret)
10928                 return ret;
10929
10930         /* Can't queue multiple flips, so wait for the previous
10931          * one to finish before executing the next.
10932          */
10933         if (intel_crtc->plane)
10934                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10935         else
10936                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10937         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10938         intel_ring_emit(ring, MI_NOOP);
10939         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10940                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10941         intel_ring_emit(ring, fb->pitches[0]);
10942         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10943         intel_ring_emit(ring, 0); /* aux display base address, unused */
10944
10945         intel_mark_page_flip_active(intel_crtc->unpin_work);
10946         return 0;
10947 }
10948
10949 static int intel_gen3_queue_flip(struct drm_device *dev,
10950                                  struct drm_crtc *crtc,
10951                                  struct drm_framebuffer *fb,
10952                                  struct drm_i915_gem_object *obj,
10953                                  struct drm_i915_gem_request *req,
10954                                  uint32_t flags)
10955 {
10956         struct intel_engine_cs *ring = req->ring;
10957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10958         u32 flip_mask;
10959         int ret;
10960
10961         ret = intel_ring_begin(req, 6);
10962         if (ret)
10963                 return ret;
10964
10965         if (intel_crtc->plane)
10966                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10967         else
10968                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10969         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10970         intel_ring_emit(ring, MI_NOOP);
10971         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10972                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10973         intel_ring_emit(ring, fb->pitches[0]);
10974         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10975         intel_ring_emit(ring, MI_NOOP);
10976
10977         intel_mark_page_flip_active(intel_crtc->unpin_work);
10978         return 0;
10979 }
10980
10981 static int intel_gen4_queue_flip(struct drm_device *dev,
10982                                  struct drm_crtc *crtc,
10983                                  struct drm_framebuffer *fb,
10984                                  struct drm_i915_gem_object *obj,
10985                                  struct drm_i915_gem_request *req,
10986                                  uint32_t flags)
10987 {
10988         struct intel_engine_cs *ring = req->ring;
10989         struct drm_i915_private *dev_priv = dev->dev_private;
10990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10991         uint32_t pf, pipesrc;
10992         int ret;
10993
10994         ret = intel_ring_begin(req, 4);
10995         if (ret)
10996                 return ret;
10997
10998         /* i965+ uses the linear or tiled offsets from the
10999          * Display Registers (which do not change across a page-flip)
11000          * so we need only reprogram the base address.
11001          */
11002         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11003                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11004         intel_ring_emit(ring, fb->pitches[0]);
11005         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11006                         obj->tiling_mode);
11007
11008         /* XXX Enabling the panel-fitter across page-flip is so far
11009          * untested on non-native modes, so ignore it for now.
11010          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11011          */
11012         pf = 0;
11013         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11014         intel_ring_emit(ring, pf | pipesrc);
11015
11016         intel_mark_page_flip_active(intel_crtc->unpin_work);
11017         return 0;
11018 }
11019
11020 static int intel_gen6_queue_flip(struct drm_device *dev,
11021                                  struct drm_crtc *crtc,
11022                                  struct drm_framebuffer *fb,
11023                                  struct drm_i915_gem_object *obj,
11024                                  struct drm_i915_gem_request *req,
11025                                  uint32_t flags)
11026 {
11027         struct intel_engine_cs *ring = req->ring;
11028         struct drm_i915_private *dev_priv = dev->dev_private;
11029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11030         uint32_t pf, pipesrc;
11031         int ret;
11032
11033         ret = intel_ring_begin(req, 4);
11034         if (ret)
11035                 return ret;
11036
11037         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11038                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11039         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11040         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11041
11042         /* Contrary to the suggestions in the documentation,
11043          * "Enable Panel Fitter" does not seem to be required when page
11044          * flipping with a non-native mode, and worse causes a normal
11045          * modeset to fail.
11046          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11047          */
11048         pf = 0;
11049         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11050         intel_ring_emit(ring, pf | pipesrc);
11051
11052         intel_mark_page_flip_active(intel_crtc->unpin_work);
11053         return 0;
11054 }
11055
11056 static int intel_gen7_queue_flip(struct drm_device *dev,
11057                                  struct drm_crtc *crtc,
11058                                  struct drm_framebuffer *fb,
11059                                  struct drm_i915_gem_object *obj,
11060                                  struct drm_i915_gem_request *req,
11061                                  uint32_t flags)
11062 {
11063         struct intel_engine_cs *ring = req->ring;
11064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11065         uint32_t plane_bit = 0;
11066         int len, ret;
11067
11068         switch (intel_crtc->plane) {
11069         case PLANE_A:
11070                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11071                 break;
11072         case PLANE_B:
11073                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11074                 break;
11075         case PLANE_C:
11076                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11077                 break;
11078         default:
11079                 WARN_ONCE(1, "unknown plane in flip command\n");
11080                 return -ENODEV;
11081         }
11082
11083         len = 4;
11084         if (ring->id == RCS) {
11085                 len += 6;
11086                 /*
11087                  * On Gen 8, SRM is now taking an extra dword to accommodate
11088                  * 48bits addresses, and we need a NOOP for the batch size to
11089                  * stay even.
11090                  */
11091                 if (IS_GEN8(dev))
11092                         len += 2;
11093         }
11094
11095         /*
11096          * BSpec MI_DISPLAY_FLIP for IVB:
11097          * "The full packet must be contained within the same cache line."
11098          *
11099          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11100          * cacheline, if we ever start emitting more commands before
11101          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11102          * then do the cacheline alignment, and finally emit the
11103          * MI_DISPLAY_FLIP.
11104          */
11105         ret = intel_ring_cacheline_align(req);
11106         if (ret)
11107                 return ret;
11108
11109         ret = intel_ring_begin(req, len);
11110         if (ret)
11111                 return ret;
11112
11113         /* Unmask the flip-done completion message. Note that the bspec says that
11114          * we should do this for both the BCS and RCS, and that we must not unmask
11115          * more than one flip event at any time (or ensure that one flip message
11116          * can be sent by waiting for flip-done prior to queueing new flips).
11117          * Experimentation says that BCS works despite DERRMR masking all
11118          * flip-done completion events and that unmasking all planes at once
11119          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11120          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11121          */
11122         if (ring->id == RCS) {
11123                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11124                 intel_ring_emit_reg(ring, DERRMR);
11125                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11126                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11127                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11128                 if (IS_GEN8(dev))
11129                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11130                                               MI_SRM_LRM_GLOBAL_GTT);
11131                 else
11132                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11133                                               MI_SRM_LRM_GLOBAL_GTT);
11134                 intel_ring_emit_reg(ring, DERRMR);
11135                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11136                 if (IS_GEN8(dev)) {
11137                         intel_ring_emit(ring, 0);
11138                         intel_ring_emit(ring, MI_NOOP);
11139                 }
11140         }
11141
11142         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11143         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11144         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11145         intel_ring_emit(ring, (MI_NOOP));
11146
11147         intel_mark_page_flip_active(intel_crtc->unpin_work);
11148         return 0;
11149 }
11150
11151 static bool use_mmio_flip(struct intel_engine_cs *ring,
11152                           struct drm_i915_gem_object *obj)
11153 {
11154         /*
11155          * This is not being used for older platforms, because
11156          * non-availability of flip done interrupt forces us to use
11157          * CS flips. Older platforms derive flip done using some clever
11158          * tricks involving the flip_pending status bits and vblank irqs.
11159          * So using MMIO flips there would disrupt this mechanism.
11160          */
11161
11162         if (ring == NULL)
11163                 return true;
11164
11165         if (INTEL_INFO(ring->dev)->gen < 5)
11166                 return false;
11167
11168         if (i915.use_mmio_flip < 0)
11169                 return false;
11170         else if (i915.use_mmio_flip > 0)
11171                 return true;
11172         else if (i915.enable_execlists)
11173                 return true;
11174         else
11175                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11176 }
11177
11178 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11179                              unsigned int rotation,
11180                              struct intel_unpin_work *work)
11181 {
11182         struct drm_device *dev = intel_crtc->base.dev;
11183         struct drm_i915_private *dev_priv = dev->dev_private;
11184         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11185         const enum pipe pipe = intel_crtc->pipe;
11186         u32 ctl, stride, tile_height;
11187
11188         ctl = I915_READ(PLANE_CTL(pipe, 0));
11189         ctl &= ~PLANE_CTL_TILED_MASK;
11190         switch (fb->modifier[0]) {
11191         case DRM_FORMAT_MOD_NONE:
11192                 break;
11193         case I915_FORMAT_MOD_X_TILED:
11194                 ctl |= PLANE_CTL_TILED_X;
11195                 break;
11196         case I915_FORMAT_MOD_Y_TILED:
11197                 ctl |= PLANE_CTL_TILED_Y;
11198                 break;
11199         case I915_FORMAT_MOD_Yf_TILED:
11200                 ctl |= PLANE_CTL_TILED_YF;
11201                 break;
11202         default:
11203                 MISSING_CASE(fb->modifier[0]);
11204         }
11205
11206         /*
11207          * The stride is either expressed as a multiple of 64 bytes chunks for
11208          * linear buffers or in number of tiles for tiled buffers.
11209          */
11210         if (intel_rotation_90_or_270(rotation)) {
11211                 /* stride = Surface height in tiles */
11212                 tile_height = intel_tile_height(dev, fb->pixel_format,
11213                                                 fb->modifier[0], 0);
11214                 stride = DIV_ROUND_UP(fb->height, tile_height);
11215         } else {
11216                 stride = fb->pitches[0] /
11217                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11218                                                           fb->pixel_format);
11219         }
11220
11221         /*
11222          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11223          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11224          */
11225         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11226         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11227
11228         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11229         POSTING_READ(PLANE_SURF(pipe, 0));
11230 }
11231
11232 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11233                              struct intel_unpin_work *work)
11234 {
11235         struct drm_device *dev = intel_crtc->base.dev;
11236         struct drm_i915_private *dev_priv = dev->dev_private;
11237         struct intel_framebuffer *intel_fb =
11238                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11239         struct drm_i915_gem_object *obj = intel_fb->obj;
11240         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11241         u32 dspcntr;
11242
11243         dspcntr = I915_READ(reg);
11244
11245         if (obj->tiling_mode != I915_TILING_NONE)
11246                 dspcntr |= DISPPLANE_TILED;
11247         else
11248                 dspcntr &= ~DISPPLANE_TILED;
11249
11250         I915_WRITE(reg, dspcntr);
11251
11252         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11253         POSTING_READ(DSPSURF(intel_crtc->plane));
11254 }
11255
11256 /*
11257  * XXX: This is the temporary way to update the plane registers until we get
11258  * around to using the usual plane update functions for MMIO flips
11259  */
11260 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11261 {
11262         struct intel_crtc *crtc = mmio_flip->crtc;
11263         struct intel_unpin_work *work;
11264
11265         spin_lock_irq(&crtc->base.dev->event_lock);
11266         work = crtc->unpin_work;
11267         spin_unlock_irq(&crtc->base.dev->event_lock);
11268         if (work == NULL)
11269                 return;
11270
11271         intel_mark_page_flip_active(work);
11272
11273         intel_pipe_update_start(crtc);
11274
11275         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11276                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11277         else
11278                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11279                 ilk_do_mmio_flip(crtc, work);
11280
11281         intel_pipe_update_end(crtc);
11282 }
11283
11284 static void intel_mmio_flip_work_func(struct work_struct *work)
11285 {
11286         struct intel_mmio_flip *mmio_flip =
11287                 container_of(work, struct intel_mmio_flip, work);
11288
11289         if (mmio_flip->req) {
11290                 WARN_ON(__i915_wait_request(mmio_flip->req,
11291                                             mmio_flip->crtc->reset_counter,
11292                                             false, NULL,
11293                                             &mmio_flip->i915->rps.mmioflips));
11294                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11295         }
11296
11297         intel_do_mmio_flip(mmio_flip);
11298         kfree(mmio_flip);
11299 }
11300
11301 static int intel_queue_mmio_flip(struct drm_device *dev,
11302                                  struct drm_crtc *crtc,
11303                                  struct drm_i915_gem_object *obj)
11304 {
11305         struct intel_mmio_flip *mmio_flip;
11306
11307         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11308         if (mmio_flip == NULL)
11309                 return -ENOMEM;
11310
11311         mmio_flip->i915 = to_i915(dev);
11312         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11313         mmio_flip->crtc = to_intel_crtc(crtc);
11314         mmio_flip->rotation = crtc->primary->state->rotation;
11315
11316         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11317         schedule_work(&mmio_flip->work);
11318
11319         return 0;
11320 }
11321
11322 static int intel_default_queue_flip(struct drm_device *dev,
11323                                     struct drm_crtc *crtc,
11324                                     struct drm_framebuffer *fb,
11325                                     struct drm_i915_gem_object *obj,
11326                                     struct drm_i915_gem_request *req,
11327                                     uint32_t flags)
11328 {
11329         return -ENODEV;
11330 }
11331
11332 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11333                                          struct drm_crtc *crtc)
11334 {
11335         struct drm_i915_private *dev_priv = dev->dev_private;
11336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11337         struct intel_unpin_work *work = intel_crtc->unpin_work;
11338         u32 addr;
11339
11340         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11341                 return true;
11342
11343         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11344                 return false;
11345
11346         if (!work->enable_stall_check)
11347                 return false;
11348
11349         if (work->flip_ready_vblank == 0) {
11350                 if (work->flip_queued_req &&
11351                     !i915_gem_request_completed(work->flip_queued_req, true))
11352                         return false;
11353
11354                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11355         }
11356
11357         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11358                 return false;
11359
11360         /* Potential stall - if we see that the flip has happened,
11361          * assume a missed interrupt. */
11362         if (INTEL_INFO(dev)->gen >= 4)
11363                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11364         else
11365                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11366
11367         /* There is a potential issue here with a false positive after a flip
11368          * to the same address. We could address this by checking for a
11369          * non-incrementing frame counter.
11370          */
11371         return addr == work->gtt_offset;
11372 }
11373
11374 void intel_check_page_flip(struct drm_device *dev, int pipe)
11375 {
11376         struct drm_i915_private *dev_priv = dev->dev_private;
11377         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11379         struct intel_unpin_work *work;
11380
11381         WARN_ON(!in_interrupt());
11382
11383         if (crtc == NULL)
11384                 return;
11385
11386         spin_lock(&dev->event_lock);
11387         work = intel_crtc->unpin_work;
11388         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11389                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11390                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11391                 page_flip_completed(intel_crtc);
11392                 work = NULL;
11393         }
11394         if (work != NULL &&
11395             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11396                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11397         spin_unlock(&dev->event_lock);
11398 }
11399
11400 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11401                                 struct drm_framebuffer *fb,
11402                                 struct drm_pending_vblank_event *event,
11403                                 uint32_t page_flip_flags)
11404 {
11405         struct drm_device *dev = crtc->dev;
11406         struct drm_i915_private *dev_priv = dev->dev_private;
11407         struct drm_framebuffer *old_fb = crtc->primary->fb;
11408         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11410         struct drm_plane *primary = crtc->primary;
11411         enum pipe pipe = intel_crtc->pipe;
11412         struct intel_unpin_work *work;
11413         struct intel_engine_cs *ring;
11414         bool mmio_flip;
11415         struct drm_i915_gem_request *request = NULL;
11416         int ret;
11417
11418         /*
11419          * drm_mode_page_flip_ioctl() should already catch this, but double
11420          * check to be safe.  In the future we may enable pageflipping from
11421          * a disabled primary plane.
11422          */
11423         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11424                 return -EBUSY;
11425
11426         /* Can't change pixel format via MI display flips. */
11427         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11428                 return -EINVAL;
11429
11430         /*
11431          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11432          * Note that pitch changes could also affect these register.
11433          */
11434         if (INTEL_INFO(dev)->gen > 3 &&
11435             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11436              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11437                 return -EINVAL;
11438
11439         if (i915_terminally_wedged(&dev_priv->gpu_error))
11440                 goto out_hang;
11441
11442         work = kzalloc(sizeof(*work), GFP_KERNEL);
11443         if (work == NULL)
11444                 return -ENOMEM;
11445
11446         work->event = event;
11447         work->crtc = crtc;
11448         work->old_fb = old_fb;
11449         INIT_WORK(&work->work, intel_unpin_work_fn);
11450
11451         ret = drm_crtc_vblank_get(crtc);
11452         if (ret)
11453                 goto free_work;
11454
11455         /* We borrow the event spin lock for protecting unpin_work */
11456         spin_lock_irq(&dev->event_lock);
11457         if (intel_crtc->unpin_work) {
11458                 /* Before declaring the flip queue wedged, check if
11459                  * the hardware completed the operation behind our backs.
11460                  */
11461                 if (__intel_pageflip_stall_check(dev, crtc)) {
11462                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11463                         page_flip_completed(intel_crtc);
11464                 } else {
11465                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11466                         spin_unlock_irq(&dev->event_lock);
11467
11468                         drm_crtc_vblank_put(crtc);
11469                         kfree(work);
11470                         return -EBUSY;
11471                 }
11472         }
11473         intel_crtc->unpin_work = work;
11474         spin_unlock_irq(&dev->event_lock);
11475
11476         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11477                 flush_workqueue(dev_priv->wq);
11478
11479         /* Reference the objects for the scheduled work. */
11480         drm_framebuffer_reference(work->old_fb);
11481         drm_gem_object_reference(&obj->base);
11482
11483         crtc->primary->fb = fb;
11484         update_state_fb(crtc->primary);
11485
11486         work->pending_flip_obj = obj;
11487
11488         ret = i915_mutex_lock_interruptible(dev);
11489         if (ret)
11490                 goto cleanup;
11491
11492         atomic_inc(&intel_crtc->unpin_work_count);
11493         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11494
11495         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11496                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11497
11498         if (IS_VALLEYVIEW(dev)) {
11499                 ring = &dev_priv->ring[BCS];
11500                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11501                         /* vlv: DISPLAY_FLIP fails to change tiling */
11502                         ring = NULL;
11503         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11504                 ring = &dev_priv->ring[BCS];
11505         } else if (INTEL_INFO(dev)->gen >= 7) {
11506                 ring = i915_gem_request_get_ring(obj->last_write_req);
11507                 if (ring == NULL || ring->id != RCS)
11508                         ring = &dev_priv->ring[BCS];
11509         } else {
11510                 ring = &dev_priv->ring[RCS];
11511         }
11512
11513         mmio_flip = use_mmio_flip(ring, obj);
11514
11515         /* When using CS flips, we want to emit semaphores between rings.
11516          * However, when using mmio flips we will create a task to do the
11517          * synchronisation, so all we want here is to pin the framebuffer
11518          * into the display plane and skip any waits.
11519          */
11520         if (!mmio_flip) {
11521                 ret = i915_gem_object_sync(obj, ring, &request);
11522                 if (ret)
11523                         goto cleanup_pending;
11524         }
11525
11526         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11527                                          crtc->primary->state);
11528         if (ret)
11529                 goto cleanup_pending;
11530
11531         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11532                                                   obj, 0);
11533         work->gtt_offset += intel_crtc->dspaddr_offset;
11534
11535         if (mmio_flip) {
11536                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11537                 if (ret)
11538                         goto cleanup_unpin;
11539
11540                 i915_gem_request_assign(&work->flip_queued_req,
11541                                         obj->last_write_req);
11542         } else {
11543                 if (!request) {
11544                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11545                         if (ret)
11546                                 goto cleanup_unpin;
11547                 }
11548
11549                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11550                                                    page_flip_flags);
11551                 if (ret)
11552                         goto cleanup_unpin;
11553
11554                 i915_gem_request_assign(&work->flip_queued_req, request);
11555         }
11556
11557         if (request)
11558                 i915_add_request_no_flush(request);
11559
11560         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11561         work->enable_stall_check = true;
11562
11563         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11564                           to_intel_plane(primary)->frontbuffer_bit);
11565         mutex_unlock(&dev->struct_mutex);
11566
11567         intel_fbc_disable_crtc(intel_crtc);
11568         intel_frontbuffer_flip_prepare(dev,
11569                                        to_intel_plane(primary)->frontbuffer_bit);
11570
11571         trace_i915_flip_request(intel_crtc->plane, obj);
11572
11573         return 0;
11574
11575 cleanup_unpin:
11576         intel_unpin_fb_obj(fb, crtc->primary->state);
11577 cleanup_pending:
11578         if (request)
11579                 i915_gem_request_cancel(request);
11580         atomic_dec(&intel_crtc->unpin_work_count);
11581         mutex_unlock(&dev->struct_mutex);
11582 cleanup:
11583         crtc->primary->fb = old_fb;
11584         update_state_fb(crtc->primary);
11585
11586         drm_gem_object_unreference_unlocked(&obj->base);
11587         drm_framebuffer_unreference(work->old_fb);
11588
11589         spin_lock_irq(&dev->event_lock);
11590         intel_crtc->unpin_work = NULL;
11591         spin_unlock_irq(&dev->event_lock);
11592
11593         drm_crtc_vblank_put(crtc);
11594 free_work:
11595         kfree(work);
11596
11597         if (ret == -EIO) {
11598                 struct drm_atomic_state *state;
11599                 struct drm_plane_state *plane_state;
11600
11601 out_hang:
11602                 state = drm_atomic_state_alloc(dev);
11603                 if (!state)
11604                         return -ENOMEM;
11605                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11606
11607 retry:
11608                 plane_state = drm_atomic_get_plane_state(state, primary);
11609                 ret = PTR_ERR_OR_ZERO(plane_state);
11610                 if (!ret) {
11611                         drm_atomic_set_fb_for_plane(plane_state, fb);
11612
11613                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11614                         if (!ret)
11615                                 ret = drm_atomic_commit(state);
11616                 }
11617
11618                 if (ret == -EDEADLK) {
11619                         drm_modeset_backoff(state->acquire_ctx);
11620                         drm_atomic_state_clear(state);
11621                         goto retry;
11622                 }
11623
11624                 if (ret)
11625                         drm_atomic_state_free(state);
11626
11627                 if (ret == 0 && event) {
11628                         spin_lock_irq(&dev->event_lock);
11629                         drm_send_vblank_event(dev, pipe, event);
11630                         spin_unlock_irq(&dev->event_lock);
11631                 }
11632         }
11633         return ret;
11634 }
11635
11636
11637 /**
11638  * intel_wm_need_update - Check whether watermarks need updating
11639  * @plane: drm plane
11640  * @state: new plane state
11641  *
11642  * Check current plane state versus the new one to determine whether
11643  * watermarks need to be recalculated.
11644  *
11645  * Returns true or false.
11646  */
11647 static bool intel_wm_need_update(struct drm_plane *plane,
11648                                  struct drm_plane_state *state)
11649 {
11650         struct intel_plane_state *new = to_intel_plane_state(state);
11651         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11652
11653         /* Update watermarks on tiling or size changes. */
11654         if (!plane->state->fb || !state->fb ||
11655             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11656             plane->state->rotation != state->rotation ||
11657             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11658             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11659             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11660             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11661                 return true;
11662
11663         return false;
11664 }
11665
11666 static bool needs_scaling(struct intel_plane_state *state)
11667 {
11668         int src_w = drm_rect_width(&state->src) >> 16;
11669         int src_h = drm_rect_height(&state->src) >> 16;
11670         int dst_w = drm_rect_width(&state->dst);
11671         int dst_h = drm_rect_height(&state->dst);
11672
11673         return (src_w != dst_w || src_h != dst_h);
11674 }
11675
11676 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11677                                     struct drm_plane_state *plane_state)
11678 {
11679         struct drm_crtc *crtc = crtc_state->crtc;
11680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11681         struct drm_plane *plane = plane_state->plane;
11682         struct drm_device *dev = crtc->dev;
11683         struct drm_i915_private *dev_priv = dev->dev_private;
11684         struct intel_plane_state *old_plane_state =
11685                 to_intel_plane_state(plane->state);
11686         int idx = intel_crtc->base.base.id, ret;
11687         int i = drm_plane_index(plane);
11688         bool mode_changed = needs_modeset(crtc_state);
11689         bool was_crtc_enabled = crtc->state->active;
11690         bool is_crtc_enabled = crtc_state->active;
11691         bool turn_off, turn_on, visible, was_visible;
11692         struct drm_framebuffer *fb = plane_state->fb;
11693
11694         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11695             plane->type != DRM_PLANE_TYPE_CURSOR) {
11696                 ret = skl_update_scaler_plane(
11697                         to_intel_crtc_state(crtc_state),
11698                         to_intel_plane_state(plane_state));
11699                 if (ret)
11700                         return ret;
11701         }
11702
11703         was_visible = old_plane_state->visible;
11704         visible = to_intel_plane_state(plane_state)->visible;
11705
11706         if (!was_crtc_enabled && WARN_ON(was_visible))
11707                 was_visible = false;
11708
11709         if (!is_crtc_enabled && WARN_ON(visible))
11710                 visible = false;
11711
11712         if (!was_visible && !visible)
11713                 return 0;
11714
11715         turn_off = was_visible && (!visible || mode_changed);
11716         turn_on = visible && (!was_visible || mode_changed);
11717
11718         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11719                          plane->base.id, fb ? fb->base.id : -1);
11720
11721         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11722                          plane->base.id, was_visible, visible,
11723                          turn_off, turn_on, mode_changed);
11724
11725         if (turn_on) {
11726                 intel_crtc->atomic.update_wm_pre = true;
11727                 /* must disable cxsr around plane enable/disable */
11728                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11729                         intel_crtc->atomic.disable_cxsr = true;
11730                         /* to potentially re-enable cxsr */
11731                         intel_crtc->atomic.wait_vblank = true;
11732                         intel_crtc->atomic.update_wm_post = true;
11733                 }
11734         } else if (turn_off) {
11735                 intel_crtc->atomic.update_wm_post = true;
11736                 /* must disable cxsr around plane enable/disable */
11737                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11738                         if (is_crtc_enabled)
11739                                 intel_crtc->atomic.wait_vblank = true;
11740                         intel_crtc->atomic.disable_cxsr = true;
11741                 }
11742         } else if (intel_wm_need_update(plane, plane_state)) {
11743                 intel_crtc->atomic.update_wm_pre = true;
11744         }
11745
11746         if (visible || was_visible)
11747                 intel_crtc->atomic.fb_bits |=
11748                         to_intel_plane(plane)->frontbuffer_bit;
11749
11750         switch (plane->type) {
11751         case DRM_PLANE_TYPE_PRIMARY:
11752                 intel_crtc->atomic.pre_disable_primary = turn_off;
11753                 intel_crtc->atomic.post_enable_primary = turn_on;
11754
11755                 if (turn_off) {
11756                         /*
11757                          * FIXME: Actually if we will still have any other
11758                          * plane enabled on the pipe we could let IPS enabled
11759                          * still, but for now lets consider that when we make
11760                          * primary invisible by setting DSPCNTR to 0 on
11761                          * update_primary_plane function IPS needs to be
11762                          * disable.
11763                          */
11764                         intel_crtc->atomic.disable_ips = true;
11765
11766                         intel_crtc->atomic.disable_fbc = true;
11767                 }
11768
11769                 /*
11770                  * FBC does not work on some platforms for rotated
11771                  * planes, so disable it when rotation is not 0 and
11772                  * update it when rotation is set back to 0.
11773                  *
11774                  * FIXME: This is redundant with the fbc update done in
11775                  * the primary plane enable function except that that
11776                  * one is done too late. We eventually need to unify
11777                  * this.
11778                  */
11779
11780                 if (visible &&
11781                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11782                     dev_priv->fbc.crtc == intel_crtc &&
11783                     plane_state->rotation != BIT(DRM_ROTATE_0))
11784                         intel_crtc->atomic.disable_fbc = true;
11785
11786                 /*
11787                  * BDW signals flip done immediately if the plane
11788                  * is disabled, even if the plane enable is already
11789                  * armed to occur at the next vblank :(
11790                  */
11791                 if (turn_on && IS_BROADWELL(dev))
11792                         intel_crtc->atomic.wait_vblank = true;
11793
11794                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11795                 break;
11796         case DRM_PLANE_TYPE_CURSOR:
11797                 break;
11798         case DRM_PLANE_TYPE_OVERLAY:
11799                 /*
11800                  * WaCxSRDisabledForSpriteScaling:ivb
11801                  *
11802                  * cstate->update_wm was already set above, so this flag will
11803                  * take effect when we commit and program watermarks.
11804                  */
11805                 if (IS_IVYBRIDGE(dev) &&
11806                     needs_scaling(to_intel_plane_state(plane_state)) &&
11807                     !needs_scaling(old_plane_state)) {
11808                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11809                 } else if (turn_off && !mode_changed) {
11810                         intel_crtc->atomic.wait_vblank = true;
11811                         intel_crtc->atomic.update_sprite_watermarks |=
11812                                 1 << i;
11813                 }
11814
11815                 break;
11816         }
11817         return 0;
11818 }
11819
11820 static bool encoders_cloneable(const struct intel_encoder *a,
11821                                const struct intel_encoder *b)
11822 {
11823         /* masks could be asymmetric, so check both ways */
11824         return a == b || (a->cloneable & (1 << b->type) &&
11825                           b->cloneable & (1 << a->type));
11826 }
11827
11828 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11829                                          struct intel_crtc *crtc,
11830                                          struct intel_encoder *encoder)
11831 {
11832         struct intel_encoder *source_encoder;
11833         struct drm_connector *connector;
11834         struct drm_connector_state *connector_state;
11835         int i;
11836
11837         for_each_connector_in_state(state, connector, connector_state, i) {
11838                 if (connector_state->crtc != &crtc->base)
11839                         continue;
11840
11841                 source_encoder =
11842                         to_intel_encoder(connector_state->best_encoder);
11843                 if (!encoders_cloneable(encoder, source_encoder))
11844                         return false;
11845         }
11846
11847         return true;
11848 }
11849
11850 static bool check_encoder_cloning(struct drm_atomic_state *state,
11851                                   struct intel_crtc *crtc)
11852 {
11853         struct intel_encoder *encoder;
11854         struct drm_connector *connector;
11855         struct drm_connector_state *connector_state;
11856         int i;
11857
11858         for_each_connector_in_state(state, connector, connector_state, i) {
11859                 if (connector_state->crtc != &crtc->base)
11860                         continue;
11861
11862                 encoder = to_intel_encoder(connector_state->best_encoder);
11863                 if (!check_single_encoder_cloning(state, crtc, encoder))
11864                         return false;
11865         }
11866
11867         return true;
11868 }
11869
11870 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11871                                    struct drm_crtc_state *crtc_state)
11872 {
11873         struct drm_device *dev = crtc->dev;
11874         struct drm_i915_private *dev_priv = dev->dev_private;
11875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11876         struct intel_crtc_state *pipe_config =
11877                 to_intel_crtc_state(crtc_state);
11878         struct drm_atomic_state *state = crtc_state->state;
11879         int ret;
11880         bool mode_changed = needs_modeset(crtc_state);
11881
11882         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11883                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11884                 return -EINVAL;
11885         }
11886
11887         if (mode_changed && !crtc_state->active)
11888                 intel_crtc->atomic.update_wm_post = true;
11889
11890         if (mode_changed && crtc_state->enable &&
11891             dev_priv->display.crtc_compute_clock &&
11892             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11893                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11894                                                            pipe_config);
11895                 if (ret)
11896                         return ret;
11897         }
11898
11899         ret = 0;
11900         if (dev_priv->display.compute_pipe_wm) {
11901                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11902                 if (ret)
11903                         return ret;
11904         }
11905
11906         if (INTEL_INFO(dev)->gen >= 9) {
11907                 if (mode_changed)
11908                         ret = skl_update_scaler_crtc(pipe_config);
11909
11910                 if (!ret)
11911                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11912                                                          pipe_config);
11913         }
11914
11915         return ret;
11916 }
11917
11918 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11919         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11920         .load_lut = intel_crtc_load_lut,
11921         .atomic_begin = intel_begin_crtc_commit,
11922         .atomic_flush = intel_finish_crtc_commit,
11923         .atomic_check = intel_crtc_atomic_check,
11924 };
11925
11926 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11927 {
11928         struct intel_connector *connector;
11929
11930         for_each_intel_connector(dev, connector) {
11931                 if (connector->base.encoder) {
11932                         connector->base.state->best_encoder =
11933                                 connector->base.encoder;
11934                         connector->base.state->crtc =
11935                                 connector->base.encoder->crtc;
11936                 } else {
11937                         connector->base.state->best_encoder = NULL;
11938                         connector->base.state->crtc = NULL;
11939                 }
11940         }
11941 }
11942
11943 static void
11944 connected_sink_compute_bpp(struct intel_connector *connector,
11945                            struct intel_crtc_state *pipe_config)
11946 {
11947         int bpp = pipe_config->pipe_bpp;
11948
11949         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11950                 connector->base.base.id,
11951                 connector->base.name);
11952
11953         /* Don't use an invalid EDID bpc value */
11954         if (connector->base.display_info.bpc &&
11955             connector->base.display_info.bpc * 3 < bpp) {
11956                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11957                               bpp, connector->base.display_info.bpc*3);
11958                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11959         }
11960
11961         /* Clamp bpp to 8 on screens without EDID 1.4 */
11962         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11963                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11964                               bpp);
11965                 pipe_config->pipe_bpp = 24;
11966         }
11967 }
11968
11969 static int
11970 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11971                           struct intel_crtc_state *pipe_config)
11972 {
11973         struct drm_device *dev = crtc->base.dev;
11974         struct drm_atomic_state *state;
11975         struct drm_connector *connector;
11976         struct drm_connector_state *connector_state;
11977         int bpp, i;
11978
11979         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11980                 bpp = 10*3;
11981         else if (INTEL_INFO(dev)->gen >= 5)
11982                 bpp = 12*3;
11983         else
11984                 bpp = 8*3;
11985
11986
11987         pipe_config->pipe_bpp = bpp;
11988
11989         state = pipe_config->base.state;
11990
11991         /* Clamp display bpp to EDID value */
11992         for_each_connector_in_state(state, connector, connector_state, i) {
11993                 if (connector_state->crtc != &crtc->base)
11994                         continue;
11995
11996                 connected_sink_compute_bpp(to_intel_connector(connector),
11997                                            pipe_config);
11998         }
11999
12000         return bpp;
12001 }
12002
12003 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12004 {
12005         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12006                         "type: 0x%x flags: 0x%x\n",
12007                 mode->crtc_clock,
12008                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12009                 mode->crtc_hsync_end, mode->crtc_htotal,
12010                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12011                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12012 }
12013
12014 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12015                                    struct intel_crtc_state *pipe_config,
12016                                    const char *context)
12017 {
12018         struct drm_device *dev = crtc->base.dev;
12019         struct drm_plane *plane;
12020         struct intel_plane *intel_plane;
12021         struct intel_plane_state *state;
12022         struct drm_framebuffer *fb;
12023
12024         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12025                       context, pipe_config, pipe_name(crtc->pipe));
12026
12027         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12028         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12029                       pipe_config->pipe_bpp, pipe_config->dither);
12030         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12031                       pipe_config->has_pch_encoder,
12032                       pipe_config->fdi_lanes,
12033                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12034                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12035                       pipe_config->fdi_m_n.tu);
12036         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12037                       pipe_config->has_dp_encoder,
12038                       pipe_config->lane_count,
12039                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12040                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12041                       pipe_config->dp_m_n.tu);
12042
12043         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12044                       pipe_config->has_dp_encoder,
12045                       pipe_config->lane_count,
12046                       pipe_config->dp_m2_n2.gmch_m,
12047                       pipe_config->dp_m2_n2.gmch_n,
12048                       pipe_config->dp_m2_n2.link_m,
12049                       pipe_config->dp_m2_n2.link_n,
12050                       pipe_config->dp_m2_n2.tu);
12051
12052         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12053                       pipe_config->has_audio,
12054                       pipe_config->has_infoframe);
12055
12056         DRM_DEBUG_KMS("requested mode:\n");
12057         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12058         DRM_DEBUG_KMS("adjusted mode:\n");
12059         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12060         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12061         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12062         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12063                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12064         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12065                       crtc->num_scalers,
12066                       pipe_config->scaler_state.scaler_users,
12067                       pipe_config->scaler_state.scaler_id);
12068         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12069                       pipe_config->gmch_pfit.control,
12070                       pipe_config->gmch_pfit.pgm_ratios,
12071                       pipe_config->gmch_pfit.lvds_border_bits);
12072         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12073                       pipe_config->pch_pfit.pos,
12074                       pipe_config->pch_pfit.size,
12075                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12076         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12077         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12078
12079         if (IS_BROXTON(dev)) {
12080                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12081                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12082                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12083                               pipe_config->ddi_pll_sel,
12084                               pipe_config->dpll_hw_state.ebb0,
12085                               pipe_config->dpll_hw_state.ebb4,
12086                               pipe_config->dpll_hw_state.pll0,
12087                               pipe_config->dpll_hw_state.pll1,
12088                               pipe_config->dpll_hw_state.pll2,
12089                               pipe_config->dpll_hw_state.pll3,
12090                               pipe_config->dpll_hw_state.pll6,
12091                               pipe_config->dpll_hw_state.pll8,
12092                               pipe_config->dpll_hw_state.pll9,
12093                               pipe_config->dpll_hw_state.pll10,
12094                               pipe_config->dpll_hw_state.pcsdw12);
12095         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12096                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12097                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12098                               pipe_config->ddi_pll_sel,
12099                               pipe_config->dpll_hw_state.ctrl1,
12100                               pipe_config->dpll_hw_state.cfgcr1,
12101                               pipe_config->dpll_hw_state.cfgcr2);
12102         } else if (HAS_DDI(dev)) {
12103                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12104                               pipe_config->ddi_pll_sel,
12105                               pipe_config->dpll_hw_state.wrpll);
12106         } else {
12107                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12108                               "fp0: 0x%x, fp1: 0x%x\n",
12109                               pipe_config->dpll_hw_state.dpll,
12110                               pipe_config->dpll_hw_state.dpll_md,
12111                               pipe_config->dpll_hw_state.fp0,
12112                               pipe_config->dpll_hw_state.fp1);
12113         }
12114
12115         DRM_DEBUG_KMS("planes on this crtc\n");
12116         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12117                 intel_plane = to_intel_plane(plane);
12118                 if (intel_plane->pipe != crtc->pipe)
12119                         continue;
12120
12121                 state = to_intel_plane_state(plane->state);
12122                 fb = state->base.fb;
12123                 if (!fb) {
12124                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12125                                 "disabled, scaler_id = %d\n",
12126                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12127                                 plane->base.id, intel_plane->pipe,
12128                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12129                                 drm_plane_index(plane), state->scaler_id);
12130                         continue;
12131                 }
12132
12133                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12134                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12135                         plane->base.id, intel_plane->pipe,
12136                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12137                         drm_plane_index(plane));
12138                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12139                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12140                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12141                         state->scaler_id,
12142                         state->src.x1 >> 16, state->src.y1 >> 16,
12143                         drm_rect_width(&state->src) >> 16,
12144                         drm_rect_height(&state->src) >> 16,
12145                         state->dst.x1, state->dst.y1,
12146                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12147         }
12148 }
12149
12150 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12151 {
12152         struct drm_device *dev = state->dev;
12153         struct intel_encoder *encoder;
12154         struct drm_connector *connector;
12155         struct drm_connector_state *connector_state;
12156         unsigned int used_ports = 0;
12157         int i;
12158
12159         /*
12160          * Walk the connector list instead of the encoder
12161          * list to detect the problem on ddi platforms
12162          * where there's just one encoder per digital port.
12163          */
12164         for_each_connector_in_state(state, connector, connector_state, i) {
12165                 if (!connector_state->best_encoder)
12166                         continue;
12167
12168                 encoder = to_intel_encoder(connector_state->best_encoder);
12169
12170                 WARN_ON(!connector_state->crtc);
12171
12172                 switch (encoder->type) {
12173                         unsigned int port_mask;
12174                 case INTEL_OUTPUT_UNKNOWN:
12175                         if (WARN_ON(!HAS_DDI(dev)))
12176                                 break;
12177                 case INTEL_OUTPUT_DISPLAYPORT:
12178                 case INTEL_OUTPUT_HDMI:
12179                 case INTEL_OUTPUT_EDP:
12180                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12181
12182                         /* the same port mustn't appear more than once */
12183                         if (used_ports & port_mask)
12184                                 return false;
12185
12186                         used_ports |= port_mask;
12187                 default:
12188                         break;
12189                 }
12190         }
12191
12192         return true;
12193 }
12194
12195 static void
12196 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12197 {
12198         struct drm_crtc_state tmp_state;
12199         struct intel_crtc_scaler_state scaler_state;
12200         struct intel_dpll_hw_state dpll_hw_state;
12201         enum intel_dpll_id shared_dpll;
12202         uint32_t ddi_pll_sel;
12203         bool force_thru;
12204
12205         /* FIXME: before the switch to atomic started, a new pipe_config was
12206          * kzalloc'd. Code that depends on any field being zero should be
12207          * fixed, so that the crtc_state can be safely duplicated. For now,
12208          * only fields that are know to not cause problems are preserved. */
12209
12210         tmp_state = crtc_state->base;
12211         scaler_state = crtc_state->scaler_state;
12212         shared_dpll = crtc_state->shared_dpll;
12213         dpll_hw_state = crtc_state->dpll_hw_state;
12214         ddi_pll_sel = crtc_state->ddi_pll_sel;
12215         force_thru = crtc_state->pch_pfit.force_thru;
12216
12217         memset(crtc_state, 0, sizeof *crtc_state);
12218
12219         crtc_state->base = tmp_state;
12220         crtc_state->scaler_state = scaler_state;
12221         crtc_state->shared_dpll = shared_dpll;
12222         crtc_state->dpll_hw_state = dpll_hw_state;
12223         crtc_state->ddi_pll_sel = ddi_pll_sel;
12224         crtc_state->pch_pfit.force_thru = force_thru;
12225 }
12226
12227 static int
12228 intel_modeset_pipe_config(struct drm_crtc *crtc,
12229                           struct intel_crtc_state *pipe_config)
12230 {
12231         struct drm_atomic_state *state = pipe_config->base.state;
12232         struct intel_encoder *encoder;
12233         struct drm_connector *connector;
12234         struct drm_connector_state *connector_state;
12235         int base_bpp, ret = -EINVAL;
12236         int i;
12237         bool retry = true;
12238
12239         clear_intel_crtc_state(pipe_config);
12240
12241         pipe_config->cpu_transcoder =
12242                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12243
12244         /*
12245          * Sanitize sync polarity flags based on requested ones. If neither
12246          * positive or negative polarity is requested, treat this as meaning
12247          * negative polarity.
12248          */
12249         if (!(pipe_config->base.adjusted_mode.flags &
12250               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12251                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12252
12253         if (!(pipe_config->base.adjusted_mode.flags &
12254               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12255                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12256
12257         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12258                                              pipe_config);
12259         if (base_bpp < 0)
12260                 goto fail;
12261
12262         /*
12263          * Determine the real pipe dimensions. Note that stereo modes can
12264          * increase the actual pipe size due to the frame doubling and
12265          * insertion of additional space for blanks between the frame. This
12266          * is stored in the crtc timings. We use the requested mode to do this
12267          * computation to clearly distinguish it from the adjusted mode, which
12268          * can be changed by the connectors in the below retry loop.
12269          */
12270         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12271                                &pipe_config->pipe_src_w,
12272                                &pipe_config->pipe_src_h);
12273
12274 encoder_retry:
12275         /* Ensure the port clock defaults are reset when retrying. */
12276         pipe_config->port_clock = 0;
12277         pipe_config->pixel_multiplier = 1;
12278
12279         /* Fill in default crtc timings, allow encoders to overwrite them. */
12280         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12281                               CRTC_STEREO_DOUBLE);
12282
12283         /* Pass our mode to the connectors and the CRTC to give them a chance to
12284          * adjust it according to limitations or connector properties, and also
12285          * a chance to reject the mode entirely.
12286          */
12287         for_each_connector_in_state(state, connector, connector_state, i) {
12288                 if (connector_state->crtc != crtc)
12289                         continue;
12290
12291                 encoder = to_intel_encoder(connector_state->best_encoder);
12292
12293                 if (!(encoder->compute_config(encoder, pipe_config))) {
12294                         DRM_DEBUG_KMS("Encoder config failure\n");
12295                         goto fail;
12296                 }
12297         }
12298
12299         /* Set default port clock if not overwritten by the encoder. Needs to be
12300          * done afterwards in case the encoder adjusts the mode. */
12301         if (!pipe_config->port_clock)
12302                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12303                         * pipe_config->pixel_multiplier;
12304
12305         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12306         if (ret < 0) {
12307                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12308                 goto fail;
12309         }
12310
12311         if (ret == RETRY) {
12312                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12313                         ret = -EINVAL;
12314                         goto fail;
12315                 }
12316
12317                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12318                 retry = false;
12319                 goto encoder_retry;
12320         }
12321
12322         /* Dithering seems to not pass-through bits correctly when it should, so
12323          * only enable it on 6bpc panels. */
12324         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12325         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12326                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12327
12328 fail:
12329         return ret;
12330 }
12331
12332 static void
12333 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12334 {
12335         struct drm_crtc *crtc;
12336         struct drm_crtc_state *crtc_state;
12337         int i;
12338
12339         /* Double check state. */
12340         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12341                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12342
12343                 /* Update hwmode for vblank functions */
12344                 if (crtc->state->active)
12345                         crtc->hwmode = crtc->state->adjusted_mode;
12346                 else
12347                         crtc->hwmode.crtc_clock = 0;
12348
12349                 /*
12350                  * Update legacy state to satisfy fbc code. This can
12351                  * be removed when fbc uses the atomic state.
12352                  */
12353                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12354                         struct drm_plane_state *plane_state = crtc->primary->state;
12355
12356                         crtc->primary->fb = plane_state->fb;
12357                         crtc->x = plane_state->src_x >> 16;
12358                         crtc->y = plane_state->src_y >> 16;
12359                 }
12360         }
12361 }
12362
12363 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12364 {
12365         int diff;
12366
12367         if (clock1 == clock2)
12368                 return true;
12369
12370         if (!clock1 || !clock2)
12371                 return false;
12372
12373         diff = abs(clock1 - clock2);
12374
12375         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12376                 return true;
12377
12378         return false;
12379 }
12380
12381 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12382         list_for_each_entry((intel_crtc), \
12383                             &(dev)->mode_config.crtc_list, \
12384                             base.head) \
12385                 if (mask & (1 <<(intel_crtc)->pipe))
12386
12387 static bool
12388 intel_compare_m_n(unsigned int m, unsigned int n,
12389                   unsigned int m2, unsigned int n2,
12390                   bool exact)
12391 {
12392         if (m == m2 && n == n2)
12393                 return true;
12394
12395         if (exact || !m || !n || !m2 || !n2)
12396                 return false;
12397
12398         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12399
12400         if (m > m2) {
12401                 while (m > m2) {
12402                         m2 <<= 1;
12403                         n2 <<= 1;
12404                 }
12405         } else if (m < m2) {
12406                 while (m < m2) {
12407                         m <<= 1;
12408                         n <<= 1;
12409                 }
12410         }
12411
12412         return m == m2 && n == n2;
12413 }
12414
12415 static bool
12416 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12417                        struct intel_link_m_n *m2_n2,
12418                        bool adjust)
12419 {
12420         if (m_n->tu == m2_n2->tu &&
12421             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12422                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12423             intel_compare_m_n(m_n->link_m, m_n->link_n,
12424                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12425                 if (adjust)
12426                         *m2_n2 = *m_n;
12427
12428                 return true;
12429         }
12430
12431         return false;
12432 }
12433
12434 static bool
12435 intel_pipe_config_compare(struct drm_device *dev,
12436                           struct intel_crtc_state *current_config,
12437                           struct intel_crtc_state *pipe_config,
12438                           bool adjust)
12439 {
12440         bool ret = true;
12441
12442 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12443         do { \
12444                 if (!adjust) \
12445                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12446                 else \
12447                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12448         } while (0)
12449
12450 #define PIPE_CONF_CHECK_X(name) \
12451         if (current_config->name != pipe_config->name) { \
12452                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12453                           "(expected 0x%08x, found 0x%08x)\n", \
12454                           current_config->name, \
12455                           pipe_config->name); \
12456                 ret = false; \
12457         }
12458
12459 #define PIPE_CONF_CHECK_I(name) \
12460         if (current_config->name != pipe_config->name) { \
12461                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12462                           "(expected %i, found %i)\n", \
12463                           current_config->name, \
12464                           pipe_config->name); \
12465                 ret = false; \
12466         }
12467
12468 #define PIPE_CONF_CHECK_M_N(name) \
12469         if (!intel_compare_link_m_n(&current_config->name, \
12470                                     &pipe_config->name,\
12471                                     adjust)) { \
12472                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12473                           "(expected tu %i gmch %i/%i link %i/%i, " \
12474                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12475                           current_config->name.tu, \
12476                           current_config->name.gmch_m, \
12477                           current_config->name.gmch_n, \
12478                           current_config->name.link_m, \
12479                           current_config->name.link_n, \
12480                           pipe_config->name.tu, \
12481                           pipe_config->name.gmch_m, \
12482                           pipe_config->name.gmch_n, \
12483                           pipe_config->name.link_m, \
12484                           pipe_config->name.link_n); \
12485                 ret = false; \
12486         }
12487
12488 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12489         if (!intel_compare_link_m_n(&current_config->name, \
12490                                     &pipe_config->name, adjust) && \
12491             !intel_compare_link_m_n(&current_config->alt_name, \
12492                                     &pipe_config->name, adjust)) { \
12493                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12494                           "(expected tu %i gmch %i/%i link %i/%i, " \
12495                           "or tu %i gmch %i/%i link %i/%i, " \
12496                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12497                           current_config->name.tu, \
12498                           current_config->name.gmch_m, \
12499                           current_config->name.gmch_n, \
12500                           current_config->name.link_m, \
12501                           current_config->name.link_n, \
12502                           current_config->alt_name.tu, \
12503                           current_config->alt_name.gmch_m, \
12504                           current_config->alt_name.gmch_n, \
12505                           current_config->alt_name.link_m, \
12506                           current_config->alt_name.link_n, \
12507                           pipe_config->name.tu, \
12508                           pipe_config->name.gmch_m, \
12509                           pipe_config->name.gmch_n, \
12510                           pipe_config->name.link_m, \
12511                           pipe_config->name.link_n); \
12512                 ret = false; \
12513         }
12514
12515 /* This is required for BDW+ where there is only one set of registers for
12516  * switching between high and low RR.
12517  * This macro can be used whenever a comparison has to be made between one
12518  * hw state and multiple sw state variables.
12519  */
12520 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12521         if ((current_config->name != pipe_config->name) && \
12522                 (current_config->alt_name != pipe_config->name)) { \
12523                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12524                                   "(expected %i or %i, found %i)\n", \
12525                                   current_config->name, \
12526                                   current_config->alt_name, \
12527                                   pipe_config->name); \
12528                         ret = false; \
12529         }
12530
12531 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12532         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12533                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12534                           "(expected %i, found %i)\n", \
12535                           current_config->name & (mask), \
12536                           pipe_config->name & (mask)); \
12537                 ret = false; \
12538         }
12539
12540 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12541         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12542                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12543                           "(expected %i, found %i)\n", \
12544                           current_config->name, \
12545                           pipe_config->name); \
12546                 ret = false; \
12547         }
12548
12549 #define PIPE_CONF_QUIRK(quirk)  \
12550         ((current_config->quirks | pipe_config->quirks) & (quirk))
12551
12552         PIPE_CONF_CHECK_I(cpu_transcoder);
12553
12554         PIPE_CONF_CHECK_I(has_pch_encoder);
12555         PIPE_CONF_CHECK_I(fdi_lanes);
12556         PIPE_CONF_CHECK_M_N(fdi_m_n);
12557
12558         PIPE_CONF_CHECK_I(has_dp_encoder);
12559         PIPE_CONF_CHECK_I(lane_count);
12560
12561         if (INTEL_INFO(dev)->gen < 8) {
12562                 PIPE_CONF_CHECK_M_N(dp_m_n);
12563
12564                 PIPE_CONF_CHECK_I(has_drrs);
12565                 if (current_config->has_drrs)
12566                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12567         } else
12568                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12569
12570         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12571         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12572         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12573         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12574         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12575         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12576
12577         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12578         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12579         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12580         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12581         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12582         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12583
12584         PIPE_CONF_CHECK_I(pixel_multiplier);
12585         PIPE_CONF_CHECK_I(has_hdmi_sink);
12586         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12587             IS_VALLEYVIEW(dev))
12588                 PIPE_CONF_CHECK_I(limited_color_range);
12589         PIPE_CONF_CHECK_I(has_infoframe);
12590
12591         PIPE_CONF_CHECK_I(has_audio);
12592
12593         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12594                               DRM_MODE_FLAG_INTERLACE);
12595
12596         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12597                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12598                                       DRM_MODE_FLAG_PHSYNC);
12599                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12600                                       DRM_MODE_FLAG_NHSYNC);
12601                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12602                                       DRM_MODE_FLAG_PVSYNC);
12603                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12604                                       DRM_MODE_FLAG_NVSYNC);
12605         }
12606
12607         PIPE_CONF_CHECK_X(gmch_pfit.control);
12608         /* pfit ratios are autocomputed by the hw on gen4+ */
12609         if (INTEL_INFO(dev)->gen < 4)
12610                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12611         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12612
12613         if (!adjust) {
12614                 PIPE_CONF_CHECK_I(pipe_src_w);
12615                 PIPE_CONF_CHECK_I(pipe_src_h);
12616
12617                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12618                 if (current_config->pch_pfit.enabled) {
12619                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12620                         PIPE_CONF_CHECK_X(pch_pfit.size);
12621                 }
12622
12623                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12624         }
12625
12626         /* BDW+ don't expose a synchronous way to read the state */
12627         if (IS_HASWELL(dev))
12628                 PIPE_CONF_CHECK_I(ips_enabled);
12629
12630         PIPE_CONF_CHECK_I(double_wide);
12631
12632         PIPE_CONF_CHECK_X(ddi_pll_sel);
12633
12634         PIPE_CONF_CHECK_I(shared_dpll);
12635         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12636         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12637         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12638         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12639         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12640         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12641         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12642         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12643
12644         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12645                 PIPE_CONF_CHECK_I(pipe_bpp);
12646
12647         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12648         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12649
12650 #undef PIPE_CONF_CHECK_X
12651 #undef PIPE_CONF_CHECK_I
12652 #undef PIPE_CONF_CHECK_I_ALT
12653 #undef PIPE_CONF_CHECK_FLAGS
12654 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12655 #undef PIPE_CONF_QUIRK
12656 #undef INTEL_ERR_OR_DBG_KMS
12657
12658         return ret;
12659 }
12660
12661 static void check_wm_state(struct drm_device *dev)
12662 {
12663         struct drm_i915_private *dev_priv = dev->dev_private;
12664         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12665         struct intel_crtc *intel_crtc;
12666         int plane;
12667
12668         if (INTEL_INFO(dev)->gen < 9)
12669                 return;
12670
12671         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12672         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12673
12674         for_each_intel_crtc(dev, intel_crtc) {
12675                 struct skl_ddb_entry *hw_entry, *sw_entry;
12676                 const enum pipe pipe = intel_crtc->pipe;
12677
12678                 if (!intel_crtc->active)
12679                         continue;
12680
12681                 /* planes */
12682                 for_each_plane(dev_priv, pipe, plane) {
12683                         hw_entry = &hw_ddb.plane[pipe][plane];
12684                         sw_entry = &sw_ddb->plane[pipe][plane];
12685
12686                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12687                                 continue;
12688
12689                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12690                                   "(expected (%u,%u), found (%u,%u))\n",
12691                                   pipe_name(pipe), plane + 1,
12692                                   sw_entry->start, sw_entry->end,
12693                                   hw_entry->start, hw_entry->end);
12694                 }
12695
12696                 /* cursor */
12697                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12698                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12699
12700                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12701                         continue;
12702
12703                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12704                           "(expected (%u,%u), found (%u,%u))\n",
12705                           pipe_name(pipe),
12706                           sw_entry->start, sw_entry->end,
12707                           hw_entry->start, hw_entry->end);
12708         }
12709 }
12710
12711 static void
12712 check_connector_state(struct drm_device *dev,
12713                       struct drm_atomic_state *old_state)
12714 {
12715         struct drm_connector_state *old_conn_state;
12716         struct drm_connector *connector;
12717         int i;
12718
12719         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12720                 struct drm_encoder *encoder = connector->encoder;
12721                 struct drm_connector_state *state = connector->state;
12722
12723                 /* This also checks the encoder/connector hw state with the
12724                  * ->get_hw_state callbacks. */
12725                 intel_connector_check_state(to_intel_connector(connector));
12726
12727                 I915_STATE_WARN(state->best_encoder != encoder,
12728                      "connector's atomic encoder doesn't match legacy encoder\n");
12729         }
12730 }
12731
12732 static void
12733 check_encoder_state(struct drm_device *dev)
12734 {
12735         struct intel_encoder *encoder;
12736         struct intel_connector *connector;
12737
12738         for_each_intel_encoder(dev, encoder) {
12739                 bool enabled = false;
12740                 enum pipe pipe;
12741
12742                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12743                               encoder->base.base.id,
12744                               encoder->base.name);
12745
12746                 for_each_intel_connector(dev, connector) {
12747                         if (connector->base.state->best_encoder != &encoder->base)
12748                                 continue;
12749                         enabled = true;
12750
12751                         I915_STATE_WARN(connector->base.state->crtc !=
12752                                         encoder->base.crtc,
12753                              "connector's crtc doesn't match encoder crtc\n");
12754                 }
12755
12756                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12757                      "encoder's enabled state mismatch "
12758                      "(expected %i, found %i)\n",
12759                      !!encoder->base.crtc, enabled);
12760
12761                 if (!encoder->base.crtc) {
12762                         bool active;
12763
12764                         active = encoder->get_hw_state(encoder, &pipe);
12765                         I915_STATE_WARN(active,
12766                              "encoder detached but still enabled on pipe %c.\n",
12767                              pipe_name(pipe));
12768                 }
12769         }
12770 }
12771
12772 static void
12773 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12774 {
12775         struct drm_i915_private *dev_priv = dev->dev_private;
12776         struct intel_encoder *encoder;
12777         struct drm_crtc_state *old_crtc_state;
12778         struct drm_crtc *crtc;
12779         int i;
12780
12781         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12782                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12783                 struct intel_crtc_state *pipe_config, *sw_config;
12784                 bool active;
12785
12786                 if (!needs_modeset(crtc->state) &&
12787                     !to_intel_crtc_state(crtc->state)->update_pipe)
12788                         continue;
12789
12790                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12791                 pipe_config = to_intel_crtc_state(old_crtc_state);
12792                 memset(pipe_config, 0, sizeof(*pipe_config));
12793                 pipe_config->base.crtc = crtc;
12794                 pipe_config->base.state = old_state;
12795
12796                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12797                               crtc->base.id);
12798
12799                 active = dev_priv->display.get_pipe_config(intel_crtc,
12800                                                            pipe_config);
12801
12802                 /* hw state is inconsistent with the pipe quirk */
12803                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12804                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12805                         active = crtc->state->active;
12806
12807                 I915_STATE_WARN(crtc->state->active != active,
12808                      "crtc active state doesn't match with hw state "
12809                      "(expected %i, found %i)\n", crtc->state->active, active);
12810
12811                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12812                      "transitional active state does not match atomic hw state "
12813                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12814
12815                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12816                         enum pipe pipe;
12817
12818                         active = encoder->get_hw_state(encoder, &pipe);
12819                         I915_STATE_WARN(active != crtc->state->active,
12820                                 "[ENCODER:%i] active %i with crtc active %i\n",
12821                                 encoder->base.base.id, active, crtc->state->active);
12822
12823                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12824                                         "Encoder connected to wrong pipe %c\n",
12825                                         pipe_name(pipe));
12826
12827                         if (active)
12828                                 encoder->get_config(encoder, pipe_config);
12829                 }
12830
12831                 if (!crtc->state->active)
12832                         continue;
12833
12834                 sw_config = to_intel_crtc_state(crtc->state);
12835                 if (!intel_pipe_config_compare(dev, sw_config,
12836                                                pipe_config, false)) {
12837                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12838                         intel_dump_pipe_config(intel_crtc, pipe_config,
12839                                                "[hw state]");
12840                         intel_dump_pipe_config(intel_crtc, sw_config,
12841                                                "[sw state]");
12842                 }
12843         }
12844 }
12845
12846 static void
12847 check_shared_dpll_state(struct drm_device *dev)
12848 {
12849         struct drm_i915_private *dev_priv = dev->dev_private;
12850         struct intel_crtc *crtc;
12851         struct intel_dpll_hw_state dpll_hw_state;
12852         int i;
12853
12854         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12855                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12856                 int enabled_crtcs = 0, active_crtcs = 0;
12857                 bool active;
12858
12859                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12860
12861                 DRM_DEBUG_KMS("%s\n", pll->name);
12862
12863                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12864
12865                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12866                      "more active pll users than references: %i vs %i\n",
12867                      pll->active, hweight32(pll->config.crtc_mask));
12868                 I915_STATE_WARN(pll->active && !pll->on,
12869                      "pll in active use but not on in sw tracking\n");
12870                 I915_STATE_WARN(pll->on && !pll->active,
12871                      "pll in on but not on in use in sw tracking\n");
12872                 I915_STATE_WARN(pll->on != active,
12873                      "pll on state mismatch (expected %i, found %i)\n",
12874                      pll->on, active);
12875
12876                 for_each_intel_crtc(dev, crtc) {
12877                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12878                                 enabled_crtcs++;
12879                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12880                                 active_crtcs++;
12881                 }
12882                 I915_STATE_WARN(pll->active != active_crtcs,
12883                      "pll active crtcs mismatch (expected %i, found %i)\n",
12884                      pll->active, active_crtcs);
12885                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12886                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12887                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12888
12889                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12890                                        sizeof(dpll_hw_state)),
12891                      "pll hw state mismatch\n");
12892         }
12893 }
12894
12895 static void
12896 intel_modeset_check_state(struct drm_device *dev,
12897                           struct drm_atomic_state *old_state)
12898 {
12899         check_wm_state(dev);
12900         check_connector_state(dev, old_state);
12901         check_encoder_state(dev);
12902         check_crtc_state(dev, old_state);
12903         check_shared_dpll_state(dev);
12904 }
12905
12906 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12907                                      int dotclock)
12908 {
12909         /*
12910          * FDI already provided one idea for the dotclock.
12911          * Yell if the encoder disagrees.
12912          */
12913         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12914              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12915              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12916 }
12917
12918 static void update_scanline_offset(struct intel_crtc *crtc)
12919 {
12920         struct drm_device *dev = crtc->base.dev;
12921
12922         /*
12923          * The scanline counter increments at the leading edge of hsync.
12924          *
12925          * On most platforms it starts counting from vtotal-1 on the
12926          * first active line. That means the scanline counter value is
12927          * always one less than what we would expect. Ie. just after
12928          * start of vblank, which also occurs at start of hsync (on the
12929          * last active line), the scanline counter will read vblank_start-1.
12930          *
12931          * On gen2 the scanline counter starts counting from 1 instead
12932          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12933          * to keep the value positive), instead of adding one.
12934          *
12935          * On HSW+ the behaviour of the scanline counter depends on the output
12936          * type. For DP ports it behaves like most other platforms, but on HDMI
12937          * there's an extra 1 line difference. So we need to add two instead of
12938          * one to the value.
12939          */
12940         if (IS_GEN2(dev)) {
12941                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12942                 int vtotal;
12943
12944                 vtotal = adjusted_mode->crtc_vtotal;
12945                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12946                         vtotal /= 2;
12947
12948                 crtc->scanline_offset = vtotal - 1;
12949         } else if (HAS_DDI(dev) &&
12950                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12951                 crtc->scanline_offset = 2;
12952         } else
12953                 crtc->scanline_offset = 1;
12954 }
12955
12956 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12957 {
12958         struct drm_device *dev = state->dev;
12959         struct drm_i915_private *dev_priv = to_i915(dev);
12960         struct intel_shared_dpll_config *shared_dpll = NULL;
12961         struct intel_crtc *intel_crtc;
12962         struct intel_crtc_state *intel_crtc_state;
12963         struct drm_crtc *crtc;
12964         struct drm_crtc_state *crtc_state;
12965         int i;
12966
12967         if (!dev_priv->display.crtc_compute_clock)
12968                 return;
12969
12970         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12971                 int dpll;
12972
12973                 intel_crtc = to_intel_crtc(crtc);
12974                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12975                 dpll = intel_crtc_state->shared_dpll;
12976
12977                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12978                         continue;
12979
12980                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12981
12982                 if (!shared_dpll)
12983                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12984
12985                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12986         }
12987 }
12988
12989 /*
12990  * This implements the workaround described in the "notes" section of the mode
12991  * set sequence documentation. When going from no pipes or single pipe to
12992  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12993  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12994  */
12995 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12996 {
12997         struct drm_crtc_state *crtc_state;
12998         struct intel_crtc *intel_crtc;
12999         struct drm_crtc *crtc;
13000         struct intel_crtc_state *first_crtc_state = NULL;
13001         struct intel_crtc_state *other_crtc_state = NULL;
13002         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13003         int i;
13004
13005         /* look at all crtc's that are going to be enabled in during modeset */
13006         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13007                 intel_crtc = to_intel_crtc(crtc);
13008
13009                 if (!crtc_state->active || !needs_modeset(crtc_state))
13010                         continue;
13011
13012                 if (first_crtc_state) {
13013                         other_crtc_state = to_intel_crtc_state(crtc_state);
13014                         break;
13015                 } else {
13016                         first_crtc_state = to_intel_crtc_state(crtc_state);
13017                         first_pipe = intel_crtc->pipe;
13018                 }
13019         }
13020
13021         /* No workaround needed? */
13022         if (!first_crtc_state)
13023                 return 0;
13024
13025         /* w/a possibly needed, check how many crtc's are already enabled. */
13026         for_each_intel_crtc(state->dev, intel_crtc) {
13027                 struct intel_crtc_state *pipe_config;
13028
13029                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13030                 if (IS_ERR(pipe_config))
13031                         return PTR_ERR(pipe_config);
13032
13033                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13034
13035                 if (!pipe_config->base.active ||
13036                     needs_modeset(&pipe_config->base))
13037                         continue;
13038
13039                 /* 2 or more enabled crtcs means no need for w/a */
13040                 if (enabled_pipe != INVALID_PIPE)
13041                         return 0;
13042
13043                 enabled_pipe = intel_crtc->pipe;
13044         }
13045
13046         if (enabled_pipe != INVALID_PIPE)
13047                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13048         else if (other_crtc_state)
13049                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13050
13051         return 0;
13052 }
13053
13054 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13055 {
13056         struct drm_crtc *crtc;
13057         struct drm_crtc_state *crtc_state;
13058         int ret = 0;
13059
13060         /* add all active pipes to the state */
13061         for_each_crtc(state->dev, crtc) {
13062                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13063                 if (IS_ERR(crtc_state))
13064                         return PTR_ERR(crtc_state);
13065
13066                 if (!crtc_state->active || needs_modeset(crtc_state))
13067                         continue;
13068
13069                 crtc_state->mode_changed = true;
13070
13071                 ret = drm_atomic_add_affected_connectors(state, crtc);
13072                 if (ret)
13073                         break;
13074
13075                 ret = drm_atomic_add_affected_planes(state, crtc);
13076                 if (ret)
13077                         break;
13078         }
13079
13080         return ret;
13081 }
13082
13083 static int intel_modeset_checks(struct drm_atomic_state *state)
13084 {
13085         struct drm_device *dev = state->dev;
13086         struct drm_i915_private *dev_priv = dev->dev_private;
13087         int ret;
13088
13089         if (!check_digital_port_conflicts(state)) {
13090                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13091                 return -EINVAL;
13092         }
13093
13094         /*
13095          * See if the config requires any additional preparation, e.g.
13096          * to adjust global state with pipes off.  We need to do this
13097          * here so we can get the modeset_pipe updated config for the new
13098          * mode set on this crtc.  For other crtcs we need to use the
13099          * adjusted_mode bits in the crtc directly.
13100          */
13101         if (dev_priv->display.modeset_calc_cdclk) {
13102                 unsigned int cdclk;
13103
13104                 ret = dev_priv->display.modeset_calc_cdclk(state);
13105
13106                 cdclk = to_intel_atomic_state(state)->cdclk;
13107                 if (!ret && cdclk != dev_priv->cdclk_freq)
13108                         ret = intel_modeset_all_pipes(state);
13109
13110                 if (ret < 0)
13111                         return ret;
13112         } else
13113                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13114
13115         intel_modeset_clear_plls(state);
13116
13117         if (IS_HASWELL(dev))
13118                 return haswell_mode_set_planes_workaround(state);
13119
13120         return 0;
13121 }
13122
13123 /*
13124  * Handle calculation of various watermark data at the end of the atomic check
13125  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13126  * handlers to ensure that all derived state has been updated.
13127  */
13128 static void calc_watermark_data(struct drm_atomic_state *state)
13129 {
13130         struct drm_device *dev = state->dev;
13131         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13132         struct drm_crtc *crtc;
13133         struct drm_crtc_state *cstate;
13134         struct drm_plane *plane;
13135         struct drm_plane_state *pstate;
13136
13137         /*
13138          * Calculate watermark configuration details now that derived
13139          * plane/crtc state is all properly updated.
13140          */
13141         drm_for_each_crtc(crtc, dev) {
13142                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13143                         crtc->state;
13144
13145                 if (cstate->active)
13146                         intel_state->wm_config.num_pipes_active++;
13147         }
13148         drm_for_each_legacy_plane(plane, dev) {
13149                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13150                         plane->state;
13151
13152                 if (!to_intel_plane_state(pstate)->visible)
13153                         continue;
13154
13155                 intel_state->wm_config.sprites_enabled = true;
13156                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13157                     pstate->crtc_h != pstate->src_h >> 16)
13158                         intel_state->wm_config.sprites_scaled = true;
13159         }
13160 }
13161
13162 /**
13163  * intel_atomic_check - validate state object
13164  * @dev: drm device
13165  * @state: state to validate
13166  */
13167 static int intel_atomic_check(struct drm_device *dev,
13168                               struct drm_atomic_state *state)
13169 {
13170         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13171         struct drm_crtc *crtc;
13172         struct drm_crtc_state *crtc_state;
13173         int ret, i;
13174         bool any_ms = false;
13175
13176         ret = drm_atomic_helper_check_modeset(dev, state);
13177         if (ret)
13178                 return ret;
13179
13180         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13181                 struct intel_crtc_state *pipe_config =
13182                         to_intel_crtc_state(crtc_state);
13183
13184                 /* Catch I915_MODE_FLAG_INHERITED */
13185                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13186                         crtc_state->mode_changed = true;
13187
13188                 if (!crtc_state->enable) {
13189                         if (needs_modeset(crtc_state))
13190                                 any_ms = true;
13191                         continue;
13192                 }
13193
13194                 if (!needs_modeset(crtc_state))
13195                         continue;
13196
13197                 /* FIXME: For only active_changed we shouldn't need to do any
13198                  * state recomputation at all. */
13199
13200                 ret = drm_atomic_add_affected_connectors(state, crtc);
13201                 if (ret)
13202                         return ret;
13203
13204                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13205                 if (ret)
13206                         return ret;
13207
13208                 if (intel_pipe_config_compare(state->dev,
13209                                         to_intel_crtc_state(crtc->state),
13210                                         pipe_config, true)) {
13211                         crtc_state->mode_changed = false;
13212                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13213                 }
13214
13215                 if (needs_modeset(crtc_state)) {
13216                         any_ms = true;
13217
13218                         ret = drm_atomic_add_affected_planes(state, crtc);
13219                         if (ret)
13220                                 return ret;
13221                 }
13222
13223                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13224                                        needs_modeset(crtc_state) ?
13225                                        "[modeset]" : "[fastset]");
13226         }
13227
13228         if (any_ms) {
13229                 ret = intel_modeset_checks(state);
13230
13231                 if (ret)
13232                         return ret;
13233         } else
13234                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13235
13236         ret = drm_atomic_helper_check_planes(state->dev, state);
13237         if (ret)
13238                 return ret;
13239
13240         calc_watermark_data(state);
13241
13242         return 0;
13243 }
13244
13245 static int intel_atomic_prepare_commit(struct drm_device *dev,
13246                                        struct drm_atomic_state *state,
13247                                        bool async)
13248 {
13249         struct drm_i915_private *dev_priv = dev->dev_private;
13250         struct drm_plane_state *plane_state;
13251         struct drm_crtc_state *crtc_state;
13252         struct drm_plane *plane;
13253         struct drm_crtc *crtc;
13254         int i, ret;
13255
13256         if (async) {
13257                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13258                 return -EINVAL;
13259         }
13260
13261         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13262                 ret = intel_crtc_wait_for_pending_flips(crtc);
13263                 if (ret)
13264                         return ret;
13265
13266                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13267                         flush_workqueue(dev_priv->wq);
13268         }
13269
13270         ret = mutex_lock_interruptible(&dev->struct_mutex);
13271         if (ret)
13272                 return ret;
13273
13274         ret = drm_atomic_helper_prepare_planes(dev, state);
13275         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13276                 u32 reset_counter;
13277
13278                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13279                 mutex_unlock(&dev->struct_mutex);
13280
13281                 for_each_plane_in_state(state, plane, plane_state, i) {
13282                         struct intel_plane_state *intel_plane_state =
13283                                 to_intel_plane_state(plane_state);
13284
13285                         if (!intel_plane_state->wait_req)
13286                                 continue;
13287
13288                         ret = __i915_wait_request(intel_plane_state->wait_req,
13289                                                   reset_counter, true,
13290                                                   NULL, NULL);
13291
13292                         /* Swallow -EIO errors to allow updates during hw lockup. */
13293                         if (ret == -EIO)
13294                                 ret = 0;
13295
13296                         if (ret)
13297                                 break;
13298                 }
13299
13300                 if (!ret)
13301                         return 0;
13302
13303                 mutex_lock(&dev->struct_mutex);
13304                 drm_atomic_helper_cleanup_planes(dev, state);
13305         }
13306
13307         mutex_unlock(&dev->struct_mutex);
13308         return ret;
13309 }
13310
13311 /**
13312  * intel_atomic_commit - commit validated state object
13313  * @dev: DRM device
13314  * @state: the top-level driver state object
13315  * @async: asynchronous commit
13316  *
13317  * This function commits a top-level state object that has been validated
13318  * with drm_atomic_helper_check().
13319  *
13320  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13321  * we can only handle plane-related operations and do not yet support
13322  * asynchronous commit.
13323  *
13324  * RETURNS
13325  * Zero for success or -errno.
13326  */
13327 static int intel_atomic_commit(struct drm_device *dev,
13328                                struct drm_atomic_state *state,
13329                                bool async)
13330 {
13331         struct drm_i915_private *dev_priv = dev->dev_private;
13332         struct drm_crtc_state *crtc_state;
13333         struct drm_crtc *crtc;
13334         int ret = 0;
13335         int i;
13336         bool any_ms = false;
13337
13338         ret = intel_atomic_prepare_commit(dev, state, async);
13339         if (ret) {
13340                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13341                 return ret;
13342         }
13343
13344         drm_atomic_helper_swap_state(dev, state);
13345         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13346
13347         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13348                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13349
13350                 if (!needs_modeset(crtc->state))
13351                         continue;
13352
13353                 any_ms = true;
13354                 intel_pre_plane_update(intel_crtc);
13355
13356                 if (crtc_state->active) {
13357                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13358                         dev_priv->display.crtc_disable(crtc);
13359                         intel_crtc->active = false;
13360                         intel_disable_shared_dpll(intel_crtc);
13361                 }
13362         }
13363
13364         /* Only after disabling all output pipelines that will be changed can we
13365          * update the the output configuration. */
13366         intel_modeset_update_crtc_state(state);
13367
13368         if (any_ms) {
13369                 intel_shared_dpll_commit(state);
13370
13371                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13372                 modeset_update_crtc_power_domains(state);
13373         }
13374
13375         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13376         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13377                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13378                 bool modeset = needs_modeset(crtc->state);
13379                 bool update_pipe = !modeset &&
13380                         to_intel_crtc_state(crtc->state)->update_pipe;
13381                 unsigned long put_domains = 0;
13382
13383                 if (modeset)
13384                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13385
13386                 if (modeset && crtc->state->active) {
13387                         update_scanline_offset(to_intel_crtc(crtc));
13388                         dev_priv->display.crtc_enable(crtc);
13389                 }
13390
13391                 if (update_pipe) {
13392                         put_domains = modeset_get_crtc_power_domains(crtc);
13393
13394                         /* make sure intel_modeset_check_state runs */
13395                         any_ms = true;
13396                 }
13397
13398                 if (!modeset)
13399                         intel_pre_plane_update(intel_crtc);
13400
13401                 if (crtc->state->active &&
13402                     (crtc->state->planes_changed || update_pipe))
13403                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13404
13405                 if (put_domains)
13406                         modeset_put_power_domains(dev_priv, put_domains);
13407
13408                 intel_post_plane_update(intel_crtc);
13409
13410                 if (modeset)
13411                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13412         }
13413
13414         /* FIXME: add subpixel order */
13415
13416         drm_atomic_helper_wait_for_vblanks(dev, state);
13417
13418         mutex_lock(&dev->struct_mutex);
13419         drm_atomic_helper_cleanup_planes(dev, state);
13420         mutex_unlock(&dev->struct_mutex);
13421
13422         if (any_ms)
13423                 intel_modeset_check_state(dev, state);
13424
13425         drm_atomic_state_free(state);
13426
13427         return 0;
13428 }
13429
13430 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13431 {
13432         struct drm_device *dev = crtc->dev;
13433         struct drm_atomic_state *state;
13434         struct drm_crtc_state *crtc_state;
13435         int ret;
13436
13437         state = drm_atomic_state_alloc(dev);
13438         if (!state) {
13439                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13440                               crtc->base.id);
13441                 return;
13442         }
13443
13444         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13445
13446 retry:
13447         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13448         ret = PTR_ERR_OR_ZERO(crtc_state);
13449         if (!ret) {
13450                 if (!crtc_state->active)
13451                         goto out;
13452
13453                 crtc_state->mode_changed = true;
13454                 ret = drm_atomic_commit(state);
13455         }
13456
13457         if (ret == -EDEADLK) {
13458                 drm_atomic_state_clear(state);
13459                 drm_modeset_backoff(state->acquire_ctx);
13460                 goto retry;
13461         }
13462
13463         if (ret)
13464 out:
13465                 drm_atomic_state_free(state);
13466 }
13467
13468 #undef for_each_intel_crtc_masked
13469
13470 static const struct drm_crtc_funcs intel_crtc_funcs = {
13471         .gamma_set = intel_crtc_gamma_set,
13472         .set_config = drm_atomic_helper_set_config,
13473         .destroy = intel_crtc_destroy,
13474         .page_flip = intel_crtc_page_flip,
13475         .atomic_duplicate_state = intel_crtc_duplicate_state,
13476         .atomic_destroy_state = intel_crtc_destroy_state,
13477 };
13478
13479 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13480                                       struct intel_shared_dpll *pll,
13481                                       struct intel_dpll_hw_state *hw_state)
13482 {
13483         uint32_t val;
13484
13485         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13486                 return false;
13487
13488         val = I915_READ(PCH_DPLL(pll->id));
13489         hw_state->dpll = val;
13490         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13491         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13492
13493         return val & DPLL_VCO_ENABLE;
13494 }
13495
13496 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13497                                   struct intel_shared_dpll *pll)
13498 {
13499         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13500         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13501 }
13502
13503 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13504                                 struct intel_shared_dpll *pll)
13505 {
13506         /* PCH refclock must be enabled first */
13507         ibx_assert_pch_refclk_enabled(dev_priv);
13508
13509         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13510
13511         /* Wait for the clocks to stabilize. */
13512         POSTING_READ(PCH_DPLL(pll->id));
13513         udelay(150);
13514
13515         /* The pixel multiplier can only be updated once the
13516          * DPLL is enabled and the clocks are stable.
13517          *
13518          * So write it again.
13519          */
13520         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13521         POSTING_READ(PCH_DPLL(pll->id));
13522         udelay(200);
13523 }
13524
13525 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13526                                  struct intel_shared_dpll *pll)
13527 {
13528         struct drm_device *dev = dev_priv->dev;
13529         struct intel_crtc *crtc;
13530
13531         /* Make sure no transcoder isn't still depending on us. */
13532         for_each_intel_crtc(dev, crtc) {
13533                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13534                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13535         }
13536
13537         I915_WRITE(PCH_DPLL(pll->id), 0);
13538         POSTING_READ(PCH_DPLL(pll->id));
13539         udelay(200);
13540 }
13541
13542 static char *ibx_pch_dpll_names[] = {
13543         "PCH DPLL A",
13544         "PCH DPLL B",
13545 };
13546
13547 static void ibx_pch_dpll_init(struct drm_device *dev)
13548 {
13549         struct drm_i915_private *dev_priv = dev->dev_private;
13550         int i;
13551
13552         dev_priv->num_shared_dpll = 2;
13553
13554         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13555                 dev_priv->shared_dplls[i].id = i;
13556                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13557                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13558                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13559                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13560                 dev_priv->shared_dplls[i].get_hw_state =
13561                         ibx_pch_dpll_get_hw_state;
13562         }
13563 }
13564
13565 static void intel_shared_dpll_init(struct drm_device *dev)
13566 {
13567         struct drm_i915_private *dev_priv = dev->dev_private;
13568
13569         if (HAS_DDI(dev))
13570                 intel_ddi_pll_init(dev);
13571         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13572                 ibx_pch_dpll_init(dev);
13573         else
13574                 dev_priv->num_shared_dpll = 0;
13575
13576         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13577 }
13578
13579 /**
13580  * intel_prepare_plane_fb - Prepare fb for usage on plane
13581  * @plane: drm plane to prepare for
13582  * @fb: framebuffer to prepare for presentation
13583  *
13584  * Prepares a framebuffer for usage on a display plane.  Generally this
13585  * involves pinning the underlying object and updating the frontbuffer tracking
13586  * bits.  Some older platforms need special physical address handling for
13587  * cursor planes.
13588  *
13589  * Must be called with struct_mutex held.
13590  *
13591  * Returns 0 on success, negative error code on failure.
13592  */
13593 int
13594 intel_prepare_plane_fb(struct drm_plane *plane,
13595                        const struct drm_plane_state *new_state)
13596 {
13597         struct drm_device *dev = plane->dev;
13598         struct drm_framebuffer *fb = new_state->fb;
13599         struct intel_plane *intel_plane = to_intel_plane(plane);
13600         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13601         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13602         int ret = 0;
13603
13604         if (!obj && !old_obj)
13605                 return 0;
13606
13607         if (old_obj) {
13608                 struct drm_crtc_state *crtc_state =
13609                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13610
13611                 /* Big Hammer, we also need to ensure that any pending
13612                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13613                  * current scanout is retired before unpinning the old
13614                  * framebuffer. Note that we rely on userspace rendering
13615                  * into the buffer attached to the pipe they are waiting
13616                  * on. If not, userspace generates a GPU hang with IPEHR
13617                  * point to the MI_WAIT_FOR_EVENT.
13618                  *
13619                  * This should only fail upon a hung GPU, in which case we
13620                  * can safely continue.
13621                  */
13622                 if (needs_modeset(crtc_state))
13623                         ret = i915_gem_object_wait_rendering(old_obj, true);
13624
13625                 /* Swallow -EIO errors to allow updates during hw lockup. */
13626                 if (ret && ret != -EIO)
13627                         return ret;
13628         }
13629
13630         if (!obj) {
13631                 ret = 0;
13632         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13633             INTEL_INFO(dev)->cursor_needs_physical) {
13634                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13635                 ret = i915_gem_object_attach_phys(obj, align);
13636                 if (ret)
13637                         DRM_DEBUG_KMS("failed to attach phys object\n");
13638         } else {
13639                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13640         }
13641
13642         if (ret == 0) {
13643                 if (obj) {
13644                         struct intel_plane_state *plane_state =
13645                                 to_intel_plane_state(new_state);
13646
13647                         i915_gem_request_assign(&plane_state->wait_req,
13648                                                 obj->last_write_req);
13649                 }
13650
13651                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13652         }
13653
13654         return ret;
13655 }
13656
13657 /**
13658  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13659  * @plane: drm plane to clean up for
13660  * @fb: old framebuffer that was on plane
13661  *
13662  * Cleans up a framebuffer that has just been removed from a plane.
13663  *
13664  * Must be called with struct_mutex held.
13665  */
13666 void
13667 intel_cleanup_plane_fb(struct drm_plane *plane,
13668                        const struct drm_plane_state *old_state)
13669 {
13670         struct drm_device *dev = plane->dev;
13671         struct intel_plane *intel_plane = to_intel_plane(plane);
13672         struct intel_plane_state *old_intel_state;
13673         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13674         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13675
13676         old_intel_state = to_intel_plane_state(old_state);
13677
13678         if (!obj && !old_obj)
13679                 return;
13680
13681         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13682             !INTEL_INFO(dev)->cursor_needs_physical))
13683                 intel_unpin_fb_obj(old_state->fb, old_state);
13684
13685         /* prepare_fb aborted? */
13686         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13687             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13688                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13689
13690         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13691
13692 }
13693
13694 int
13695 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13696 {
13697         int max_scale;
13698         struct drm_device *dev;
13699         struct drm_i915_private *dev_priv;
13700         int crtc_clock, cdclk;
13701
13702         if (!intel_crtc || !crtc_state)
13703                 return DRM_PLANE_HELPER_NO_SCALING;
13704
13705         dev = intel_crtc->base.dev;
13706         dev_priv = dev->dev_private;
13707         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13708         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13709
13710         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13711                 return DRM_PLANE_HELPER_NO_SCALING;
13712
13713         /*
13714          * skl max scale is lower of:
13715          *    close to 3 but not 3, -1 is for that purpose
13716          *            or
13717          *    cdclk/crtc_clock
13718          */
13719         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13720
13721         return max_scale;
13722 }
13723
13724 static int
13725 intel_check_primary_plane(struct drm_plane *plane,
13726                           struct intel_crtc_state *crtc_state,
13727                           struct intel_plane_state *state)
13728 {
13729         struct drm_crtc *crtc = state->base.crtc;
13730         struct drm_framebuffer *fb = state->base.fb;
13731         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13732         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13733         bool can_position = false;
13734
13735         /* use scaler when colorkey is not required */
13736         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13737             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13738                 min_scale = 1;
13739                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13740                 can_position = true;
13741         }
13742
13743         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13744                                              &state->dst, &state->clip,
13745                                              min_scale, max_scale,
13746                                              can_position, true,
13747                                              &state->visible);
13748 }
13749
13750 static void
13751 intel_commit_primary_plane(struct drm_plane *plane,
13752                            struct intel_plane_state *state)
13753 {
13754         struct drm_crtc *crtc = state->base.crtc;
13755         struct drm_framebuffer *fb = state->base.fb;
13756         struct drm_device *dev = plane->dev;
13757         struct drm_i915_private *dev_priv = dev->dev_private;
13758
13759         crtc = crtc ? crtc : plane->crtc;
13760
13761         dev_priv->display.update_primary_plane(crtc, fb,
13762                                                state->src.x1 >> 16,
13763                                                state->src.y1 >> 16);
13764 }
13765
13766 static void
13767 intel_disable_primary_plane(struct drm_plane *plane,
13768                             struct drm_crtc *crtc)
13769 {
13770         struct drm_device *dev = plane->dev;
13771         struct drm_i915_private *dev_priv = dev->dev_private;
13772
13773         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13774 }
13775
13776 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13777                                     struct drm_crtc_state *old_crtc_state)
13778 {
13779         struct drm_device *dev = crtc->dev;
13780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13781         struct intel_crtc_state *old_intel_state =
13782                 to_intel_crtc_state(old_crtc_state);
13783         bool modeset = needs_modeset(crtc->state);
13784
13785         if (intel_crtc->atomic.update_wm_pre)
13786                 intel_update_watermarks(crtc);
13787
13788         /* Perform vblank evasion around commit operation */
13789         intel_pipe_update_start(intel_crtc);
13790
13791         if (modeset)
13792                 return;
13793
13794         if (to_intel_crtc_state(crtc->state)->update_pipe)
13795                 intel_update_pipe_config(intel_crtc, old_intel_state);
13796         else if (INTEL_INFO(dev)->gen >= 9)
13797                 skl_detach_scalers(intel_crtc);
13798 }
13799
13800 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13801                                      struct drm_crtc_state *old_crtc_state)
13802 {
13803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13804
13805         intel_pipe_update_end(intel_crtc);
13806 }
13807
13808 /**
13809  * intel_plane_destroy - destroy a plane
13810  * @plane: plane to destroy
13811  *
13812  * Common destruction function for all types of planes (primary, cursor,
13813  * sprite).
13814  */
13815 void intel_plane_destroy(struct drm_plane *plane)
13816 {
13817         struct intel_plane *intel_plane = to_intel_plane(plane);
13818         drm_plane_cleanup(plane);
13819         kfree(intel_plane);
13820 }
13821
13822 const struct drm_plane_funcs intel_plane_funcs = {
13823         .update_plane = drm_atomic_helper_update_plane,
13824         .disable_plane = drm_atomic_helper_disable_plane,
13825         .destroy = intel_plane_destroy,
13826         .set_property = drm_atomic_helper_plane_set_property,
13827         .atomic_get_property = intel_plane_atomic_get_property,
13828         .atomic_set_property = intel_plane_atomic_set_property,
13829         .atomic_duplicate_state = intel_plane_duplicate_state,
13830         .atomic_destroy_state = intel_plane_destroy_state,
13831
13832 };
13833
13834 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13835                                                     int pipe)
13836 {
13837         struct intel_plane *primary;
13838         struct intel_plane_state *state;
13839         const uint32_t *intel_primary_formats;
13840         unsigned int num_formats;
13841
13842         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13843         if (primary == NULL)
13844                 return NULL;
13845
13846         state = intel_create_plane_state(&primary->base);
13847         if (!state) {
13848                 kfree(primary);
13849                 return NULL;
13850         }
13851         primary->base.state = &state->base;
13852
13853         primary->can_scale = false;
13854         primary->max_downscale = 1;
13855         if (INTEL_INFO(dev)->gen >= 9) {
13856                 primary->can_scale = true;
13857                 state->scaler_id = -1;
13858         }
13859         primary->pipe = pipe;
13860         primary->plane = pipe;
13861         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13862         primary->check_plane = intel_check_primary_plane;
13863         primary->commit_plane = intel_commit_primary_plane;
13864         primary->disable_plane = intel_disable_primary_plane;
13865         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13866                 primary->plane = !pipe;
13867
13868         if (INTEL_INFO(dev)->gen >= 9) {
13869                 intel_primary_formats = skl_primary_formats;
13870                 num_formats = ARRAY_SIZE(skl_primary_formats);
13871         } else if (INTEL_INFO(dev)->gen >= 4) {
13872                 intel_primary_formats = i965_primary_formats;
13873                 num_formats = ARRAY_SIZE(i965_primary_formats);
13874         } else {
13875                 intel_primary_formats = i8xx_primary_formats;
13876                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13877         }
13878
13879         drm_universal_plane_init(dev, &primary->base, 0,
13880                                  &intel_plane_funcs,
13881                                  intel_primary_formats, num_formats,
13882                                  DRM_PLANE_TYPE_PRIMARY);
13883
13884         if (INTEL_INFO(dev)->gen >= 4)
13885                 intel_create_rotation_property(dev, primary);
13886
13887         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13888
13889         return &primary->base;
13890 }
13891
13892 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13893 {
13894         if (!dev->mode_config.rotation_property) {
13895                 unsigned long flags = BIT(DRM_ROTATE_0) |
13896                         BIT(DRM_ROTATE_180);
13897
13898                 if (INTEL_INFO(dev)->gen >= 9)
13899                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13900
13901                 dev->mode_config.rotation_property =
13902                         drm_mode_create_rotation_property(dev, flags);
13903         }
13904         if (dev->mode_config.rotation_property)
13905                 drm_object_attach_property(&plane->base.base,
13906                                 dev->mode_config.rotation_property,
13907                                 plane->base.state->rotation);
13908 }
13909
13910 static int
13911 intel_check_cursor_plane(struct drm_plane *plane,
13912                          struct intel_crtc_state *crtc_state,
13913                          struct intel_plane_state *state)
13914 {
13915         struct drm_crtc *crtc = crtc_state->base.crtc;
13916         struct drm_framebuffer *fb = state->base.fb;
13917         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13918         unsigned stride;
13919         int ret;
13920
13921         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13922                                             &state->dst, &state->clip,
13923                                             DRM_PLANE_HELPER_NO_SCALING,
13924                                             DRM_PLANE_HELPER_NO_SCALING,
13925                                             true, true, &state->visible);
13926         if (ret)
13927                 return ret;
13928
13929         /* if we want to turn off the cursor ignore width and height */
13930         if (!obj)
13931                 return 0;
13932
13933         /* Check for which cursor types we support */
13934         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13935                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13936                           state->base.crtc_w, state->base.crtc_h);
13937                 return -EINVAL;
13938         }
13939
13940         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13941         if (obj->base.size < stride * state->base.crtc_h) {
13942                 DRM_DEBUG_KMS("buffer is too small\n");
13943                 return -ENOMEM;
13944         }
13945
13946         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13947                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13948                 return -EINVAL;
13949         }
13950
13951         return 0;
13952 }
13953
13954 static void
13955 intel_disable_cursor_plane(struct drm_plane *plane,
13956                            struct drm_crtc *crtc)
13957 {
13958         intel_crtc_update_cursor(crtc, false);
13959 }
13960
13961 static void
13962 intel_commit_cursor_plane(struct drm_plane *plane,
13963                           struct intel_plane_state *state)
13964 {
13965         struct drm_crtc *crtc = state->base.crtc;
13966         struct drm_device *dev = plane->dev;
13967         struct intel_crtc *intel_crtc;
13968         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13969         uint32_t addr;
13970
13971         crtc = crtc ? crtc : plane->crtc;
13972         intel_crtc = to_intel_crtc(crtc);
13973
13974         if (intel_crtc->cursor_bo == obj)
13975                 goto update;
13976
13977         if (!obj)
13978                 addr = 0;
13979         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13980                 addr = i915_gem_obj_ggtt_offset(obj);
13981         else
13982                 addr = obj->phys_handle->busaddr;
13983
13984         intel_crtc->cursor_addr = addr;
13985         intel_crtc->cursor_bo = obj;
13986
13987 update:
13988         intel_crtc_update_cursor(crtc, state->visible);
13989 }
13990
13991 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13992                                                    int pipe)
13993 {
13994         struct intel_plane *cursor;
13995         struct intel_plane_state *state;
13996
13997         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13998         if (cursor == NULL)
13999                 return NULL;
14000
14001         state = intel_create_plane_state(&cursor->base);
14002         if (!state) {
14003                 kfree(cursor);
14004                 return NULL;
14005         }
14006         cursor->base.state = &state->base;
14007
14008         cursor->can_scale = false;
14009         cursor->max_downscale = 1;
14010         cursor->pipe = pipe;
14011         cursor->plane = pipe;
14012         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14013         cursor->check_plane = intel_check_cursor_plane;
14014         cursor->commit_plane = intel_commit_cursor_plane;
14015         cursor->disable_plane = intel_disable_cursor_plane;
14016
14017         drm_universal_plane_init(dev, &cursor->base, 0,
14018                                  &intel_plane_funcs,
14019                                  intel_cursor_formats,
14020                                  ARRAY_SIZE(intel_cursor_formats),
14021                                  DRM_PLANE_TYPE_CURSOR);
14022
14023         if (INTEL_INFO(dev)->gen >= 4) {
14024                 if (!dev->mode_config.rotation_property)
14025                         dev->mode_config.rotation_property =
14026                                 drm_mode_create_rotation_property(dev,
14027                                                         BIT(DRM_ROTATE_0) |
14028                                                         BIT(DRM_ROTATE_180));
14029                 if (dev->mode_config.rotation_property)
14030                         drm_object_attach_property(&cursor->base.base,
14031                                 dev->mode_config.rotation_property,
14032                                 state->base.rotation);
14033         }
14034
14035         if (INTEL_INFO(dev)->gen >=9)
14036                 state->scaler_id = -1;
14037
14038         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14039
14040         return &cursor->base;
14041 }
14042
14043 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14044         struct intel_crtc_state *crtc_state)
14045 {
14046         int i;
14047         struct intel_scaler *intel_scaler;
14048         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14049
14050         for (i = 0; i < intel_crtc->num_scalers; i++) {
14051                 intel_scaler = &scaler_state->scalers[i];
14052                 intel_scaler->in_use = 0;
14053                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14054         }
14055
14056         scaler_state->scaler_id = -1;
14057 }
14058
14059 static void intel_crtc_init(struct drm_device *dev, int pipe)
14060 {
14061         struct drm_i915_private *dev_priv = dev->dev_private;
14062         struct intel_crtc *intel_crtc;
14063         struct intel_crtc_state *crtc_state = NULL;
14064         struct drm_plane *primary = NULL;
14065         struct drm_plane *cursor = NULL;
14066         int i, ret;
14067
14068         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14069         if (intel_crtc == NULL)
14070                 return;
14071
14072         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14073         if (!crtc_state)
14074                 goto fail;
14075         intel_crtc->config = crtc_state;
14076         intel_crtc->base.state = &crtc_state->base;
14077         crtc_state->base.crtc = &intel_crtc->base;
14078
14079         /* initialize shared scalers */
14080         if (INTEL_INFO(dev)->gen >= 9) {
14081                 if (pipe == PIPE_C)
14082                         intel_crtc->num_scalers = 1;
14083                 else
14084                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14085
14086                 skl_init_scalers(dev, intel_crtc, crtc_state);
14087         }
14088
14089         primary = intel_primary_plane_create(dev, pipe);
14090         if (!primary)
14091                 goto fail;
14092
14093         cursor = intel_cursor_plane_create(dev, pipe);
14094         if (!cursor)
14095                 goto fail;
14096
14097         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14098                                         cursor, &intel_crtc_funcs);
14099         if (ret)
14100                 goto fail;
14101
14102         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14103         for (i = 0; i < 256; i++) {
14104                 intel_crtc->lut_r[i] = i;
14105                 intel_crtc->lut_g[i] = i;
14106                 intel_crtc->lut_b[i] = i;
14107         }
14108
14109         /*
14110          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14111          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14112          */
14113         intel_crtc->pipe = pipe;
14114         intel_crtc->plane = pipe;
14115         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14116                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14117                 intel_crtc->plane = !pipe;
14118         }
14119
14120         intel_crtc->cursor_base = ~0;
14121         intel_crtc->cursor_cntl = ~0;
14122         intel_crtc->cursor_size = ~0;
14123
14124         intel_crtc->wm.cxsr_allowed = true;
14125
14126         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14127                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14128         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14129         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14130
14131         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14132
14133         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14134         return;
14135
14136 fail:
14137         if (primary)
14138                 drm_plane_cleanup(primary);
14139         if (cursor)
14140                 drm_plane_cleanup(cursor);
14141         kfree(crtc_state);
14142         kfree(intel_crtc);
14143 }
14144
14145 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14146 {
14147         struct drm_encoder *encoder = connector->base.encoder;
14148         struct drm_device *dev = connector->base.dev;
14149
14150         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14151
14152         if (!encoder || WARN_ON(!encoder->crtc))
14153                 return INVALID_PIPE;
14154
14155         return to_intel_crtc(encoder->crtc)->pipe;
14156 }
14157
14158 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14159                                 struct drm_file *file)
14160 {
14161         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14162         struct drm_crtc *drmmode_crtc;
14163         struct intel_crtc *crtc;
14164
14165         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14166
14167         if (!drmmode_crtc) {
14168                 DRM_ERROR("no such CRTC id\n");
14169                 return -ENOENT;
14170         }
14171
14172         crtc = to_intel_crtc(drmmode_crtc);
14173         pipe_from_crtc_id->pipe = crtc->pipe;
14174
14175         return 0;
14176 }
14177
14178 static int intel_encoder_clones(struct intel_encoder *encoder)
14179 {
14180         struct drm_device *dev = encoder->base.dev;
14181         struct intel_encoder *source_encoder;
14182         int index_mask = 0;
14183         int entry = 0;
14184
14185         for_each_intel_encoder(dev, source_encoder) {
14186                 if (encoders_cloneable(encoder, source_encoder))
14187                         index_mask |= (1 << entry);
14188
14189                 entry++;
14190         }
14191
14192         return index_mask;
14193 }
14194
14195 static bool has_edp_a(struct drm_device *dev)
14196 {
14197         struct drm_i915_private *dev_priv = dev->dev_private;
14198
14199         if (!IS_MOBILE(dev))
14200                 return false;
14201
14202         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14203                 return false;
14204
14205         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14206                 return false;
14207
14208         return true;
14209 }
14210
14211 static bool intel_crt_present(struct drm_device *dev)
14212 {
14213         struct drm_i915_private *dev_priv = dev->dev_private;
14214
14215         if (INTEL_INFO(dev)->gen >= 9)
14216                 return false;
14217
14218         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14219                 return false;
14220
14221         if (IS_CHERRYVIEW(dev))
14222                 return false;
14223
14224         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14225                 return false;
14226
14227         return true;
14228 }
14229
14230 static void intel_setup_outputs(struct drm_device *dev)
14231 {
14232         struct drm_i915_private *dev_priv = dev->dev_private;
14233         struct intel_encoder *encoder;
14234         bool dpd_is_edp = false;
14235
14236         intel_lvds_init(dev);
14237
14238         if (intel_crt_present(dev))
14239                 intel_crt_init(dev);
14240
14241         if (IS_BROXTON(dev)) {
14242                 /*
14243                  * FIXME: Broxton doesn't support port detection via the
14244                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14245                  * detect the ports.
14246                  */
14247                 intel_ddi_init(dev, PORT_A);
14248                 intel_ddi_init(dev, PORT_B);
14249                 intel_ddi_init(dev, PORT_C);
14250         } else if (HAS_DDI(dev)) {
14251                 int found;
14252
14253                 /*
14254                  * Haswell uses DDI functions to detect digital outputs.
14255                  * On SKL pre-D0 the strap isn't connected, so we assume
14256                  * it's there.
14257                  */
14258                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14259                 /* WaIgnoreDDIAStrap: skl */
14260                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14261                         intel_ddi_init(dev, PORT_A);
14262
14263                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14264                  * register */
14265                 found = I915_READ(SFUSE_STRAP);
14266
14267                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14268                         intel_ddi_init(dev, PORT_B);
14269                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14270                         intel_ddi_init(dev, PORT_C);
14271                 if (found & SFUSE_STRAP_DDID_DETECTED)
14272                         intel_ddi_init(dev, PORT_D);
14273                 /*
14274                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14275                  */
14276                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14277                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14278                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14279                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14280                         intel_ddi_init(dev, PORT_E);
14281
14282         } else if (HAS_PCH_SPLIT(dev)) {
14283                 int found;
14284                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14285
14286                 if (has_edp_a(dev))
14287                         intel_dp_init(dev, DP_A, PORT_A);
14288
14289                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14290                         /* PCH SDVOB multiplex with HDMIB */
14291                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14292                         if (!found)
14293                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14294                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14295                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14296                 }
14297
14298                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14299                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14300
14301                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14302                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14303
14304                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14305                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14306
14307                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14308                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14309         } else if (IS_VALLEYVIEW(dev)) {
14310                 /*
14311                  * The DP_DETECTED bit is the latched state of the DDC
14312                  * SDA pin at boot. However since eDP doesn't require DDC
14313                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14314                  * eDP ports may have been muxed to an alternate function.
14315                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14316                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14317                  * detect eDP ports.
14318                  */
14319                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14320                     !intel_dp_is_edp(dev, PORT_B))
14321                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14322                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14323                     intel_dp_is_edp(dev, PORT_B))
14324                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14325
14326                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14327                     !intel_dp_is_edp(dev, PORT_C))
14328                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14329                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14330                     intel_dp_is_edp(dev, PORT_C))
14331                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14332
14333                 if (IS_CHERRYVIEW(dev)) {
14334                         /* eDP not supported on port D, so don't check VBT */
14335                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14336                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14337                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14338                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14339                 }
14340
14341                 intel_dsi_init(dev);
14342         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14343                 bool found = false;
14344
14345                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14346                         DRM_DEBUG_KMS("probing SDVOB\n");
14347                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14348                         if (!found && IS_G4X(dev)) {
14349                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14350                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14351                         }
14352
14353                         if (!found && IS_G4X(dev))
14354                                 intel_dp_init(dev, DP_B, PORT_B);
14355                 }
14356
14357                 /* Before G4X SDVOC doesn't have its own detect register */
14358
14359                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14360                         DRM_DEBUG_KMS("probing SDVOC\n");
14361                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14362                 }
14363
14364                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14365
14366                         if (IS_G4X(dev)) {
14367                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14368                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14369                         }
14370                         if (IS_G4X(dev))
14371                                 intel_dp_init(dev, DP_C, PORT_C);
14372                 }
14373
14374                 if (IS_G4X(dev) &&
14375                     (I915_READ(DP_D) & DP_DETECTED))
14376                         intel_dp_init(dev, DP_D, PORT_D);
14377         } else if (IS_GEN2(dev))
14378                 intel_dvo_init(dev);
14379
14380         if (SUPPORTS_TV(dev))
14381                 intel_tv_init(dev);
14382
14383         intel_psr_init(dev);
14384
14385         for_each_intel_encoder(dev, encoder) {
14386                 encoder->base.possible_crtcs = encoder->crtc_mask;
14387                 encoder->base.possible_clones =
14388                         intel_encoder_clones(encoder);
14389         }
14390
14391         intel_init_pch_refclk(dev);
14392
14393         drm_helper_move_panel_connectors_to_head(dev);
14394 }
14395
14396 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14397 {
14398         struct drm_device *dev = fb->dev;
14399         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14400
14401         drm_framebuffer_cleanup(fb);
14402         mutex_lock(&dev->struct_mutex);
14403         WARN_ON(!intel_fb->obj->framebuffer_references--);
14404         drm_gem_object_unreference(&intel_fb->obj->base);
14405         mutex_unlock(&dev->struct_mutex);
14406         kfree(intel_fb);
14407 }
14408
14409 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14410                                                 struct drm_file *file,
14411                                                 unsigned int *handle)
14412 {
14413         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14414         struct drm_i915_gem_object *obj = intel_fb->obj;
14415
14416         return drm_gem_handle_create(file, &obj->base, handle);
14417 }
14418
14419 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14420                                         struct drm_file *file,
14421                                         unsigned flags, unsigned color,
14422                                         struct drm_clip_rect *clips,
14423                                         unsigned num_clips)
14424 {
14425         struct drm_device *dev = fb->dev;
14426         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14427         struct drm_i915_gem_object *obj = intel_fb->obj;
14428
14429         mutex_lock(&dev->struct_mutex);
14430         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14431         mutex_unlock(&dev->struct_mutex);
14432
14433         return 0;
14434 }
14435
14436 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14437         .destroy = intel_user_framebuffer_destroy,
14438         .create_handle = intel_user_framebuffer_create_handle,
14439         .dirty = intel_user_framebuffer_dirty,
14440 };
14441
14442 static
14443 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14444                          uint32_t pixel_format)
14445 {
14446         u32 gen = INTEL_INFO(dev)->gen;
14447
14448         if (gen >= 9) {
14449                 /* "The stride in bytes must not exceed the of the size of 8K
14450                  *  pixels and 32K bytes."
14451                  */
14452                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14453         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14454                 return 32*1024;
14455         } else if (gen >= 4) {
14456                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14457                         return 16*1024;
14458                 else
14459                         return 32*1024;
14460         } else if (gen >= 3) {
14461                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14462                         return 8*1024;
14463                 else
14464                         return 16*1024;
14465         } else {
14466                 /* XXX DSPC is limited to 4k tiled */
14467                 return 8*1024;
14468         }
14469 }
14470
14471 static int intel_framebuffer_init(struct drm_device *dev,
14472                                   struct intel_framebuffer *intel_fb,
14473                                   struct drm_mode_fb_cmd2 *mode_cmd,
14474                                   struct drm_i915_gem_object *obj)
14475 {
14476         unsigned int aligned_height;
14477         int ret;
14478         u32 pitch_limit, stride_alignment;
14479
14480         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14481
14482         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14483                 /* Enforce that fb modifier and tiling mode match, but only for
14484                  * X-tiled. This is needed for FBC. */
14485                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14486                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14487                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14488                         return -EINVAL;
14489                 }
14490         } else {
14491                 if (obj->tiling_mode == I915_TILING_X)
14492                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14493                 else if (obj->tiling_mode == I915_TILING_Y) {
14494                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14495                         return -EINVAL;
14496                 }
14497         }
14498
14499         /* Passed in modifier sanity checking. */
14500         switch (mode_cmd->modifier[0]) {
14501         case I915_FORMAT_MOD_Y_TILED:
14502         case I915_FORMAT_MOD_Yf_TILED:
14503                 if (INTEL_INFO(dev)->gen < 9) {
14504                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14505                                   mode_cmd->modifier[0]);
14506                         return -EINVAL;
14507                 }
14508         case DRM_FORMAT_MOD_NONE:
14509         case I915_FORMAT_MOD_X_TILED:
14510                 break;
14511         default:
14512                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14513                           mode_cmd->modifier[0]);
14514                 return -EINVAL;
14515         }
14516
14517         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14518                                                      mode_cmd->pixel_format);
14519         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14520                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14521                           mode_cmd->pitches[0], stride_alignment);
14522                 return -EINVAL;
14523         }
14524
14525         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14526                                            mode_cmd->pixel_format);
14527         if (mode_cmd->pitches[0] > pitch_limit) {
14528                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14529                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14530                           "tiled" : "linear",
14531                           mode_cmd->pitches[0], pitch_limit);
14532                 return -EINVAL;
14533         }
14534
14535         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14536             mode_cmd->pitches[0] != obj->stride) {
14537                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14538                           mode_cmd->pitches[0], obj->stride);
14539                 return -EINVAL;
14540         }
14541
14542         /* Reject formats not supported by any plane early. */
14543         switch (mode_cmd->pixel_format) {
14544         case DRM_FORMAT_C8:
14545         case DRM_FORMAT_RGB565:
14546         case DRM_FORMAT_XRGB8888:
14547         case DRM_FORMAT_ARGB8888:
14548                 break;
14549         case DRM_FORMAT_XRGB1555:
14550                 if (INTEL_INFO(dev)->gen > 3) {
14551                         DRM_DEBUG("unsupported pixel format: %s\n",
14552                                   drm_get_format_name(mode_cmd->pixel_format));
14553                         return -EINVAL;
14554                 }
14555                 break;
14556         case DRM_FORMAT_ABGR8888:
14557                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14558                         DRM_DEBUG("unsupported pixel format: %s\n",
14559                                   drm_get_format_name(mode_cmd->pixel_format));
14560                         return -EINVAL;
14561                 }
14562                 break;
14563         case DRM_FORMAT_XBGR8888:
14564         case DRM_FORMAT_XRGB2101010:
14565         case DRM_FORMAT_XBGR2101010:
14566                 if (INTEL_INFO(dev)->gen < 4) {
14567                         DRM_DEBUG("unsupported pixel format: %s\n",
14568                                   drm_get_format_name(mode_cmd->pixel_format));
14569                         return -EINVAL;
14570                 }
14571                 break;
14572         case DRM_FORMAT_ABGR2101010:
14573                 if (!IS_VALLEYVIEW(dev)) {
14574                         DRM_DEBUG("unsupported pixel format: %s\n",
14575                                   drm_get_format_name(mode_cmd->pixel_format));
14576                         return -EINVAL;
14577                 }
14578                 break;
14579         case DRM_FORMAT_YUYV:
14580         case DRM_FORMAT_UYVY:
14581         case DRM_FORMAT_YVYU:
14582         case DRM_FORMAT_VYUY:
14583                 if (INTEL_INFO(dev)->gen < 5) {
14584                         DRM_DEBUG("unsupported pixel format: %s\n",
14585                                   drm_get_format_name(mode_cmd->pixel_format));
14586                         return -EINVAL;
14587                 }
14588                 break;
14589         default:
14590                 DRM_DEBUG("unsupported pixel format: %s\n",
14591                           drm_get_format_name(mode_cmd->pixel_format));
14592                 return -EINVAL;
14593         }
14594
14595         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14596         if (mode_cmd->offsets[0] != 0)
14597                 return -EINVAL;
14598
14599         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14600                                                mode_cmd->pixel_format,
14601                                                mode_cmd->modifier[0]);
14602         /* FIXME drm helper for size checks (especially planar formats)? */
14603         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14604                 return -EINVAL;
14605
14606         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14607         intel_fb->obj = obj;
14608         intel_fb->obj->framebuffer_references++;
14609
14610         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14611         if (ret) {
14612                 DRM_ERROR("framebuffer init failed %d\n", ret);
14613                 return ret;
14614         }
14615
14616         return 0;
14617 }
14618
14619 static struct drm_framebuffer *
14620 intel_user_framebuffer_create(struct drm_device *dev,
14621                               struct drm_file *filp,
14622                               struct drm_mode_fb_cmd2 *mode_cmd)
14623 {
14624         struct drm_framebuffer *fb;
14625         struct drm_i915_gem_object *obj;
14626
14627         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14628                                                 mode_cmd->handles[0]));
14629         if (&obj->base == NULL)
14630                 return ERR_PTR(-ENOENT);
14631
14632         fb = intel_framebuffer_create(dev, mode_cmd, obj);
14633         if (IS_ERR(fb))
14634                 drm_gem_object_unreference_unlocked(&obj->base);
14635
14636         return fb;
14637 }
14638
14639 #ifndef CONFIG_DRM_FBDEV_EMULATION
14640 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14641 {
14642 }
14643 #endif
14644
14645 static const struct drm_mode_config_funcs intel_mode_funcs = {
14646         .fb_create = intel_user_framebuffer_create,
14647         .output_poll_changed = intel_fbdev_output_poll_changed,
14648         .atomic_check = intel_atomic_check,
14649         .atomic_commit = intel_atomic_commit,
14650         .atomic_state_alloc = intel_atomic_state_alloc,
14651         .atomic_state_clear = intel_atomic_state_clear,
14652 };
14653
14654 /* Set up chip specific display functions */
14655 static void intel_init_display(struct drm_device *dev)
14656 {
14657         struct drm_i915_private *dev_priv = dev->dev_private;
14658
14659         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14660                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14661         else if (IS_CHERRYVIEW(dev))
14662                 dev_priv->display.find_dpll = chv_find_best_dpll;
14663         else if (IS_VALLEYVIEW(dev))
14664                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14665         else if (IS_PINEVIEW(dev))
14666                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14667         else
14668                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14669
14670         if (INTEL_INFO(dev)->gen >= 9) {
14671                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14672                 dev_priv->display.get_initial_plane_config =
14673                         skylake_get_initial_plane_config;
14674                 dev_priv->display.crtc_compute_clock =
14675                         haswell_crtc_compute_clock;
14676                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14677                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14678                 dev_priv->display.update_primary_plane =
14679                         skylake_update_primary_plane;
14680         } else if (HAS_DDI(dev)) {
14681                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14682                 dev_priv->display.get_initial_plane_config =
14683                         ironlake_get_initial_plane_config;
14684                 dev_priv->display.crtc_compute_clock =
14685                         haswell_crtc_compute_clock;
14686                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14687                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14688                 dev_priv->display.update_primary_plane =
14689                         ironlake_update_primary_plane;
14690         } else if (HAS_PCH_SPLIT(dev)) {
14691                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14692                 dev_priv->display.get_initial_plane_config =
14693                         ironlake_get_initial_plane_config;
14694                 dev_priv->display.crtc_compute_clock =
14695                         ironlake_crtc_compute_clock;
14696                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14697                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14698                 dev_priv->display.update_primary_plane =
14699                         ironlake_update_primary_plane;
14700         } else if (IS_VALLEYVIEW(dev)) {
14701                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14702                 dev_priv->display.get_initial_plane_config =
14703                         i9xx_get_initial_plane_config;
14704                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14705                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14706                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14707                 dev_priv->display.update_primary_plane =
14708                         i9xx_update_primary_plane;
14709         } else {
14710                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14711                 dev_priv->display.get_initial_plane_config =
14712                         i9xx_get_initial_plane_config;
14713                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14714                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14715                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14716                 dev_priv->display.update_primary_plane =
14717                         i9xx_update_primary_plane;
14718         }
14719
14720         /* Returns the core display clock speed */
14721         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14722                 dev_priv->display.get_display_clock_speed =
14723                         skylake_get_display_clock_speed;
14724         else if (IS_BROXTON(dev))
14725                 dev_priv->display.get_display_clock_speed =
14726                         broxton_get_display_clock_speed;
14727         else if (IS_BROADWELL(dev))
14728                 dev_priv->display.get_display_clock_speed =
14729                         broadwell_get_display_clock_speed;
14730         else if (IS_HASWELL(dev))
14731                 dev_priv->display.get_display_clock_speed =
14732                         haswell_get_display_clock_speed;
14733         else if (IS_VALLEYVIEW(dev))
14734                 dev_priv->display.get_display_clock_speed =
14735                         valleyview_get_display_clock_speed;
14736         else if (IS_GEN5(dev))
14737                 dev_priv->display.get_display_clock_speed =
14738                         ilk_get_display_clock_speed;
14739         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14740                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14741                 dev_priv->display.get_display_clock_speed =
14742                         i945_get_display_clock_speed;
14743         else if (IS_GM45(dev))
14744                 dev_priv->display.get_display_clock_speed =
14745                         gm45_get_display_clock_speed;
14746         else if (IS_CRESTLINE(dev))
14747                 dev_priv->display.get_display_clock_speed =
14748                         i965gm_get_display_clock_speed;
14749         else if (IS_PINEVIEW(dev))
14750                 dev_priv->display.get_display_clock_speed =
14751                         pnv_get_display_clock_speed;
14752         else if (IS_G33(dev) || IS_G4X(dev))
14753                 dev_priv->display.get_display_clock_speed =
14754                         g33_get_display_clock_speed;
14755         else if (IS_I915G(dev))
14756                 dev_priv->display.get_display_clock_speed =
14757                         i915_get_display_clock_speed;
14758         else if (IS_I945GM(dev) || IS_845G(dev))
14759                 dev_priv->display.get_display_clock_speed =
14760                         i9xx_misc_get_display_clock_speed;
14761         else if (IS_PINEVIEW(dev))
14762                 dev_priv->display.get_display_clock_speed =
14763                         pnv_get_display_clock_speed;
14764         else if (IS_I915GM(dev))
14765                 dev_priv->display.get_display_clock_speed =
14766                         i915gm_get_display_clock_speed;
14767         else if (IS_I865G(dev))
14768                 dev_priv->display.get_display_clock_speed =
14769                         i865_get_display_clock_speed;
14770         else if (IS_I85X(dev))
14771                 dev_priv->display.get_display_clock_speed =
14772                         i85x_get_display_clock_speed;
14773         else { /* 830 */
14774                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14775                 dev_priv->display.get_display_clock_speed =
14776                         i830_get_display_clock_speed;
14777         }
14778
14779         if (IS_GEN5(dev)) {
14780                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14781         } else if (IS_GEN6(dev)) {
14782                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14783         } else if (IS_IVYBRIDGE(dev)) {
14784                 /* FIXME: detect B0+ stepping and use auto training */
14785                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14786         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14787                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14788                 if (IS_BROADWELL(dev)) {
14789                         dev_priv->display.modeset_commit_cdclk =
14790                                 broadwell_modeset_commit_cdclk;
14791                         dev_priv->display.modeset_calc_cdclk =
14792                                 broadwell_modeset_calc_cdclk;
14793                 }
14794         } else if (IS_VALLEYVIEW(dev)) {
14795                 dev_priv->display.modeset_commit_cdclk =
14796                         valleyview_modeset_commit_cdclk;
14797                 dev_priv->display.modeset_calc_cdclk =
14798                         valleyview_modeset_calc_cdclk;
14799         } else if (IS_BROXTON(dev)) {
14800                 dev_priv->display.modeset_commit_cdclk =
14801                         broxton_modeset_commit_cdclk;
14802                 dev_priv->display.modeset_calc_cdclk =
14803                         broxton_modeset_calc_cdclk;
14804         }
14805
14806         switch (INTEL_INFO(dev)->gen) {
14807         case 2:
14808                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14809                 break;
14810
14811         case 3:
14812                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14813                 break;
14814
14815         case 4:
14816         case 5:
14817                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14818                 break;
14819
14820         case 6:
14821                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14822                 break;
14823         case 7:
14824         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14825                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14826                 break;
14827         case 9:
14828                 /* Drop through - unsupported since execlist only. */
14829         default:
14830                 /* Default just returns -ENODEV to indicate unsupported */
14831                 dev_priv->display.queue_flip = intel_default_queue_flip;
14832         }
14833
14834         mutex_init(&dev_priv->pps_mutex);
14835 }
14836
14837 /*
14838  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14839  * resume, or other times.  This quirk makes sure that's the case for
14840  * affected systems.
14841  */
14842 static void quirk_pipea_force(struct drm_device *dev)
14843 {
14844         struct drm_i915_private *dev_priv = dev->dev_private;
14845
14846         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14847         DRM_INFO("applying pipe a force quirk\n");
14848 }
14849
14850 static void quirk_pipeb_force(struct drm_device *dev)
14851 {
14852         struct drm_i915_private *dev_priv = dev->dev_private;
14853
14854         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14855         DRM_INFO("applying pipe b force quirk\n");
14856 }
14857
14858 /*
14859  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14860  */
14861 static void quirk_ssc_force_disable(struct drm_device *dev)
14862 {
14863         struct drm_i915_private *dev_priv = dev->dev_private;
14864         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14865         DRM_INFO("applying lvds SSC disable quirk\n");
14866 }
14867
14868 /*
14869  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14870  * brightness value
14871  */
14872 static void quirk_invert_brightness(struct drm_device *dev)
14873 {
14874         struct drm_i915_private *dev_priv = dev->dev_private;
14875         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14876         DRM_INFO("applying inverted panel brightness quirk\n");
14877 }
14878
14879 /* Some VBT's incorrectly indicate no backlight is present */
14880 static void quirk_backlight_present(struct drm_device *dev)
14881 {
14882         struct drm_i915_private *dev_priv = dev->dev_private;
14883         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14884         DRM_INFO("applying backlight present quirk\n");
14885 }
14886
14887 struct intel_quirk {
14888         int device;
14889         int subsystem_vendor;
14890         int subsystem_device;
14891         void (*hook)(struct drm_device *dev);
14892 };
14893
14894 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14895 struct intel_dmi_quirk {
14896         void (*hook)(struct drm_device *dev);
14897         const struct dmi_system_id (*dmi_id_list)[];
14898 };
14899
14900 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14901 {
14902         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14903         return 1;
14904 }
14905
14906 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14907         {
14908                 .dmi_id_list = &(const struct dmi_system_id[]) {
14909                         {
14910                                 .callback = intel_dmi_reverse_brightness,
14911                                 .ident = "NCR Corporation",
14912                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14913                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14914                                 },
14915                         },
14916                         { }  /* terminating entry */
14917                 },
14918                 .hook = quirk_invert_brightness,
14919         },
14920 };
14921
14922 static struct intel_quirk intel_quirks[] = {
14923         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14924         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14925
14926         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14927         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14928
14929         /* 830 needs to leave pipe A & dpll A up */
14930         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14931
14932         /* 830 needs to leave pipe B & dpll B up */
14933         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14934
14935         /* Lenovo U160 cannot use SSC on LVDS */
14936         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14937
14938         /* Sony Vaio Y cannot use SSC on LVDS */
14939         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14940
14941         /* Acer Aspire 5734Z must invert backlight brightness */
14942         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14943
14944         /* Acer/eMachines G725 */
14945         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14946
14947         /* Acer/eMachines e725 */
14948         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14949
14950         /* Acer/Packard Bell NCL20 */
14951         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14952
14953         /* Acer Aspire 4736Z */
14954         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14955
14956         /* Acer Aspire 5336 */
14957         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14958
14959         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14960         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14961
14962         /* Acer C720 Chromebook (Core i3 4005U) */
14963         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14964
14965         /* Apple Macbook 2,1 (Core 2 T7400) */
14966         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14967
14968         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14969         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14970
14971         /* HP Chromebook 14 (Celeron 2955U) */
14972         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14973
14974         /* Dell Chromebook 11 */
14975         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14976 };
14977
14978 static void intel_init_quirks(struct drm_device *dev)
14979 {
14980         struct pci_dev *d = dev->pdev;
14981         int i;
14982
14983         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14984                 struct intel_quirk *q = &intel_quirks[i];
14985
14986                 if (d->device == q->device &&
14987                     (d->subsystem_vendor == q->subsystem_vendor ||
14988                      q->subsystem_vendor == PCI_ANY_ID) &&
14989                     (d->subsystem_device == q->subsystem_device ||
14990                      q->subsystem_device == PCI_ANY_ID))
14991                         q->hook(dev);
14992         }
14993         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14994                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14995                         intel_dmi_quirks[i].hook(dev);
14996         }
14997 }
14998
14999 /* Disable the VGA plane that we never use */
15000 static void i915_disable_vga(struct drm_device *dev)
15001 {
15002         struct drm_i915_private *dev_priv = dev->dev_private;
15003         u8 sr1;
15004         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15005
15006         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15007         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15008         outb(SR01, VGA_SR_INDEX);
15009         sr1 = inb(VGA_SR_DATA);
15010         outb(sr1 | 1<<5, VGA_SR_DATA);
15011         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15012         udelay(300);
15013
15014         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15015         POSTING_READ(vga_reg);
15016 }
15017
15018 void intel_modeset_init_hw(struct drm_device *dev)
15019 {
15020         intel_update_cdclk(dev);
15021         intel_prepare_ddi(dev);
15022         intel_init_clock_gating(dev);
15023         intel_enable_gt_powersave(dev);
15024 }
15025
15026 void intel_modeset_init(struct drm_device *dev)
15027 {
15028         struct drm_i915_private *dev_priv = dev->dev_private;
15029         int sprite, ret;
15030         enum pipe pipe;
15031         struct intel_crtc *crtc;
15032
15033         drm_mode_config_init(dev);
15034
15035         dev->mode_config.min_width = 0;
15036         dev->mode_config.min_height = 0;
15037
15038         dev->mode_config.preferred_depth = 24;
15039         dev->mode_config.prefer_shadow = 1;
15040
15041         dev->mode_config.allow_fb_modifiers = true;
15042
15043         dev->mode_config.funcs = &intel_mode_funcs;
15044
15045         intel_init_quirks(dev);
15046
15047         intel_init_pm(dev);
15048
15049         if (INTEL_INFO(dev)->num_pipes == 0)
15050                 return;
15051
15052         /*
15053          * There may be no VBT; and if the BIOS enabled SSC we can
15054          * just keep using it to avoid unnecessary flicker.  Whereas if the
15055          * BIOS isn't using it, don't assume it will work even if the VBT
15056          * indicates as much.
15057          */
15058         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15059                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15060                                             DREF_SSC1_ENABLE);
15061
15062                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15063                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15064                                      bios_lvds_use_ssc ? "en" : "dis",
15065                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15066                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15067                 }
15068         }
15069
15070         intel_init_display(dev);
15071         intel_init_audio(dev);
15072
15073         if (IS_GEN2(dev)) {
15074                 dev->mode_config.max_width = 2048;
15075                 dev->mode_config.max_height = 2048;
15076         } else if (IS_GEN3(dev)) {
15077                 dev->mode_config.max_width = 4096;
15078                 dev->mode_config.max_height = 4096;
15079         } else {
15080                 dev->mode_config.max_width = 8192;
15081                 dev->mode_config.max_height = 8192;
15082         }
15083
15084         if (IS_845G(dev) || IS_I865G(dev)) {
15085                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15086                 dev->mode_config.cursor_height = 1023;
15087         } else if (IS_GEN2(dev)) {
15088                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15089                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15090         } else {
15091                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15092                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15093         }
15094
15095         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15096
15097         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15098                       INTEL_INFO(dev)->num_pipes,
15099                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15100
15101         for_each_pipe(dev_priv, pipe) {
15102                 intel_crtc_init(dev, pipe);
15103                 for_each_sprite(dev_priv, pipe, sprite) {
15104                         ret = intel_plane_init(dev, pipe, sprite);
15105                         if (ret)
15106                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15107                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15108                 }
15109         }
15110
15111         intel_update_czclk(dev_priv);
15112         intel_update_cdclk(dev);
15113
15114         intel_shared_dpll_init(dev);
15115
15116         /* Just disable it once at startup */
15117         i915_disable_vga(dev);
15118         intel_setup_outputs(dev);
15119
15120         drm_modeset_lock_all(dev);
15121         intel_modeset_setup_hw_state(dev);
15122         drm_modeset_unlock_all(dev);
15123
15124         for_each_intel_crtc(dev, crtc) {
15125                 struct intel_initial_plane_config plane_config = {};
15126
15127                 if (!crtc->active)
15128                         continue;
15129
15130                 /*
15131                  * Note that reserving the BIOS fb up front prevents us
15132                  * from stuffing other stolen allocations like the ring
15133                  * on top.  This prevents some ugliness at boot time, and
15134                  * can even allow for smooth boot transitions if the BIOS
15135                  * fb is large enough for the active pipe configuration.
15136                  */
15137                 dev_priv->display.get_initial_plane_config(crtc,
15138                                                            &plane_config);
15139
15140                 /*
15141                  * If the fb is shared between multiple heads, we'll
15142                  * just get the first one.
15143                  */
15144                 intel_find_initial_plane_obj(crtc, &plane_config);
15145         }
15146 }
15147
15148 static void intel_enable_pipe_a(struct drm_device *dev)
15149 {
15150         struct intel_connector *connector;
15151         struct drm_connector *crt = NULL;
15152         struct intel_load_detect_pipe load_detect_temp;
15153         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15154
15155         /* We can't just switch on the pipe A, we need to set things up with a
15156          * proper mode and output configuration. As a gross hack, enable pipe A
15157          * by enabling the load detect pipe once. */
15158         for_each_intel_connector(dev, connector) {
15159                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15160                         crt = &connector->base;
15161                         break;
15162                 }
15163         }
15164
15165         if (!crt)
15166                 return;
15167
15168         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15169                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15170 }
15171
15172 static bool
15173 intel_check_plane_mapping(struct intel_crtc *crtc)
15174 {
15175         struct drm_device *dev = crtc->base.dev;
15176         struct drm_i915_private *dev_priv = dev->dev_private;
15177         u32 val;
15178
15179         if (INTEL_INFO(dev)->num_pipes == 1)
15180                 return true;
15181
15182         val = I915_READ(DSPCNTR(!crtc->plane));
15183
15184         if ((val & DISPLAY_PLANE_ENABLE) &&
15185             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15186                 return false;
15187
15188         return true;
15189 }
15190
15191 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15192 {
15193         struct drm_device *dev = crtc->base.dev;
15194         struct intel_encoder *encoder;
15195
15196         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15197                 return true;
15198
15199         return false;
15200 }
15201
15202 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15203 {
15204         struct drm_device *dev = crtc->base.dev;
15205         struct drm_i915_private *dev_priv = dev->dev_private;
15206         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15207
15208         /* Clear any frame start delays used for debugging left by the BIOS */
15209         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15210
15211         /* restore vblank interrupts to correct state */
15212         drm_crtc_vblank_reset(&crtc->base);
15213         if (crtc->active) {
15214                 struct intel_plane *plane;
15215
15216                 drm_crtc_vblank_on(&crtc->base);
15217
15218                 /* Disable everything but the primary plane */
15219                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15220                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15221                                 continue;
15222
15223                         plane->disable_plane(&plane->base, &crtc->base);
15224                 }
15225         }
15226
15227         /* We need to sanitize the plane -> pipe mapping first because this will
15228          * disable the crtc (and hence change the state) if it is wrong. Note
15229          * that gen4+ has a fixed plane -> pipe mapping.  */
15230         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15231                 bool plane;
15232
15233                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15234                               crtc->base.base.id);
15235
15236                 /* Pipe has the wrong plane attached and the plane is active.
15237                  * Temporarily change the plane mapping and disable everything
15238                  * ...  */
15239                 plane = crtc->plane;
15240                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15241                 crtc->plane = !plane;
15242                 intel_crtc_disable_noatomic(&crtc->base);
15243                 crtc->plane = plane;
15244         }
15245
15246         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15247             crtc->pipe == PIPE_A && !crtc->active) {
15248                 /* BIOS forgot to enable pipe A, this mostly happens after
15249                  * resume. Force-enable the pipe to fix this, the update_dpms
15250                  * call below we restore the pipe to the right state, but leave
15251                  * the required bits on. */
15252                 intel_enable_pipe_a(dev);
15253         }
15254
15255         /* Adjust the state of the output pipe according to whether we
15256          * have active connectors/encoders. */
15257         if (!intel_crtc_has_encoders(crtc))
15258                 intel_crtc_disable_noatomic(&crtc->base);
15259
15260         if (crtc->active != crtc->base.state->active) {
15261                 struct intel_encoder *encoder;
15262
15263                 /* This can happen either due to bugs in the get_hw_state
15264                  * functions or because of calls to intel_crtc_disable_noatomic,
15265                  * or because the pipe is force-enabled due to the
15266                  * pipe A quirk. */
15267                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15268                               crtc->base.base.id,
15269                               crtc->base.state->enable ? "enabled" : "disabled",
15270                               crtc->active ? "enabled" : "disabled");
15271
15272                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15273                 crtc->base.state->active = crtc->active;
15274                 crtc->base.enabled = crtc->active;
15275
15276                 /* Because we only establish the connector -> encoder ->
15277                  * crtc links if something is active, this means the
15278                  * crtc is now deactivated. Break the links. connector
15279                  * -> encoder links are only establish when things are
15280                  *  actually up, hence no need to break them. */
15281                 WARN_ON(crtc->active);
15282
15283                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15284                         encoder->base.crtc = NULL;
15285         }
15286
15287         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15288                 /*
15289                  * We start out with underrun reporting disabled to avoid races.
15290                  * For correct bookkeeping mark this on active crtcs.
15291                  *
15292                  * Also on gmch platforms we dont have any hardware bits to
15293                  * disable the underrun reporting. Which means we need to start
15294                  * out with underrun reporting disabled also on inactive pipes,
15295                  * since otherwise we'll complain about the garbage we read when
15296                  * e.g. coming up after runtime pm.
15297                  *
15298                  * No protection against concurrent access is required - at
15299                  * worst a fifo underrun happens which also sets this to false.
15300                  */
15301                 crtc->cpu_fifo_underrun_disabled = true;
15302                 crtc->pch_fifo_underrun_disabled = true;
15303         }
15304 }
15305
15306 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15307 {
15308         struct intel_connector *connector;
15309         struct drm_device *dev = encoder->base.dev;
15310         bool active = false;
15311
15312         /* We need to check both for a crtc link (meaning that the
15313          * encoder is active and trying to read from a pipe) and the
15314          * pipe itself being active. */
15315         bool has_active_crtc = encoder->base.crtc &&
15316                 to_intel_crtc(encoder->base.crtc)->active;
15317
15318         for_each_intel_connector(dev, connector) {
15319                 if (connector->base.encoder != &encoder->base)
15320                         continue;
15321
15322                 active = true;
15323                 break;
15324         }
15325
15326         if (active && !has_active_crtc) {
15327                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15328                               encoder->base.base.id,
15329                               encoder->base.name);
15330
15331                 /* Connector is active, but has no active pipe. This is
15332                  * fallout from our resume register restoring. Disable
15333                  * the encoder manually again. */
15334                 if (encoder->base.crtc) {
15335                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15336                                       encoder->base.base.id,
15337                                       encoder->base.name);
15338                         encoder->disable(encoder);
15339                         if (encoder->post_disable)
15340                                 encoder->post_disable(encoder);
15341                 }
15342                 encoder->base.crtc = NULL;
15343
15344                 /* Inconsistent output/port/pipe state happens presumably due to
15345                  * a bug in one of the get_hw_state functions. Or someplace else
15346                  * in our code, like the register restore mess on resume. Clamp
15347                  * things to off as a safer default. */
15348                 for_each_intel_connector(dev, connector) {
15349                         if (connector->encoder != encoder)
15350                                 continue;
15351                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15352                         connector->base.encoder = NULL;
15353                 }
15354         }
15355         /* Enabled encoders without active connectors will be fixed in
15356          * the crtc fixup. */
15357 }
15358
15359 void i915_redisable_vga_power_on(struct drm_device *dev)
15360 {
15361         struct drm_i915_private *dev_priv = dev->dev_private;
15362         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15363
15364         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15365                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15366                 i915_disable_vga(dev);
15367         }
15368 }
15369
15370 void i915_redisable_vga(struct drm_device *dev)
15371 {
15372         struct drm_i915_private *dev_priv = dev->dev_private;
15373
15374         /* This function can be called both from intel_modeset_setup_hw_state or
15375          * at a very early point in our resume sequence, where the power well
15376          * structures are not yet restored. Since this function is at a very
15377          * paranoid "someone might have enabled VGA while we were not looking"
15378          * level, just check if the power well is enabled instead of trying to
15379          * follow the "don't touch the power well if we don't need it" policy
15380          * the rest of the driver uses. */
15381         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15382                 return;
15383
15384         i915_redisable_vga_power_on(dev);
15385 }
15386
15387 static bool primary_get_hw_state(struct intel_plane *plane)
15388 {
15389         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15390
15391         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15392 }
15393
15394 /* FIXME read out full plane state for all planes */
15395 static void readout_plane_state(struct intel_crtc *crtc)
15396 {
15397         struct drm_plane *primary = crtc->base.primary;
15398         struct intel_plane_state *plane_state =
15399                 to_intel_plane_state(primary->state);
15400
15401         plane_state->visible = crtc->active &&
15402                 primary_get_hw_state(to_intel_plane(primary));
15403
15404         if (plane_state->visible)
15405                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15406 }
15407
15408 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15409 {
15410         struct drm_i915_private *dev_priv = dev->dev_private;
15411         enum pipe pipe;
15412         struct intel_crtc *crtc;
15413         struct intel_encoder *encoder;
15414         struct intel_connector *connector;
15415         int i;
15416
15417         for_each_intel_crtc(dev, crtc) {
15418                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15419                 memset(crtc->config, 0, sizeof(*crtc->config));
15420                 crtc->config->base.crtc = &crtc->base;
15421
15422                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15423                                                                  crtc->config);
15424
15425                 crtc->base.state->active = crtc->active;
15426                 crtc->base.enabled = crtc->active;
15427
15428                 readout_plane_state(crtc);
15429
15430                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15431                               crtc->base.base.id,
15432                               crtc->active ? "enabled" : "disabled");
15433         }
15434
15435         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15436                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15437
15438                 pll->on = pll->get_hw_state(dev_priv, pll,
15439                                             &pll->config.hw_state);
15440                 pll->active = 0;
15441                 pll->config.crtc_mask = 0;
15442                 for_each_intel_crtc(dev, crtc) {
15443                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15444                                 pll->active++;
15445                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15446                         }
15447                 }
15448
15449                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15450                               pll->name, pll->config.crtc_mask, pll->on);
15451
15452                 if (pll->config.crtc_mask)
15453                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15454         }
15455
15456         for_each_intel_encoder(dev, encoder) {
15457                 pipe = 0;
15458
15459                 if (encoder->get_hw_state(encoder, &pipe)) {
15460                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15461                         encoder->base.crtc = &crtc->base;
15462                         encoder->get_config(encoder, crtc->config);
15463                 } else {
15464                         encoder->base.crtc = NULL;
15465                 }
15466
15467                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15468                               encoder->base.base.id,
15469                               encoder->base.name,
15470                               encoder->base.crtc ? "enabled" : "disabled",
15471                               pipe_name(pipe));
15472         }
15473
15474         for_each_intel_connector(dev, connector) {
15475                 if (connector->get_hw_state(connector)) {
15476                         connector->base.dpms = DRM_MODE_DPMS_ON;
15477                         connector->base.encoder = &connector->encoder->base;
15478                 } else {
15479                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15480                         connector->base.encoder = NULL;
15481                 }
15482                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15483                               connector->base.base.id,
15484                               connector->base.name,
15485                               connector->base.encoder ? "enabled" : "disabled");
15486         }
15487
15488         for_each_intel_crtc(dev, crtc) {
15489                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15490
15491                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15492                 if (crtc->base.state->active) {
15493                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15494                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15495                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15496
15497                         /*
15498                          * The initial mode needs to be set in order to keep
15499                          * the atomic core happy. It wants a valid mode if the
15500                          * crtc's enabled, so we do the above call.
15501                          *
15502                          * At this point some state updated by the connectors
15503                          * in their ->detect() callback has not run yet, so
15504                          * no recalculation can be done yet.
15505                          *
15506                          * Even if we could do a recalculation and modeset
15507                          * right now it would cause a double modeset if
15508                          * fbdev or userspace chooses a different initial mode.
15509                          *
15510                          * If that happens, someone indicated they wanted a
15511                          * mode change, which means it's safe to do a full
15512                          * recalculation.
15513                          */
15514                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15515
15516                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15517                         update_scanline_offset(crtc);
15518                 }
15519         }
15520 }
15521
15522 /* Scan out the current hw modeset state,
15523  * and sanitizes it to the current state
15524  */
15525 static void
15526 intel_modeset_setup_hw_state(struct drm_device *dev)
15527 {
15528         struct drm_i915_private *dev_priv = dev->dev_private;
15529         enum pipe pipe;
15530         struct intel_crtc *crtc;
15531         struct intel_encoder *encoder;
15532         int i;
15533
15534         intel_modeset_readout_hw_state(dev);
15535
15536         /* HW state is read out, now we need to sanitize this mess. */
15537         for_each_intel_encoder(dev, encoder) {
15538                 intel_sanitize_encoder(encoder);
15539         }
15540
15541         for_each_pipe(dev_priv, pipe) {
15542                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15543                 intel_sanitize_crtc(crtc);
15544                 intel_dump_pipe_config(crtc, crtc->config,
15545                                        "[setup_hw_state]");
15546         }
15547
15548         intel_modeset_update_connector_atomic_state(dev);
15549
15550         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15551                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15552
15553                 if (!pll->on || pll->active)
15554                         continue;
15555
15556                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15557
15558                 pll->disable(dev_priv, pll);
15559                 pll->on = false;
15560         }
15561
15562         if (IS_VALLEYVIEW(dev))
15563                 vlv_wm_get_hw_state(dev);
15564         else if (IS_GEN9(dev))
15565                 skl_wm_get_hw_state(dev);
15566         else if (HAS_PCH_SPLIT(dev))
15567                 ilk_wm_get_hw_state(dev);
15568
15569         for_each_intel_crtc(dev, crtc) {
15570                 unsigned long put_domains;
15571
15572                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15573                 if (WARN_ON(put_domains))
15574                         modeset_put_power_domains(dev_priv, put_domains);
15575         }
15576         intel_display_set_init_power(dev_priv, false);
15577 }
15578
15579 void intel_display_resume(struct drm_device *dev)
15580 {
15581         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15582         struct intel_connector *conn;
15583         struct intel_plane *plane;
15584         struct drm_crtc *crtc;
15585         int ret;
15586
15587         if (!state)
15588                 return;
15589
15590         state->acquire_ctx = dev->mode_config.acquire_ctx;
15591
15592         /* preserve complete old state, including dpll */
15593         intel_atomic_get_shared_dpll_state(state);
15594
15595         for_each_crtc(dev, crtc) {
15596                 struct drm_crtc_state *crtc_state =
15597                         drm_atomic_get_crtc_state(state, crtc);
15598
15599                 ret = PTR_ERR_OR_ZERO(crtc_state);
15600                 if (ret)
15601                         goto err;
15602
15603                 /* force a restore */
15604                 crtc_state->mode_changed = true;
15605         }
15606
15607         for_each_intel_plane(dev, plane) {
15608                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15609                 if (ret)
15610                         goto err;
15611         }
15612
15613         for_each_intel_connector(dev, conn) {
15614                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15615                 if (ret)
15616                         goto err;
15617         }
15618
15619         intel_modeset_setup_hw_state(dev);
15620
15621         i915_redisable_vga(dev);
15622         ret = drm_atomic_commit(state);
15623         if (!ret)
15624                 return;
15625
15626 err:
15627         DRM_ERROR("Restoring old state failed with %i\n", ret);
15628         drm_atomic_state_free(state);
15629 }
15630
15631 void intel_modeset_gem_init(struct drm_device *dev)
15632 {
15633         struct drm_crtc *c;
15634         struct drm_i915_gem_object *obj;
15635         int ret;
15636
15637         mutex_lock(&dev->struct_mutex);
15638         intel_init_gt_powersave(dev);
15639         mutex_unlock(&dev->struct_mutex);
15640
15641         intel_modeset_init_hw(dev);
15642
15643         intel_setup_overlay(dev);
15644
15645         /*
15646          * Make sure any fbs we allocated at startup are properly
15647          * pinned & fenced.  When we do the allocation it's too early
15648          * for this.
15649          */
15650         for_each_crtc(dev, c) {
15651                 obj = intel_fb_obj(c->primary->fb);
15652                 if (obj == NULL)
15653                         continue;
15654
15655                 mutex_lock(&dev->struct_mutex);
15656                 ret = intel_pin_and_fence_fb_obj(c->primary,
15657                                                  c->primary->fb,
15658                                                  c->primary->state);
15659                 mutex_unlock(&dev->struct_mutex);
15660                 if (ret) {
15661                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15662                                   to_intel_crtc(c)->pipe);
15663                         drm_framebuffer_unreference(c->primary->fb);
15664                         c->primary->fb = NULL;
15665                         c->primary->crtc = c->primary->state->crtc = NULL;
15666                         update_state_fb(c->primary);
15667                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15668                 }
15669         }
15670
15671         intel_backlight_register(dev);
15672 }
15673
15674 void intel_connector_unregister(struct intel_connector *intel_connector)
15675 {
15676         struct drm_connector *connector = &intel_connector->base;
15677
15678         intel_panel_destroy_backlight(connector);
15679         drm_connector_unregister(connector);
15680 }
15681
15682 void intel_modeset_cleanup(struct drm_device *dev)
15683 {
15684         struct drm_i915_private *dev_priv = dev->dev_private;
15685         struct drm_connector *connector;
15686
15687         intel_disable_gt_powersave(dev);
15688
15689         intel_backlight_unregister(dev);
15690
15691         /*
15692          * Interrupts and polling as the first thing to avoid creating havoc.
15693          * Too much stuff here (turning of connectors, ...) would
15694          * experience fancy races otherwise.
15695          */
15696         intel_irq_uninstall(dev_priv);
15697
15698         /*
15699          * Due to the hpd irq storm handling the hotplug work can re-arm the
15700          * poll handlers. Hence disable polling after hpd handling is shut down.
15701          */
15702         drm_kms_helper_poll_fini(dev);
15703
15704         intel_unregister_dsm_handler();
15705
15706         intel_fbc_disable(dev_priv);
15707
15708         /* flush any delayed tasks or pending work */
15709         flush_scheduled_work();
15710
15711         /* destroy the backlight and sysfs files before encoders/connectors */
15712         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15713                 struct intel_connector *intel_connector;
15714
15715                 intel_connector = to_intel_connector(connector);
15716                 intel_connector->unregister(intel_connector);
15717         }
15718
15719         drm_mode_config_cleanup(dev);
15720
15721         intel_cleanup_overlay(dev);
15722
15723         mutex_lock(&dev->struct_mutex);
15724         intel_cleanup_gt_powersave(dev);
15725         mutex_unlock(&dev->struct_mutex);
15726 }
15727
15728 /*
15729  * Return which encoder is currently attached for connector.
15730  */
15731 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15732 {
15733         return &intel_attached_encoder(connector)->base;
15734 }
15735
15736 void intel_connector_attach_encoder(struct intel_connector *connector,
15737                                     struct intel_encoder *encoder)
15738 {
15739         connector->encoder = encoder;
15740         drm_mode_connector_attach_encoder(&connector->base,
15741                                           &encoder->base);
15742 }
15743
15744 /*
15745  * set vga decode state - true == enable VGA decode
15746  */
15747 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15748 {
15749         struct drm_i915_private *dev_priv = dev->dev_private;
15750         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15751         u16 gmch_ctrl;
15752
15753         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15754                 DRM_ERROR("failed to read control word\n");
15755                 return -EIO;
15756         }
15757
15758         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15759                 return 0;
15760
15761         if (state)
15762                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15763         else
15764                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15765
15766         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15767                 DRM_ERROR("failed to write control word\n");
15768                 return -EIO;
15769         }
15770
15771         return 0;
15772 }
15773
15774 struct intel_display_error_state {
15775
15776         u32 power_well_driver;
15777
15778         int num_transcoders;
15779
15780         struct intel_cursor_error_state {
15781                 u32 control;
15782                 u32 position;
15783                 u32 base;
15784                 u32 size;
15785         } cursor[I915_MAX_PIPES];
15786
15787         struct intel_pipe_error_state {
15788                 bool power_domain_on;
15789                 u32 source;
15790                 u32 stat;
15791         } pipe[I915_MAX_PIPES];
15792
15793         struct intel_plane_error_state {
15794                 u32 control;
15795                 u32 stride;
15796                 u32 size;
15797                 u32 pos;
15798                 u32 addr;
15799                 u32 surface;
15800                 u32 tile_offset;
15801         } plane[I915_MAX_PIPES];
15802
15803         struct intel_transcoder_error_state {
15804                 bool power_domain_on;
15805                 enum transcoder cpu_transcoder;
15806
15807                 u32 conf;
15808
15809                 u32 htotal;
15810                 u32 hblank;
15811                 u32 hsync;
15812                 u32 vtotal;
15813                 u32 vblank;
15814                 u32 vsync;
15815         } transcoder[4];
15816 };
15817
15818 struct intel_display_error_state *
15819 intel_display_capture_error_state(struct drm_device *dev)
15820 {
15821         struct drm_i915_private *dev_priv = dev->dev_private;
15822         struct intel_display_error_state *error;
15823         int transcoders[] = {
15824                 TRANSCODER_A,
15825                 TRANSCODER_B,
15826                 TRANSCODER_C,
15827                 TRANSCODER_EDP,
15828         };
15829         int i;
15830
15831         if (INTEL_INFO(dev)->num_pipes == 0)
15832                 return NULL;
15833
15834         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15835         if (error == NULL)
15836                 return NULL;
15837
15838         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15839                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15840
15841         for_each_pipe(dev_priv, i) {
15842                 error->pipe[i].power_domain_on =
15843                         __intel_display_power_is_enabled(dev_priv,
15844                                                          POWER_DOMAIN_PIPE(i));
15845                 if (!error->pipe[i].power_domain_on)
15846                         continue;
15847
15848                 error->cursor[i].control = I915_READ(CURCNTR(i));
15849                 error->cursor[i].position = I915_READ(CURPOS(i));
15850                 error->cursor[i].base = I915_READ(CURBASE(i));
15851
15852                 error->plane[i].control = I915_READ(DSPCNTR(i));
15853                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15854                 if (INTEL_INFO(dev)->gen <= 3) {
15855                         error->plane[i].size = I915_READ(DSPSIZE(i));
15856                         error->plane[i].pos = I915_READ(DSPPOS(i));
15857                 }
15858                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15859                         error->plane[i].addr = I915_READ(DSPADDR(i));
15860                 if (INTEL_INFO(dev)->gen >= 4) {
15861                         error->plane[i].surface = I915_READ(DSPSURF(i));
15862                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15863                 }
15864
15865                 error->pipe[i].source = I915_READ(PIPESRC(i));
15866
15867                 if (HAS_GMCH_DISPLAY(dev))
15868                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15869         }
15870
15871         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15872         if (HAS_DDI(dev_priv->dev))
15873                 error->num_transcoders++; /* Account for eDP. */
15874
15875         for (i = 0; i < error->num_transcoders; i++) {
15876                 enum transcoder cpu_transcoder = transcoders[i];
15877
15878                 error->transcoder[i].power_domain_on =
15879                         __intel_display_power_is_enabled(dev_priv,
15880                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15881                 if (!error->transcoder[i].power_domain_on)
15882                         continue;
15883
15884                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15885
15886                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15887                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15888                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15889                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15890                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15891                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15892                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15893         }
15894
15895         return error;
15896 }
15897
15898 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15899
15900 void
15901 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15902                                 struct drm_device *dev,
15903                                 struct intel_display_error_state *error)
15904 {
15905         struct drm_i915_private *dev_priv = dev->dev_private;
15906         int i;
15907
15908         if (!error)
15909                 return;
15910
15911         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15912         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15913                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15914                            error->power_well_driver);
15915         for_each_pipe(dev_priv, i) {
15916                 err_printf(m, "Pipe [%d]:\n", i);
15917                 err_printf(m, "  Power: %s\n",
15918                            error->pipe[i].power_domain_on ? "on" : "off");
15919                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15920                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15921
15922                 err_printf(m, "Plane [%d]:\n", i);
15923                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15924                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15925                 if (INTEL_INFO(dev)->gen <= 3) {
15926                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15927                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15928                 }
15929                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15930                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15931                 if (INTEL_INFO(dev)->gen >= 4) {
15932                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15933                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15934                 }
15935
15936                 err_printf(m, "Cursor [%d]:\n", i);
15937                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15938                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15939                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15940         }
15941
15942         for (i = 0; i < error->num_transcoders; i++) {
15943                 err_printf(m, "CPU transcoder: %c\n",
15944                            transcoder_name(error->transcoder[i].cpu_transcoder));
15945                 err_printf(m, "  Power: %s\n",
15946                            error->transcoder[i].power_domain_on ? "on" : "off");
15947                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15948                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15949                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15950                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15951                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15952                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15953                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15954         }
15955 }
15956
15957 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15958 {
15959         struct intel_crtc *crtc;
15960
15961         for_each_intel_crtc(dev, crtc) {
15962                 struct intel_unpin_work *work;
15963
15964                 spin_lock_irq(&dev->event_lock);
15965
15966                 work = crtc->unpin_work;
15967
15968                 if (work && work->event &&
15969                     work->event->base.file_priv == file) {
15970                         kfree(work->event);
15971                         work->event = NULL;
15972                 }
15973
15974                 spin_unlock_irq(&dev->event_lock);
15975         }
15976 }