1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
33 (pipe) == PIPE_B ? (b) : (c))
34 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
35 (port) == PORT_B ? (b) : (c))
37 #define _MASKED_FIELD(mask, value) ({ \
38 if (__builtin_constant_p(mask)) \
39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
40 if (__builtin_constant_p(value)) \
41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
43 BUILD_BUG_ON_MSG((value) & ~(mask), \
44 "Incorrect value for mask"); \
45 (mask) << 16 | (value); })
46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
47 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
51 /* PCI config space */
53 #define HPLLCC 0xc0 /* 85x only */
54 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
55 #define GC_CLOCK_133_200 (0 << 0)
56 #define GC_CLOCK_100_200 (1 << 0)
57 #define GC_CLOCK_100_133 (2 << 0)
58 #define GC_CLOCK_133_266 (3 << 0)
59 #define GC_CLOCK_133_200_2 (4 << 0)
60 #define GC_CLOCK_133_266_2 (5 << 0)
61 #define GC_CLOCK_166_266 (6 << 0)
62 #define GC_CLOCK_166_250 (7 << 0)
65 #define GCFGC 0xf0 /* 915+ only */
66 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
67 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
68 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
69 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
70 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
71 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
72 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
73 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
74 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
75 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
76 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
77 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
78 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
79 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
80 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
81 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
82 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
83 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
84 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
85 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
86 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
87 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
90 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
91 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
92 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
93 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
94 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
96 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
99 /* Graphics reset regs */
100 #define I915_GDRST 0xc0 /* PCI config register */
101 #define GRDOM_FULL (0<<2)
102 #define GRDOM_RENDER (1<<2)
103 #define GRDOM_MEDIA (3<<2)
104 #define GRDOM_MASK (3<<2)
105 #define GRDOM_RESET_STATUS (1<<1)
106 #define GRDOM_RESET_ENABLE (1<<0)
108 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
109 #define ILK_GRDOM_FULL (0<<1)
110 #define ILK_GRDOM_RENDER (1<<1)
111 #define ILK_GRDOM_MEDIA (3<<1)
112 #define ILK_GRDOM_MASK (3<<1)
113 #define ILK_GRDOM_RESET_ENABLE (1<<0)
115 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
116 #define GEN6_MBC_SNPCR_SHIFT 21
117 #define GEN6_MBC_SNPCR_MASK (3<<21)
118 #define GEN6_MBC_SNPCR_MAX (0<<21)
119 #define GEN6_MBC_SNPCR_MED (1<<21)
120 #define GEN6_MBC_SNPCR_LOW (2<<21)
121 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
123 #define VLV_G3DCTL 0x9024
124 #define VLV_GSCKGCTL 0x9028
126 #define GEN6_MBCTL 0x0907c
127 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
128 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
129 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
130 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
131 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
133 #define GEN6_GDRST 0x941c
134 #define GEN6_GRDOM_FULL (1 << 0)
135 #define GEN6_GRDOM_RENDER (1 << 1)
136 #define GEN6_GRDOM_MEDIA (1 << 2)
137 #define GEN6_GRDOM_BLT (1 << 3)
139 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
140 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
141 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
142 #define PP_DIR_DCLV_2G 0xffffffff
144 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
145 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
147 #define GEN8_R_PWR_CLK_STATE 0x20C8
148 #define GEN8_RPCS_ENABLE (1 << 31)
149 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
150 #define GEN8_RPCS_S_CNT_SHIFT 15
151 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
152 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
153 #define GEN8_RPCS_SS_CNT_SHIFT 8
154 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
155 #define GEN8_RPCS_EU_MAX_SHIFT 4
156 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
157 #define GEN8_RPCS_EU_MIN_SHIFT 0
158 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
160 #define GAM_ECOCHK 0x4090
161 #define BDW_DISABLE_HDC_INVALIDATION (1<<25)
162 #define ECOCHK_SNB_BIT (1<<10)
163 #define ECOCHK_DIS_TLB (1<<8)
164 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
165 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
166 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
167 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
168 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
169 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
170 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
171 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
173 #define GAC_ECO_BITS 0x14090
174 #define ECOBITS_SNB_BIT (1<<13)
175 #define ECOBITS_PPGTT_CACHE64B (3<<8)
176 #define ECOBITS_PPGTT_CACHE4B (0<<8)
178 #define GAB_CTL 0x24000
179 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
181 #define GEN7_BIOS_RESERVED 0x1082C0
182 #define GEN7_BIOS_RESERVED_1M (0 << 5)
183 #define GEN7_BIOS_RESERVED_256K (1 << 5)
184 #define GEN8_BIOS_RESERVED_SHIFT 7
185 #define GEN7_BIOS_RESERVED_MASK 0x1
186 #define GEN8_BIOS_RESERVED_MASK 0x3
191 #define VGA_ST01_MDA 0x3ba
192 #define VGA_ST01_CGA 0x3da
194 #define VGA_MSR_WRITE 0x3c2
195 #define VGA_MSR_READ 0x3cc
196 #define VGA_MSR_MEM_EN (1<<1)
197 #define VGA_MSR_CGA_MODE (1<<0)
199 #define VGA_SR_INDEX 0x3c4
201 #define VGA_SR_DATA 0x3c5
203 #define VGA_AR_INDEX 0x3c0
204 #define VGA_AR_VID_EN (1<<5)
205 #define VGA_AR_DATA_WRITE 0x3c0
206 #define VGA_AR_DATA_READ 0x3c1
208 #define VGA_GR_INDEX 0x3ce
209 #define VGA_GR_DATA 0x3cf
211 #define VGA_GR_MEM_READ_MODE_SHIFT 3
212 #define VGA_GR_MEM_READ_MODE_PLANE 1
214 #define VGA_GR_MEM_MODE_MASK 0xc
215 #define VGA_GR_MEM_MODE_SHIFT 2
216 #define VGA_GR_MEM_A0000_AFFFF 0
217 #define VGA_GR_MEM_A0000_BFFFF 1
218 #define VGA_GR_MEM_B0000_B7FFF 2
219 #define VGA_GR_MEM_B0000_BFFFF 3
221 #define VGA_DACMASK 0x3c6
222 #define VGA_DACRX 0x3c7
223 #define VGA_DACWX 0x3c8
224 #define VGA_DACDATA 0x3c9
226 #define VGA_CR_INDEX_MDA 0x3b4
227 #define VGA_CR_DATA_MDA 0x3b5
228 #define VGA_CR_INDEX_CGA 0x3d4
229 #define VGA_CR_DATA_CGA 0x3d5
232 * Instruction field definitions used by the command parser
234 #define INSTR_CLIENT_SHIFT 29
235 #define INSTR_CLIENT_MASK 0xE0000000
236 #define INSTR_MI_CLIENT 0x0
237 #define INSTR_BC_CLIENT 0x2
238 #define INSTR_RC_CLIENT 0x3
239 #define INSTR_SUBCLIENT_SHIFT 27
240 #define INSTR_SUBCLIENT_MASK 0x18000000
241 #define INSTR_MEDIA_SUBCLIENT 0x2
242 #define INSTR_26_TO_24_MASK 0x7000000
243 #define INSTR_26_TO_24_SHIFT 24
246 * Memory interface instructions used by the kernel
248 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
249 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
250 #define MI_GLOBAL_GTT (1<<22)
252 #define MI_NOOP MI_INSTR(0, 0)
253 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
254 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
255 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
256 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
257 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
258 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
259 #define MI_FLUSH MI_INSTR(0x04, 0)
260 #define MI_READ_FLUSH (1 << 0)
261 #define MI_EXE_FLUSH (1 << 1)
262 #define MI_NO_WRITE_FLUSH (1 << 2)
263 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
264 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
265 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
266 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
267 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
268 #define MI_ARB_ENABLE (1<<0)
269 #define MI_ARB_DISABLE (0<<0)
270 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
271 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
272 #define MI_SUSPEND_FLUSH_EN (1<<0)
273 #define MI_SET_APPID MI_INSTR(0x0e, 0)
274 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
275 #define MI_OVERLAY_CONTINUE (0x0<<21)
276 #define MI_OVERLAY_ON (0x1<<21)
277 #define MI_OVERLAY_OFF (0x2<<21)
278 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
279 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
280 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
281 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
282 /* IVB has funny definitions for which plane to flip. */
283 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
284 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
285 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
286 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
287 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
288 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
290 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
291 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
292 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
293 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
294 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
295 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
296 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
297 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
298 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
299 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
300 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
301 #define MI_SEMAPHORE_UPDATE (1<<21)
302 #define MI_SEMAPHORE_COMPARE (1<<20)
303 #define MI_SEMAPHORE_REGISTER (1<<18)
304 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
305 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
306 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
307 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
308 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
309 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
310 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
311 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
312 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
313 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
314 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
315 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
316 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
317 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
318 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
319 #define MI_MM_SPACE_GTT (1<<8)
320 #define MI_MM_SPACE_PHYSICAL (0<<8)
321 #define MI_SAVE_EXT_STATE_EN (1<<3)
322 #define MI_RESTORE_EXT_STATE_EN (1<<2)
323 #define MI_FORCE_RESTORE (1<<1)
324 #define MI_RESTORE_INHIBIT (1<<0)
325 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
326 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
327 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
328 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
329 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
330 #define MI_SEMAPHORE_POLL (1<<15)
331 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
332 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
333 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
334 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
335 #define MI_USE_GGTT (1 << 22) /* g4x+ */
336 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
337 #define MI_STORE_DWORD_INDEX_SHIFT 2
338 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
339 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
340 * simply ignores the register load under certain conditions.
341 * - One can actually load arbitrary many arbitrary registers: Simply issue x
342 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
344 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
345 #define MI_LRI_FORCE_POSTED (1<<12)
346 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
347 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
348 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
349 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
350 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
351 #define MI_INVALIDATE_TLB (1<<18)
352 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
353 #define MI_FLUSH_DW_OP_MASK (3<<14)
354 #define MI_FLUSH_DW_NOTIFY (1<<8)
355 #define MI_INVALIDATE_BSD (1<<7)
356 #define MI_FLUSH_DW_USE_GTT (1<<2)
357 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
358 #define MI_LOAD_REGISTER_MEM(x) MI_INSTR(0x29, 2*(x)-1)
359 #define MI_LOAD_REGISTER_MEM_GEN8(x) MI_INSTR(0x29, 3*(x)-1)
360 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
361 #define MI_BATCH_NON_SECURE (1)
362 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
363 #define MI_BATCH_NON_SECURE_I965 (1<<8)
364 #define MI_BATCH_PPGTT_HSW (1<<8)
365 #define MI_BATCH_NON_SECURE_HSW (1<<13)
366 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
367 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
368 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
369 #define MI_BATCH_RESOURCE_STREAMER (1<<10)
371 #define MI_PREDICATE_SRC0 (0x2400)
372 #define MI_PREDICATE_SRC1 (0x2408)
374 #define MI_PREDICATE_RESULT_2 (0x2214)
375 #define LOWER_SLICE_ENABLED (1<<0)
376 #define LOWER_SLICE_DISABLED (0<<0)
379 * 3D instructions used by the kernel
381 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
383 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
384 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
385 #define SC_UPDATE_SCISSOR (0x1<<1)
386 #define SC_ENABLE_MASK (0x1<<0)
387 #define SC_ENABLE (0x1<<0)
388 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
389 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
390 #define SCI_YMIN_MASK (0xffff<<16)
391 #define SCI_XMIN_MASK (0xffff<<0)
392 #define SCI_YMAX_MASK (0xffff<<16)
393 #define SCI_XMAX_MASK (0xffff<<0)
394 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
395 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
396 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
397 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
398 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
399 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
400 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
401 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
402 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
404 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
405 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
406 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
407 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
408 #define BLT_WRITE_A (2<<20)
409 #define BLT_WRITE_RGB (1<<20)
410 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
411 #define BLT_DEPTH_8 (0<<24)
412 #define BLT_DEPTH_16_565 (1<<24)
413 #define BLT_DEPTH_16_1555 (2<<24)
414 #define BLT_DEPTH_32 (3<<24)
415 #define BLT_ROP_SRC_COPY (0xcc<<16)
416 #define BLT_ROP_COLOR_COPY (0xf0<<16)
417 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
418 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
419 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
420 #define ASYNC_FLIP (1<<22)
421 #define DISPLAY_PLANE_A (0<<20)
422 #define DISPLAY_PLANE_B (1<<20)
423 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
424 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
425 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
426 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
427 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
428 #define PIPE_CONTROL_CS_STALL (1<<20)
429 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
430 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
431 #define PIPE_CONTROL_QW_WRITE (1<<14)
432 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
433 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
434 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
435 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
436 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
437 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
438 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
439 #define PIPE_CONTROL_NOTIFY (1<<8)
440 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
441 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
442 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
443 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
444 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
445 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
446 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
447 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
450 * Commands used only by the command parser
452 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
453 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
454 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
455 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
456 #define MI_PREDICATE MI_INSTR(0x0C, 0)
457 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
458 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
459 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
460 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
461 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
462 #define MI_CLFLUSH MI_INSTR(0x27, 0)
463 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
464 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
465 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
466 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
467 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
468 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
469 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
471 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
472 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
473 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
474 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
475 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
476 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
477 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
478 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
479 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
480 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
481 #define GFX_OP_3DSTATE_SO_DECL_LIST \
482 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
484 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
485 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
486 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
487 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
488 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
489 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
490 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
491 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
492 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
493 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
495 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
497 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
498 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
501 * Registers used only by the command parser
503 #define BCS_SWCTRL 0x22200
505 #define GPGPU_THREADS_DISPATCHED 0x2290
506 #define HS_INVOCATION_COUNT 0x2300
507 #define DS_INVOCATION_COUNT 0x2308
508 #define IA_VERTICES_COUNT 0x2310
509 #define IA_PRIMITIVES_COUNT 0x2318
510 #define VS_INVOCATION_COUNT 0x2320
511 #define GS_INVOCATION_COUNT 0x2328
512 #define GS_PRIMITIVES_COUNT 0x2330
513 #define CL_INVOCATION_COUNT 0x2338
514 #define CL_PRIMITIVES_COUNT 0x2340
515 #define PS_INVOCATION_COUNT 0x2348
516 #define PS_DEPTH_COUNT 0x2350
518 /* There are the 4 64-bit counter registers, one for each stream output */
519 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
521 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
523 #define GEN7_3DPRIM_END_OFFSET 0x2420
524 #define GEN7_3DPRIM_START_VERTEX 0x2430
525 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
526 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
527 #define GEN7_3DPRIM_START_INSTANCE 0x243C
528 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
530 #define OACONTROL 0x2360
532 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
533 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
534 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
535 _GEN7_PIPEA_DE_LOAD_SL, \
536 _GEN7_PIPEB_DE_LOAD_SL)
541 #define DEBUG_RESET_I830 0x6070
542 #define DEBUG_RESET_FULL (1<<7)
543 #define DEBUG_RESET_RENDER (1<<8)
544 #define DEBUG_RESET_DISPLAY (1<<9)
549 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
550 #define IOSF_DEVFN_SHIFT 24
551 #define IOSF_OPCODE_SHIFT 16
552 #define IOSF_PORT_SHIFT 8
553 #define IOSF_BYTE_ENABLES_SHIFT 4
554 #define IOSF_BAR_SHIFT 1
555 #define IOSF_SB_BUSY (1<<0)
556 #define IOSF_PORT_BUNIT 0x3
557 #define IOSF_PORT_PUNIT 0x4
558 #define IOSF_PORT_NC 0x11
559 #define IOSF_PORT_DPIO 0x12
560 #define IOSF_PORT_DPIO_2 0x1a
561 #define IOSF_PORT_GPIO_NC 0x13
562 #define IOSF_PORT_CCK 0x14
563 #define IOSF_PORT_CCU 0xA9
564 #define IOSF_PORT_GPS_CORE 0x48
565 #define IOSF_PORT_FLISDSI 0x1B
566 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
567 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
569 /* See configdb bunit SB addr map */
570 #define BUNIT_REG_BISOC 0x11
572 #define PUNIT_REG_DSPFREQ 0x36
573 #define DSPFREQSTAT_SHIFT_CHV 24
574 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
575 #define DSPFREQGUAR_SHIFT_CHV 8
576 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
577 #define DSPFREQSTAT_SHIFT 30
578 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
579 #define DSPFREQGUAR_SHIFT 14
580 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
581 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
582 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
583 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
584 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
585 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
586 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
587 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
588 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
589 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
590 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
591 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
592 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
593 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
594 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
595 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
597 /* See the PUNIT HAS v0.8 for the below bits */
598 enum punit_power_well {
599 PUNIT_POWER_WELL_RENDER = 0,
600 PUNIT_POWER_WELL_MEDIA = 1,
601 PUNIT_POWER_WELL_DISP2D = 3,
602 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
603 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
604 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
605 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
606 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
607 PUNIT_POWER_WELL_DPIO_RX0 = 10,
608 PUNIT_POWER_WELL_DPIO_RX1 = 11,
609 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
611 PUNIT_POWER_WELL_NUM,
614 enum skl_disp_power_wells {
624 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
625 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
627 #define PUNIT_REG_PWRGT_CTRL 0x60
628 #define PUNIT_REG_PWRGT_STATUS 0x61
629 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
630 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
631 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
632 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
633 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
635 #define PUNIT_REG_GPU_LFM 0xd3
636 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
637 #define PUNIT_REG_GPU_FREQ_STS 0xd8
638 #define GPLLENABLE (1<<4)
639 #define GENFREQSTATUS (1<<0)
640 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
641 #define PUNIT_REG_CZ_TIMESTAMP 0xce
643 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
644 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
646 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
647 #define FB_GFX_FREQ_FUSE_MASK 0xff
648 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
649 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
650 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
652 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
653 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
655 #define PUNIT_REG_DDR_SETUP2 0x139
656 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
657 #define FORCE_DDR_LOW_FREQ (1 << 1)
658 #define FORCE_DDR_HIGH_FREQ (1 << 0)
660 #define PUNIT_GPU_STATUS_REG 0xdb
661 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
662 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
663 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
664 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
666 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
667 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
668 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
670 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
671 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
672 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
673 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
674 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
675 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
676 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
677 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
678 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
679 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
681 #define VLV_TURBO_SOC_OVERRIDE 0x04
682 #define VLV_OVERRIDE_EN 1
683 #define VLV_SOC_TDP_EN (1 << 1)
684 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
685 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
687 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
689 /* vlv2 north clock has */
690 #define CCK_FUSE_REG 0x8
691 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
692 #define CCK_REG_DSI_PLL_FUSE 0x44
693 #define CCK_REG_DSI_PLL_CONTROL 0x48
694 #define DSI_PLL_VCO_EN (1 << 31)
695 #define DSI_PLL_LDO_GATE (1 << 30)
696 #define DSI_PLL_P1_POST_DIV_SHIFT 17
697 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
698 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
699 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
700 #define DSI_PLL_MUX_MASK (3 << 9)
701 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
702 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
703 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
704 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
705 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
706 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
707 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
708 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
709 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
710 #define DSI_PLL_LOCK (1 << 0)
711 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
712 #define DSI_PLL_LFSR (1 << 31)
713 #define DSI_PLL_FRACTION_EN (1 << 30)
714 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
715 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
716 #define DSI_PLL_USYNC_CNT_SHIFT 18
717 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
718 #define DSI_PLL_N1_DIV_SHIFT 16
719 #define DSI_PLL_N1_DIV_MASK (3 << 16)
720 #define DSI_PLL_M1_DIV_SHIFT 0
721 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
722 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
723 #define DISPLAY_TRUNK_FORCE_ON (1 << 17)
724 #define DISPLAY_TRUNK_FORCE_OFF (1 << 16)
725 #define DISPLAY_FREQUENCY_STATUS (0x1f << 8)
726 #define DISPLAY_FREQUENCY_STATUS_SHIFT 8
727 #define DISPLAY_FREQUENCY_VALUES (0x1f << 0)
732 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
733 * ports. DPIO is the name given to such a display PHY. These PHYs
734 * don't follow the standard programming model using direct MMIO
735 * registers, and instead their registers must be accessed trough IOSF
736 * sideband. VLV has one such PHY for driving ports B and C, and CHV
737 * adds another PHY for driving port D. Each PHY responds to specific
740 * Each display PHY is made up of one or two channels. Each channel
741 * houses a common lane part which contains the PLL and other common
742 * logic. CH0 common lane also contains the IOSF-SB logic for the
743 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
744 * must be running when any DPIO registers are accessed.
746 * In addition to having their own registers, the PHYs are also
747 * controlled through some dedicated signals from the display
748 * controller. These include PLL reference clock enable, PLL enable,
749 * and CRI clock selection, for example.
751 * Eeach channel also has two splines (also called data lanes), and
752 * each spline is made up of one Physical Access Coding Sub-Layer
753 * (PCS) block and two TX lanes. So each channel has two PCS blocks
754 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
755 * data/clock pairs depending on the output type.
757 * Additionally the PHY also contains an AUX lane with AUX blocks
758 * for each channel. This is used for DP AUX communication, but
759 * this fact isn't really relevant for the driver since AUX is
760 * controlled from the display controller side. No DPIO registers
761 * need to be accessed during AUX communication,
763 * Generally on VLV/CHV the common lane corresponds to the pipe and
764 * the spline (PCS/TX) corresponds to the port.
766 * For dual channel PHY (VLV/CHV):
768 * pipe A == CMN/PLL/REF CH0
770 * pipe B == CMN/PLL/REF CH1
772 * port B == PCS/TX CH0
774 * port C == PCS/TX CH1
776 * This is especially important when we cross the streams
777 * ie. drive port B with pipe B, or port C with pipe A.
779 * For single channel PHY (CHV):
781 * pipe C == CMN/PLL/REF CH0
783 * port D == PCS/TX CH0
785 * On BXT the entire PHY channel corresponds to the port. That means
786 * the PLL is also now associated with the port rather than the pipe,
787 * and so the clock needs to be routed to the appropriate transcoder.
788 * Port A PLL is directly connected to transcoder EDP and port B/C
789 * PLLs can be routed to any transcoder A/B/C.
791 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
792 * digital port D (CHV) or port A (BXT).
795 * Dual channel PHY (VLV/CHV/BXT)
796 * ---------------------------------
798 * | CMN/PLL/REF | CMN/PLL/REF |
799 * |---------------|---------------| Display PHY
800 * | PCS01 | PCS23 | PCS01 | PCS23 |
801 * |-------|-------|-------|-------|
802 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
803 * ---------------------------------
804 * | DDI0 | DDI1 | DP/HDMI ports
805 * ---------------------------------
807 * Single channel PHY (CHV/BXT)
811 * |---------------| Display PHY
816 * | DDI2 | DP/HDMI port
821 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
822 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
823 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
824 #define DPIO_SFR_BYPASS (1<<1)
825 #define DPIO_CMNRST (1<<0)
827 #define DPIO_PHY(pipe) ((pipe) >> 1)
828 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
831 * Per pipe/PLL DPIO regs
833 #define _VLV_PLL_DW3_CH0 0x800c
834 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
835 #define DPIO_POST_DIV_DAC 0
836 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
837 #define DPIO_POST_DIV_LVDS1 2
838 #define DPIO_POST_DIV_LVDS2 3
839 #define DPIO_K_SHIFT (24) /* 4 bits */
840 #define DPIO_P1_SHIFT (21) /* 3 bits */
841 #define DPIO_P2_SHIFT (16) /* 5 bits */
842 #define DPIO_N_SHIFT (12) /* 4 bits */
843 #define DPIO_ENABLE_CALIBRATION (1<<11)
844 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
845 #define DPIO_M2DIV_MASK 0xff
846 #define _VLV_PLL_DW3_CH1 0x802c
847 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
849 #define _VLV_PLL_DW5_CH0 0x8014
850 #define DPIO_REFSEL_OVERRIDE 27
851 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
852 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
853 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
854 #define DPIO_PLL_REFCLK_SEL_MASK 3
855 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
856 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
857 #define _VLV_PLL_DW5_CH1 0x8034
858 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
860 #define _VLV_PLL_DW7_CH0 0x801c
861 #define _VLV_PLL_DW7_CH1 0x803c
862 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
864 #define _VLV_PLL_DW8_CH0 0x8040
865 #define _VLV_PLL_DW8_CH1 0x8060
866 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
868 #define VLV_PLL_DW9_BCAST 0xc044
869 #define _VLV_PLL_DW9_CH0 0x8044
870 #define _VLV_PLL_DW9_CH1 0x8064
871 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
873 #define _VLV_PLL_DW10_CH0 0x8048
874 #define _VLV_PLL_DW10_CH1 0x8068
875 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
877 #define _VLV_PLL_DW11_CH0 0x804c
878 #define _VLV_PLL_DW11_CH1 0x806c
879 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
881 /* Spec for ref block start counts at DW10 */
882 #define VLV_REF_DW13 0x80ac
884 #define VLV_CMN_DW0 0x8100
887 * Per DDI channel DPIO regs
890 #define _VLV_PCS_DW0_CH0 0x8200
891 #define _VLV_PCS_DW0_CH1 0x8400
892 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
893 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
894 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
895 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
896 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
898 #define _VLV_PCS01_DW0_CH0 0x200
899 #define _VLV_PCS23_DW0_CH0 0x400
900 #define _VLV_PCS01_DW0_CH1 0x2600
901 #define _VLV_PCS23_DW0_CH1 0x2800
902 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
903 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
905 #define _VLV_PCS_DW1_CH0 0x8204
906 #define _VLV_PCS_DW1_CH1 0x8404
907 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
908 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
909 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
910 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
911 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
912 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
914 #define _VLV_PCS01_DW1_CH0 0x204
915 #define _VLV_PCS23_DW1_CH0 0x404
916 #define _VLV_PCS01_DW1_CH1 0x2604
917 #define _VLV_PCS23_DW1_CH1 0x2804
918 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
919 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
921 #define _VLV_PCS_DW8_CH0 0x8220
922 #define _VLV_PCS_DW8_CH1 0x8420
923 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
924 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
925 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
927 #define _VLV_PCS01_DW8_CH0 0x0220
928 #define _VLV_PCS23_DW8_CH0 0x0420
929 #define _VLV_PCS01_DW8_CH1 0x2620
930 #define _VLV_PCS23_DW8_CH1 0x2820
931 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
932 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
934 #define _VLV_PCS_DW9_CH0 0x8224
935 #define _VLV_PCS_DW9_CH1 0x8424
936 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
937 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
938 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
939 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
940 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
941 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
942 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
944 #define _VLV_PCS01_DW9_CH0 0x224
945 #define _VLV_PCS23_DW9_CH0 0x424
946 #define _VLV_PCS01_DW9_CH1 0x2624
947 #define _VLV_PCS23_DW9_CH1 0x2824
948 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
949 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
951 #define _CHV_PCS_DW10_CH0 0x8228
952 #define _CHV_PCS_DW10_CH1 0x8428
953 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
954 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
955 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
956 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
957 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
958 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
959 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
960 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
961 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
963 #define _VLV_PCS01_DW10_CH0 0x0228
964 #define _VLV_PCS23_DW10_CH0 0x0428
965 #define _VLV_PCS01_DW10_CH1 0x2628
966 #define _VLV_PCS23_DW10_CH1 0x2828
967 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
968 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
970 #define _VLV_PCS_DW11_CH0 0x822c
971 #define _VLV_PCS_DW11_CH1 0x842c
972 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
973 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
974 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
975 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
976 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
978 #define _VLV_PCS01_DW11_CH0 0x022c
979 #define _VLV_PCS23_DW11_CH0 0x042c
980 #define _VLV_PCS01_DW11_CH1 0x262c
981 #define _VLV_PCS23_DW11_CH1 0x282c
982 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
983 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
985 #define _VLV_PCS01_DW12_CH0 0x0230
986 #define _VLV_PCS23_DW12_CH0 0x0430
987 #define _VLV_PCS01_DW12_CH1 0x2630
988 #define _VLV_PCS23_DW12_CH1 0x2830
989 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
990 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
992 #define _VLV_PCS_DW12_CH0 0x8230
993 #define _VLV_PCS_DW12_CH1 0x8430
994 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
995 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
996 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
997 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
998 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
999 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1001 #define _VLV_PCS_DW14_CH0 0x8238
1002 #define _VLV_PCS_DW14_CH1 0x8438
1003 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1005 #define _VLV_PCS_DW23_CH0 0x825c
1006 #define _VLV_PCS_DW23_CH1 0x845c
1007 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1009 #define _VLV_TX_DW2_CH0 0x8288
1010 #define _VLV_TX_DW2_CH1 0x8488
1011 #define DPIO_SWING_MARGIN000_SHIFT 16
1012 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1013 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1014 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1016 #define _VLV_TX_DW3_CH0 0x828c
1017 #define _VLV_TX_DW3_CH1 0x848c
1018 /* The following bit for CHV phy */
1019 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1020 #define DPIO_SWING_MARGIN101_SHIFT 16
1021 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1022 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1024 #define _VLV_TX_DW4_CH0 0x8290
1025 #define _VLV_TX_DW4_CH1 0x8490
1026 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1027 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1028 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1029 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1030 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1032 #define _VLV_TX3_DW4_CH0 0x690
1033 #define _VLV_TX3_DW4_CH1 0x2a90
1034 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1036 #define _VLV_TX_DW5_CH0 0x8294
1037 #define _VLV_TX_DW5_CH1 0x8494
1038 #define DPIO_TX_OCALINIT_EN (1<<31)
1039 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1041 #define _VLV_TX_DW11_CH0 0x82ac
1042 #define _VLV_TX_DW11_CH1 0x84ac
1043 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1045 #define _VLV_TX_DW14_CH0 0x82b8
1046 #define _VLV_TX_DW14_CH1 0x84b8
1047 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1049 /* CHV dpPhy registers */
1050 #define _CHV_PLL_DW0_CH0 0x8000
1051 #define _CHV_PLL_DW0_CH1 0x8180
1052 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1054 #define _CHV_PLL_DW1_CH0 0x8004
1055 #define _CHV_PLL_DW1_CH1 0x8184
1056 #define DPIO_CHV_N_DIV_SHIFT 8
1057 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1058 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1060 #define _CHV_PLL_DW2_CH0 0x8008
1061 #define _CHV_PLL_DW2_CH1 0x8188
1062 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1064 #define _CHV_PLL_DW3_CH0 0x800c
1065 #define _CHV_PLL_DW3_CH1 0x818c
1066 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1067 #define DPIO_CHV_FIRST_MOD (0 << 8)
1068 #define DPIO_CHV_SECOND_MOD (1 << 8)
1069 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1070 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1071 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1073 #define _CHV_PLL_DW6_CH0 0x8018
1074 #define _CHV_PLL_DW6_CH1 0x8198
1075 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1076 #define DPIO_CHV_INT_COEFF_SHIFT 8
1077 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1078 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1080 #define _CHV_PLL_DW8_CH0 0x8020
1081 #define _CHV_PLL_DW8_CH1 0x81A0
1082 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1083 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1084 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1086 #define _CHV_PLL_DW9_CH0 0x8024
1087 #define _CHV_PLL_DW9_CH1 0x81A4
1088 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1089 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1090 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1091 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1093 #define _CHV_CMN_DW5_CH0 0x8114
1094 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1095 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1096 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1097 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1098 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1099 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1100 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1101 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1103 #define _CHV_CMN_DW13_CH0 0x8134
1104 #define _CHV_CMN_DW0_CH1 0x8080
1105 #define DPIO_CHV_S1_DIV_SHIFT 21
1106 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1107 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1108 #define DPIO_CHV_K_DIV_SHIFT 4
1109 #define DPIO_PLL_FREQLOCK (1 << 1)
1110 #define DPIO_PLL_LOCK (1 << 0)
1111 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1113 #define _CHV_CMN_DW14_CH0 0x8138
1114 #define _CHV_CMN_DW1_CH1 0x8084
1115 #define DPIO_AFC_RECAL (1 << 14)
1116 #define DPIO_DCLKP_EN (1 << 13)
1117 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1118 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1119 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1120 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1121 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1122 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1123 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1124 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1125 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1127 #define _CHV_CMN_DW19_CH0 0x814c
1128 #define _CHV_CMN_DW6_CH1 0x8098
1129 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1130 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1132 #define CHV_CMN_DW30 0x8178
1133 #define DPIO_LRC_BYPASS (1 << 3)
1135 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1136 (lane) * 0x200 + (offset))
1138 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1139 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1140 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1141 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1142 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1143 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1144 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1145 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1146 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1147 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1148 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1149 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1150 #define DPIO_FRC_LATENCY_SHFIT 8
1151 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1152 #define DPIO_UPAR_SHIFT 30
1154 /* BXT PHY registers */
1155 #define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))
1157 #define BXT_P_CR_GT_DISP_PWRON 0x138090
1158 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1160 #define _PHY_CTL_FAMILY_EDP 0x64C80
1161 #define _PHY_CTL_FAMILY_DDI 0x64C90
1162 #define COMMON_RESET_DIS (1 << 31)
1163 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1164 _PHY_CTL_FAMILY_EDP)
1166 /* BXT PHY PLL registers */
1167 #define _PORT_PLL_A 0x46074
1168 #define _PORT_PLL_B 0x46078
1169 #define _PORT_PLL_C 0x4607c
1170 #define PORT_PLL_ENABLE (1 << 31)
1171 #define PORT_PLL_LOCK (1 << 30)
1172 #define PORT_PLL_REF_SEL (1 << 27)
1173 #define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1175 #define _PORT_PLL_EBB_0_A 0x162034
1176 #define _PORT_PLL_EBB_0_B 0x6C034
1177 #define _PORT_PLL_EBB_0_C 0x6C340
1178 #define PORT_PLL_P1_SHIFT 13
1179 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1180 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1181 #define PORT_PLL_P2_SHIFT 8
1182 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1183 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1184 #define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \
1185 _PORT_PLL_EBB_0_B, \
1188 #define _PORT_PLL_EBB_4_A 0x162038
1189 #define _PORT_PLL_EBB_4_B 0x6C038
1190 #define _PORT_PLL_EBB_4_C 0x6C344
1191 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1192 #define PORT_PLL_RECALIBRATE (1 << 14)
1193 #define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \
1194 _PORT_PLL_EBB_4_B, \
1197 #define _PORT_PLL_0_A 0x162100
1198 #define _PORT_PLL_0_B 0x6C100
1199 #define _PORT_PLL_0_C 0x6C380
1201 #define PORT_PLL_M2_MASK 0xFF
1203 #define PORT_PLL_N_SHIFT 8
1204 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1205 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1207 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1209 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1211 #define PORT_PLL_PROP_COEFF_MASK 0xF
1212 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1213 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1214 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1215 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1217 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1219 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1220 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1222 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1223 #define PORT_PLL_DCO_AMP_DEFAULT 15
1224 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1225 #define PORT_PLL_DCO_AMP(x) (x<<10)
1226 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1229 #define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4)
1231 /* BXT PHY common lane registers */
1232 #define _PORT_CL1CM_DW0_A 0x162000
1233 #define _PORT_CL1CM_DW0_BC 0x6C000
1234 #define PHY_POWER_GOOD (1 << 16)
1235 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1238 #define _PORT_CL1CM_DW9_A 0x162024
1239 #define _PORT_CL1CM_DW9_BC 0x6C024
1240 #define IREF0RC_OFFSET_SHIFT 8
1241 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1242 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1245 #define _PORT_CL1CM_DW10_A 0x162028
1246 #define _PORT_CL1CM_DW10_BC 0x6C028
1247 #define IREF1RC_OFFSET_SHIFT 8
1248 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1249 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1252 #define _PORT_CL1CM_DW28_A 0x162070
1253 #define _PORT_CL1CM_DW28_BC 0x6C070
1254 #define OCL1_POWER_DOWN_EN (1 << 23)
1255 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1256 #define SUS_CLK_CONFIG 0x3
1257 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1260 #define _PORT_CL1CM_DW30_A 0x162078
1261 #define _PORT_CL1CM_DW30_BC 0x6C078
1262 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1263 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1266 /* Defined for PHY0 only */
1267 #define BXT_PORT_CL2CM_DW6_BC 0x6C358
1268 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1270 /* BXT PHY Ref registers */
1271 #define _PORT_REF_DW3_A 0x16218C
1272 #define _PORT_REF_DW3_BC 0x6C18C
1273 #define GRC_DONE (1 << 22)
1274 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1277 #define _PORT_REF_DW6_A 0x162198
1278 #define _PORT_REF_DW6_BC 0x6C198
1280 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1283 #define GRC_CODE_SHIFT 23
1284 #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
1285 #define GRC_CODE_FAST_SHIFT 16
1286 #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
1287 #define GRC_CODE_SLOW_SHIFT 8
1288 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1289 #define GRC_CODE_NOM_MASK 0xFF
1290 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1293 #define _PORT_REF_DW8_A 0x1621A0
1294 #define _PORT_REF_DW8_BC 0x6C1A0
1295 #define GRC_DIS (1 << 15)
1296 #define GRC_RDY_OVRD (1 << 1)
1297 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1300 /* BXT PHY PCS registers */
1301 #define _PORT_PCS_DW10_LN01_A 0x162428
1302 #define _PORT_PCS_DW10_LN01_B 0x6C428
1303 #define _PORT_PCS_DW10_LN01_C 0x6C828
1304 #define _PORT_PCS_DW10_GRP_A 0x162C28
1305 #define _PORT_PCS_DW10_GRP_B 0x6CC28
1306 #define _PORT_PCS_DW10_GRP_C 0x6CE28
1307 #define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \
1308 _PORT_PCS_DW10_LN01_B, \
1309 _PORT_PCS_DW10_LN01_C)
1310 #define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \
1311 _PORT_PCS_DW10_GRP_B, \
1312 _PORT_PCS_DW10_GRP_C)
1313 #define TX2_SWING_CALC_INIT (1 << 31)
1314 #define TX1_SWING_CALC_INIT (1 << 30)
1316 #define _PORT_PCS_DW12_LN01_A 0x162430
1317 #define _PORT_PCS_DW12_LN01_B 0x6C430
1318 #define _PORT_PCS_DW12_LN01_C 0x6C830
1319 #define _PORT_PCS_DW12_LN23_A 0x162630
1320 #define _PORT_PCS_DW12_LN23_B 0x6C630
1321 #define _PORT_PCS_DW12_LN23_C 0x6CA30
1322 #define _PORT_PCS_DW12_GRP_A 0x162c30
1323 #define _PORT_PCS_DW12_GRP_B 0x6CC30
1324 #define _PORT_PCS_DW12_GRP_C 0x6CE30
1325 #define LANESTAGGER_STRAP_OVRD (1 << 6)
1326 #define LANE_STAGGER_MASK 0x1F
1327 #define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \
1328 _PORT_PCS_DW12_LN01_B, \
1329 _PORT_PCS_DW12_LN01_C)
1330 #define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \
1331 _PORT_PCS_DW12_LN23_B, \
1332 _PORT_PCS_DW12_LN23_C)
1333 #define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \
1334 _PORT_PCS_DW12_GRP_B, \
1335 _PORT_PCS_DW12_GRP_C)
1337 /* BXT PHY TX registers */
1338 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1339 ((lane) & 1) * 0x80)
1341 #define _PORT_TX_DW2_LN0_A 0x162508
1342 #define _PORT_TX_DW2_LN0_B 0x6C508
1343 #define _PORT_TX_DW2_LN0_C 0x6C908
1344 #define _PORT_TX_DW2_GRP_A 0x162D08
1345 #define _PORT_TX_DW2_GRP_B 0x6CD08
1346 #define _PORT_TX_DW2_GRP_C 0x6CF08
1347 #define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \
1348 _PORT_TX_DW2_GRP_B, \
1350 #define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \
1351 _PORT_TX_DW2_LN0_B, \
1353 #define MARGIN_000_SHIFT 16
1354 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1355 #define UNIQ_TRANS_SCALE_SHIFT 8
1356 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1358 #define _PORT_TX_DW3_LN0_A 0x16250C
1359 #define _PORT_TX_DW3_LN0_B 0x6C50C
1360 #define _PORT_TX_DW3_LN0_C 0x6C90C
1361 #define _PORT_TX_DW3_GRP_A 0x162D0C
1362 #define _PORT_TX_DW3_GRP_B 0x6CD0C
1363 #define _PORT_TX_DW3_GRP_C 0x6CF0C
1364 #define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \
1365 _PORT_TX_DW3_GRP_B, \
1367 #define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \
1368 _PORT_TX_DW3_LN0_B, \
1370 #define UNIQE_TRANGE_EN_METHOD (1 << 27)
1372 #define _PORT_TX_DW4_LN0_A 0x162510
1373 #define _PORT_TX_DW4_LN0_B 0x6C510
1374 #define _PORT_TX_DW4_LN0_C 0x6C910
1375 #define _PORT_TX_DW4_GRP_A 0x162D10
1376 #define _PORT_TX_DW4_GRP_B 0x6CD10
1377 #define _PORT_TX_DW4_GRP_C 0x6CF10
1378 #define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \
1379 _PORT_TX_DW4_LN0_B, \
1381 #define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \
1382 _PORT_TX_DW4_GRP_B, \
1384 #define DEEMPH_SHIFT 24
1385 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1387 #define _PORT_TX_DW14_LN0_A 0x162538
1388 #define _PORT_TX_DW14_LN0_B 0x6C538
1389 #define _PORT_TX_DW14_LN0_C 0x6C938
1390 #define LATENCY_OPTIM_SHIFT 30
1391 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1392 #define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \
1393 _PORT_TX_DW14_LN0_B, \
1394 _PORT_TX_DW14_LN0_C) + \
1395 _BXT_LANE_OFFSET(lane))
1397 /* UAIMI scratch pad register 1 */
1398 #define UAIMI_SPR1 0x4F074
1399 /* SKL VccIO mask */
1400 #define SKL_VCCIO_MASK 0x1
1401 /* SKL balance leg register */
1402 #define DISPIO_CR_TX_BMU_CR0 0x6C00C
1403 /* I_boost values */
1404 #define BALANCE_LEG_SHIFT(port) (8+3*(port))
1405 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1406 /* Balance leg disable bits */
1407 #define BALANCE_LEG_DISABLE_SHIFT 23
1412 #define FENCE_REG_830_0 0x2000
1413 #define FENCE_REG_945_8 0x3000
1414 #define I830_FENCE_START_MASK 0x07f80000
1415 #define I830_FENCE_TILING_Y_SHIFT 12
1416 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1417 #define I830_FENCE_PITCH_SHIFT 4
1418 #define I830_FENCE_REG_VALID (1<<0)
1419 #define I915_FENCE_MAX_PITCH_VAL 4
1420 #define I830_FENCE_MAX_PITCH_VAL 6
1421 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
1423 #define I915_FENCE_START_MASK 0x0ff00000
1424 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1426 #define FENCE_REG_965_0 0x03000
1427 #define I965_FENCE_PITCH_SHIFT 2
1428 #define I965_FENCE_TILING_Y_SHIFT 1
1429 #define I965_FENCE_REG_VALID (1<<0)
1430 #define I965_FENCE_MAX_PITCH_VAL 0x0400
1432 #define FENCE_REG_SANDYBRIDGE_0 0x100000
1433 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
1434 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1437 /* control register for cpu gtt access */
1438 #define TILECTL 0x101000
1439 #define TILECTL_SWZCTL (1 << 0)
1440 #define TILECTL_TLBPF (1 << 1)
1441 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1442 #define TILECTL_BACKSNOOP_DIS (1 << 3)
1445 * Instruction and interrupt control regs
1447 #define PGTBL_CTL 0x02020
1448 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1449 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1450 #define PGTBL_ER 0x02024
1451 #define PRB0_BASE (0x2030-0x30)
1452 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1453 #define PRB2_BASE (0x2050-0x30) /* gen3 */
1454 #define SRB0_BASE (0x2100-0x30) /* gen2 */
1455 #define SRB1_BASE (0x2110-0x30) /* gen2 */
1456 #define SRB2_BASE (0x2120-0x30) /* 830 */
1457 #define SRB3_BASE (0x2130-0x30) /* 830 */
1458 #define RENDER_RING_BASE 0x02000
1459 #define BSD_RING_BASE 0x04000
1460 #define GEN6_BSD_RING_BASE 0x12000
1461 #define GEN8_BSD2_RING_BASE 0x1c000
1462 #define VEBOX_RING_BASE 0x1a000
1463 #define BLT_RING_BASE 0x22000
1464 #define RING_TAIL(base) ((base)+0x30)
1465 #define RING_HEAD(base) ((base)+0x34)
1466 #define RING_START(base) ((base)+0x38)
1467 #define RING_CTL(base) ((base)+0x3c)
1468 #define RING_SYNC_0(base) ((base)+0x40)
1469 #define RING_SYNC_1(base) ((base)+0x44)
1470 #define RING_SYNC_2(base) ((base)+0x48)
1471 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1472 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1473 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1474 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1475 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1476 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1477 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1478 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1479 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1480 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1481 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1482 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1483 #define GEN6_NOSYNC 0
1484 #define RING_PSMI_CTL(base) ((base)+0x50)
1485 #define RING_MAX_IDLE(base) ((base)+0x54)
1486 #define RING_HWS_PGA(base) ((base)+0x80)
1487 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
1488 #define RING_RESET_CTL(base) ((base)+0xd0)
1489 #define RESET_CTL_REQUEST_RESET (1 << 0)
1490 #define RESET_CTL_READY_TO_RESET (1 << 1)
1492 #define HSW_GTT_CACHE_EN 0x4024
1493 #define GTT_CACHE_EN_ALL 0xF0007FFF
1494 #define GEN7_WR_WATERMARK 0x4028
1495 #define GEN7_GFX_PRIO_CTRL 0x402C
1496 #define ARB_MODE 0x4030
1497 #define ARB_MODE_SWIZZLE_SNB (1<<4)
1498 #define ARB_MODE_SWIZZLE_IVB (1<<5)
1499 #define GEN7_GFX_PEND_TLB0 0x4034
1500 #define GEN7_GFX_PEND_TLB1 0x4038
1501 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1502 #define GEN7_LRA_LIMITS_BASE 0x403C
1503 #define GEN7_LRA_LIMITS_REG_NUM 13
1504 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070
1505 #define GEN7_GFX_MAX_REQ_COUNT 0x4074
1507 #define GAMTARBMODE 0x04a08
1508 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
1509 #define ARB_MODE_SWIZZLE_BDW (1<<1)
1510 #define RENDER_HWS_PGA_GEN7 (0x04080)
1511 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
1512 #define RING_FAULT_GTTSEL_MASK (1<<11)
1513 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
1514 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
1515 #define RING_FAULT_VALID (1<<0)
1516 #define DONE_REG 0x40b0
1517 #define GEN8_PRIVATE_PAT 0x40e0
1518 #define BSD_HWS_PGA_GEN7 (0x04180)
1519 #define BLT_HWS_PGA_GEN7 (0x04280)
1520 #define VEBOX_HWS_PGA_GEN7 (0x04380)
1521 #define RING_ACTHD(base) ((base)+0x74)
1522 #define RING_ACTHD_UDW(base) ((base)+0x5c)
1523 #define RING_NOPID(base) ((base)+0x94)
1524 #define RING_IMR(base) ((base)+0xa8)
1525 #define RING_HWSTAM(base) ((base)+0x98)
1526 #define RING_TIMESTAMP(base) ((base)+0x358)
1527 #define TAIL_ADDR 0x001FFFF8
1528 #define HEAD_WRAP_COUNT 0xFFE00000
1529 #define HEAD_WRAP_ONE 0x00200000
1530 #define HEAD_ADDR 0x001FFFFC
1531 #define RING_NR_PAGES 0x001FF000
1532 #define RING_REPORT_MASK 0x00000006
1533 #define RING_REPORT_64K 0x00000002
1534 #define RING_REPORT_128K 0x00000004
1535 #define RING_NO_REPORT 0x00000000
1536 #define RING_VALID_MASK 0x00000001
1537 #define RING_VALID 0x00000001
1538 #define RING_INVALID 0x00000000
1539 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1540 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1541 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1543 #define GEN7_TLB_RD_ADDR 0x4700
1546 #define PRB0_TAIL 0x02030
1547 #define PRB0_HEAD 0x02034
1548 #define PRB0_START 0x02038
1549 #define PRB0_CTL 0x0203c
1550 #define PRB1_TAIL 0x02040 /* 915+ only */
1551 #define PRB1_HEAD 0x02044 /* 915+ only */
1552 #define PRB1_START 0x02048 /* 915+ only */
1553 #define PRB1_CTL 0x0204c /* 915+ only */
1555 #define IPEIR_I965 0x02064
1556 #define IPEHR_I965 0x02068
1557 #define INSTDONE_I965 0x0206c
1558 #define GEN7_INSTDONE_1 0x0206c
1559 #define GEN7_SC_INSTDONE 0x07100
1560 #define GEN7_SAMPLER_INSTDONE 0x0e160
1561 #define GEN7_ROW_INSTDONE 0x0e164
1562 #define I915_NUM_INSTDONE_REG 4
1563 #define RING_IPEIR(base) ((base)+0x64)
1564 #define RING_IPEHR(base) ((base)+0x68)
1565 #define RING_INSTDONE(base) ((base)+0x6c)
1566 #define RING_INSTPS(base) ((base)+0x70)
1567 #define RING_DMA_FADD(base) ((base)+0x78)
1568 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
1569 #define RING_INSTPM(base) ((base)+0xc0)
1570 #define RING_MI_MODE(base) ((base)+0x9c)
1571 #define INSTPS 0x02070 /* 965+ only */
1572 #define INSTDONE1 0x0207c /* 965+ only */
1573 #define ACTHD_I965 0x02074
1574 #define HWS_PGA 0x02080
1575 #define HWS_ADDRESS_MASK 0xfffff000
1576 #define HWS_START_ADDRESS_SHIFT 4
1577 #define PWRCTXA 0x2088 /* 965GM+ only */
1578 #define PWRCTX_EN (1<<0)
1579 #define IPEIR 0x02088
1580 #define IPEHR 0x0208c
1581 #define INSTDONE 0x02090
1582 #define NOPID 0x02094
1583 #define HWSTAM 0x02098
1584 #define DMA_FADD_I8XX 0x020d0
1585 #define RING_BBSTATE(base) ((base)+0x110)
1586 #define RING_BBADDR(base) ((base)+0x140)
1587 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
1589 #define ERROR_GEN6 0x040a0
1590 #define GEN7_ERR_INT 0x44040
1591 #define ERR_INT_POISON (1<<31)
1592 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
1593 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1594 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1595 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1596 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1597 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1598 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
1599 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1600 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
1602 #define GEN8_FAULT_TLB_DATA0 0x04b10
1603 #define GEN8_FAULT_TLB_DATA1 0x04b14
1605 #define FPGA_DBG 0x42300
1606 #define FPGA_DBG_RM_NOCLAIM (1<<31)
1608 #define DERRMR 0x44050
1609 /* Note that HBLANK events are reserved on bdw+ */
1610 #define DERRMR_PIPEA_SCANLINE (1<<0)
1611 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1612 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1613 #define DERRMR_PIPEA_VBLANK (1<<3)
1614 #define DERRMR_PIPEA_HBLANK (1<<5)
1615 #define DERRMR_PIPEB_SCANLINE (1<<8)
1616 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1617 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1618 #define DERRMR_PIPEB_VBLANK (1<<11)
1619 #define DERRMR_PIPEB_HBLANK (1<<13)
1620 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1621 #define DERRMR_PIPEC_SCANLINE (1<<14)
1622 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1623 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1624 #define DERRMR_PIPEC_VBLANK (1<<21)
1625 #define DERRMR_PIPEC_HBLANK (1<<22)
1628 /* GM45+ chicken bits -- debug workaround bits that may be required
1629 * for various sorts of correct behavior. The top 16 bits of each are
1630 * the enables for writing to the corresponding low bit.
1632 #define _3D_CHICKEN 0x02084
1633 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1634 #define _3D_CHICKEN2 0x0208c
1635 /* Disables pipelining of read flushes past the SF-WIZ interface.
1636 * Required on all Ironlake steppings according to the B-Spec, but the
1637 * particular danger of not doing so is not specified.
1639 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1640 #define _3D_CHICKEN3 0x02090
1641 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1642 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1643 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1644 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1646 #define MI_MODE 0x0209c
1647 # define VS_TIMER_DISPATCH (1 << 6)
1648 # define MI_FLUSH_ENABLE (1 << 12)
1649 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1650 # define MODE_IDLE (1 << 9)
1651 # define STOP_RING (1 << 8)
1653 #define GEN6_GT_MODE 0x20d0
1654 #define GEN7_GT_MODE 0x7008
1655 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1656 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1657 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1658 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1659 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
1660 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1661 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2))
1662 #define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2))
1664 #define GFX_MODE 0x02520
1665 #define GFX_MODE_GEN7 0x0229c
1666 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
1667 #define GFX_RUN_LIST_ENABLE (1<<15)
1668 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1669 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
1670 #define GFX_REPLAY_MODE (1<<11)
1671 #define GFX_PSMI_GRANULARITY (1<<10)
1672 #define GFX_PPGTT_ENABLE (1<<9)
1674 #define VLV_DISPLAY_BASE 0x180000
1675 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1677 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030)
1678 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034)
1679 #define SCPD0 0x0209c /* 915+ only */
1684 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
1685 #define GINT_DIS (1<<22)
1686 #define GCFG_DIS (1<<8)
1687 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064)
1688 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
1689 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
1690 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
1691 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
1692 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
1693 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
1694 #define VLV_PCBR_ADDR_SHIFT 12
1696 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1700 #define GM45_ERROR_PAGE_TABLE (1<<5)
1701 #define GM45_ERROR_MEM_PRIV (1<<4)
1702 #define I915_ERROR_PAGE_TABLE (1<<4)
1703 #define GM45_ERROR_CP_PRIV (1<<3)
1704 #define I915_ERROR_MEMORY_REFRESH (1<<1)
1705 #define I915_ERROR_INSTRUCTION (1<<0)
1706 #define INSTPM 0x020c0
1707 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
1708 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1709 will not assert AGPBUSY# and will only
1710 be delivered when out of C3. */
1711 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1712 #define INSTPM_TLB_INVALIDATE (1<<9)
1713 #define INSTPM_SYNC_FLUSH (1<<5)
1714 #define ACTHD 0x020c8
1715 #define MEM_MODE 0x020cc
1716 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1717 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1718 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1719 #define FW_BLC 0x020d8
1720 #define FW_BLC2 0x020dc
1721 #define FW_BLC_SELF 0x020e0 /* 915+ only */
1722 #define FW_BLC_SELF_EN_MASK (1<<31)
1723 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1724 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
1725 #define MM_BURST_LENGTH 0x00700000
1726 #define MM_FIFO_WATERMARK 0x0001F000
1727 #define LM_BURST_LENGTH 0x00000700
1728 #define LM_FIFO_WATERMARK 0x0000001F
1729 #define MI_ARB_STATE 0x020e4 /* 915+ only */
1731 /* Make render/texture TLB fetches lower priorty than associated data
1732 * fetches. This is not turned on by default
1734 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1736 /* Isoch request wait on GTT enable (Display A/B/C streams).
1737 * Make isoch requests stall on the TLB update. May cause
1738 * display underruns (test mode only)
1740 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1742 /* Block grant count for isoch requests when block count is
1743 * set to a finite value.
1745 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1746 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1747 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1748 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1749 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1751 /* Enable render writes to complete in C2/C3/C4 power states.
1752 * If this isn't enabled, render writes are prevented in low
1753 * power states. That seems bad to me.
1755 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1757 /* This acknowledges an async flip immediately instead
1758 * of waiting for 2TLB fetches.
1760 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1762 /* Enables non-sequential data reads through arbiter
1764 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1766 /* Disable FSB snooping of cacheable write cycles from binner/render
1769 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1771 /* Arbiter time slice for non-isoch streams */
1772 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1773 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1774 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1775 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1776 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1777 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1778 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1779 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1780 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1782 /* Low priority grace period page size */
1783 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1784 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1786 /* Disable display A/B trickle feed */
1787 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1789 /* Set display plane priority */
1790 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1791 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1793 #define MI_STATE 0x020e4 /* gen2 only */
1794 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1795 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1797 #define CACHE_MODE_0 0x02120 /* 915+ only */
1798 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1799 #define CM0_IZ_OPT_DISABLE (1<<6)
1800 #define CM0_ZR_OPT_DISABLE (1<<5)
1801 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1802 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
1803 #define CM0_COLOR_EVICT_DISABLE (1<<3)
1804 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
1805 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1806 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
1807 #define GFX_FLSH_CNTL_GEN6 0x101008
1808 #define GFX_FLSH_CNTL_EN (1<<0)
1809 #define ECOSKPD 0x021d0
1810 #define ECO_GATING_CX_ONLY (1<<3)
1811 #define ECO_FLIP_DONE (1<<0)
1813 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
1814 #define RC_OP_FLUSH_ENABLE (1<<0)
1815 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1816 #define CACHE_MODE_1 0x7004 /* IVB+ */
1817 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1818 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1819 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
1821 #define GEN6_BLITTER_ECOSKPD 0x221d0
1822 #define GEN6_BLITTER_LOCK_SHIFT 16
1823 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1825 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
1826 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
1827 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1828 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1830 /* Fuse readout registers for GT */
1831 #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
1832 #define CHV_FGT_DISABLE_SS0 (1 << 10)
1833 #define CHV_FGT_DISABLE_SS1 (1 << 11)
1834 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1835 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1836 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1837 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1838 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1839 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1840 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1841 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1843 #define GEN8_FUSE2 0x9120
1844 #define GEN8_F2_S_ENA_SHIFT 25
1845 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
1847 #define GEN9_F2_SS_DIS_SHIFT 20
1848 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1850 #define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
1852 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
1853 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1854 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1855 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1856 #define GEN6_BSD_GO_INDICATOR (1 << 4)
1858 /* On modern GEN architectures interrupt control consists of two sets
1859 * of registers. The first set pertains to the ring generating the
1860 * interrupt. The second control is for the functional block generating the
1861 * interrupt. These are PM, GT, DE, etc.
1863 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1864 * GT interrupt bits, so we don't need to duplicate the defines.
1866 * These defines should cover us well from SNB->HSW with minor exceptions
1867 * it can also work on ILK.
1869 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1870 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1871 #define GT_BLT_USER_INTERRUPT (1 << 22)
1872 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1873 #define GT_BSD_USER_INTERRUPT (1 << 12)
1874 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1875 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1876 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1877 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1878 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1879 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1880 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1881 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1883 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1884 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1886 #define GT_PARITY_ERROR(dev) \
1887 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1888 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1890 /* These are all the "old" interrupts */
1891 #define ILK_BSD_USER_INTERRUPT (1<<5)
1893 #define I915_PM_INTERRUPT (1<<31)
1894 #define I915_ISP_INTERRUPT (1<<22)
1895 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
1896 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
1897 #define I915_MIPIC_INTERRUPT (1<<19)
1898 #define I915_MIPIA_INTERRUPT (1<<18)
1899 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1900 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1901 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
1902 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
1903 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1904 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
1905 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1906 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
1907 #define I915_HWB_OOM_INTERRUPT (1<<13)
1908 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
1909 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
1910 #define I915_MISC_INTERRUPT (1<<11)
1911 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1912 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
1913 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1914 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
1915 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1916 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
1917 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1918 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1919 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1920 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1921 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1922 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
1923 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
1924 #define I915_DEBUG_INTERRUPT (1<<2)
1925 #define I915_WINVALID_INTERRUPT (1<<1)
1926 #define I915_USER_INTERRUPT (1<<1)
1927 #define I915_ASLE_INTERRUPT (1<<0)
1928 #define I915_BSD_USER_INTERRUPT (1<<25)
1930 #define GEN6_BSD_RNCID 0x12198
1932 #define GEN7_FF_THREAD_MODE 0x20a0
1933 #define GEN7_FF_SCHED_MASK 0x0077070
1934 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1935 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1936 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1937 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1938 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
1939 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1940 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1941 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1942 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1943 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
1944 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1945 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1946 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1947 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
1950 * Framebuffer compression (915+ only)
1953 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1954 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
1955 #define FBC_CONTROL 0x03208
1956 #define FBC_CTL_EN (1<<31)
1957 #define FBC_CTL_PERIODIC (1<<30)
1958 #define FBC_CTL_INTERVAL_SHIFT (16)
1959 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1960 #define FBC_CTL_C3_IDLE (1<<13)
1961 #define FBC_CTL_STRIDE_SHIFT (5)
1962 #define FBC_CTL_FENCENO_SHIFT (0)
1963 #define FBC_COMMAND 0x0320c
1964 #define FBC_CMD_COMPRESS (1<<0)
1965 #define FBC_STATUS 0x03210
1966 #define FBC_STAT_COMPRESSING (1<<31)
1967 #define FBC_STAT_COMPRESSED (1<<30)
1968 #define FBC_STAT_MODIFIED (1<<29)
1969 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
1970 #define FBC_CONTROL2 0x03214
1971 #define FBC_CTL_FENCE_DBL (0<<4)
1972 #define FBC_CTL_IDLE_IMM (0<<2)
1973 #define FBC_CTL_IDLE_FULL (1<<2)
1974 #define FBC_CTL_IDLE_LINE (2<<2)
1975 #define FBC_CTL_IDLE_DEBUG (3<<2)
1976 #define FBC_CTL_CPU_FENCE (1<<1)
1977 #define FBC_CTL_PLANE(plane) ((plane)<<0)
1978 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
1979 #define FBC_TAG 0x03300
1981 #define FBC_STATUS2 0x43214
1982 #define FBC_COMPRESSION_MASK 0x7ff
1984 #define FBC_LL_SIZE (1536)
1986 /* Framebuffer compression for GM45+ */
1987 #define DPFC_CB_BASE 0x3200
1988 #define DPFC_CONTROL 0x3208
1989 #define DPFC_CTL_EN (1<<31)
1990 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
1991 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
1992 #define DPFC_CTL_FENCE_EN (1<<29)
1993 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
1994 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
1995 #define DPFC_SR_EN (1<<10)
1996 #define DPFC_CTL_LIMIT_1X (0<<6)
1997 #define DPFC_CTL_LIMIT_2X (1<<6)
1998 #define DPFC_CTL_LIMIT_4X (2<<6)
1999 #define DPFC_RECOMP_CTL 0x320c
2000 #define DPFC_RECOMP_STALL_EN (1<<27)
2001 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
2002 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2003 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2004 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2005 #define DPFC_STATUS 0x3210
2006 #define DPFC_INVAL_SEG_SHIFT (16)
2007 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
2008 #define DPFC_COMP_SEG_SHIFT (0)
2009 #define DPFC_COMP_SEG_MASK (0x000003ff)
2010 #define DPFC_STATUS2 0x3214
2011 #define DPFC_FENCE_YOFF 0x3218
2012 #define DPFC_CHICKEN 0x3224
2013 #define DPFC_HT_MODIFY (1<<31)
2015 /* Framebuffer compression for Ironlake */
2016 #define ILK_DPFC_CB_BASE 0x43200
2017 #define ILK_DPFC_CONTROL 0x43208
2018 #define FBC_CTL_FALSE_COLOR (1<<10)
2019 /* The bit 28-8 is reserved */
2020 #define DPFC_RESERVED (0x1FFFFF00)
2021 #define ILK_DPFC_RECOMP_CTL 0x4320c
2022 #define ILK_DPFC_STATUS 0x43210
2023 #define ILK_DPFC_FENCE_YOFF 0x43218
2024 #define ILK_DPFC_CHICKEN 0x43224
2025 #define ILK_FBC_RT_BASE 0x2128
2026 #define ILK_FBC_RT_VALID (1<<0)
2027 #define SNB_FBC_FRONT_BUFFER (1<<1)
2029 #define ILK_DISPLAY_CHICKEN1 0x42000
2030 #define ILK_FBCQ_DIS (1<<22)
2031 #define ILK_PABSTRETCH_DIS (1<<21)
2035 * Framebuffer compression for Sandybridge
2037 * The following two registers are of type GTTMMADR
2039 #define SNB_DPFC_CTL_SA 0x100100
2040 #define SNB_CPU_FENCE_ENABLE (1<<29)
2041 #define DPFC_CPU_FENCE_OFFSET 0x100104
2043 /* Framebuffer compression for Ivybridge */
2044 #define IVB_FBC_RT_BASE 0x7020
2046 #define IPS_CTL 0x43408
2047 #define IPS_ENABLE (1 << 31)
2049 #define MSG_FBC_REND_STATE 0x50380
2050 #define FBC_REND_NUKE (1<<2)
2051 #define FBC_REND_CACHE_CLEAN (1<<1)
2056 #define GPIOA 0x5010
2057 #define GPIOB 0x5014
2058 #define GPIOC 0x5018
2059 #define GPIOD 0x501c
2060 #define GPIOE 0x5020
2061 #define GPIOF 0x5024
2062 #define GPIOG 0x5028
2063 #define GPIOH 0x502c
2064 # define GPIO_CLOCK_DIR_MASK (1 << 0)
2065 # define GPIO_CLOCK_DIR_IN (0 << 1)
2066 # define GPIO_CLOCK_DIR_OUT (1 << 1)
2067 # define GPIO_CLOCK_VAL_MASK (1 << 2)
2068 # define GPIO_CLOCK_VAL_OUT (1 << 3)
2069 # define GPIO_CLOCK_VAL_IN (1 << 4)
2070 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2071 # define GPIO_DATA_DIR_MASK (1 << 8)
2072 # define GPIO_DATA_DIR_IN (0 << 9)
2073 # define GPIO_DATA_DIR_OUT (1 << 9)
2074 # define GPIO_DATA_VAL_MASK (1 << 10)
2075 # define GPIO_DATA_VAL_OUT (1 << 11)
2076 # define GPIO_DATA_VAL_IN (1 << 12)
2077 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2079 #define GMBUS0 0x5100 /* clock/port select */
2080 #define GMBUS_RATE_100KHZ (0<<8)
2081 #define GMBUS_RATE_50KHZ (1<<8)
2082 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2083 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2084 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
2085 #define GMBUS_PIN_DISABLED 0
2086 #define GMBUS_PIN_SSC 1
2087 #define GMBUS_PIN_VGADDC 2
2088 #define GMBUS_PIN_PANEL 3
2089 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2090 #define GMBUS_PIN_DPC 4 /* HDMIC */
2091 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2092 #define GMBUS_PIN_DPD 6 /* HDMID */
2093 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
2094 #define GMBUS_PIN_1_BXT 1
2095 #define GMBUS_PIN_2_BXT 2
2096 #define GMBUS_PIN_3_BXT 3
2097 #define GMBUS_NUM_PINS 7 /* including 0 */
2098 #define GMBUS1 0x5104 /* command/status */
2099 #define GMBUS_SW_CLR_INT (1<<31)
2100 #define GMBUS_SW_RDY (1<<30)
2101 #define GMBUS_ENT (1<<29) /* enable timeout */
2102 #define GMBUS_CYCLE_NONE (0<<25)
2103 #define GMBUS_CYCLE_WAIT (1<<25)
2104 #define GMBUS_CYCLE_INDEX (2<<25)
2105 #define GMBUS_CYCLE_STOP (4<<25)
2106 #define GMBUS_BYTE_COUNT_SHIFT 16
2107 #define GMBUS_BYTE_COUNT_MAX 256U
2108 #define GMBUS_SLAVE_INDEX_SHIFT 8
2109 #define GMBUS_SLAVE_ADDR_SHIFT 1
2110 #define GMBUS_SLAVE_READ (1<<0)
2111 #define GMBUS_SLAVE_WRITE (0<<0)
2112 #define GMBUS2 0x5108 /* status */
2113 #define GMBUS_INUSE (1<<15)
2114 #define GMBUS_HW_WAIT_PHASE (1<<14)
2115 #define GMBUS_STALL_TIMEOUT (1<<13)
2116 #define GMBUS_INT (1<<12)
2117 #define GMBUS_HW_RDY (1<<11)
2118 #define GMBUS_SATOER (1<<10)
2119 #define GMBUS_ACTIVE (1<<9)
2120 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
2121 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
2122 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2123 #define GMBUS_NAK_EN (1<<3)
2124 #define GMBUS_IDLE_EN (1<<2)
2125 #define GMBUS_HW_WAIT_EN (1<<1)
2126 #define GMBUS_HW_RDY_EN (1<<0)
2127 #define GMBUS5 0x5120 /* byte index */
2128 #define GMBUS_2BYTE_INDEX_EN (1<<31)
2131 * Clock control & power management
2133 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2134 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2135 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2136 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2140 #define VGA_PD 0x6010
2141 #define VGA0_PD_P2_DIV_4 (1 << 7)
2142 #define VGA0_PD_P1_DIV_2 (1 << 5)
2143 #define VGA0_PD_P1_SHIFT 0
2144 #define VGA0_PD_P1_MASK (0x1f << 0)
2145 #define VGA1_PD_P2_DIV_4 (1 << 15)
2146 #define VGA1_PD_P1_DIV_2 (1 << 13)
2147 #define VGA1_PD_P1_SHIFT 8
2148 #define VGA1_PD_P1_MASK (0x1f << 8)
2149 #define DPLL_VCO_ENABLE (1 << 31)
2150 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
2151 #define DPLL_DVO_2X_MODE (1 << 30)
2152 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
2153 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
2154 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
2155 #define DPLL_VGA_MODE_DIS (1 << 28)
2156 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2157 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2158 #define DPLL_MODE_MASK (3 << 26)
2159 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2160 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2161 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2162 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2163 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2164 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
2165 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
2166 #define DPLL_LOCK_VLV (1<<15)
2167 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
2168 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2169 #define DPLL_SSC_REF_CLK_CHV (1<<13)
2170 #define DPLL_PORTC_READY_MASK (0xf << 4)
2171 #define DPLL_PORTB_READY_MASK (0xf)
2173 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
2175 /* Additional CHV pll/phy registers */
2176 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
2177 #define DPLL_PORTD_READY_MASK (0xf)
2178 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
2179 #define PHY_LDO_DELAY_0NS 0x0
2180 #define PHY_LDO_DELAY_200NS 0x1
2181 #define PHY_LDO_DELAY_600NS 0x2
2182 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
2183 #define PHY_CH_SU_PSR 0x1
2184 #define PHY_CH_DEEP_PSR 0x7
2185 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2186 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
2187 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
2188 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2191 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2192 * this field (only one bit may be set).
2194 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2195 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
2196 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2197 /* i830, required in DVO non-gang */
2198 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
2199 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2200 #define PLL_REF_INPUT_DREFCLK (0 << 13)
2201 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2202 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2203 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2204 #define PLL_REF_INPUT_MASK (3 << 13)
2205 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
2207 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2208 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2209 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2210 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2211 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2214 * Parallel to Serial Load Pulse phase selection.
2215 * Selects the phase for the 10X DPLL clock for the PCIe
2216 * digital display port. The range is 4 to 13; 10 or more
2217 * is just a flip delay. The default is 6
2219 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2220 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2222 * SDVO multiplier for 945G/GM. Not used on 965.
2224 #define SDVO_MULTIPLIER_MASK 0x000000ff
2225 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
2226 #define SDVO_MULTIPLIER_SHIFT_VGA 0
2228 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2229 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2230 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2231 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2234 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2236 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2238 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2239 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
2240 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2241 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2242 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2244 * SDVO/UDI pixel multiplier.
2246 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2247 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2248 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2249 * dummy bytes in the datastream at an increased clock rate, with both sides of
2250 * the link knowing how many bytes are fill.
2252 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2253 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2254 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2255 * through an SDVO command.
2257 * This register field has values of multiplication factor minus 1, with
2258 * a maximum multiplier of 5 for SDVO.
2260 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2261 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2263 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2264 * This best be set to the default value (3) or the CRT won't work. No,
2265 * I don't entirely understand what this does...
2267 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2268 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
2270 #define _FPA0 0x06040
2271 #define _FPA1 0x06044
2272 #define _FPB0 0x06048
2273 #define _FPB1 0x0604c
2274 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
2275 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
2276 #define FP_N_DIV_MASK 0x003f0000
2277 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
2278 #define FP_N_DIV_SHIFT 16
2279 #define FP_M1_DIV_MASK 0x00003f00
2280 #define FP_M1_DIV_SHIFT 8
2281 #define FP_M2_DIV_MASK 0x0000003f
2282 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
2283 #define FP_M2_DIV_SHIFT 0
2284 #define DPLL_TEST 0x606c
2285 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2286 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2287 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2288 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2289 #define DPLLB_TEST_N_BYPASS (1 << 19)
2290 #define DPLLB_TEST_M_BYPASS (1 << 18)
2291 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2292 #define DPLLA_TEST_N_BYPASS (1 << 3)
2293 #define DPLLA_TEST_M_BYPASS (1 << 2)
2294 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2295 #define D_STATE 0x6104
2296 #define DSTATE_GFX_RESET_I830 (1<<6)
2297 #define DSTATE_PLL_D3_OFF (1<<3)
2298 #define DSTATE_GFX_CLOCK_GATING (1<<1)
2299 #define DSTATE_DOT_CLOCK_GATING (1<<0)
2300 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
2301 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2302 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2303 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2304 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2305 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2306 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2307 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2308 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2309 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2310 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2311 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2312 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2313 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2314 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2315 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2316 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2317 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2318 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2319 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2320 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2321 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2322 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2323 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2324 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2325 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2326 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2327 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2328 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
2330 * This bit must be set on the 830 to prevent hangs when turning off the
2333 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2334 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2335 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2336 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2337 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2339 #define RENCLK_GATE_D1 0x6204
2340 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2341 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2342 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2343 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2344 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2345 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2346 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2347 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2348 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
2349 /* This bit must be unset on 855,865 */
2350 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
2351 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2352 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
2353 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
2354 /* This bit must be set on 855,865. */
2355 # define SV_CLOCK_GATE_DISABLE (1 << 0)
2356 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2357 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2358 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2359 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2360 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2361 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2362 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2363 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2364 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2365 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2366 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2367 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2368 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2369 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2370 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2371 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2372 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2374 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
2375 /* This bit must always be set on 965G/965GM */
2376 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2377 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2378 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2379 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2380 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2381 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
2382 /* This bit must always be set on 965G */
2383 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2384 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2385 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2386 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2387 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2388 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2389 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2390 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2391 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2392 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2393 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2394 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2395 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2396 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2397 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2398 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2399 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2400 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2401 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2403 #define RENCLK_GATE_D2 0x6208
2404 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2405 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2406 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2408 #define VDECCLK_GATE_D 0x620C /* g4x only */
2409 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2411 #define RAMCLK_GATE_D 0x6210 /* CRL only */
2412 #define DEUC 0x6214 /* CRL only */
2414 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
2415 #define FW_CSPWRDWNEN (1<<15)
2417 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
2419 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
2420 #define CDCLK_FREQ_SHIFT 4
2421 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2422 #define CZCLK_FREQ_MASK 0xf
2424 #define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C)
2425 #define PFI_CREDIT_63 (9 << 28) /* chv only */
2426 #define PFI_CREDIT_31 (8 << 28) /* chv only */
2427 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2428 #define PFI_CREDIT_RESEND (1 << 27)
2429 #define VGA_FAST_MODE_DISABLE (1 << 14)
2431 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
2436 #define PALETTE_A_OFFSET 0xa000
2437 #define PALETTE_B_OFFSET 0xa800
2438 #define CHV_PALETTE_C_OFFSET 0xc000
2439 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2440 dev_priv->info.display_mmio_offset)
2442 /* MCH MMIO space */
2447 * This mirrors the MCHBAR MMIO space whose location is determined by
2448 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2449 * every way. It is not accessible from the CP register read instructions.
2451 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2454 #define MCHBAR_MIRROR_BASE 0x10000
2456 #define MCHBAR_MIRROR_BASE_SNB 0x140000
2458 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2459 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2461 /* 915-945 and GM965 MCH register controlling DRAM channel access */
2463 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2464 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2465 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2466 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
2467 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2468 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2469 #define DCC2 0x10204
2470 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2472 /* Pineview MCH register contains DDR3 setting */
2473 #define CSHRDDR3CTL 0x101a8
2474 #define CSHRDDR3CTL_DDR3 (1 << 2)
2476 /* 965 MCH register controlling DRAM channel configuration */
2477 #define C0DRB3 0x10206
2478 #define C1DRB3 0x10606
2480 /* snb MCH registers for reading the DRAM channel configuration */
2481 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
2482 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
2483 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
2484 #define MAD_DIMM_ECC_MASK (0x3 << 24)
2485 #define MAD_DIMM_ECC_OFF (0x0 << 24)
2486 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2487 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2488 #define MAD_DIMM_ECC_ON (0x3 << 24)
2489 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2490 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2491 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2492 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2493 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2494 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2495 #define MAD_DIMM_A_SELECT (0x1 << 16)
2496 /* DIMM sizes are in multiples of 256mb. */
2497 #define MAD_DIMM_B_SIZE_SHIFT 8
2498 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2499 #define MAD_DIMM_A_SIZE_SHIFT 0
2500 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2502 /* snb MCH registers for priority tuning */
2503 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2504 #define MCH_SSKPD_WM0_MASK 0x3f
2505 #define MCH_SSKPD_WM0_VAL 0xc
2507 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
2509 /* Clocking configuration register */
2510 #define CLKCFG 0x10c00
2511 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2512 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2513 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2514 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2515 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2516 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2517 /* Note, below two are guess */
2518 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2519 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2520 #define CLKCFG_FSB_MASK (7 << 0)
2521 #define CLKCFG_MEM_533 (1 << 4)
2522 #define CLKCFG_MEM_667 (2 << 4)
2523 #define CLKCFG_MEM_800 (3 << 4)
2524 #define CLKCFG_MEM_MASK (7 << 4)
2526 #define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38)
2527 #define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f)
2529 #define TSC1 0x11001
2532 #define TSFS 0x11020
2533 #define TSFS_SLOPE_MASK 0x0000ff00
2534 #define TSFS_SLOPE_SHIFT 8
2535 #define TSFS_INTR_MASK 0x000000ff
2537 #define CRSTANDVID 0x11100
2538 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2539 #define PXVFREQ_PX_MASK 0x7f000000
2540 #define PXVFREQ_PX_SHIFT 24
2541 #define VIDFREQ_BASE 0x11110
2542 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2543 #define VIDFREQ2 0x11114
2544 #define VIDFREQ3 0x11118
2545 #define VIDFREQ4 0x1111c
2546 #define VIDFREQ_P0_MASK 0x1f000000
2547 #define VIDFREQ_P0_SHIFT 24
2548 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2549 #define VIDFREQ_P0_CSCLK_SHIFT 20
2550 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2551 #define VIDFREQ_P0_CRCLK_SHIFT 16
2552 #define VIDFREQ_P1_MASK 0x00001f00
2553 #define VIDFREQ_P1_SHIFT 8
2554 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2555 #define VIDFREQ_P1_CSCLK_SHIFT 4
2556 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2557 #define INTTOEXT_BASE_ILK 0x11300
2558 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
2559 #define INTTOEXT_MAP3_SHIFT 24
2560 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2561 #define INTTOEXT_MAP2_SHIFT 16
2562 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2563 #define INTTOEXT_MAP1_SHIFT 8
2564 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2565 #define INTTOEXT_MAP0_SHIFT 0
2566 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2567 #define MEMSWCTL 0x11170 /* Ironlake only */
2568 #define MEMCTL_CMD_MASK 0xe000
2569 #define MEMCTL_CMD_SHIFT 13
2570 #define MEMCTL_CMD_RCLK_OFF 0
2571 #define MEMCTL_CMD_RCLK_ON 1
2572 #define MEMCTL_CMD_CHFREQ 2
2573 #define MEMCTL_CMD_CHVID 3
2574 #define MEMCTL_CMD_VMMOFF 4
2575 #define MEMCTL_CMD_VMMON 5
2576 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2577 when command complete */
2578 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2579 #define MEMCTL_FREQ_SHIFT 8
2580 #define MEMCTL_SFCAVM (1<<7)
2581 #define MEMCTL_TGT_VID_MASK 0x007f
2582 #define MEMIHYST 0x1117c
2583 #define MEMINTREN 0x11180 /* 16 bits */
2584 #define MEMINT_RSEXIT_EN (1<<8)
2585 #define MEMINT_CX_SUPR_EN (1<<7)
2586 #define MEMINT_CONT_BUSY_EN (1<<6)
2587 #define MEMINT_AVG_BUSY_EN (1<<5)
2588 #define MEMINT_EVAL_CHG_EN (1<<4)
2589 #define MEMINT_MON_IDLE_EN (1<<3)
2590 #define MEMINT_UP_EVAL_EN (1<<2)
2591 #define MEMINT_DOWN_EVAL_EN (1<<1)
2592 #define MEMINT_SW_CMD_EN (1<<0)
2593 #define MEMINTRSTR 0x11182 /* 16 bits */
2594 #define MEM_RSEXIT_MASK 0xc000
2595 #define MEM_RSEXIT_SHIFT 14
2596 #define MEM_CONT_BUSY_MASK 0x3000
2597 #define MEM_CONT_BUSY_SHIFT 12
2598 #define MEM_AVG_BUSY_MASK 0x0c00
2599 #define MEM_AVG_BUSY_SHIFT 10
2600 #define MEM_EVAL_CHG_MASK 0x0300
2601 #define MEM_EVAL_BUSY_SHIFT 8
2602 #define MEM_MON_IDLE_MASK 0x00c0
2603 #define MEM_MON_IDLE_SHIFT 6
2604 #define MEM_UP_EVAL_MASK 0x0030
2605 #define MEM_UP_EVAL_SHIFT 4
2606 #define MEM_DOWN_EVAL_MASK 0x000c
2607 #define MEM_DOWN_EVAL_SHIFT 2
2608 #define MEM_SW_CMD_MASK 0x0003
2609 #define MEM_INT_STEER_GFX 0
2610 #define MEM_INT_STEER_CMR 1
2611 #define MEM_INT_STEER_SMI 2
2612 #define MEM_INT_STEER_SCI 3
2613 #define MEMINTRSTS 0x11184
2614 #define MEMINT_RSEXIT (1<<7)
2615 #define MEMINT_CONT_BUSY (1<<6)
2616 #define MEMINT_AVG_BUSY (1<<5)
2617 #define MEMINT_EVAL_CHG (1<<4)
2618 #define MEMINT_MON_IDLE (1<<3)
2619 #define MEMINT_UP_EVAL (1<<2)
2620 #define MEMINT_DOWN_EVAL (1<<1)
2621 #define MEMINT_SW_CMD (1<<0)
2622 #define MEMMODECTL 0x11190
2623 #define MEMMODE_BOOST_EN (1<<31)
2624 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2625 #define MEMMODE_BOOST_FREQ_SHIFT 24
2626 #define MEMMODE_IDLE_MODE_MASK 0x00030000
2627 #define MEMMODE_IDLE_MODE_SHIFT 16
2628 #define MEMMODE_IDLE_MODE_EVAL 0
2629 #define MEMMODE_IDLE_MODE_CONT 1
2630 #define MEMMODE_HWIDLE_EN (1<<15)
2631 #define MEMMODE_SWMODE_EN (1<<14)
2632 #define MEMMODE_RCLK_GATE (1<<13)
2633 #define MEMMODE_HW_UPDATE (1<<12)
2634 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2635 #define MEMMODE_FSTART_SHIFT 8
2636 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2637 #define MEMMODE_FMAX_SHIFT 4
2638 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2639 #define RCBMAXAVG 0x1119c
2640 #define MEMSWCTL2 0x1119e /* Cantiga only */
2641 #define SWMEMCMD_RENDER_OFF (0 << 13)
2642 #define SWMEMCMD_RENDER_ON (1 << 13)
2643 #define SWMEMCMD_SWFREQ (2 << 13)
2644 #define SWMEMCMD_TARVID (3 << 13)
2645 #define SWMEMCMD_VRM_OFF (4 << 13)
2646 #define SWMEMCMD_VRM_ON (5 << 13)
2647 #define CMDSTS (1<<12)
2648 #define SFCAVM (1<<11)
2649 #define SWFREQ_MASK 0x0380 /* P0-7 */
2650 #define SWFREQ_SHIFT 7
2651 #define TARVID_MASK 0x001f
2652 #define MEMSTAT_CTG 0x111a0
2653 #define RCBMINAVG 0x111a0
2654 #define RCUPEI 0x111b0
2655 #define RCDNEI 0x111b4
2656 #define RSTDBYCTL 0x111b8
2657 #define RS1EN (1<<31)
2658 #define RS2EN (1<<30)
2659 #define RS3EN (1<<29)
2660 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2661 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2662 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2663 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2664 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2665 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2666 #define RSX_STATUS_MASK (7<<20)
2667 #define RSX_STATUS_ON (0<<20)
2668 #define RSX_STATUS_RC1 (1<<20)
2669 #define RSX_STATUS_RC1E (2<<20)
2670 #define RSX_STATUS_RS1 (3<<20)
2671 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2672 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2673 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2674 #define RSX_STATUS_RSVD2 (7<<20)
2675 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2676 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2677 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
2678 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2679 #define RS1CONTSAV_MASK (3<<14)
2680 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2681 #define RS1CONTSAV_RSVD (1<<14)
2682 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2683 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2684 #define NORMSLEXLAT_MASK (3<<12)
2685 #define SLOW_RS123 (0<<12)
2686 #define SLOW_RS23 (1<<12)
2687 #define SLOW_RS3 (2<<12)
2688 #define NORMAL_RS123 (3<<12)
2689 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2690 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2691 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2692 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2693 #define RS_CSTATE_MASK (3<<4)
2694 #define RS_CSTATE_C367_RS1 (0<<4)
2695 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2696 #define RS_CSTATE_RSVD (2<<4)
2697 #define RS_CSTATE_C367_RS2 (3<<4)
2698 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2699 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2700 #define VIDCTL 0x111c0
2701 #define VIDSTS 0x111c8
2702 #define VIDSTART 0x111cc /* 8 bits */
2703 #define MEMSTAT_ILK 0x111f8
2704 #define MEMSTAT_VID_MASK 0x7f00
2705 #define MEMSTAT_VID_SHIFT 8
2706 #define MEMSTAT_PSTATE_MASK 0x00f8
2707 #define MEMSTAT_PSTATE_SHIFT 3
2708 #define MEMSTAT_MON_ACTV (1<<2)
2709 #define MEMSTAT_SRC_CTL_MASK 0x0003
2710 #define MEMSTAT_SRC_CTL_CORE 0
2711 #define MEMSTAT_SRC_CTL_TRB 1
2712 #define MEMSTAT_SRC_CTL_THM 2
2713 #define MEMSTAT_SRC_CTL_STDBY 3
2714 #define RCPREVBSYTUPAVG 0x113b8
2715 #define RCPREVBSYTDNAVG 0x113bc
2716 #define PMMISC 0x11214
2717 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2718 #define SDEW 0x1124c
2719 #define CSIEW0 0x11250
2720 #define CSIEW1 0x11254
2721 #define CSIEW2 0x11258
2724 #define MCHAFE 0x112c0
2725 #define CSIEC 0x112e0
2726 #define DMIEC 0x112e4
2727 #define DDREC 0x112e8
2728 #define PEG0EC 0x112ec
2729 #define PEG1EC 0x112f0
2730 #define GFXEC 0x112f4
2731 #define RPPREVBSYTUPAVG 0x113b8
2732 #define RPPREVBSYTDNAVG 0x113bc
2734 #define ECR_GPFE (1<<31)
2735 #define ECR_IMONE (1<<30)
2736 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2737 #define OGW0 0x11608
2738 #define OGW1 0x1160c
2748 #define PXWL 0x11680
2749 #define LCFUSE02 0x116c0
2750 #define LCFUSE_HIV_MASK 0x000000ff
2751 #define CSIPLL0 0x12c10
2752 #define DDRMPLL1 0X12c20
2753 #define PEG_BAND_GAP_DATA 0x14d68
2755 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
2756 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2758 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
2759 #define BXT_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x7070)
2760 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
2761 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
2762 #define BXT_RP_STATE_CAP 0x138170
2764 #define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
2765 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2766 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2767 INTERVAL_1_33_US(us) : \
2768 INTERVAL_1_28_US(us))
2771 * Logical Context regs
2774 #define CCID_EN (1<<0)
2776 * Notes on SNB/IVB/VLV context size:
2777 * - Power context is saved elsewhere (LLC or stolen)
2778 * - Ring/execlist context is saved on SNB, not on IVB
2779 * - Extended context size already includes render context size
2780 * - We always need to follow the extended context size.
2781 * SNB BSpec has comments indicating that we should use the
2782 * render context size instead if execlists are disabled, but
2783 * based on empirical testing that's just nonsense.
2784 * - Pipelined/VF state is saved on SNB/IVB respectively
2785 * - GT1 size just indicates how much of render context
2786 * doesn't need saving on GT1
2788 #define CXT_SIZE 0x21a0
2789 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
2790 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
2791 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
2792 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
2793 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
2794 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2795 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2796 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2797 #define GEN7_CXT_SIZE 0x21a8
2798 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
2799 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
2800 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
2801 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
2802 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
2803 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
2804 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2805 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2806 /* Haswell does have the CXT_SIZE register however it does not appear to be
2807 * valid. Now, docs explain in dwords what is in the context object. The full
2808 * size is 70720 bytes, however, the power context and execlist context will
2809 * never be saved (power context is stored elsewhere, and execlists don't work
2810 * on HSW) - so the final size, including the extra state required for the
2811 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
2813 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
2814 /* Same as Haswell, but 72064 bytes now. */
2815 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2817 #define CHV_CLK_CTL1 0x101100
2818 #define VLV_CLK_CTL2 0x101104
2819 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2825 #define OVADD 0x30000
2826 #define DOVSTA 0x30008
2827 #define OC_BUF (0x3<<20)
2828 #define OGAMC5 0x30010
2829 #define OGAMC4 0x30014
2830 #define OGAMC3 0x30018
2831 #define OGAMC2 0x3001c
2832 #define OGAMC1 0x30020
2833 #define OGAMC0 0x30024
2836 * Display engine regs
2839 /* Pipe A CRC regs */
2840 #define _PIPE_CRC_CTL_A 0x60050
2841 #define PIPE_CRC_ENABLE (1 << 31)
2842 /* ivb+ source selection */
2843 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
2844 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
2845 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
2846 /* ilk+ source selection */
2847 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
2848 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
2849 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
2850 /* embedded DP port on the north display block, reserved on ivb */
2851 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
2852 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
2853 /* vlv source selection */
2854 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
2855 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
2856 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
2857 /* with DP port the pipe source is invalid */
2858 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
2859 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
2860 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
2861 /* gen3+ source selection */
2862 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
2863 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
2864 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
2865 /* with DP/TV port the pipe source is invalid */
2866 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
2867 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
2868 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
2869 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
2870 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
2871 /* gen2 doesn't have source selection bits */
2872 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
2874 #define _PIPE_CRC_RES_1_A_IVB 0x60064
2875 #define _PIPE_CRC_RES_2_A_IVB 0x60068
2876 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
2877 #define _PIPE_CRC_RES_4_A_IVB 0x60070
2878 #define _PIPE_CRC_RES_5_A_IVB 0x60074
2880 #define _PIPE_CRC_RES_RED_A 0x60060
2881 #define _PIPE_CRC_RES_GREEN_A 0x60064
2882 #define _PIPE_CRC_RES_BLUE_A 0x60068
2883 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
2884 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
2886 /* Pipe B CRC regs */
2887 #define _PIPE_CRC_RES_1_B_IVB 0x61064
2888 #define _PIPE_CRC_RES_2_B_IVB 0x61068
2889 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
2890 #define _PIPE_CRC_RES_4_B_IVB 0x61070
2891 #define _PIPE_CRC_RES_5_B_IVB 0x61074
2893 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
2894 #define PIPE_CRC_RES_1_IVB(pipe) \
2895 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
2896 #define PIPE_CRC_RES_2_IVB(pipe) \
2897 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
2898 #define PIPE_CRC_RES_3_IVB(pipe) \
2899 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
2900 #define PIPE_CRC_RES_4_IVB(pipe) \
2901 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
2902 #define PIPE_CRC_RES_5_IVB(pipe) \
2903 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
2905 #define PIPE_CRC_RES_RED(pipe) \
2906 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
2907 #define PIPE_CRC_RES_GREEN(pipe) \
2908 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
2909 #define PIPE_CRC_RES_BLUE(pipe) \
2910 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
2911 #define PIPE_CRC_RES_RES1_I915(pipe) \
2912 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
2913 #define PIPE_CRC_RES_RES2_G4X(pipe) \
2914 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
2916 /* Pipe A timing regs */
2917 #define _HTOTAL_A 0x60000
2918 #define _HBLANK_A 0x60004
2919 #define _HSYNC_A 0x60008
2920 #define _VTOTAL_A 0x6000c
2921 #define _VBLANK_A 0x60010
2922 #define _VSYNC_A 0x60014
2923 #define _PIPEASRC 0x6001c
2924 #define _BCLRPAT_A 0x60020
2925 #define _VSYNCSHIFT_A 0x60028
2926 #define _PIPE_MULT_A 0x6002c
2928 /* Pipe B timing regs */
2929 #define _HTOTAL_B 0x61000
2930 #define _HBLANK_B 0x61004
2931 #define _HSYNC_B 0x61008
2932 #define _VTOTAL_B 0x6100c
2933 #define _VBLANK_B 0x61010
2934 #define _VSYNC_B 0x61014
2935 #define _PIPEBSRC 0x6101c
2936 #define _BCLRPAT_B 0x61020
2937 #define _VSYNCSHIFT_B 0x61028
2938 #define _PIPE_MULT_B 0x6102c
2940 #define TRANSCODER_A_OFFSET 0x60000
2941 #define TRANSCODER_B_OFFSET 0x61000
2942 #define TRANSCODER_C_OFFSET 0x62000
2943 #define CHV_TRANSCODER_C_OFFSET 0x63000
2944 #define TRANSCODER_EDP_OFFSET 0x6f000
2946 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2947 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2948 dev_priv->info.display_mmio_offset)
2950 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2951 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2952 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2953 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2954 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2955 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2956 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2957 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2958 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2959 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A)
2961 /* VLV eDP PSR registers */
2962 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
2963 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
2964 #define VLV_EDP_PSR_ENABLE (1<<0)
2965 #define VLV_EDP_PSR_RESET (1<<1)
2966 #define VLV_EDP_PSR_MODE_MASK (7<<2)
2967 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
2968 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
2969 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
2970 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
2971 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
2972 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
2973 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
2974 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
2975 #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB)
2977 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
2978 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
2979 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
2980 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
2981 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
2982 #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB)
2984 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
2985 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
2986 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
2987 #define VLV_EDP_PSR_CURR_STATE_MASK 7
2988 #define VLV_EDP_PSR_DISABLED (0<<0)
2989 #define VLV_EDP_PSR_INACTIVE (1<<0)
2990 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
2991 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
2992 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
2993 #define VLV_EDP_PSR_EXIT (5<<0)
2994 #define VLV_EDP_PSR_IN_TRANS (1<<7)
2995 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
2997 /* HSW+ eDP PSR registers */
2998 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2999 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
3000 #define EDP_PSR_ENABLE (1<<31)
3001 #define BDW_PSR_SINGLE_FRAME (1<<30)
3002 #define EDP_PSR_LINK_STANDBY (1<<27)
3003 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3004 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3005 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3006 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3007 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3008 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3009 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3010 #define EDP_PSR_TP1_TP2_SEL (0<<11)
3011 #define EDP_PSR_TP1_TP3_SEL (1<<11)
3012 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3013 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3014 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3015 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3016 #define EDP_PSR_TP1_TIME_500us (0<<4)
3017 #define EDP_PSR_TP1_TIME_100us (1<<4)
3018 #define EDP_PSR_TP1_TIME_2500us (2<<4)
3019 #define EDP_PSR_TP1_TIME_0us (3<<4)
3020 #define EDP_PSR_IDLE_FRAME_SHIFT 0
3022 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
3023 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
3024 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
3025 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
3026 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
3027 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
3029 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
3030 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
3031 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3032 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3033 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3034 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3035 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3036 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3037 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3038 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
3039 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3040 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3041 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3042 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3043 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3044 #define EDP_PSR_STATUS_COUNT_SHIFT 16
3045 #define EDP_PSR_STATUS_COUNT_MASK 0xf
3046 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3047 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3048 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3049 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3050 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3051 #define EDP_PSR_STATUS_IDLE_MASK 0xf
3053 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
3054 #define EDP_PSR_PERF_CNT_MASK 0xffffff
3056 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
3057 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3058 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3059 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3061 #define EDP_PSR2_CTL 0x6f900
3062 #define EDP_PSR2_ENABLE (1<<31)
3063 #define EDP_SU_TRACK_ENABLE (1<<30)
3064 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3065 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3066 #define EDP_PSR2_TP2_TIME_500 (0<<8)
3067 #define EDP_PSR2_TP2_TIME_100 (1<<8)
3068 #define EDP_PSR2_TP2_TIME_2500 (2<<8)
3069 #define EDP_PSR2_TP2_TIME_50 (3<<8)
3070 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
3071 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3072 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3073 #define EDP_PSR2_IDLE_MASK 0xf
3075 /* VGA port control */
3076 #define ADPA 0x61100
3077 #define PCH_ADPA 0xe1100
3078 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
3080 #define ADPA_DAC_ENABLE (1<<31)
3081 #define ADPA_DAC_DISABLE 0
3082 #define ADPA_PIPE_SELECT_MASK (1<<30)
3083 #define ADPA_PIPE_A_SELECT 0
3084 #define ADPA_PIPE_B_SELECT (1<<30)
3085 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3086 /* CPT uses bits 29:30 for pch transcoder select */
3087 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3088 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3089 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3090 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3091 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3092 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3093 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3094 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3095 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3096 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3097 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3098 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3099 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3100 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3101 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3102 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3103 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3104 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3105 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3106 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
3107 #define ADPA_SETS_HVPOLARITY 0
3108 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
3109 #define ADPA_VSYNC_CNTL_ENABLE 0
3110 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
3111 #define ADPA_HSYNC_CNTL_ENABLE 0
3112 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3113 #define ADPA_VSYNC_ACTIVE_LOW 0
3114 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3115 #define ADPA_HSYNC_ACTIVE_LOW 0
3116 #define ADPA_DPMS_MASK (~(3<<10))
3117 #define ADPA_DPMS_ON (0<<10)
3118 #define ADPA_DPMS_SUSPEND (1<<10)
3119 #define ADPA_DPMS_STANDBY (2<<10)
3120 #define ADPA_DPMS_OFF (3<<10)
3123 /* Hotplug control (945+ only) */
3124 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
3125 #define PORTB_HOTPLUG_INT_EN (1 << 29)
3126 #define PORTC_HOTPLUG_INT_EN (1 << 28)
3127 #define PORTD_HOTPLUG_INT_EN (1 << 27)
3128 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
3129 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
3130 #define TV_HOTPLUG_INT_EN (1 << 18)
3131 #define CRT_HOTPLUG_INT_EN (1 << 9)
3132 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3133 PORTC_HOTPLUG_INT_EN | \
3134 PORTD_HOTPLUG_INT_EN | \
3135 SDVOC_HOTPLUG_INT_EN | \
3136 SDVOB_HOTPLUG_INT_EN | \
3138 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
3139 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3140 /* must use period 64 on GM45 according to docs */
3141 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3142 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3143 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3144 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3145 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3146 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3147 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3148 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3149 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3150 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3151 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3152 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
3154 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
3156 * HDMI/DP bits are gen4+
3158 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3159 * Please check the detailed lore in the commit message for for experimental
3162 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
3163 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
3164 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
3165 /* VLV DP/HDMI bits again match Bspec */
3166 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
3167 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
3168 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
3169 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
3170 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3171 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
3172 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
3173 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3174 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
3175 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
3176 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3177 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
3178 /* CRT/TV common between gen3+ */
3179 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
3180 #define TV_HOTPLUG_INT_STATUS (1 << 10)
3181 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3182 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3183 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3184 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
3185 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3186 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3187 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
3188 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3190 /* SDVO is different across gen3/4 */
3191 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3192 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
3194 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3195 * since reality corrobates that they're the same as on gen3. But keep these
3196 * bits here (and the comment!) to help any other lost wanderers back onto the
3199 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3200 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3201 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3202 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
3203 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3204 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3205 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3206 PORTB_HOTPLUG_INT_STATUS | \
3207 PORTC_HOTPLUG_INT_STATUS | \
3208 PORTD_HOTPLUG_INT_STATUS)
3210 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3211 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3212 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3213 PORTB_HOTPLUG_INT_STATUS | \
3214 PORTC_HOTPLUG_INT_STATUS | \
3215 PORTD_HOTPLUG_INT_STATUS)
3217 /* SDVO and HDMI port control.
3218 * The same register may be used for SDVO or HDMI */
3219 #define GEN3_SDVOB 0x61140
3220 #define GEN3_SDVOC 0x61160
3221 #define GEN4_HDMIB GEN3_SDVOB
3222 #define GEN4_HDMIC GEN3_SDVOC
3223 #define CHV_HDMID 0x6116C
3224 #define PCH_SDVOB 0xe1140
3225 #define PCH_HDMIB PCH_SDVOB
3226 #define PCH_HDMIC 0xe1150
3227 #define PCH_HDMID 0xe1160
3229 #define PORT_DFT_I9XX 0x61150
3230 #define DC_BALANCE_RESET (1 << 25)
3231 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
3232 #define DC_BALANCE_RESET_VLV (1 << 31)
3233 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3234 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
3235 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
3236 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
3238 /* Gen 3 SDVO bits: */
3239 #define SDVO_ENABLE (1 << 31)
3240 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3241 #define SDVO_PIPE_SEL_MASK (1 << 30)
3242 #define SDVO_PIPE_B_SELECT (1 << 30)
3243 #define SDVO_STALL_SELECT (1 << 29)
3244 #define SDVO_INTERRUPT_ENABLE (1 << 26)
3246 * 915G/GM SDVO pixel multiplier.
3247 * Programmed value is multiplier - 1, up to 5x.
3248 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3250 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
3251 #define SDVO_PORT_MULTIPLY_SHIFT 23
3252 #define SDVO_PHASE_SELECT_MASK (15 << 19)
3253 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3254 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3255 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3256 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3257 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3258 #define SDVO_DETECTED (1 << 2)
3259 /* Bits to be preserved when writing */
3260 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3261 SDVO_INTERRUPT_ENABLE)
3262 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3264 /* Gen 4 SDVO/HDMI bits: */
3265 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
3266 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
3267 #define SDVO_ENCODING_SDVO (0 << 10)
3268 #define SDVO_ENCODING_HDMI (2 << 10)
3269 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3270 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
3271 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
3272 #define SDVO_AUDIO_ENABLE (1 << 6)
3273 /* VSYNC/HSYNC bits new with 965, default is to be set */
3274 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3275 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3277 /* Gen 5 (IBX) SDVO/HDMI bits: */
3278 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
3279 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3281 /* Gen 6 (CPT) SDVO/HDMI bits: */
3282 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3283 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
3285 /* CHV SDVO/HDMI bits: */
3286 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3287 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3290 /* DVO port control */
3291 #define DVOA 0x61120
3292 #define DVOB 0x61140
3293 #define DVOC 0x61160
3294 #define DVO_ENABLE (1 << 31)
3295 #define DVO_PIPE_B_SELECT (1 << 30)
3296 #define DVO_PIPE_STALL_UNUSED (0 << 28)
3297 #define DVO_PIPE_STALL (1 << 28)
3298 #define DVO_PIPE_STALL_TV (2 << 28)
3299 #define DVO_PIPE_STALL_MASK (3 << 28)
3300 #define DVO_USE_VGA_SYNC (1 << 15)
3301 #define DVO_DATA_ORDER_I740 (0 << 14)
3302 #define DVO_DATA_ORDER_FP (1 << 14)
3303 #define DVO_VSYNC_DISABLE (1 << 11)
3304 #define DVO_HSYNC_DISABLE (1 << 10)
3305 #define DVO_VSYNC_TRISTATE (1 << 9)
3306 #define DVO_HSYNC_TRISTATE (1 << 8)
3307 #define DVO_BORDER_ENABLE (1 << 7)
3308 #define DVO_DATA_ORDER_GBRG (1 << 6)
3309 #define DVO_DATA_ORDER_RGGB (0 << 6)
3310 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3311 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3312 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3313 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3314 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3315 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3316 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3317 #define DVO_PRESERVE_MASK (0x7<<24)
3318 #define DVOA_SRCDIM 0x61124
3319 #define DVOB_SRCDIM 0x61144
3320 #define DVOC_SRCDIM 0x61164
3321 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3322 #define DVO_SRCDIM_VERTICAL_SHIFT 0
3324 /* LVDS port control */
3325 #define LVDS 0x61180
3327 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3328 * the DPLL semantics change when the LVDS is assigned to that pipe.
3330 #define LVDS_PORT_EN (1 << 31)
3331 /* Selects pipe B for LVDS data. Must be set on pre-965. */
3332 #define LVDS_PIPEB_SELECT (1 << 30)
3333 #define LVDS_PIPE_MASK (1 << 30)
3334 #define LVDS_PIPE(pipe) ((pipe) << 30)
3335 /* LVDS dithering flag on 965/g4x platform */
3336 #define LVDS_ENABLE_DITHER (1 << 25)
3337 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
3338 #define LVDS_VSYNC_POLARITY (1 << 21)
3339 #define LVDS_HSYNC_POLARITY (1 << 20)
3341 /* Enable border for unscaled (or aspect-scaled) display */
3342 #define LVDS_BORDER_ENABLE (1 << 15)
3344 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3347 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3348 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3349 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3351 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3352 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3355 #define LVDS_A3_POWER_MASK (3 << 6)
3356 #define LVDS_A3_POWER_DOWN (0 << 6)
3357 #define LVDS_A3_POWER_UP (3 << 6)
3359 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3362 #define LVDS_CLKB_POWER_MASK (3 << 4)
3363 #define LVDS_CLKB_POWER_DOWN (0 << 4)
3364 #define LVDS_CLKB_POWER_UP (3 << 4)
3366 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3367 * setting for whether we are in dual-channel mode. The B3 pair will
3368 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3370 #define LVDS_B0B3_POWER_MASK (3 << 2)
3371 #define LVDS_B0B3_POWER_DOWN (0 << 2)
3372 #define LVDS_B0B3_POWER_UP (3 << 2)
3374 /* Video Data Island Packet control */
3375 #define VIDEO_DIP_DATA 0x61178
3376 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3377 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3378 * of the infoframe structure specified by CEA-861. */
3379 #define VIDEO_DIP_DATA_SIZE 32
3380 #define VIDEO_DIP_VSC_DATA_SIZE 36
3381 #define VIDEO_DIP_CTL 0x61170
3383 #define VIDEO_DIP_ENABLE (1 << 31)
3384 #define VIDEO_DIP_PORT(port) ((port) << 29)
3385 #define VIDEO_DIP_PORT_MASK (3 << 29)
3386 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
3387 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
3388 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
3389 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
3390 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
3391 #define VIDEO_DIP_SELECT_AVI (0 << 19)
3392 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3393 #define VIDEO_DIP_SELECT_SPD (3 << 19)
3394 #define VIDEO_DIP_SELECT_MASK (3 << 19)
3395 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
3396 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3397 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
3398 #define VIDEO_DIP_FREQ_MASK (3 << 16)
3399 /* HSW and later: */
3400 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3401 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
3402 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
3403 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3404 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
3405 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3407 /* Panel power sequencing */
3408 #define PP_STATUS 0x61200
3409 #define PP_ON (1 << 31)
3411 * Indicates that all dependencies of the panel are on:
3415 * - LVDS/DVOB/DVOC on
3417 #define PP_READY (1 << 30)
3418 #define PP_SEQUENCE_NONE (0 << 28)
3419 #define PP_SEQUENCE_POWER_UP (1 << 28)
3420 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
3421 #define PP_SEQUENCE_MASK (3 << 28)
3422 #define PP_SEQUENCE_SHIFT 28
3423 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
3424 #define PP_SEQUENCE_STATE_MASK 0x0000000f
3425 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3426 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3427 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3428 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3429 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3430 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3431 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3432 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3433 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
3434 #define PP_CONTROL 0x61204
3435 #define POWER_TARGET_ON (1 << 0)
3436 #define PP_ON_DELAYS 0x61208
3437 #define PP_OFF_DELAYS 0x6120c
3438 #define PP_DIVISOR 0x61210
3441 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
3442 #define PFIT_ENABLE (1 << 31)
3443 #define PFIT_PIPE_MASK (3 << 29)
3444 #define PFIT_PIPE_SHIFT 29
3445 #define VERT_INTERP_DISABLE (0 << 10)
3446 #define VERT_INTERP_BILINEAR (1 << 10)
3447 #define VERT_INTERP_MASK (3 << 10)
3448 #define VERT_AUTO_SCALE (1 << 9)
3449 #define HORIZ_INTERP_DISABLE (0 << 6)
3450 #define HORIZ_INTERP_BILINEAR (1 << 6)
3451 #define HORIZ_INTERP_MASK (3 << 6)
3452 #define HORIZ_AUTO_SCALE (1 << 5)
3453 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3454 #define PFIT_FILTER_FUZZY (0 << 24)
3455 #define PFIT_SCALING_AUTO (0 << 26)
3456 #define PFIT_SCALING_PROGRAMMED (1 << 26)
3457 #define PFIT_SCALING_PILLAR (2 << 26)
3458 #define PFIT_SCALING_LETTER (3 << 26)
3459 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3461 #define PFIT_VERT_SCALE_SHIFT 20
3462 #define PFIT_VERT_SCALE_MASK 0xfff00000
3463 #define PFIT_HORIZ_SCALE_SHIFT 4
3464 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3466 #define PFIT_VERT_SCALE_SHIFT_965 16
3467 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3468 #define PFIT_HORIZ_SCALE_SHIFT_965 0
3469 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3471 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3473 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3474 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3475 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3476 _VLV_BLC_PWM_CTL2_B)
3478 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3479 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3480 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3483 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3484 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3485 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3486 _VLV_BLC_HIST_CTL_B)
3488 /* Backlight control */
3489 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3490 #define BLM_PWM_ENABLE (1 << 31)
3491 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3492 #define BLM_PIPE_SELECT (1 << 29)
3493 #define BLM_PIPE_SELECT_IVB (3 << 29)
3494 #define BLM_PIPE_A (0 << 29)
3495 #define BLM_PIPE_B (1 << 29)
3496 #define BLM_PIPE_C (2 << 29) /* ivb + */
3497 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3498 #define BLM_TRANSCODER_B BLM_PIPE_B
3499 #define BLM_TRANSCODER_C BLM_PIPE_C
3500 #define BLM_TRANSCODER_EDP (3 << 29)
3501 #define BLM_PIPE(pipe) ((pipe) << 29)
3502 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3503 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3504 #define BLM_PHASE_IN_ENABLE (1 << 25)
3505 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3506 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3507 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3508 #define BLM_PHASE_IN_COUNT_SHIFT (8)
3509 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3510 #define BLM_PHASE_IN_INCR_SHIFT (0)
3511 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3512 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3514 * This is the most significant 15 bits of the number of backlight cycles in a
3515 * complete cycle of the modulated backlight control.
3517 * The actual value is this field multiplied by two.
3519 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3520 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3521 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3523 * This is the number of cycles out of the backlight modulation cycle for which
3524 * the backlight is on.
3526 * This field must be no greater than the number of cycles in the complete
3527 * backlight modulation cycle.
3529 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3530 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3531 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3532 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3534 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
3535 #define BLM_HISTOGRAM_ENABLE (1 << 31)
3537 /* New registers for PCH-split platforms. Safe where new bits show up, the
3538 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3539 #define BLC_PWM_CPU_CTL2 0x48250
3540 #define BLC_PWM_CPU_CTL 0x48254
3542 #define HSW_BLC_PWM2_CTL 0x48350
3544 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3545 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3546 #define BLC_PWM_PCH_CTL1 0xc8250
3547 #define BLM_PCH_PWM_ENABLE (1 << 31)
3548 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3549 #define BLM_PCH_POLARITY (1 << 29)
3550 #define BLC_PWM_PCH_CTL2 0xc8254
3552 #define UTIL_PIN_CTL 0x48400
3553 #define UTIL_PIN_ENABLE (1 << 31)
3555 /* BXT backlight register definition. */
3556 #define BXT_BLC_PWM_CTL1 0xC8250
3557 #define BXT_BLC_PWM_ENABLE (1 << 31)
3558 #define BXT_BLC_PWM_POLARITY (1 << 29)
3559 #define BXT_BLC_PWM_FREQ1 0xC8254
3560 #define BXT_BLC_PWM_DUTY1 0xC8258
3562 #define BXT_BLC_PWM_CTL2 0xC8350
3563 #define BXT_BLC_PWM_FREQ2 0xC8354
3564 #define BXT_BLC_PWM_DUTY2 0xC8358
3567 #define PCH_GTC_CTL 0xe7000
3568 #define PCH_GTC_ENABLE (1 << 31)
3570 /* TV port control */
3571 #define TV_CTL 0x68000
3572 /* Enables the TV encoder */
3573 # define TV_ENC_ENABLE (1 << 31)
3574 /* Sources the TV encoder input from pipe B instead of A. */
3575 # define TV_ENC_PIPEB_SELECT (1 << 30)
3576 /* Outputs composite video (DAC A only) */
3577 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3578 /* Outputs SVideo video (DAC B/C) */
3579 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3580 /* Outputs Component video (DAC A/B/C) */
3581 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3582 /* Outputs Composite and SVideo (DAC A/B/C) */
3583 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3584 # define TV_TRILEVEL_SYNC (1 << 21)
3585 /* Enables slow sync generation (945GM only) */
3586 # define TV_SLOW_SYNC (1 << 20)
3587 /* Selects 4x oversampling for 480i and 576p */
3588 # define TV_OVERSAMPLE_4X (0 << 18)
3589 /* Selects 2x oversampling for 720p and 1080i */
3590 # define TV_OVERSAMPLE_2X (1 << 18)
3591 /* Selects no oversampling for 1080p */
3592 # define TV_OVERSAMPLE_NONE (2 << 18)
3593 /* Selects 8x oversampling */
3594 # define TV_OVERSAMPLE_8X (3 << 18)
3595 /* Selects progressive mode rather than interlaced */
3596 # define TV_PROGRESSIVE (1 << 17)
3597 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3598 # define TV_PAL_BURST (1 << 16)
3599 /* Field for setting delay of Y compared to C */
3600 # define TV_YC_SKEW_MASK (7 << 12)
3601 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3602 # define TV_ENC_SDP_FIX (1 << 11)
3604 * Enables a fix for the 915GM only.
3606 * Not sure what it does.
3608 # define TV_ENC_C0_FIX (1 << 10)
3609 /* Bits that must be preserved by software */
3610 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3611 # define TV_FUSE_STATE_MASK (3 << 4)
3612 /* Read-only state that reports all features enabled */
3613 # define TV_FUSE_STATE_ENABLED (0 << 4)
3614 /* Read-only state that reports that Macrovision is disabled in hardware*/
3615 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3616 /* Read-only state that reports that TV-out is disabled in hardware. */
3617 # define TV_FUSE_STATE_DISABLED (2 << 4)
3618 /* Normal operation */
3619 # define TV_TEST_MODE_NORMAL (0 << 0)
3620 /* Encoder test pattern 1 - combo pattern */
3621 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
3622 /* Encoder test pattern 2 - full screen vertical 75% color bars */
3623 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
3624 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3625 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
3626 /* Encoder test pattern 4 - random noise */
3627 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
3628 /* Encoder test pattern 5 - linear color ramps */
3629 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
3631 * This test mode forces the DACs to 50% of full output.
3633 * This is used for load detection in combination with TVDAC_SENSE_MASK
3635 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3636 # define TV_TEST_MODE_MASK (7 << 0)
3638 #define TV_DAC 0x68004
3639 # define TV_DAC_SAVE 0x00ffff00
3641 * Reports that DAC state change logic has reported change (RO).
3643 * This gets cleared when TV_DAC_STATE_EN is cleared
3645 # define TVDAC_STATE_CHG (1 << 31)
3646 # define TVDAC_SENSE_MASK (7 << 28)
3647 /* Reports that DAC A voltage is above the detect threshold */
3648 # define TVDAC_A_SENSE (1 << 30)
3649 /* Reports that DAC B voltage is above the detect threshold */
3650 # define TVDAC_B_SENSE (1 << 29)
3651 /* Reports that DAC C voltage is above the detect threshold */
3652 # define TVDAC_C_SENSE (1 << 28)
3654 * Enables DAC state detection logic, for load-based TV detection.
3656 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3657 * to off, for load detection to work.
3659 # define TVDAC_STATE_CHG_EN (1 << 27)
3660 /* Sets the DAC A sense value to high */
3661 # define TVDAC_A_SENSE_CTL (1 << 26)
3662 /* Sets the DAC B sense value to high */
3663 # define TVDAC_B_SENSE_CTL (1 << 25)
3664 /* Sets the DAC C sense value to high */
3665 # define TVDAC_C_SENSE_CTL (1 << 24)
3666 /* Overrides the ENC_ENABLE and DAC voltage levels */
3667 # define DAC_CTL_OVERRIDE (1 << 7)
3668 /* Sets the slew rate. Must be preserved in software */
3669 # define ENC_TVDAC_SLEW_FAST (1 << 6)
3670 # define DAC_A_1_3_V (0 << 4)
3671 # define DAC_A_1_1_V (1 << 4)
3672 # define DAC_A_0_7_V (2 << 4)
3673 # define DAC_A_MASK (3 << 4)
3674 # define DAC_B_1_3_V (0 << 2)
3675 # define DAC_B_1_1_V (1 << 2)
3676 # define DAC_B_0_7_V (2 << 2)
3677 # define DAC_B_MASK (3 << 2)
3678 # define DAC_C_1_3_V (0 << 0)
3679 # define DAC_C_1_1_V (1 << 0)
3680 # define DAC_C_0_7_V (2 << 0)
3681 # define DAC_C_MASK (3 << 0)
3684 * CSC coefficients are stored in a floating point format with 9 bits of
3685 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3686 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3687 * -1 (0x3) being the only legal negative value.
3689 #define TV_CSC_Y 0x68010
3690 # define TV_RY_MASK 0x07ff0000
3691 # define TV_RY_SHIFT 16
3692 # define TV_GY_MASK 0x00000fff
3693 # define TV_GY_SHIFT 0
3695 #define TV_CSC_Y2 0x68014
3696 # define TV_BY_MASK 0x07ff0000
3697 # define TV_BY_SHIFT 16
3699 * Y attenuation for component video.
3701 * Stored in 1.9 fixed point.
3703 # define TV_AY_MASK 0x000003ff
3704 # define TV_AY_SHIFT 0
3706 #define TV_CSC_U 0x68018
3707 # define TV_RU_MASK 0x07ff0000
3708 # define TV_RU_SHIFT 16
3709 # define TV_GU_MASK 0x000007ff
3710 # define TV_GU_SHIFT 0
3712 #define TV_CSC_U2 0x6801c
3713 # define TV_BU_MASK 0x07ff0000
3714 # define TV_BU_SHIFT 16
3716 * U attenuation for component video.
3718 * Stored in 1.9 fixed point.
3720 # define TV_AU_MASK 0x000003ff
3721 # define TV_AU_SHIFT 0
3723 #define TV_CSC_V 0x68020
3724 # define TV_RV_MASK 0x0fff0000
3725 # define TV_RV_SHIFT 16
3726 # define TV_GV_MASK 0x000007ff
3727 # define TV_GV_SHIFT 0
3729 #define TV_CSC_V2 0x68024
3730 # define TV_BV_MASK 0x07ff0000
3731 # define TV_BV_SHIFT 16
3733 * V attenuation for component video.
3735 * Stored in 1.9 fixed point.
3737 # define TV_AV_MASK 0x000007ff
3738 # define TV_AV_SHIFT 0
3740 #define TV_CLR_KNOBS 0x68028
3741 /* 2s-complement brightness adjustment */
3742 # define TV_BRIGHTNESS_MASK 0xff000000
3743 # define TV_BRIGHTNESS_SHIFT 24
3744 /* Contrast adjustment, as a 2.6 unsigned floating point number */
3745 # define TV_CONTRAST_MASK 0x00ff0000
3746 # define TV_CONTRAST_SHIFT 16
3747 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3748 # define TV_SATURATION_MASK 0x0000ff00
3749 # define TV_SATURATION_SHIFT 8
3750 /* Hue adjustment, as an integer phase angle in degrees */
3751 # define TV_HUE_MASK 0x000000ff
3752 # define TV_HUE_SHIFT 0
3754 #define TV_CLR_LEVEL 0x6802c
3755 /* Controls the DAC level for black */
3756 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3757 # define TV_BLACK_LEVEL_SHIFT 16
3758 /* Controls the DAC level for blanking */
3759 # define TV_BLANK_LEVEL_MASK 0x000001ff
3760 # define TV_BLANK_LEVEL_SHIFT 0
3762 #define TV_H_CTL_1 0x68030
3763 /* Number of pixels in the hsync. */
3764 # define TV_HSYNC_END_MASK 0x1fff0000
3765 # define TV_HSYNC_END_SHIFT 16
3766 /* Total number of pixels minus one in the line (display and blanking). */
3767 # define TV_HTOTAL_MASK 0x00001fff
3768 # define TV_HTOTAL_SHIFT 0
3770 #define TV_H_CTL_2 0x68034
3771 /* Enables the colorburst (needed for non-component color) */
3772 # define TV_BURST_ENA (1 << 31)
3773 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3774 # define TV_HBURST_START_SHIFT 16
3775 # define TV_HBURST_START_MASK 0x1fff0000
3776 /* Length of the colorburst */
3777 # define TV_HBURST_LEN_SHIFT 0
3778 # define TV_HBURST_LEN_MASK 0x0001fff
3780 #define TV_H_CTL_3 0x68038
3781 /* End of hblank, measured in pixels minus one from start of hsync */
3782 # define TV_HBLANK_END_SHIFT 16
3783 # define TV_HBLANK_END_MASK 0x1fff0000
3784 /* Start of hblank, measured in pixels minus one from start of hsync */
3785 # define TV_HBLANK_START_SHIFT 0
3786 # define TV_HBLANK_START_MASK 0x0001fff
3788 #define TV_V_CTL_1 0x6803c
3790 # define TV_NBR_END_SHIFT 16
3791 # define TV_NBR_END_MASK 0x07ff0000
3793 # define TV_VI_END_F1_SHIFT 8
3794 # define TV_VI_END_F1_MASK 0x00003f00
3796 # define TV_VI_END_F2_SHIFT 0
3797 # define TV_VI_END_F2_MASK 0x0000003f
3799 #define TV_V_CTL_2 0x68040
3800 /* Length of vsync, in half lines */
3801 # define TV_VSYNC_LEN_MASK 0x07ff0000
3802 # define TV_VSYNC_LEN_SHIFT 16
3803 /* Offset of the start of vsync in field 1, measured in one less than the
3804 * number of half lines.
3806 # define TV_VSYNC_START_F1_MASK 0x00007f00
3807 # define TV_VSYNC_START_F1_SHIFT 8
3809 * Offset of the start of vsync in field 2, measured in one less than the
3810 * number of half lines.
3812 # define TV_VSYNC_START_F2_MASK 0x0000007f
3813 # define TV_VSYNC_START_F2_SHIFT 0
3815 #define TV_V_CTL_3 0x68044
3816 /* Enables generation of the equalization signal */
3817 # define TV_EQUAL_ENA (1 << 31)
3818 /* Length of vsync, in half lines */
3819 # define TV_VEQ_LEN_MASK 0x007f0000
3820 # define TV_VEQ_LEN_SHIFT 16
3821 /* Offset of the start of equalization in field 1, measured in one less than
3822 * the number of half lines.
3824 # define TV_VEQ_START_F1_MASK 0x0007f00
3825 # define TV_VEQ_START_F1_SHIFT 8
3827 * Offset of the start of equalization in field 2, measured in one less than
3828 * the number of half lines.
3830 # define TV_VEQ_START_F2_MASK 0x000007f
3831 # define TV_VEQ_START_F2_SHIFT 0
3833 #define TV_V_CTL_4 0x68048
3835 * Offset to start of vertical colorburst, measured in one less than the
3836 * number of lines from vertical start.
3838 # define TV_VBURST_START_F1_MASK 0x003f0000
3839 # define TV_VBURST_START_F1_SHIFT 16
3841 * Offset to the end of vertical colorburst, measured in one less than the
3842 * number of lines from the start of NBR.
3844 # define TV_VBURST_END_F1_MASK 0x000000ff
3845 # define TV_VBURST_END_F1_SHIFT 0
3847 #define TV_V_CTL_5 0x6804c
3849 * Offset to start of vertical colorburst, measured in one less than the
3850 * number of lines from vertical start.
3852 # define TV_VBURST_START_F2_MASK 0x003f0000
3853 # define TV_VBURST_START_F2_SHIFT 16
3855 * Offset to the end of vertical colorburst, measured in one less than the
3856 * number of lines from the start of NBR.
3858 # define TV_VBURST_END_F2_MASK 0x000000ff
3859 # define TV_VBURST_END_F2_SHIFT 0
3861 #define TV_V_CTL_6 0x68050
3863 * Offset to start of vertical colorburst, measured in one less than the
3864 * number of lines from vertical start.
3866 # define TV_VBURST_START_F3_MASK 0x003f0000
3867 # define TV_VBURST_START_F3_SHIFT 16
3869 * Offset to the end of vertical colorburst, measured in one less than the
3870 * number of lines from the start of NBR.
3872 # define TV_VBURST_END_F3_MASK 0x000000ff
3873 # define TV_VBURST_END_F3_SHIFT 0
3875 #define TV_V_CTL_7 0x68054
3877 * Offset to start of vertical colorburst, measured in one less than the
3878 * number of lines from vertical start.
3880 # define TV_VBURST_START_F4_MASK 0x003f0000
3881 # define TV_VBURST_START_F4_SHIFT 16
3883 * Offset to the end of vertical colorburst, measured in one less than the
3884 * number of lines from the start of NBR.
3886 # define TV_VBURST_END_F4_MASK 0x000000ff
3887 # define TV_VBURST_END_F4_SHIFT 0
3889 #define TV_SC_CTL_1 0x68060
3890 /* Turns on the first subcarrier phase generation DDA */
3891 # define TV_SC_DDA1_EN (1 << 31)
3892 /* Turns on the first subcarrier phase generation DDA */
3893 # define TV_SC_DDA2_EN (1 << 30)
3894 /* Turns on the first subcarrier phase generation DDA */
3895 # define TV_SC_DDA3_EN (1 << 29)
3896 /* Sets the subcarrier DDA to reset frequency every other field */
3897 # define TV_SC_RESET_EVERY_2 (0 << 24)
3898 /* Sets the subcarrier DDA to reset frequency every fourth field */
3899 # define TV_SC_RESET_EVERY_4 (1 << 24)
3900 /* Sets the subcarrier DDA to reset frequency every eighth field */
3901 # define TV_SC_RESET_EVERY_8 (2 << 24)
3902 /* Sets the subcarrier DDA to never reset the frequency */
3903 # define TV_SC_RESET_NEVER (3 << 24)
3904 /* Sets the peak amplitude of the colorburst.*/
3905 # define TV_BURST_LEVEL_MASK 0x00ff0000
3906 # define TV_BURST_LEVEL_SHIFT 16
3907 /* Sets the increment of the first subcarrier phase generation DDA */
3908 # define TV_SCDDA1_INC_MASK 0x00000fff
3909 # define TV_SCDDA1_INC_SHIFT 0
3911 #define TV_SC_CTL_2 0x68064
3912 /* Sets the rollover for the second subcarrier phase generation DDA */
3913 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
3914 # define TV_SCDDA2_SIZE_SHIFT 16
3915 /* Sets the increent of the second subcarrier phase generation DDA */
3916 # define TV_SCDDA2_INC_MASK 0x00007fff
3917 # define TV_SCDDA2_INC_SHIFT 0
3919 #define TV_SC_CTL_3 0x68068
3920 /* Sets the rollover for the third subcarrier phase generation DDA */
3921 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
3922 # define TV_SCDDA3_SIZE_SHIFT 16
3923 /* Sets the increent of the third subcarrier phase generation DDA */
3924 # define TV_SCDDA3_INC_MASK 0x00007fff
3925 # define TV_SCDDA3_INC_SHIFT 0
3927 #define TV_WIN_POS 0x68070
3928 /* X coordinate of the display from the start of horizontal active */
3929 # define TV_XPOS_MASK 0x1fff0000
3930 # define TV_XPOS_SHIFT 16
3931 /* Y coordinate of the display from the start of vertical active (NBR) */
3932 # define TV_YPOS_MASK 0x00000fff
3933 # define TV_YPOS_SHIFT 0
3935 #define TV_WIN_SIZE 0x68074
3936 /* Horizontal size of the display window, measured in pixels*/
3937 # define TV_XSIZE_MASK 0x1fff0000
3938 # define TV_XSIZE_SHIFT 16
3940 * Vertical size of the display window, measured in pixels.
3942 * Must be even for interlaced modes.
3944 # define TV_YSIZE_MASK 0x00000fff
3945 # define TV_YSIZE_SHIFT 0
3947 #define TV_FILTER_CTL_1 0x68080
3949 * Enables automatic scaling calculation.
3951 * If set, the rest of the registers are ignored, and the calculated values can
3952 * be read back from the register.
3954 # define TV_AUTO_SCALE (1 << 31)
3956 * Disables the vertical filter.
3958 * This is required on modes more than 1024 pixels wide */
3959 # define TV_V_FILTER_BYPASS (1 << 29)
3960 /* Enables adaptive vertical filtering */
3961 # define TV_VADAPT (1 << 28)
3962 # define TV_VADAPT_MODE_MASK (3 << 26)
3963 /* Selects the least adaptive vertical filtering mode */
3964 # define TV_VADAPT_MODE_LEAST (0 << 26)
3965 /* Selects the moderately adaptive vertical filtering mode */
3966 # define TV_VADAPT_MODE_MODERATE (1 << 26)
3967 /* Selects the most adaptive vertical filtering mode */
3968 # define TV_VADAPT_MODE_MOST (3 << 26)
3970 * Sets the horizontal scaling factor.
3972 * This should be the fractional part of the horizontal scaling factor divided
3973 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3975 * (src width - 1) / ((oversample * dest width) - 1)
3977 # define TV_HSCALE_FRAC_MASK 0x00003fff
3978 # define TV_HSCALE_FRAC_SHIFT 0
3980 #define TV_FILTER_CTL_2 0x68084
3982 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3984 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3986 # define TV_VSCALE_INT_MASK 0x00038000
3987 # define TV_VSCALE_INT_SHIFT 15
3989 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3991 * \sa TV_VSCALE_INT_MASK
3993 # define TV_VSCALE_FRAC_MASK 0x00007fff
3994 # define TV_VSCALE_FRAC_SHIFT 0
3996 #define TV_FILTER_CTL_3 0x68088
3998 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4000 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4002 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4004 # define TV_VSCALE_IP_INT_MASK 0x00038000
4005 # define TV_VSCALE_IP_INT_SHIFT 15
4007 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4009 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4011 * \sa TV_VSCALE_IP_INT_MASK
4013 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4014 # define TV_VSCALE_IP_FRAC_SHIFT 0
4016 #define TV_CC_CONTROL 0x68090
4017 # define TV_CC_ENABLE (1 << 31)
4019 * Specifies which field to send the CC data in.
4021 * CC data is usually sent in field 0.
4023 # define TV_CC_FID_MASK (1 << 27)
4024 # define TV_CC_FID_SHIFT 27
4025 /* Sets the horizontal position of the CC data. Usually 135. */
4026 # define TV_CC_HOFF_MASK 0x03ff0000
4027 # define TV_CC_HOFF_SHIFT 16
4028 /* Sets the vertical position of the CC data. Usually 21 */
4029 # define TV_CC_LINE_MASK 0x0000003f
4030 # define TV_CC_LINE_SHIFT 0
4032 #define TV_CC_DATA 0x68094
4033 # define TV_CC_RDY (1 << 31)
4034 /* Second word of CC data to be transmitted. */
4035 # define TV_CC_DATA_2_MASK 0x007f0000
4036 # define TV_CC_DATA_2_SHIFT 16
4037 /* First word of CC data to be transmitted. */
4038 # define TV_CC_DATA_1_MASK 0x0000007f
4039 # define TV_CC_DATA_1_SHIFT 0
4041 #define TV_H_LUMA_0 0x68100
4042 #define TV_H_LUMA_59 0x681ec
4043 #define TV_H_CHROMA_0 0x68200
4044 #define TV_H_CHROMA_59 0x682ec
4045 #define TV_V_LUMA_0 0x68300
4046 #define TV_V_LUMA_42 0x683a8
4047 #define TV_V_CHROMA_0 0x68400
4048 #define TV_V_CHROMA_42 0x684a8
4051 #define DP_A 0x64000 /* eDP */
4052 #define DP_B 0x64100
4053 #define DP_C 0x64200
4054 #define DP_D 0x64300
4056 #define DP_PORT_EN (1 << 31)
4057 #define DP_PIPEB_SELECT (1 << 30)
4058 #define DP_PIPE_MASK (1 << 30)
4059 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4060 #define DP_PIPE_MASK_CHV (3 << 16)
4062 /* Link training mode - select a suitable mode for each stage */
4063 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
4064 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
4065 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4066 #define DP_LINK_TRAIN_OFF (3 << 28)
4067 #define DP_LINK_TRAIN_MASK (3 << 28)
4068 #define DP_LINK_TRAIN_SHIFT 28
4069 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4070 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
4072 /* CPT Link training mode */
4073 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4074 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4075 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4076 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4077 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4078 #define DP_LINK_TRAIN_SHIFT_CPT 8
4080 /* Signal voltages. These are mostly controlled by the other end */
4081 #define DP_VOLTAGE_0_4 (0 << 25)
4082 #define DP_VOLTAGE_0_6 (1 << 25)
4083 #define DP_VOLTAGE_0_8 (2 << 25)
4084 #define DP_VOLTAGE_1_2 (3 << 25)
4085 #define DP_VOLTAGE_MASK (7 << 25)
4086 #define DP_VOLTAGE_SHIFT 25
4088 /* Signal pre-emphasis levels, like voltages, the other end tells us what
4091 #define DP_PRE_EMPHASIS_0 (0 << 22)
4092 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
4093 #define DP_PRE_EMPHASIS_6 (2 << 22)
4094 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
4095 #define DP_PRE_EMPHASIS_MASK (7 << 22)
4096 #define DP_PRE_EMPHASIS_SHIFT 22
4098 /* How many wires to use. I guess 3 was too hard */
4099 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
4100 #define DP_PORT_WIDTH_MASK (7 << 19)
4102 /* Mystic DPCD version 1.1 special mode */
4103 #define DP_ENHANCED_FRAMING (1 << 18)
4106 #define DP_PLL_FREQ_270MHZ (0 << 16)
4107 #define DP_PLL_FREQ_160MHZ (1 << 16)
4108 #define DP_PLL_FREQ_MASK (3 << 16)
4110 /* locked once port is enabled */
4111 #define DP_PORT_REVERSAL (1 << 15)
4114 #define DP_PLL_ENABLE (1 << 14)
4116 /* sends the clock on lane 15 of the PEG for debug */
4117 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4119 #define DP_SCRAMBLING_DISABLE (1 << 12)
4120 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
4122 /* limit RGB values to avoid confusing TVs */
4123 #define DP_COLOR_RANGE_16_235 (1 << 8)
4125 /* Turn on the audio link */
4126 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4128 /* vs and hs sync polarity */
4129 #define DP_SYNC_VS_HIGH (1 << 4)
4130 #define DP_SYNC_HS_HIGH (1 << 3)
4133 #define DP_DETECTED (1 << 2)
4135 /* The aux channel provides a way to talk to the
4136 * signal sink for DDC etc. Max packet size supported
4137 * is 20 bytes in each direction, hence the 5 fixed
4140 #define DPA_AUX_CH_CTL 0x64010
4141 #define DPA_AUX_CH_DATA1 0x64014
4142 #define DPA_AUX_CH_DATA2 0x64018
4143 #define DPA_AUX_CH_DATA3 0x6401c
4144 #define DPA_AUX_CH_DATA4 0x64020
4145 #define DPA_AUX_CH_DATA5 0x64024
4147 #define DPB_AUX_CH_CTL 0x64110
4148 #define DPB_AUX_CH_DATA1 0x64114
4149 #define DPB_AUX_CH_DATA2 0x64118
4150 #define DPB_AUX_CH_DATA3 0x6411c
4151 #define DPB_AUX_CH_DATA4 0x64120
4152 #define DPB_AUX_CH_DATA5 0x64124
4154 #define DPC_AUX_CH_CTL 0x64210
4155 #define DPC_AUX_CH_DATA1 0x64214
4156 #define DPC_AUX_CH_DATA2 0x64218
4157 #define DPC_AUX_CH_DATA3 0x6421c
4158 #define DPC_AUX_CH_DATA4 0x64220
4159 #define DPC_AUX_CH_DATA5 0x64224
4161 #define DPD_AUX_CH_CTL 0x64310
4162 #define DPD_AUX_CH_DATA1 0x64314
4163 #define DPD_AUX_CH_DATA2 0x64318
4164 #define DPD_AUX_CH_DATA3 0x6431c
4165 #define DPD_AUX_CH_DATA4 0x64320
4166 #define DPD_AUX_CH_DATA5 0x64324
4168 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4169 #define DP_AUX_CH_CTL_DONE (1 << 30)
4170 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4171 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4172 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4173 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4174 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4175 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4176 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4177 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4178 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4179 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4180 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4181 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4182 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4183 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4184 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4185 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4186 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4187 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4188 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
4189 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4190 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4191 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
4192 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
4193 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
4194 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
4197 * Computing GMCH M and N values for the Display Port link
4199 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4201 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4203 * The GMCH value is used internally
4205 * bytes_per_pixel is the number of bytes coming out of the plane,
4206 * which is after the LUTs, so we want the bytes for our color format.
4207 * For our current usage, this is always 3, one byte for R, G and B.
4209 #define _PIPEA_DATA_M_G4X 0x70050
4210 #define _PIPEB_DATA_M_G4X 0x71050
4212 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
4213 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
4214 #define TU_SIZE_SHIFT 25
4215 #define TU_SIZE_MASK (0x3f << 25)
4217 #define DATA_LINK_M_N_MASK (0xffffff)
4218 #define DATA_LINK_N_MAX (0x800000)
4220 #define _PIPEA_DATA_N_G4X 0x70054
4221 #define _PIPEB_DATA_N_G4X 0x71054
4222 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
4225 * Computing Link M and N values for the Display Port link
4227 * Link M / N = pixel_clock / ls_clk
4229 * (the DP spec calls pixel_clock the 'strm_clk')
4231 * The Link value is transmitted in the Main Stream
4232 * Attributes and VB-ID.
4235 #define _PIPEA_LINK_M_G4X 0x70060
4236 #define _PIPEB_LINK_M_G4X 0x71060
4237 #define PIPEA_DP_LINK_M_MASK (0xffffff)
4239 #define _PIPEA_LINK_N_G4X 0x70064
4240 #define _PIPEB_LINK_N_G4X 0x71064
4241 #define PIPEA_DP_LINK_N_MASK (0xffffff)
4243 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4244 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4245 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4246 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4248 /* Display & cursor control */
4251 #define _PIPEADSL 0x70000
4252 #define DSL_LINEMASK_GEN2 0x00000fff
4253 #define DSL_LINEMASK_GEN3 0x00001fff
4254 #define _PIPEACONF 0x70008
4255 #define PIPECONF_ENABLE (1<<31)
4256 #define PIPECONF_DISABLE 0
4257 #define PIPECONF_DOUBLE_WIDE (1<<30)
4258 #define I965_PIPECONF_ACTIVE (1<<30)
4259 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
4260 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
4261 #define PIPECONF_SINGLE_WIDE 0
4262 #define PIPECONF_PIPE_UNLOCKED 0
4263 #define PIPECONF_PIPE_LOCKED (1<<25)
4264 #define PIPECONF_PALETTE 0
4265 #define PIPECONF_GAMMA (1<<24)
4266 #define PIPECONF_FORCE_BORDER (1<<25)
4267 #define PIPECONF_INTERLACE_MASK (7 << 21)
4268 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
4269 /* Note that pre-gen3 does not support interlaced display directly. Panel
4270 * fitting must be disabled on pre-ilk for interlaced. */
4271 #define PIPECONF_PROGRESSIVE (0 << 21)
4272 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4273 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4274 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4275 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4276 /* Ironlake and later have a complete new set of values for interlaced. PFIT
4277 * means panel fitter required, PF means progressive fetch, DBL means power
4278 * saving pixel doubling. */
4279 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4280 #define PIPECONF_INTERLACED_ILK (3 << 21)
4281 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4282 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
4283 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
4284 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
4285 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
4286 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
4287 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
4288 #define PIPECONF_BPC_MASK (0x7 << 5)
4289 #define PIPECONF_8BPC (0<<5)
4290 #define PIPECONF_10BPC (1<<5)
4291 #define PIPECONF_6BPC (2<<5)
4292 #define PIPECONF_12BPC (3<<5)
4293 #define PIPECONF_DITHER_EN (1<<4)
4294 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4295 #define PIPECONF_DITHER_TYPE_SP (0<<2)
4296 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4297 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4298 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
4299 #define _PIPEASTAT 0x70024
4300 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
4301 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
4302 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4303 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
4304 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
4305 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
4306 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
4307 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4308 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4309 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4310 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
4311 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
4312 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4313 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4314 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
4315 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
4316 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
4317 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4318 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
4319 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
4320 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
4321 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
4322 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
4323 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4324 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
4325 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4326 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
4327 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
4328 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
4329 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
4330 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4331 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4332 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4333 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
4334 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
4335 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
4336 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4337 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
4338 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
4339 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
4340 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4341 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
4342 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
4343 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
4344 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
4345 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4347 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4348 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4350 #define PIPE_A_OFFSET 0x70000
4351 #define PIPE_B_OFFSET 0x71000
4352 #define PIPE_C_OFFSET 0x72000
4353 #define CHV_PIPE_C_OFFSET 0x74000
4355 * There's actually no pipe EDP. Some pipe registers have
4356 * simply shifted from the pipe to the transcoder, while
4357 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4358 * to access such registers in transcoder EDP.
4360 #define PIPE_EDP_OFFSET 0x7f000
4362 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4363 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4364 dev_priv->info.display_mmio_offset)
4366 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
4367 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
4368 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
4369 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
4370 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
4372 #define _PIPE_MISC_A 0x70030
4373 #define _PIPE_MISC_B 0x71030
4374 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
4375 #define PIPEMISC_DITHER_8_BPC (0<<5)
4376 #define PIPEMISC_DITHER_10_BPC (1<<5)
4377 #define PIPEMISC_DITHER_6_BPC (2<<5)
4378 #define PIPEMISC_DITHER_12_BPC (3<<5)
4379 #define PIPEMISC_DITHER_ENABLE (1<<4)
4380 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4381 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
4382 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
4384 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
4385 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
4386 #define PIPEB_HLINE_INT_EN (1<<28)
4387 #define PIPEB_VBLANK_INT_EN (1<<27)
4388 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
4389 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4390 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
4391 #define PIPE_PSR_INT_EN (1<<22)
4392 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
4393 #define PIPEA_HLINE_INT_EN (1<<20)
4394 #define PIPEA_VBLANK_INT_EN (1<<19)
4395 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4396 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
4397 #define PLANEA_FLIPDONE_INT_EN (1<<16)
4398 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4399 #define PIPEC_HLINE_INT_EN (1<<12)
4400 #define PIPEC_VBLANK_INT_EN (1<<11)
4401 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
4402 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
4403 #define PLANEC_FLIPDONE_INT_EN (1<<8)
4405 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4406 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4407 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4408 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
4409 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
4410 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
4411 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
4412 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
4413 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4414 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
4415 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4416 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4417 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
4418 #define DPINVGTT_EN_MASK 0xff0000
4419 #define DPINVGTT_EN_MASK_CHV 0xfff0000
4420 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
4421 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
4422 #define PLANEC_INVALID_GTT_STATUS (1<<9)
4423 #define CURSORC_INVALID_GTT_STATUS (1<<8)
4424 #define CURSORB_INVALID_GTT_STATUS (1<<7)
4425 #define CURSORA_INVALID_GTT_STATUS (1<<6)
4426 #define SPRITED_INVALID_GTT_STATUS (1<<5)
4427 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
4428 #define PLANEB_INVALID_GTT_STATUS (1<<3)
4429 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
4430 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
4431 #define PLANEA_INVALID_GTT_STATUS (1<<0)
4432 #define DPINVGTT_STATUS_MASK 0xff
4433 #define DPINVGTT_STATUS_MASK_CHV 0xfff
4435 #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
4436 #define DSPARB_CSTART_MASK (0x7f << 7)
4437 #define DSPARB_CSTART_SHIFT 7
4438 #define DSPARB_BSTART_MASK (0x7f)
4439 #define DSPARB_BSTART_SHIFT 0
4440 #define DSPARB_BEND_SHIFT 9 /* on 855 */
4441 #define DSPARB_AEND_SHIFT 0
4442 #define DSPARB_SPRITEA_SHIFT_VLV 0
4443 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4444 #define DSPARB_SPRITEB_SHIFT_VLV 8
4445 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4446 #define DSPARB_SPRITEC_SHIFT_VLV 16
4447 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4448 #define DSPARB_SPRITED_SHIFT_VLV 24
4449 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
4450 #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4451 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4452 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4453 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4454 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4455 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4456 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4457 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
4458 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4459 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4460 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4461 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4462 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
4463 #define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */
4464 #define DSPARB_SPRITEE_SHIFT_VLV 0
4465 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4466 #define DSPARB_SPRITEF_SHIFT_VLV 8
4467 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
4469 /* pnv/gen4/g4x/vlv/chv */
4470 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
4471 #define DSPFW_SR_SHIFT 23
4472 #define DSPFW_SR_MASK (0x1ff<<23)
4473 #define DSPFW_CURSORB_SHIFT 16
4474 #define DSPFW_CURSORB_MASK (0x3f<<16)
4475 #define DSPFW_PLANEB_SHIFT 8
4476 #define DSPFW_PLANEB_MASK (0x7f<<8)
4477 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4478 #define DSPFW_PLANEA_SHIFT 0
4479 #define DSPFW_PLANEA_MASK (0x7f<<0)
4480 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4481 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
4482 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4483 #define DSPFW_FBC_SR_SHIFT 28
4484 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4485 #define DSPFW_FBC_HPLL_SR_SHIFT 24
4486 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4487 #define DSPFW_SPRITEB_SHIFT (16)
4488 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4489 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4490 #define DSPFW_CURSORA_SHIFT 8
4491 #define DSPFW_CURSORA_MASK (0x3f<<8)
4492 #define DSPFW_PLANEC_OLD_SHIFT 0
4493 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
4494 #define DSPFW_SPRITEA_SHIFT 0
4495 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4496 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4497 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
4498 #define DSPFW_HPLL_SR_EN (1<<31)
4499 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
4500 #define DSPFW_CURSOR_SR_SHIFT 24
4501 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4502 #define DSPFW_HPLL_CURSOR_SHIFT 16
4503 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
4504 #define DSPFW_HPLL_SR_SHIFT 0
4505 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4508 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
4509 #define DSPFW_SPRITEB_WM1_SHIFT 16
4510 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4511 #define DSPFW_CURSORA_WM1_SHIFT 8
4512 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4513 #define DSPFW_SPRITEA_WM1_SHIFT 0
4514 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4515 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
4516 #define DSPFW_PLANEB_WM1_SHIFT 24
4517 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4518 #define DSPFW_PLANEA_WM1_SHIFT 16
4519 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4520 #define DSPFW_CURSORB_WM1_SHIFT 8
4521 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4522 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
4523 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4524 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
4525 #define DSPFW_SR_WM1_SHIFT 0
4526 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
4527 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
4528 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4529 #define DSPFW_SPRITED_WM1_SHIFT 24
4530 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4531 #define DSPFW_SPRITED_SHIFT 16
4532 #define DSPFW_SPRITED_MASK_VLV (0xff<<16)
4533 #define DSPFW_SPRITEC_WM1_SHIFT 8
4534 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4535 #define DSPFW_SPRITEC_SHIFT 0
4536 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
4537 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
4538 #define DSPFW_SPRITEF_WM1_SHIFT 24
4539 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4540 #define DSPFW_SPRITEF_SHIFT 16
4541 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
4542 #define DSPFW_SPRITEE_WM1_SHIFT 8
4543 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4544 #define DSPFW_SPRITEE_SHIFT 0
4545 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
4546 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4547 #define DSPFW_PLANEC_WM1_SHIFT 24
4548 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4549 #define DSPFW_PLANEC_SHIFT 16
4550 #define DSPFW_PLANEC_MASK_VLV (0xff<<16)
4551 #define DSPFW_CURSORC_WM1_SHIFT 8
4552 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4553 #define DSPFW_CURSORC_SHIFT 0
4554 #define DSPFW_CURSORC_MASK (0x3f<<0)
4556 /* vlv/chv high order bits */
4557 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
4558 #define DSPFW_SR_HI_SHIFT 24
4559 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4560 #define DSPFW_SPRITEF_HI_SHIFT 23
4561 #define DSPFW_SPRITEF_HI_MASK (1<<23)
4562 #define DSPFW_SPRITEE_HI_SHIFT 22
4563 #define DSPFW_SPRITEE_HI_MASK (1<<22)
4564 #define DSPFW_PLANEC_HI_SHIFT 21
4565 #define DSPFW_PLANEC_HI_MASK (1<<21)
4566 #define DSPFW_SPRITED_HI_SHIFT 20
4567 #define DSPFW_SPRITED_HI_MASK (1<<20)
4568 #define DSPFW_SPRITEC_HI_SHIFT 16
4569 #define DSPFW_SPRITEC_HI_MASK (1<<16)
4570 #define DSPFW_PLANEB_HI_SHIFT 12
4571 #define DSPFW_PLANEB_HI_MASK (1<<12)
4572 #define DSPFW_SPRITEB_HI_SHIFT 8
4573 #define DSPFW_SPRITEB_HI_MASK (1<<8)
4574 #define DSPFW_SPRITEA_HI_SHIFT 4
4575 #define DSPFW_SPRITEA_HI_MASK (1<<4)
4576 #define DSPFW_PLANEA_HI_SHIFT 0
4577 #define DSPFW_PLANEA_HI_MASK (1<<0)
4578 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
4579 #define DSPFW_SR_WM1_HI_SHIFT 24
4580 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4581 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4582 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4583 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4584 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4585 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
4586 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4587 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
4588 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4589 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4590 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4591 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
4592 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4593 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4594 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4595 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4596 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4597 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
4598 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4600 /* drain latency register values*/
4601 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4602 #define DDL_CURSOR_SHIFT 24
4603 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4604 #define DDL_PLANE_SHIFT 0
4605 #define DDL_PRECISION_HIGH (1<<7)
4606 #define DDL_PRECISION_LOW (0<<7)
4607 #define DRAIN_LATENCY_MASK 0x7f
4609 #define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
4610 #define CBR_PND_DEADLINE_DISABLE (1<<31)
4612 /* FIFO watermark sizes etc */
4613 #define G4X_FIFO_LINE_SIZE 64
4614 #define I915_FIFO_LINE_SIZE 64
4615 #define I830_FIFO_LINE_SIZE 32
4617 #define VALLEYVIEW_FIFO_SIZE 255
4618 #define G4X_FIFO_SIZE 127
4619 #define I965_FIFO_SIZE 512
4620 #define I945_FIFO_SIZE 127
4621 #define I915_FIFO_SIZE 95
4622 #define I855GM_FIFO_SIZE 127 /* In cachelines */
4623 #define I830_FIFO_SIZE 95
4625 #define VALLEYVIEW_MAX_WM 0xff
4626 #define G4X_MAX_WM 0x3f
4627 #define I915_MAX_WM 0x3f
4629 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4630 #define PINEVIEW_FIFO_LINE_SIZE 64
4631 #define PINEVIEW_MAX_WM 0x1ff
4632 #define PINEVIEW_DFT_WM 0x3f
4633 #define PINEVIEW_DFT_HPLLOFF_WM 0
4634 #define PINEVIEW_GUARD_WM 10
4635 #define PINEVIEW_CURSOR_FIFO 64
4636 #define PINEVIEW_CURSOR_MAX_WM 0x3f
4637 #define PINEVIEW_CURSOR_DFT_WM 0
4638 #define PINEVIEW_CURSOR_GUARD_WM 5
4640 #define VALLEYVIEW_CURSOR_MAX_WM 64
4641 #define I965_CURSOR_FIFO 64
4642 #define I965_CURSOR_MAX_WM 32
4643 #define I965_CURSOR_DFT_WM 8
4645 /* Watermark register definitions for SKL */
4646 #define CUR_WM_A_0 0x70140
4647 #define CUR_WM_B_0 0x71140
4648 #define PLANE_WM_1_A_0 0x70240
4649 #define PLANE_WM_1_B_0 0x71240
4650 #define PLANE_WM_2_A_0 0x70340
4651 #define PLANE_WM_2_B_0 0x71340
4652 #define PLANE_WM_TRANS_1_A_0 0x70268
4653 #define PLANE_WM_TRANS_1_B_0 0x71268
4654 #define PLANE_WM_TRANS_2_A_0 0x70368
4655 #define PLANE_WM_TRANS_2_B_0 0x71368
4656 #define CUR_WM_TRANS_A_0 0x70168
4657 #define CUR_WM_TRANS_B_0 0x71168
4658 #define PLANE_WM_EN (1 << 31)
4659 #define PLANE_WM_LINES_SHIFT 14
4660 #define PLANE_WM_LINES_MASK 0x1f
4661 #define PLANE_WM_BLOCKS_MASK 0x3ff
4663 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0)
4664 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level)))
4665 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0)
4667 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0)
4668 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0)
4669 #define _PLANE_WM_BASE(pipe, plane) \
4670 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4671 #define PLANE_WM(pipe, plane, level) \
4672 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4673 #define _PLANE_WM_TRANS_1(pipe) \
4674 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0)
4675 #define _PLANE_WM_TRANS_2(pipe) \
4676 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0)
4677 #define PLANE_WM_TRANS(pipe, plane) \
4678 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))
4680 /* define the Watermark register on Ironlake */
4681 #define WM0_PIPEA_ILK 0x45100
4682 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
4683 #define WM0_PIPE_PLANE_SHIFT 16
4684 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
4685 #define WM0_PIPE_SPRITE_SHIFT 8
4686 #define WM0_PIPE_CURSOR_MASK (0xff)
4688 #define WM0_PIPEB_ILK 0x45104
4689 #define WM0_PIPEC_IVB 0x45200
4690 #define WM1_LP_ILK 0x45108
4691 #define WM1_LP_SR_EN (1<<31)
4692 #define WM1_LP_LATENCY_SHIFT 24
4693 #define WM1_LP_LATENCY_MASK (0x7f<<24)
4694 #define WM1_LP_FBC_MASK (0xf<<20)
4695 #define WM1_LP_FBC_SHIFT 20
4696 #define WM1_LP_FBC_SHIFT_BDW 19
4697 #define WM1_LP_SR_MASK (0x7ff<<8)
4698 #define WM1_LP_SR_SHIFT 8
4699 #define WM1_LP_CURSOR_MASK (0xff)
4700 #define WM2_LP_ILK 0x4510c
4701 #define WM2_LP_EN (1<<31)
4702 #define WM3_LP_ILK 0x45110
4703 #define WM3_LP_EN (1<<31)
4704 #define WM1S_LP_ILK 0x45120
4705 #define WM2S_LP_IVB 0x45124
4706 #define WM3S_LP_IVB 0x45128
4707 #define WM1S_LP_EN (1<<31)
4709 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4710 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4711 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4713 /* Memory latency timer register */
4714 #define MLTR_ILK 0x11222
4715 #define MLTR_WM1_SHIFT 0
4716 #define MLTR_WM2_SHIFT 8
4717 /* the unit of memory self-refresh latency time is 0.5us */
4718 #define ILK_SRLT_MASK 0x3f
4721 /* the address where we get all kinds of latency value */
4722 #define SSKPD 0x5d10
4723 #define SSKPD_WM_MASK 0x3f
4724 #define SSKPD_WM0_SHIFT 0
4725 #define SSKPD_WM1_SHIFT 8
4726 #define SSKPD_WM2_SHIFT 16
4727 #define SSKPD_WM3_SHIFT 24
4730 * The two pipe frame counter registers are not synchronized, so
4731 * reading a stable value is somewhat tricky. The following code
4735 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4736 * PIPE_FRAME_HIGH_SHIFT;
4737 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4738 * PIPE_FRAME_LOW_SHIFT);
4739 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4740 * PIPE_FRAME_HIGH_SHIFT);
4741 * } while (high1 != high2);
4742 * frame = (high1 << 8) | low1;
4744 #define _PIPEAFRAMEHIGH 0x70040
4745 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4746 #define PIPE_FRAME_HIGH_SHIFT 0
4747 #define _PIPEAFRAMEPIXEL 0x70044
4748 #define PIPE_FRAME_LOW_MASK 0xff000000
4749 #define PIPE_FRAME_LOW_SHIFT 24
4750 #define PIPE_PIXEL_MASK 0x00ffffff
4751 #define PIPE_PIXEL_SHIFT 0
4752 /* GM45+ just has to be different */
4753 #define _PIPEA_FRMCOUNT_GM45 0x70040
4754 #define _PIPEA_FLIPCOUNT_GM45 0x70044
4755 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
4756 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
4758 /* Cursor A & B regs */
4759 #define _CURACNTR 0x70080
4760 /* Old style CUR*CNTR flags (desktop 8xx) */
4761 #define CURSOR_ENABLE 0x80000000
4762 #define CURSOR_GAMMA_ENABLE 0x40000000
4763 #define CURSOR_STRIDE_SHIFT 28
4764 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4765 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
4766 #define CURSOR_FORMAT_SHIFT 24
4767 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4768 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4769 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4770 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4771 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4772 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4773 /* New style CUR*CNTR flags */
4774 #define CURSOR_MODE 0x27
4775 #define CURSOR_MODE_DISABLE 0x00
4776 #define CURSOR_MODE_128_32B_AX 0x02
4777 #define CURSOR_MODE_256_32B_AX 0x03
4778 #define CURSOR_MODE_64_32B_AX 0x07
4779 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4780 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4781 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4782 #define MCURSOR_PIPE_SELECT (1 << 28)
4783 #define MCURSOR_PIPE_A 0x00
4784 #define MCURSOR_PIPE_B (1 << 28)
4785 #define MCURSOR_GAMMA_ENABLE (1 << 26)
4786 #define CURSOR_ROTATE_180 (1<<15)
4787 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4788 #define _CURABASE 0x70084
4789 #define _CURAPOS 0x70088
4790 #define CURSOR_POS_MASK 0x007FF
4791 #define CURSOR_POS_SIGN 0x8000
4792 #define CURSOR_X_SHIFT 0
4793 #define CURSOR_Y_SHIFT 16
4794 #define CURSIZE 0x700a0
4795 #define _CURBCNTR 0x700c0
4796 #define _CURBBASE 0x700c4
4797 #define _CURBPOS 0x700c8
4799 #define _CURBCNTR_IVB 0x71080
4800 #define _CURBBASE_IVB 0x71084
4801 #define _CURBPOS_IVB 0x71088
4803 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4804 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4805 dev_priv->info.display_mmio_offset)
4807 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4808 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4809 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4811 #define CURSOR_A_OFFSET 0x70080
4812 #define CURSOR_B_OFFSET 0x700c0
4813 #define CHV_CURSOR_C_OFFSET 0x700e0
4814 #define IVB_CURSOR_B_OFFSET 0x71080
4815 #define IVB_CURSOR_C_OFFSET 0x72080
4817 /* Display A control */
4818 #define _DSPACNTR 0x70180
4819 #define DISPLAY_PLANE_ENABLE (1<<31)
4820 #define DISPLAY_PLANE_DISABLE 0
4821 #define DISPPLANE_GAMMA_ENABLE (1<<30)
4822 #define DISPPLANE_GAMMA_DISABLE 0
4823 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
4824 #define DISPPLANE_YUV422 (0x0<<26)
4825 #define DISPPLANE_8BPP (0x2<<26)
4826 #define DISPPLANE_BGRA555 (0x3<<26)
4827 #define DISPPLANE_BGRX555 (0x4<<26)
4828 #define DISPPLANE_BGRX565 (0x5<<26)
4829 #define DISPPLANE_BGRX888 (0x6<<26)
4830 #define DISPPLANE_BGRA888 (0x7<<26)
4831 #define DISPPLANE_RGBX101010 (0x8<<26)
4832 #define DISPPLANE_RGBA101010 (0x9<<26)
4833 #define DISPPLANE_BGRX101010 (0xa<<26)
4834 #define DISPPLANE_RGBX161616 (0xc<<26)
4835 #define DISPPLANE_RGBX888 (0xe<<26)
4836 #define DISPPLANE_RGBA888 (0xf<<26)
4837 #define DISPPLANE_STEREO_ENABLE (1<<25)
4838 #define DISPPLANE_STEREO_DISABLE 0
4839 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
4840 #define DISPPLANE_SEL_PIPE_SHIFT 24
4841 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
4842 #define DISPPLANE_SEL_PIPE_A 0
4843 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
4844 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
4845 #define DISPPLANE_SRC_KEY_DISABLE 0
4846 #define DISPPLANE_LINE_DOUBLE (1<<20)
4847 #define DISPPLANE_NO_LINE_DOUBLE 0
4848 #define DISPPLANE_STEREO_POLARITY_FIRST 0
4849 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
4850 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
4851 #define DISPPLANE_ROTATE_180 (1<<15)
4852 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
4853 #define DISPPLANE_TILED (1<<10)
4854 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
4855 #define _DSPAADDR 0x70184
4856 #define _DSPASTRIDE 0x70188
4857 #define _DSPAPOS 0x7018C /* reserved */
4858 #define _DSPASIZE 0x70190
4859 #define _DSPASURF 0x7019C /* 965+ only */
4860 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4861 #define _DSPAOFFSET 0x701A4 /* HSW */
4862 #define _DSPASURFLIVE 0x701AC
4864 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
4865 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
4866 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
4867 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
4868 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
4869 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
4870 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
4871 #define DSPLINOFF(plane) DSPADDR(plane)
4872 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
4873 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
4875 /* CHV pipe B blender and primary plane */
4876 #define _CHV_BLEND_A 0x60a00
4877 #define CHV_BLEND_LEGACY (0<<30)
4878 #define CHV_BLEND_ANDROID (1<<30)
4879 #define CHV_BLEND_MPO (2<<30)
4880 #define CHV_BLEND_MASK (3<<30)
4881 #define _CHV_CANVAS_A 0x60a04
4882 #define _PRIMPOS_A 0x60a08
4883 #define _PRIMSIZE_A 0x60a0c
4884 #define _PRIMCNSTALPHA_A 0x60a10
4885 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
4887 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
4888 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
4889 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
4890 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
4891 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
4893 /* Display/Sprite base address macros */
4894 #define DISP_BASEADDR_MASK (0xfffff000)
4895 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
4896 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
4899 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4900 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4901 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4902 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4903 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4904 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4905 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4906 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4907 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4908 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4909 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4910 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4911 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
4914 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4915 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4916 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
4917 #define _PIPEBFRAMEHIGH 0x71040
4918 #define _PIPEBFRAMEPIXEL 0x71044
4919 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4920 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
4923 /* Display B control */
4924 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
4925 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
4926 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
4927 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
4928 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
4929 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4930 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4931 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4932 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4933 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4934 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4935 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4936 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
4938 /* Sprite A control */
4939 #define _DVSACNTR 0x72180
4940 #define DVS_ENABLE (1<<31)
4941 #define DVS_GAMMA_ENABLE (1<<30)
4942 #define DVS_PIXFORMAT_MASK (3<<25)
4943 #define DVS_FORMAT_YUV422 (0<<25)
4944 #define DVS_FORMAT_RGBX101010 (1<<25)
4945 #define DVS_FORMAT_RGBX888 (2<<25)
4946 #define DVS_FORMAT_RGBX161616 (3<<25)
4947 #define DVS_PIPE_CSC_ENABLE (1<<24)
4948 #define DVS_SOURCE_KEY (1<<22)
4949 #define DVS_RGB_ORDER_XBGR (1<<20)
4950 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
4951 #define DVS_YUV_ORDER_YUYV (0<<16)
4952 #define DVS_YUV_ORDER_UYVY (1<<16)
4953 #define DVS_YUV_ORDER_YVYU (2<<16)
4954 #define DVS_YUV_ORDER_VYUY (3<<16)
4955 #define DVS_ROTATE_180 (1<<15)
4956 #define DVS_DEST_KEY (1<<2)
4957 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
4958 #define DVS_TILED (1<<10)
4959 #define _DVSALINOFF 0x72184
4960 #define _DVSASTRIDE 0x72188
4961 #define _DVSAPOS 0x7218c
4962 #define _DVSASIZE 0x72190
4963 #define _DVSAKEYVAL 0x72194
4964 #define _DVSAKEYMSK 0x72198
4965 #define _DVSASURF 0x7219c
4966 #define _DVSAKEYMAXVAL 0x721a0
4967 #define _DVSATILEOFF 0x721a4
4968 #define _DVSASURFLIVE 0x721ac
4969 #define _DVSASCALE 0x72204
4970 #define DVS_SCALE_ENABLE (1<<31)
4971 #define DVS_FILTER_MASK (3<<29)
4972 #define DVS_FILTER_MEDIUM (0<<29)
4973 #define DVS_FILTER_ENHANCING (1<<29)
4974 #define DVS_FILTER_SOFTENING (2<<29)
4975 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
4976 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
4977 #define _DVSAGAMC 0x72300
4979 #define _DVSBCNTR 0x73180
4980 #define _DVSBLINOFF 0x73184
4981 #define _DVSBSTRIDE 0x73188
4982 #define _DVSBPOS 0x7318c
4983 #define _DVSBSIZE 0x73190
4984 #define _DVSBKEYVAL 0x73194
4985 #define _DVSBKEYMSK 0x73198
4986 #define _DVSBSURF 0x7319c
4987 #define _DVSBKEYMAXVAL 0x731a0
4988 #define _DVSBTILEOFF 0x731a4
4989 #define _DVSBSURFLIVE 0x731ac
4990 #define _DVSBSCALE 0x73204
4991 #define _DVSBGAMC 0x73300
4993 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4994 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4995 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4996 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
4997 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
4998 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4999 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5000 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5001 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5002 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5003 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5004 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5006 #define _SPRA_CTL 0x70280
5007 #define SPRITE_ENABLE (1<<31)
5008 #define SPRITE_GAMMA_ENABLE (1<<30)
5009 #define SPRITE_PIXFORMAT_MASK (7<<25)
5010 #define SPRITE_FORMAT_YUV422 (0<<25)
5011 #define SPRITE_FORMAT_RGBX101010 (1<<25)
5012 #define SPRITE_FORMAT_RGBX888 (2<<25)
5013 #define SPRITE_FORMAT_RGBX161616 (3<<25)
5014 #define SPRITE_FORMAT_YUV444 (4<<25)
5015 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
5016 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
5017 #define SPRITE_SOURCE_KEY (1<<22)
5018 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5019 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5020 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5021 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5022 #define SPRITE_YUV_ORDER_YUYV (0<<16)
5023 #define SPRITE_YUV_ORDER_UYVY (1<<16)
5024 #define SPRITE_YUV_ORDER_YVYU (2<<16)
5025 #define SPRITE_YUV_ORDER_VYUY (3<<16)
5026 #define SPRITE_ROTATE_180 (1<<15)
5027 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5028 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
5029 #define SPRITE_TILED (1<<10)
5030 #define SPRITE_DEST_KEY (1<<2)
5031 #define _SPRA_LINOFF 0x70284
5032 #define _SPRA_STRIDE 0x70288
5033 #define _SPRA_POS 0x7028c
5034 #define _SPRA_SIZE 0x70290
5035 #define _SPRA_KEYVAL 0x70294
5036 #define _SPRA_KEYMSK 0x70298
5037 #define _SPRA_SURF 0x7029c
5038 #define _SPRA_KEYMAX 0x702a0
5039 #define _SPRA_TILEOFF 0x702a4
5040 #define _SPRA_OFFSET 0x702a4
5041 #define _SPRA_SURFLIVE 0x702ac
5042 #define _SPRA_SCALE 0x70304
5043 #define SPRITE_SCALE_ENABLE (1<<31)
5044 #define SPRITE_FILTER_MASK (3<<29)
5045 #define SPRITE_FILTER_MEDIUM (0<<29)
5046 #define SPRITE_FILTER_ENHANCING (1<<29)
5047 #define SPRITE_FILTER_SOFTENING (2<<29)
5048 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5049 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5050 #define _SPRA_GAMC 0x70400
5052 #define _SPRB_CTL 0x71280
5053 #define _SPRB_LINOFF 0x71284
5054 #define _SPRB_STRIDE 0x71288
5055 #define _SPRB_POS 0x7128c
5056 #define _SPRB_SIZE 0x71290
5057 #define _SPRB_KEYVAL 0x71294
5058 #define _SPRB_KEYMSK 0x71298
5059 #define _SPRB_SURF 0x7129c
5060 #define _SPRB_KEYMAX 0x712a0
5061 #define _SPRB_TILEOFF 0x712a4
5062 #define _SPRB_OFFSET 0x712a4
5063 #define _SPRB_SURFLIVE 0x712ac
5064 #define _SPRB_SCALE 0x71304
5065 #define _SPRB_GAMC 0x71400
5067 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5068 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5069 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5070 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
5071 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5072 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5073 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5074 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5075 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5076 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5077 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5078 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5079 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5080 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5082 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5083 #define SP_ENABLE (1<<31)
5084 #define SP_GAMMA_ENABLE (1<<30)
5085 #define SP_PIXFORMAT_MASK (0xf<<26)
5086 #define SP_FORMAT_YUV422 (0<<26)
5087 #define SP_FORMAT_BGR565 (5<<26)
5088 #define SP_FORMAT_BGRX8888 (6<<26)
5089 #define SP_FORMAT_BGRA8888 (7<<26)
5090 #define SP_FORMAT_RGBX1010102 (8<<26)
5091 #define SP_FORMAT_RGBA1010102 (9<<26)
5092 #define SP_FORMAT_RGBX8888 (0xe<<26)
5093 #define SP_FORMAT_RGBA8888 (0xf<<26)
5094 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
5095 #define SP_SOURCE_KEY (1<<22)
5096 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
5097 #define SP_YUV_ORDER_YUYV (0<<16)
5098 #define SP_YUV_ORDER_UYVY (1<<16)
5099 #define SP_YUV_ORDER_YVYU (2<<16)
5100 #define SP_YUV_ORDER_VYUY (3<<16)
5101 #define SP_ROTATE_180 (1<<15)
5102 #define SP_TILED (1<<10)
5103 #define SP_MIRROR (1<<8) /* CHV pipe B */
5104 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5105 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5106 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5107 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5108 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5109 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5110 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5111 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5112 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5113 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
5114 #define SP_CONST_ALPHA_ENABLE (1<<31)
5115 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
5117 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5118 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5119 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5120 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5121 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5122 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5123 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5124 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5125 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5126 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5127 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5128 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5130 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
5131 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
5132 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
5133 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
5134 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
5135 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
5136 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
5137 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
5138 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5139 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
5140 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
5141 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
5144 * CHV pipe B sprite CSC
5146 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5147 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5148 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5150 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5151 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5152 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5153 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5154 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5156 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5157 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5158 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5159 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5160 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5161 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5162 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5164 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5165 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5166 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5167 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5168 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5170 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5171 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5172 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5173 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5174 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5176 /* Skylake plane registers */
5178 #define _PLANE_CTL_1_A 0x70180
5179 #define _PLANE_CTL_2_A 0x70280
5180 #define _PLANE_CTL_3_A 0x70380
5181 #define PLANE_CTL_ENABLE (1 << 31)
5182 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5183 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
5184 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5185 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5186 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5187 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5188 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5189 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5190 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5191 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5192 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
5193 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5194 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5195 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
5196 #define PLANE_CTL_ORDER_BGRX (0 << 20)
5197 #define PLANE_CTL_ORDER_RGBX (1 << 20)
5198 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5199 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5200 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5201 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5202 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5203 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5204 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5205 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5206 #define PLANE_CTL_TILED_MASK (0x7 << 10)
5207 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5208 #define PLANE_CTL_TILED_X ( 1 << 10)
5209 #define PLANE_CTL_TILED_Y ( 4 << 10)
5210 #define PLANE_CTL_TILED_YF ( 5 << 10)
5211 #define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5212 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5213 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5214 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
5215 #define PLANE_CTL_ROTATE_MASK 0x3
5216 #define PLANE_CTL_ROTATE_0 0x0
5217 #define PLANE_CTL_ROTATE_90 0x1
5218 #define PLANE_CTL_ROTATE_180 0x2
5219 #define PLANE_CTL_ROTATE_270 0x3
5220 #define _PLANE_STRIDE_1_A 0x70188
5221 #define _PLANE_STRIDE_2_A 0x70288
5222 #define _PLANE_STRIDE_3_A 0x70388
5223 #define _PLANE_POS_1_A 0x7018c
5224 #define _PLANE_POS_2_A 0x7028c
5225 #define _PLANE_POS_3_A 0x7038c
5226 #define _PLANE_SIZE_1_A 0x70190
5227 #define _PLANE_SIZE_2_A 0x70290
5228 #define _PLANE_SIZE_3_A 0x70390
5229 #define _PLANE_SURF_1_A 0x7019c
5230 #define _PLANE_SURF_2_A 0x7029c
5231 #define _PLANE_SURF_3_A 0x7039c
5232 #define _PLANE_OFFSET_1_A 0x701a4
5233 #define _PLANE_OFFSET_2_A 0x702a4
5234 #define _PLANE_OFFSET_3_A 0x703a4
5235 #define _PLANE_KEYVAL_1_A 0x70194
5236 #define _PLANE_KEYVAL_2_A 0x70294
5237 #define _PLANE_KEYMSK_1_A 0x70198
5238 #define _PLANE_KEYMSK_2_A 0x70298
5239 #define _PLANE_KEYMAX_1_A 0x701a0
5240 #define _PLANE_KEYMAX_2_A 0x702a0
5241 #define _PLANE_BUF_CFG_1_A 0x7027c
5242 #define _PLANE_BUF_CFG_2_A 0x7037c
5243 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
5244 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
5246 #define _PLANE_CTL_1_B 0x71180
5247 #define _PLANE_CTL_2_B 0x71280
5248 #define _PLANE_CTL_3_B 0x71380
5249 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5250 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5251 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5252 #define PLANE_CTL(pipe, plane) \
5253 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5255 #define _PLANE_STRIDE_1_B 0x71188
5256 #define _PLANE_STRIDE_2_B 0x71288
5257 #define _PLANE_STRIDE_3_B 0x71388
5258 #define _PLANE_STRIDE_1(pipe) \
5259 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5260 #define _PLANE_STRIDE_2(pipe) \
5261 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5262 #define _PLANE_STRIDE_3(pipe) \
5263 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5264 #define PLANE_STRIDE(pipe, plane) \
5265 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5267 #define _PLANE_POS_1_B 0x7118c
5268 #define _PLANE_POS_2_B 0x7128c
5269 #define _PLANE_POS_3_B 0x7138c
5270 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5271 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5272 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5273 #define PLANE_POS(pipe, plane) \
5274 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5276 #define _PLANE_SIZE_1_B 0x71190
5277 #define _PLANE_SIZE_2_B 0x71290
5278 #define _PLANE_SIZE_3_B 0x71390
5279 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5280 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5281 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5282 #define PLANE_SIZE(pipe, plane) \
5283 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5285 #define _PLANE_SURF_1_B 0x7119c
5286 #define _PLANE_SURF_2_B 0x7129c
5287 #define _PLANE_SURF_3_B 0x7139c
5288 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5289 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5290 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5291 #define PLANE_SURF(pipe, plane) \
5292 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5294 #define _PLANE_OFFSET_1_B 0x711a4
5295 #define _PLANE_OFFSET_2_B 0x712a4
5296 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5297 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5298 #define PLANE_OFFSET(pipe, plane) \
5299 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5301 #define _PLANE_KEYVAL_1_B 0x71194
5302 #define _PLANE_KEYVAL_2_B 0x71294
5303 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5304 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5305 #define PLANE_KEYVAL(pipe, plane) \
5306 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5308 #define _PLANE_KEYMSK_1_B 0x71198
5309 #define _PLANE_KEYMSK_2_B 0x71298
5310 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5311 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5312 #define PLANE_KEYMSK(pipe, plane) \
5313 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5315 #define _PLANE_KEYMAX_1_B 0x711a0
5316 #define _PLANE_KEYMAX_2_B 0x712a0
5317 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5318 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5319 #define PLANE_KEYMAX(pipe, plane) \
5320 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5322 #define _PLANE_BUF_CFG_1_B 0x7127c
5323 #define _PLANE_BUF_CFG_2_B 0x7137c
5324 #define _PLANE_BUF_CFG_1(pipe) \
5325 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5326 #define _PLANE_BUF_CFG_2(pipe) \
5327 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5328 #define PLANE_BUF_CFG(pipe, plane) \
5329 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5331 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
5332 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
5333 #define _PLANE_NV12_BUF_CFG_1(pipe) \
5334 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5335 #define _PLANE_NV12_BUF_CFG_2(pipe) \
5336 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5337 #define PLANE_NV12_BUF_CFG(pipe, plane) \
5338 _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5340 /* SKL new cursor registers */
5341 #define _CUR_BUF_CFG_A 0x7017c
5342 #define _CUR_BUF_CFG_B 0x7117c
5343 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5346 #define VGACNTRL 0x71400
5347 # define VGA_DISP_DISABLE (1 << 31)
5348 # define VGA_2X_MODE (1 << 30)
5349 # define VGA_PIPE_B_SELECT (1 << 29)
5351 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
5355 #define CPU_VGACNTRL 0x41000
5357 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
5358 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5359 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
5360 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
5361 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
5362 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
5363 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
5364 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
5365 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
5367 /* refresh rate hardware control */
5368 #define RR_HW_CTL 0x45300
5369 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5370 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5372 #define FDI_PLL_BIOS_0 0x46000
5373 #define FDI_PLL_FB_CLOCK_MASK 0xff
5374 #define FDI_PLL_BIOS_1 0x46004
5375 #define FDI_PLL_BIOS_2 0x46008
5376 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
5377 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
5378 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
5380 #define PCH_3DCGDIS0 0x46020
5381 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5382 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5384 #define PCH_3DCGDIS1 0x46024
5385 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5387 #define FDI_PLL_FREQ_CTL 0x46030
5388 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5389 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5390 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5393 #define _PIPEA_DATA_M1 0x60030
5394 #define PIPE_DATA_M1_OFFSET 0
5395 #define _PIPEA_DATA_N1 0x60034
5396 #define PIPE_DATA_N1_OFFSET 0
5398 #define _PIPEA_DATA_M2 0x60038
5399 #define PIPE_DATA_M2_OFFSET 0
5400 #define _PIPEA_DATA_N2 0x6003c
5401 #define PIPE_DATA_N2_OFFSET 0
5403 #define _PIPEA_LINK_M1 0x60040
5404 #define PIPE_LINK_M1_OFFSET 0
5405 #define _PIPEA_LINK_N1 0x60044
5406 #define PIPE_LINK_N1_OFFSET 0
5408 #define _PIPEA_LINK_M2 0x60048
5409 #define PIPE_LINK_M2_OFFSET 0
5410 #define _PIPEA_LINK_N2 0x6004c
5411 #define PIPE_LINK_N2_OFFSET 0
5413 /* PIPEB timing regs are same start from 0x61000 */
5415 #define _PIPEB_DATA_M1 0x61030
5416 #define _PIPEB_DATA_N1 0x61034
5417 #define _PIPEB_DATA_M2 0x61038
5418 #define _PIPEB_DATA_N2 0x6103c
5419 #define _PIPEB_LINK_M1 0x61040
5420 #define _PIPEB_LINK_N1 0x61044
5421 #define _PIPEB_LINK_M2 0x61048
5422 #define _PIPEB_LINK_N2 0x6104c
5424 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
5425 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
5426 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
5427 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
5428 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
5429 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
5430 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
5431 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
5433 /* CPU panel fitter */
5434 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5435 #define _PFA_CTL_1 0x68080
5436 #define _PFB_CTL_1 0x68880
5437 #define PF_ENABLE (1<<31)
5438 #define PF_PIPE_SEL_MASK_IVB (3<<29)
5439 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
5440 #define PF_FILTER_MASK (3<<23)
5441 #define PF_FILTER_PROGRAMMED (0<<23)
5442 #define PF_FILTER_MED_3x3 (1<<23)
5443 #define PF_FILTER_EDGE_ENHANCE (2<<23)
5444 #define PF_FILTER_EDGE_SOFTEN (3<<23)
5445 #define _PFA_WIN_SZ 0x68074
5446 #define _PFB_WIN_SZ 0x68874
5447 #define _PFA_WIN_POS 0x68070
5448 #define _PFB_WIN_POS 0x68870
5449 #define _PFA_VSCALE 0x68084
5450 #define _PFB_VSCALE 0x68884
5451 #define _PFA_HSCALE 0x68090
5452 #define _PFB_HSCALE 0x68890
5454 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5455 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5456 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5457 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5458 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5460 #define _PSA_CTL 0x68180
5461 #define _PSB_CTL 0x68980
5462 #define PS_ENABLE (1<<31)
5463 #define _PSA_WIN_SZ 0x68174
5464 #define _PSB_WIN_SZ 0x68974
5465 #define _PSA_WIN_POS 0x68170
5466 #define _PSB_WIN_POS 0x68970
5468 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
5469 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5470 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5475 #define _PS_1A_CTRL 0x68180
5476 #define _PS_2A_CTRL 0x68280
5477 #define _PS_1B_CTRL 0x68980
5478 #define _PS_2B_CTRL 0x68A80
5479 #define _PS_1C_CTRL 0x69180
5480 #define PS_SCALER_EN (1 << 31)
5481 #define PS_SCALER_MODE_MASK (3 << 28)
5482 #define PS_SCALER_MODE_DYN (0 << 28)
5483 #define PS_SCALER_MODE_HQ (1 << 28)
5484 #define PS_PLANE_SEL_MASK (7 << 25)
5485 #define PS_PLANE_SEL(plane) ((plane + 1) << 25)
5486 #define PS_FILTER_MASK (3 << 23)
5487 #define PS_FILTER_MEDIUM (0 << 23)
5488 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5489 #define PS_FILTER_BILINEAR (3 << 23)
5490 #define PS_VERT3TAP (1 << 21)
5491 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5492 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5493 #define PS_PWRUP_PROGRESS (1 << 17)
5494 #define PS_V_FILTER_BYPASS (1 << 8)
5495 #define PS_VADAPT_EN (1 << 7)
5496 #define PS_VADAPT_MODE_MASK (3 << 5)
5497 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5498 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5499 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5501 #define _PS_PWR_GATE_1A 0x68160
5502 #define _PS_PWR_GATE_2A 0x68260
5503 #define _PS_PWR_GATE_1B 0x68960
5504 #define _PS_PWR_GATE_2B 0x68A60
5505 #define _PS_PWR_GATE_1C 0x69160
5506 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5507 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5508 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5509 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5510 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5511 #define PS_PWR_GATE_SLPEN_8 0
5512 #define PS_PWR_GATE_SLPEN_16 1
5513 #define PS_PWR_GATE_SLPEN_24 2
5514 #define PS_PWR_GATE_SLPEN_32 3
5516 #define _PS_WIN_POS_1A 0x68170
5517 #define _PS_WIN_POS_2A 0x68270
5518 #define _PS_WIN_POS_1B 0x68970
5519 #define _PS_WIN_POS_2B 0x68A70
5520 #define _PS_WIN_POS_1C 0x69170
5522 #define _PS_WIN_SZ_1A 0x68174
5523 #define _PS_WIN_SZ_2A 0x68274
5524 #define _PS_WIN_SZ_1B 0x68974
5525 #define _PS_WIN_SZ_2B 0x68A74
5526 #define _PS_WIN_SZ_1C 0x69174
5528 #define _PS_VSCALE_1A 0x68184
5529 #define _PS_VSCALE_2A 0x68284
5530 #define _PS_VSCALE_1B 0x68984
5531 #define _PS_VSCALE_2B 0x68A84
5532 #define _PS_VSCALE_1C 0x69184
5534 #define _PS_HSCALE_1A 0x68190
5535 #define _PS_HSCALE_2A 0x68290
5536 #define _PS_HSCALE_1B 0x68990
5537 #define _PS_HSCALE_2B 0x68A90
5538 #define _PS_HSCALE_1C 0x69190
5540 #define _PS_VPHASE_1A 0x68188
5541 #define _PS_VPHASE_2A 0x68288
5542 #define _PS_VPHASE_1B 0x68988
5543 #define _PS_VPHASE_2B 0x68A88
5544 #define _PS_VPHASE_1C 0x69188
5546 #define _PS_HPHASE_1A 0x68194
5547 #define _PS_HPHASE_2A 0x68294
5548 #define _PS_HPHASE_1B 0x68994
5549 #define _PS_HPHASE_2B 0x68A94
5550 #define _PS_HPHASE_1C 0x69194
5552 #define _PS_ECC_STAT_1A 0x681D0
5553 #define _PS_ECC_STAT_2A 0x682D0
5554 #define _PS_ECC_STAT_1B 0x689D0
5555 #define _PS_ECC_STAT_2B 0x68AD0
5556 #define _PS_ECC_STAT_1C 0x691D0
5558 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5559 #define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \
5560 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5561 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5562 #define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \
5563 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5564 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5565 #define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \
5566 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5567 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5568 #define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \
5569 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5570 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5571 #define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \
5572 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5573 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5574 #define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \
5575 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5576 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5577 #define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \
5578 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5579 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5580 #define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \
5581 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5582 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5583 #define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \
5584 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5585 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
5587 /* legacy palette */
5588 #define _LGC_PALETTE_A 0x4a000
5589 #define _LGC_PALETTE_B 0x4a800
5590 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
5592 #define _GAMMA_MODE_A 0x4a480
5593 #define _GAMMA_MODE_B 0x4ac80
5594 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5595 #define GAMMA_MODE_MODE_MASK (3 << 0)
5596 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5597 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5598 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5599 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
5602 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5603 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5604 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5605 #define DE_PLANEB_FLIP_DONE (1 << 27)
5606 #define DE_PLANEA_FLIP_DONE (1 << 26)
5607 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5608 #define DE_PCU_EVENT (1 << 25)
5609 #define DE_GTT_FAULT (1 << 24)
5610 #define DE_POISON (1 << 23)
5611 #define DE_PERFORM_COUNTER (1 << 22)
5612 #define DE_PCH_EVENT (1 << 21)
5613 #define DE_AUX_CHANNEL_A (1 << 20)
5614 #define DE_DP_A_HOTPLUG (1 << 19)
5615 #define DE_GSE (1 << 18)
5616 #define DE_PIPEB_VBLANK (1 << 15)
5617 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5618 #define DE_PIPEB_ODD_FIELD (1 << 13)
5619 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5620 #define DE_PIPEB_VSYNC (1 << 11)
5621 #define DE_PIPEB_CRC_DONE (1 << 10)
5622 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5623 #define DE_PIPEA_VBLANK (1 << 7)
5624 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
5625 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5626 #define DE_PIPEA_ODD_FIELD (1 << 5)
5627 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5628 #define DE_PIPEA_VSYNC (1 << 3)
5629 #define DE_PIPEA_CRC_DONE (1 << 2)
5630 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
5631 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5632 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
5634 /* More Ivybridge lolz */
5635 #define DE_ERR_INT_IVB (1<<30)
5636 #define DE_GSE_IVB (1<<29)
5637 #define DE_PCH_EVENT_IVB (1<<28)
5638 #define DE_DP_A_HOTPLUG_IVB (1<<27)
5639 #define DE_AUX_CHANNEL_A_IVB (1<<26)
5640 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5641 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5642 #define DE_PIPEC_VBLANK_IVB (1<<10)
5643 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
5644 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
5645 #define DE_PIPEB_VBLANK_IVB (1<<5)
5646 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5647 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
5648 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
5649 #define DE_PIPEA_VBLANK_IVB (1<<0)
5650 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
5652 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
5653 #define MASTER_INTERRUPT_ENABLE (1<<31)
5655 #define DEISR 0x44000
5656 #define DEIMR 0x44004
5657 #define DEIIR 0x44008
5658 #define DEIER 0x4400c
5660 #define GTISR 0x44010
5661 #define GTIMR 0x44014
5662 #define GTIIR 0x44018
5663 #define GTIER 0x4401c
5665 #define GEN8_MASTER_IRQ 0x44200
5666 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
5667 #define GEN8_PCU_IRQ (1<<30)
5668 #define GEN8_DE_PCH_IRQ (1<<23)
5669 #define GEN8_DE_MISC_IRQ (1<<22)
5670 #define GEN8_DE_PORT_IRQ (1<<20)
5671 #define GEN8_DE_PIPE_C_IRQ (1<<18)
5672 #define GEN8_DE_PIPE_B_IRQ (1<<17)
5673 #define GEN8_DE_PIPE_A_IRQ (1<<16)
5674 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
5675 #define GEN8_GT_VECS_IRQ (1<<6)
5676 #define GEN8_GT_PM_IRQ (1<<4)
5677 #define GEN8_GT_VCS2_IRQ (1<<3)
5678 #define GEN8_GT_VCS1_IRQ (1<<2)
5679 #define GEN8_GT_BCS_IRQ (1<<1)
5680 #define GEN8_GT_RCS_IRQ (1<<0)
5682 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
5683 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
5684 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
5685 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
5687 #define GEN8_BCS_IRQ_SHIFT 16
5688 #define GEN8_RCS_IRQ_SHIFT 0
5689 #define GEN8_VCS2_IRQ_SHIFT 16
5690 #define GEN8_VCS1_IRQ_SHIFT 0
5691 #define GEN8_VECS_IRQ_SHIFT 0
5693 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
5694 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
5695 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
5696 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
5697 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5698 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5699 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5700 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5701 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5702 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5703 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5704 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5705 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5706 #define GEN8_PIPE_VSYNC (1 << 1)
5707 #define GEN8_PIPE_VBLANK (1 << 0)
5708 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5709 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
5710 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5711 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5712 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5713 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
5714 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5715 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5716 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5717 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
5718 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5719 (GEN8_PIPE_CURSOR_FAULT | \
5720 GEN8_PIPE_SPRITE_FAULT | \
5721 GEN8_PIPE_PRIMARY_FAULT)
5722 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5723 (GEN9_PIPE_CURSOR_FAULT | \
5724 GEN9_PIPE_PLANE4_FAULT | \
5725 GEN9_PIPE_PLANE3_FAULT | \
5726 GEN9_PIPE_PLANE2_FAULT | \
5727 GEN9_PIPE_PLANE1_FAULT)
5729 #define GEN8_DE_PORT_ISR 0x44440
5730 #define GEN8_DE_PORT_IMR 0x44444
5731 #define GEN8_DE_PORT_IIR 0x44448
5732 #define GEN8_DE_PORT_IER 0x4444c
5733 #define GEN9_AUX_CHANNEL_D (1 << 27)
5734 #define GEN9_AUX_CHANNEL_C (1 << 26)
5735 #define GEN9_AUX_CHANNEL_B (1 << 25)
5736 #define BXT_DE_PORT_HP_DDIC (1 << 5)
5737 #define BXT_DE_PORT_HP_DDIB (1 << 4)
5738 #define BXT_DE_PORT_HP_DDIA (1 << 3)
5739 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
5740 BXT_DE_PORT_HP_DDIB | \
5741 BXT_DE_PORT_HP_DDIC)
5742 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
5743 #define BXT_DE_PORT_GMBUS (1 << 1)
5744 #define GEN8_AUX_CHANNEL_A (1 << 0)
5746 #define GEN8_DE_MISC_ISR 0x44460
5747 #define GEN8_DE_MISC_IMR 0x44464
5748 #define GEN8_DE_MISC_IIR 0x44468
5749 #define GEN8_DE_MISC_IER 0x4446c
5750 #define GEN8_DE_MISC_GSE (1 << 27)
5752 #define GEN8_PCU_ISR 0x444e0
5753 #define GEN8_PCU_IMR 0x444e4
5754 #define GEN8_PCU_IIR 0x444e8
5755 #define GEN8_PCU_IER 0x444ec
5757 /* BXT hotplug control */
5758 #define BXT_HOTPLUG_CTL 0xC4030
5759 #define BXT_DDIA_HPD_ENABLE (1 << 28)
5760 #define BXT_DDIA_HPD_STATUS (3 << 24)
5761 #define BXT_DDIC_HPD_ENABLE (1 << 12)
5762 #define BXT_DDIC_HPD_STATUS (3 << 8)
5763 #define BXT_DDIB_HPD_ENABLE (1 << 4)
5764 #define BXT_DDIB_HPD_STATUS (3 << 0)
5765 #define BXT_HOTPLUG_CTL_MASK (BXT_DDIA_HPD_ENABLE | \
5766 BXT_DDIB_HPD_ENABLE | \
5767 BXT_DDIC_HPD_ENABLE)
5768 #define BXT_HPD_STATUS_MASK (BXT_DDIA_HPD_STATUS | \
5769 BXT_DDIB_HPD_STATUS | \
5770 BXT_DDIC_HPD_STATUS)
5772 #define ILK_DISPLAY_CHICKEN2 0x42004
5773 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5774 #define ILK_ELPIN_409_SELECT (1 << 25)
5775 #define ILK_DPARB_GATE (1<<22)
5776 #define ILK_VSDPFD_FULL (1<<21)
5777 #define FUSE_STRAP 0x42014
5778 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5779 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5780 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5781 #define ILK_HDCP_DISABLE (1 << 25)
5782 #define ILK_eDP_A_DISABLE (1 << 24)
5783 #define HSW_CDCLK_LIMIT (1 << 24)
5784 #define ILK_DESKTOP (1 << 23)
5786 #define ILK_DSPCLK_GATE_D 0x42020
5787 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5788 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5789 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5790 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5791 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5793 #define IVB_CHICKEN3 0x4200c
5794 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5795 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5797 #define CHICKEN_PAR1_1 0x42080
5798 #define DPA_MASK_VBLANK_SRD (1 << 15)
5799 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5801 #define _CHICKEN_PIPESL_1_A 0x420b0
5802 #define _CHICKEN_PIPESL_1_B 0x420b4
5803 #define HSW_FBCQ_DIS (1 << 22)
5804 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5805 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5807 #define DISP_ARB_CTL 0x45000
5808 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5809 #define DISP_FBC_WM_DIS (1<<15)
5810 #define DISP_ARB_CTL2 0x45004
5811 #define DISP_DATA_PARTITION_5_6 (1<<6)
5812 #define DBUF_CTL 0x45008
5813 #define DBUF_POWER_REQUEST (1<<31)
5814 #define DBUF_POWER_STATE (1<<30)
5815 #define GEN7_MSG_CTL 0x45010
5816 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
5817 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
5818 #define HSW_NDE_RSTWRN_OPT 0x46408
5819 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
5821 #define SKL_DFSM 0x51000
5822 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5823 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5824 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5825 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5826 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5828 #define FF_SLICE_CS_CHICKEN2 0x20e4
5829 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
5832 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
5833 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
5834 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
5835 #define COMMON_SLICE_CHICKEN2 0x7014
5836 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
5838 #define HIZ_CHICKEN 0x7018
5839 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
5840 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
5842 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308
5843 #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
5845 #define GEN7_L3SQCREG1 0xB010
5846 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
5848 #define GEN8_L3SQCREG1 0xB100
5849 #define BDW_WA_L3SQCREG1_DEFAULT 0x784000
5851 #define GEN7_L3CNTLREG1 0xB01C
5852 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
5853 #define GEN7_L3AGDIS (1<<19)
5854 #define GEN7_L3CNTLREG2 0xB020
5855 #define GEN7_L3CNTLREG3 0xB024
5857 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
5858 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
5860 #define GEN7_L3SQCREG4 0xb034
5861 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
5863 #define GEN8_L3SQCREG4 0xb118
5864 #define GEN8_LQSC_RO_PERF_DIS (1<<27)
5865 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
5868 #define HDC_CHICKEN0 0x7300
5869 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
5870 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
5871 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
5872 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
5873 #define HDC_FORCE_NON_COHERENT (1<<4)
5874 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
5877 #define SLICE_ECO_CHICKEN0 0x7308
5878 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
5880 /* WaCatErrorRejectionIssue */
5881 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
5882 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
5884 #define HSW_SCRATCH1 0xb038
5885 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
5887 #define BDW_SCRATCH1 0xb11c
5888 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
5892 /* south display engine interrupt: IBX */
5893 #define SDE_AUDIO_POWER_D (1 << 27)
5894 #define SDE_AUDIO_POWER_C (1 << 26)
5895 #define SDE_AUDIO_POWER_B (1 << 25)
5896 #define SDE_AUDIO_POWER_SHIFT (25)
5897 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5898 #define SDE_GMBUS (1 << 24)
5899 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5900 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5901 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5902 #define SDE_AUDIO_TRANSB (1 << 21)
5903 #define SDE_AUDIO_TRANSA (1 << 20)
5904 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5905 #define SDE_POISON (1 << 19)
5907 #define SDE_FDI_RXB (1 << 17)
5908 #define SDE_FDI_RXA (1 << 16)
5909 #define SDE_FDI_MASK (3 << 16)
5910 #define SDE_AUXD (1 << 15)
5911 #define SDE_AUXC (1 << 14)
5912 #define SDE_AUXB (1 << 13)
5913 #define SDE_AUX_MASK (7 << 13)
5915 #define SDE_CRT_HOTPLUG (1 << 11)
5916 #define SDE_PORTD_HOTPLUG (1 << 10)
5917 #define SDE_PORTC_HOTPLUG (1 << 9)
5918 #define SDE_PORTB_HOTPLUG (1 << 8)
5919 #define SDE_SDVOB_HOTPLUG (1 << 6)
5920 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5921 SDE_SDVOB_HOTPLUG | \
5922 SDE_PORTB_HOTPLUG | \
5923 SDE_PORTC_HOTPLUG | \
5925 #define SDE_TRANSB_CRC_DONE (1 << 5)
5926 #define SDE_TRANSB_CRC_ERR (1 << 4)
5927 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
5928 #define SDE_TRANSA_CRC_DONE (1 << 2)
5929 #define SDE_TRANSA_CRC_ERR (1 << 1)
5930 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
5931 #define SDE_TRANS_MASK (0x3f)
5933 /* south display engine interrupt: CPT/PPT */
5934 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
5935 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
5936 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
5937 #define SDE_AUDIO_POWER_SHIFT_CPT 29
5938 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5939 #define SDE_AUXD_CPT (1 << 27)
5940 #define SDE_AUXC_CPT (1 << 26)
5941 #define SDE_AUXB_CPT (1 << 25)
5942 #define SDE_AUX_MASK_CPT (7 << 25)
5943 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5944 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5945 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
5946 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
5947 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
5948 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
5949 SDE_SDVOB_HOTPLUG_CPT | \
5950 SDE_PORTD_HOTPLUG_CPT | \
5951 SDE_PORTC_HOTPLUG_CPT | \
5952 SDE_PORTB_HOTPLUG_CPT)
5953 #define SDE_GMBUS_CPT (1 << 17)
5954 #define SDE_ERROR_CPT (1 << 16)
5955 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5956 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5957 #define SDE_FDI_RXC_CPT (1 << 8)
5958 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5959 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5960 #define SDE_FDI_RXB_CPT (1 << 4)
5961 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5962 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5963 #define SDE_FDI_RXA_CPT (1 << 0)
5964 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5965 SDE_AUDIO_CP_REQ_B_CPT | \
5966 SDE_AUDIO_CP_REQ_A_CPT)
5967 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5968 SDE_AUDIO_CP_CHG_B_CPT | \
5969 SDE_AUDIO_CP_CHG_A_CPT)
5970 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5974 #define SDEISR 0xc4000
5975 #define SDEIMR 0xc4004
5976 #define SDEIIR 0xc4008
5977 #define SDEIER 0xc400c
5979 #define SERR_INT 0xc4040
5980 #define SERR_INT_POISON (1<<31)
5981 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
5982 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
5983 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
5984 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
5986 /* digital port hotplug */
5987 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
5988 #define PORTD_HOTPLUG_ENABLE (1 << 20)
5989 #define PORTD_PULSE_DURATION_2ms (0)
5990 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
5991 #define PORTD_PULSE_DURATION_6ms (2 << 18)
5992 #define PORTD_PULSE_DURATION_100ms (3 << 18)
5993 #define PORTD_PULSE_DURATION_MASK (3 << 18)
5994 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
5995 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5996 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5997 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
5998 #define PORTC_HOTPLUG_ENABLE (1 << 12)
5999 #define PORTC_PULSE_DURATION_2ms (0)
6000 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
6001 #define PORTC_PULSE_DURATION_6ms (2 << 10)
6002 #define PORTC_PULSE_DURATION_100ms (3 << 10)
6003 #define PORTC_PULSE_DURATION_MASK (3 << 10)
6004 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
6005 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6006 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6007 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
6008 #define PORTB_HOTPLUG_ENABLE (1 << 4)
6009 #define PORTB_PULSE_DURATION_2ms (0)
6010 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
6011 #define PORTB_PULSE_DURATION_6ms (2 << 2)
6012 #define PORTB_PULSE_DURATION_100ms (3 << 2)
6013 #define PORTB_PULSE_DURATION_MASK (3 << 2)
6014 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
6015 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6016 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6017 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
6019 #define PCH_GPIOA 0xc5010
6020 #define PCH_GPIOB 0xc5014
6021 #define PCH_GPIOC 0xc5018
6022 #define PCH_GPIOD 0xc501c
6023 #define PCH_GPIOE 0xc5020
6024 #define PCH_GPIOF 0xc5024
6026 #define PCH_GMBUS0 0xc5100
6027 #define PCH_GMBUS1 0xc5104
6028 #define PCH_GMBUS2 0xc5108
6029 #define PCH_GMBUS3 0xc510c
6030 #define PCH_GMBUS4 0xc5110
6031 #define PCH_GMBUS5 0xc5120
6033 #define _PCH_DPLL_A 0xc6014
6034 #define _PCH_DPLL_B 0xc6018
6035 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6037 #define _PCH_FPA0 0xc6040
6038 #define FP_CB_TUNE (0x3<<22)
6039 #define _PCH_FPA1 0xc6044
6040 #define _PCH_FPB0 0xc6048
6041 #define _PCH_FPB1 0xc604c
6042 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6043 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6045 #define PCH_DPLL_TEST 0xc606c
6047 #define PCH_DREF_CONTROL 0xC6200
6048 #define DREF_CONTROL_MASK 0x7fc3
6049 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6050 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6051 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6052 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6053 #define DREF_SSC_SOURCE_DISABLE (0<<11)
6054 #define DREF_SSC_SOURCE_ENABLE (2<<11)
6055 #define DREF_SSC_SOURCE_MASK (3<<11)
6056 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6057 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6058 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
6059 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
6060 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6061 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
6062 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
6063 #define DREF_SSC4_DOWNSPREAD (0<<6)
6064 #define DREF_SSC4_CENTERSPREAD (1<<6)
6065 #define DREF_SSC1_DISABLE (0<<1)
6066 #define DREF_SSC1_ENABLE (1<<1)
6067 #define DREF_SSC4_DISABLE (0)
6068 #define DREF_SSC4_ENABLE (1)
6070 #define PCH_RAWCLK_FREQ 0xc6204
6071 #define FDL_TP1_TIMER_SHIFT 12
6072 #define FDL_TP1_TIMER_MASK (3<<12)
6073 #define FDL_TP2_TIMER_SHIFT 10
6074 #define FDL_TP2_TIMER_MASK (3<<10)
6075 #define RAWCLK_FREQ_MASK 0x3ff
6077 #define PCH_DPLL_TMR_CFG 0xc6208
6079 #define PCH_SSC4_PARMS 0xc6210
6080 #define PCH_SSC4_AUX_PARMS 0xc6214
6082 #define PCH_DPLL_SEL 0xc7000
6083 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
6084 #define TRANS_DPLLA_SEL(pipe) 0
6085 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
6089 #define _PCH_TRANS_HTOTAL_A 0xe0000
6090 #define TRANS_HTOTAL_SHIFT 16
6091 #define TRANS_HACTIVE_SHIFT 0
6092 #define _PCH_TRANS_HBLANK_A 0xe0004
6093 #define TRANS_HBLANK_END_SHIFT 16
6094 #define TRANS_HBLANK_START_SHIFT 0
6095 #define _PCH_TRANS_HSYNC_A 0xe0008
6096 #define TRANS_HSYNC_END_SHIFT 16
6097 #define TRANS_HSYNC_START_SHIFT 0
6098 #define _PCH_TRANS_VTOTAL_A 0xe000c
6099 #define TRANS_VTOTAL_SHIFT 16
6100 #define TRANS_VACTIVE_SHIFT 0
6101 #define _PCH_TRANS_VBLANK_A 0xe0010
6102 #define TRANS_VBLANK_END_SHIFT 16
6103 #define TRANS_VBLANK_START_SHIFT 0
6104 #define _PCH_TRANS_VSYNC_A 0xe0014
6105 #define TRANS_VSYNC_END_SHIFT 16
6106 #define TRANS_VSYNC_START_SHIFT 0
6107 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6109 #define _PCH_TRANSA_DATA_M1 0xe0030
6110 #define _PCH_TRANSA_DATA_N1 0xe0034
6111 #define _PCH_TRANSA_DATA_M2 0xe0038
6112 #define _PCH_TRANSA_DATA_N2 0xe003c
6113 #define _PCH_TRANSA_LINK_M1 0xe0040
6114 #define _PCH_TRANSA_LINK_N1 0xe0044
6115 #define _PCH_TRANSA_LINK_M2 0xe0048
6116 #define _PCH_TRANSA_LINK_N2 0xe004c
6118 /* Per-transcoder DIP controls (PCH) */
6119 #define _VIDEO_DIP_CTL_A 0xe0200
6120 #define _VIDEO_DIP_DATA_A 0xe0208
6121 #define _VIDEO_DIP_GCP_A 0xe0210
6122 #define GCP_COLOR_INDICATION (1 << 2)
6123 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6124 #define GCP_AV_MUTE (1 << 0)
6126 #define _VIDEO_DIP_CTL_B 0xe1200
6127 #define _VIDEO_DIP_DATA_B 0xe1208
6128 #define _VIDEO_DIP_GCP_B 0xe1210
6130 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6131 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6132 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6134 /* Per-transcoder DIP controls (VLV) */
6135 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6136 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6137 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6139 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6140 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6141 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6143 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6144 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6145 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6147 #define VLV_TVIDEO_DIP_CTL(pipe) \
6148 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
6149 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
6150 #define VLV_TVIDEO_DIP_DATA(pipe) \
6151 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
6152 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
6153 #define VLV_TVIDEO_DIP_GCP(pipe) \
6154 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6155 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6157 /* Haswell DIP controls */
6158 #define HSW_VIDEO_DIP_CTL_A 0x60200
6159 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6160 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
6161 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6162 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6163 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6164 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6165 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
6166 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6167 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6168 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6169 #define HSW_VIDEO_DIP_GCP_A 0x60210
6171 #define HSW_VIDEO_DIP_CTL_B 0x61200
6172 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6173 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
6174 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6175 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6176 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6177 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6178 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
6179 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6180 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6181 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6182 #define HSW_VIDEO_DIP_GCP_B 0x61210
6184 #define HSW_TVIDEO_DIP_CTL(trans) \
6185 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
6186 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
6187 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
6188 #define HSW_TVIDEO_DIP_VS_DATA(trans) \
6189 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
6190 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
6191 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
6192 #define HSW_TVIDEO_DIP_GCP(trans) \
6193 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
6194 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
6195 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
6197 #define HSW_STEREO_3D_CTL_A 0x70020
6198 #define S3D_ENABLE (1<<31)
6199 #define HSW_STEREO_3D_CTL_B 0x71020
6201 #define HSW_STEREO_3D_CTL(trans) \
6202 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
6204 #define _PCH_TRANS_HTOTAL_B 0xe1000
6205 #define _PCH_TRANS_HBLANK_B 0xe1004
6206 #define _PCH_TRANS_HSYNC_B 0xe1008
6207 #define _PCH_TRANS_VTOTAL_B 0xe100c
6208 #define _PCH_TRANS_VBLANK_B 0xe1010
6209 #define _PCH_TRANS_VSYNC_B 0xe1014
6210 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6212 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6213 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6214 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6215 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6216 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6217 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6218 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
6219 _PCH_TRANS_VSYNCSHIFT_B)
6221 #define _PCH_TRANSB_DATA_M1 0xe1030
6222 #define _PCH_TRANSB_DATA_N1 0xe1034
6223 #define _PCH_TRANSB_DATA_M2 0xe1038
6224 #define _PCH_TRANSB_DATA_N2 0xe103c
6225 #define _PCH_TRANSB_LINK_M1 0xe1040
6226 #define _PCH_TRANSB_LINK_N1 0xe1044
6227 #define _PCH_TRANSB_LINK_M2 0xe1048
6228 #define _PCH_TRANSB_LINK_N2 0xe104c
6230 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6231 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6232 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6233 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6234 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6235 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6236 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6237 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6239 #define _PCH_TRANSACONF 0xf0008
6240 #define _PCH_TRANSBCONF 0xf1008
6241 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6242 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
6243 #define TRANS_DISABLE (0<<31)
6244 #define TRANS_ENABLE (1<<31)
6245 #define TRANS_STATE_MASK (1<<30)
6246 #define TRANS_STATE_DISABLE (0<<30)
6247 #define TRANS_STATE_ENABLE (1<<30)
6248 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
6249 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
6250 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
6251 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
6252 #define TRANS_INTERLACE_MASK (7<<21)
6253 #define TRANS_PROGRESSIVE (0<<21)
6254 #define TRANS_INTERLACED (3<<21)
6255 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
6256 #define TRANS_8BPC (0<<5)
6257 #define TRANS_10BPC (1<<5)
6258 #define TRANS_6BPC (2<<5)
6259 #define TRANS_12BPC (3<<5)
6261 #define _TRANSA_CHICKEN1 0xf0060
6262 #define _TRANSB_CHICKEN1 0xf1060
6263 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6264 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
6265 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
6266 #define _TRANSA_CHICKEN2 0xf0064
6267 #define _TRANSB_CHICKEN2 0xf1064
6268 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6269 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6270 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6271 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6272 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6273 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
6275 #define SOUTH_CHICKEN1 0xc2000
6276 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
6277 #define FDIA_PHASE_SYNC_SHIFT_EN 18
6278 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6279 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6280 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
6281 #define SOUTH_CHICKEN2 0xc2004
6282 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6283 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6284 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
6286 #define _FDI_RXA_CHICKEN 0xc200c
6287 #define _FDI_RXB_CHICKEN 0xc2010
6288 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6289 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
6290 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6292 #define SOUTH_DSPCLK_GATE_D 0xc2020
6293 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6294 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6295 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6296 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
6299 #define _FDI_TXA_CTL 0x60100
6300 #define _FDI_TXB_CTL 0x61100
6301 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6302 #define FDI_TX_DISABLE (0<<31)
6303 #define FDI_TX_ENABLE (1<<31)
6304 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6305 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6306 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6307 #define FDI_LINK_TRAIN_NONE (3<<28)
6308 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6309 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6310 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6311 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6312 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6313 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6314 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6315 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
6316 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6317 SNB has different settings. */
6318 /* SNB A-stepping */
6319 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6320 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6321 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6322 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6323 /* SNB B-stepping */
6324 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6325 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6326 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6327 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6328 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
6329 #define FDI_DP_PORT_WIDTH_SHIFT 19
6330 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6331 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6332 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
6333 /* Ironlake: hardwired to 1 */
6334 #define FDI_TX_PLL_ENABLE (1<<14)
6336 /* Ivybridge has different bits for lolz */
6337 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6338 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6339 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6340 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6342 /* both Tx and Rx */
6343 #define FDI_COMPOSITE_SYNC (1<<11)
6344 #define FDI_LINK_TRAIN_AUTO (1<<10)
6345 #define FDI_SCRAMBLING_ENABLE (0<<7)
6346 #define FDI_SCRAMBLING_DISABLE (1<<7)
6348 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6349 #define _FDI_RXA_CTL 0xf000c
6350 #define _FDI_RXB_CTL 0xf100c
6351 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6352 #define FDI_RX_ENABLE (1<<31)
6353 /* train, dp width same as FDI_TX */
6354 #define FDI_FS_ERRC_ENABLE (1<<27)
6355 #define FDI_FE_ERRC_ENABLE (1<<26)
6356 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
6357 #define FDI_8BPC (0<<16)
6358 #define FDI_10BPC (1<<16)
6359 #define FDI_6BPC (2<<16)
6360 #define FDI_12BPC (3<<16)
6361 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
6362 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6363 #define FDI_RX_PLL_ENABLE (1<<13)
6364 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6365 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6366 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6367 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6368 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
6369 #define FDI_PCDCLK (1<<4)
6371 #define FDI_AUTO_TRAINING (1<<10)
6372 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6373 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6374 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6375 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6376 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
6378 #define _FDI_RXA_MISC 0xf0010
6379 #define _FDI_RXB_MISC 0xf1010
6380 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6381 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6382 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6383 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6384 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
6385 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
6386 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
6387 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6389 #define _FDI_RXA_TUSIZE1 0xf0030
6390 #define _FDI_RXA_TUSIZE2 0xf0038
6391 #define _FDI_RXB_TUSIZE1 0xf1030
6392 #define _FDI_RXB_TUSIZE2 0xf1038
6393 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6394 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6396 /* FDI_RX interrupt register format */
6397 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
6398 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6399 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6400 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6401 #define FDI_RX_FS_CODE_ERR (1<<6)
6402 #define FDI_RX_FE_CODE_ERR (1<<5)
6403 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6404 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
6405 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6406 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6407 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6409 #define _FDI_RXA_IIR 0xf0014
6410 #define _FDI_RXA_IMR 0xf0018
6411 #define _FDI_RXB_IIR 0xf1014
6412 #define _FDI_RXB_IMR 0xf1018
6413 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6414 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6416 #define FDI_PLL_CTL_1 0xfe000
6417 #define FDI_PLL_CTL_2 0xfe004
6419 #define PCH_LVDS 0xe1180
6420 #define LVDS_DETECTED (1 << 1)
6422 /* vlv has 2 sets of panel control regs. */
6423 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6424 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6425 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
6426 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
6427 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6428 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
6430 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6431 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6432 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6433 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6434 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
6436 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
6437 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
6438 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
6439 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
6440 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
6441 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
6442 #define VLV_PIPE_PP_DIVISOR(pipe) \
6443 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
6445 #define PCH_PP_STATUS 0xc7200
6446 #define PCH_PP_CONTROL 0xc7204
6447 #define PANEL_UNLOCK_REGS (0xabcd << 16)
6448 #define PANEL_UNLOCK_MASK (0xffff << 16)
6449 #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
6450 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
6451 #define EDP_FORCE_VDD (1 << 3)
6452 #define EDP_BLC_ENABLE (1 << 2)
6453 #define PANEL_POWER_RESET (1 << 1)
6454 #define PANEL_POWER_OFF (0 << 0)
6455 #define PANEL_POWER_ON (1 << 0)
6456 #define PCH_PP_ON_DELAYS 0xc7208
6457 #define PANEL_PORT_SELECT_MASK (3 << 30)
6458 #define PANEL_PORT_SELECT_LVDS (0 << 30)
6459 #define PANEL_PORT_SELECT_DPA (1 << 30)
6460 #define PANEL_PORT_SELECT_DPC (2 << 30)
6461 #define PANEL_PORT_SELECT_DPD (3 << 30)
6462 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
6463 #define PANEL_POWER_UP_DELAY_SHIFT 16
6464 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6465 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
6467 #define PCH_PP_OFF_DELAYS 0xc720c
6468 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6469 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
6470 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6471 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6473 #define PCH_PP_DIVISOR 0xc7210
6474 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6475 #define PP_REFERENCE_DIVIDER_SHIFT 8
6476 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6477 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
6479 /* BXT PPS changes - 2nd set of PPS registers */
6480 #define _BXT_PP_STATUS2 0xc7300
6481 #define _BXT_PP_CONTROL2 0xc7304
6482 #define _BXT_PP_ON_DELAYS2 0xc7308
6483 #define _BXT_PP_OFF_DELAYS2 0xc730c
6485 #define BXT_PP_STATUS(n) ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
6486 #define BXT_PP_CONTROL(n) ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
6487 #define BXT_PP_ON_DELAYS(n) ((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
6488 #define BXT_PP_OFF_DELAYS(n) ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
6490 #define PCH_DP_B 0xe4100
6491 #define PCH_DPB_AUX_CH_CTL 0xe4110
6492 #define PCH_DPB_AUX_CH_DATA1 0xe4114
6493 #define PCH_DPB_AUX_CH_DATA2 0xe4118
6494 #define PCH_DPB_AUX_CH_DATA3 0xe411c
6495 #define PCH_DPB_AUX_CH_DATA4 0xe4120
6496 #define PCH_DPB_AUX_CH_DATA5 0xe4124
6498 #define PCH_DP_C 0xe4200
6499 #define PCH_DPC_AUX_CH_CTL 0xe4210
6500 #define PCH_DPC_AUX_CH_DATA1 0xe4214
6501 #define PCH_DPC_AUX_CH_DATA2 0xe4218
6502 #define PCH_DPC_AUX_CH_DATA3 0xe421c
6503 #define PCH_DPC_AUX_CH_DATA4 0xe4220
6504 #define PCH_DPC_AUX_CH_DATA5 0xe4224
6506 #define PCH_DP_D 0xe4300
6507 #define PCH_DPD_AUX_CH_CTL 0xe4310
6508 #define PCH_DPD_AUX_CH_DATA1 0xe4314
6509 #define PCH_DPD_AUX_CH_DATA2 0xe4318
6510 #define PCH_DPD_AUX_CH_DATA3 0xe431c
6511 #define PCH_DPD_AUX_CH_DATA4 0xe4320
6512 #define PCH_DPD_AUX_CH_DATA5 0xe4324
6515 #define PORT_TRANS_A_SEL_CPT 0
6516 #define PORT_TRANS_B_SEL_CPT (1<<29)
6517 #define PORT_TRANS_C_SEL_CPT (2<<29)
6518 #define PORT_TRANS_SEL_MASK (3<<29)
6519 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
6520 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6521 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
6522 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6523 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
6525 #define TRANS_DP_CTL_A 0xe0300
6526 #define TRANS_DP_CTL_B 0xe1300
6527 #define TRANS_DP_CTL_C 0xe2300
6528 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
6529 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
6530 #define TRANS_DP_PORT_SEL_B (0<<29)
6531 #define TRANS_DP_PORT_SEL_C (1<<29)
6532 #define TRANS_DP_PORT_SEL_D (2<<29)
6533 #define TRANS_DP_PORT_SEL_NONE (3<<29)
6534 #define TRANS_DP_PORT_SEL_MASK (3<<29)
6535 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
6536 #define TRANS_DP_AUDIO_ONLY (1<<26)
6537 #define TRANS_DP_ENH_FRAMING (1<<18)
6538 #define TRANS_DP_8BPC (0<<9)
6539 #define TRANS_DP_10BPC (1<<9)
6540 #define TRANS_DP_6BPC (2<<9)
6541 #define TRANS_DP_12BPC (3<<9)
6542 #define TRANS_DP_BPC_MASK (3<<9)
6543 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6544 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
6545 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6546 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
6547 #define TRANS_DP_SYNC_MASK (3<<3)
6549 /* SNB eDP training params */
6550 /* SNB A-stepping */
6551 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6552 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6553 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6554 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6555 /* SNB B-stepping */
6556 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6557 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6558 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6559 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6560 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
6561 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6564 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6565 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6566 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6567 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6568 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6569 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
6570 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
6573 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6574 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6575 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6576 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6577 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6579 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6581 #define VLV_PMWGICZ 0x1300a4
6583 #define FORCEWAKE 0xA18C
6584 #define FORCEWAKE_VLV 0x1300b0
6585 #define FORCEWAKE_ACK_VLV 0x1300b4
6586 #define FORCEWAKE_MEDIA_VLV 0x1300b8
6587 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
6588 #define FORCEWAKE_ACK_HSW 0x130044
6589 #define FORCEWAKE_ACK 0x130090
6590 #define VLV_GTLC_WAKE_CTRL 0x130090
6591 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6592 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6593 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6595 #define VLV_GTLC_PW_STATUS 0x130094
6596 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6597 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6598 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6599 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
6600 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
6601 #define FORCEWAKE_MEDIA_GEN9 0xa270
6602 #define FORCEWAKE_RENDER_GEN9 0xa278
6603 #define FORCEWAKE_BLITTER_GEN9 0xa188
6604 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
6605 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
6606 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
6607 #define FORCEWAKE_KERNEL 0x1
6608 #define FORCEWAKE_USER 0x2
6609 #define FORCEWAKE_MT_ACK 0x130040
6610 #define ECOBUS 0xa180
6611 #define FORCEWAKE_MT_ENABLE (1<<5)
6612 #define VLV_SPAREG2H 0xA194
6614 #define GTFIFODBG 0x120000
6615 #define GT_FIFO_SBDROPERR (1<<6)
6616 #define GT_FIFO_BLOBDROPERR (1<<5)
6617 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
6618 #define GT_FIFO_DROPERR (1<<3)
6619 #define GT_FIFO_OVFERR (1<<2)
6620 #define GT_FIFO_IAWRERR (1<<1)
6621 #define GT_FIFO_IARDERR (1<<0)
6623 #define GTFIFOCTL 0x120008
6624 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
6625 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
6626 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6627 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
6629 #define HSW_IDICR 0x9008
6630 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6631 #define HSW_EDRAM_PRESENT 0x120010
6632 #define EDRAM_ENABLED 0x1
6634 #define GEN6_UCGCTL1 0x9400
6635 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6636 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6637 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
6639 #define GEN6_UCGCTL2 0x9404
6640 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
6641 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6642 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
6643 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
6644 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
6645 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
6647 #define GEN6_UCGCTL3 0x9408
6649 #define GEN7_UCGCTL4 0x940c
6650 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6652 #define GEN6_RCGCTL1 0x9410
6653 #define GEN6_RCGCTL2 0x9414
6654 #define GEN6_RSTCTL 0x9420
6656 #define GEN8_UCGCTL6 0x9430
6657 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
6658 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6659 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6661 #define GEN6_GFXPAUSE 0xA000
6662 #define GEN6_RPNSWREQ 0xA008
6663 #define GEN6_TURBO_DISABLE (1<<31)
6664 #define GEN6_FREQUENCY(x) ((x)<<25)
6665 #define HSW_FREQUENCY(x) ((x)<<24)
6666 #define GEN9_FREQUENCY(x) ((x)<<23)
6667 #define GEN6_OFFSET(x) ((x)<<19)
6668 #define GEN6_AGGRESSIVE_TURBO (0<<15)
6669 #define GEN6_RC_VIDEO_FREQ 0xA00C
6670 #define GEN6_RC_CONTROL 0xA090
6671 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6672 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6673 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
6674 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
6675 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
6676 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
6677 #define GEN7_RC_CTL_TO_MODE (1<<28)
6678 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6679 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
6680 #define GEN6_RP_DOWN_TIMEOUT 0xA010
6681 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
6682 #define GEN6_RPSTAT1 0xA01C
6683 #define GEN6_CAGF_SHIFT 8
6684 #define HSW_CAGF_SHIFT 7
6685 #define GEN9_CAGF_SHIFT 23
6686 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
6687 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
6688 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
6689 #define GEN6_RP_CONTROL 0xA024
6690 #define GEN6_RP_MEDIA_TURBO (1<<11)
6691 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6692 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6693 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6694 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
6695 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
6696 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
6697 #define GEN6_RP_ENABLE (1<<7)
6698 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6699 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6700 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
6701 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
6702 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
6703 #define GEN6_RP_UP_THRESHOLD 0xA02C
6704 #define GEN6_RP_DOWN_THRESHOLD 0xA030
6705 #define GEN6_RP_CUR_UP_EI 0xA050
6706 #define GEN6_CURICONT_MASK 0xffffff
6707 #define GEN6_RP_CUR_UP 0xA054
6708 #define GEN6_CURBSYTAVG_MASK 0xffffff
6709 #define GEN6_RP_PREV_UP 0xA058
6710 #define GEN6_RP_CUR_DOWN_EI 0xA05C
6711 #define GEN6_CURIAVG_MASK 0xffffff
6712 #define GEN6_RP_CUR_DOWN 0xA060
6713 #define GEN6_RP_PREV_DOWN 0xA064
6714 #define GEN6_RP_UP_EI 0xA068
6715 #define GEN6_RP_DOWN_EI 0xA06C
6716 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
6717 #define GEN6_RPDEUHWTC 0xA080
6718 #define GEN6_RPDEUC 0xA084
6719 #define GEN6_RPDEUCSW 0xA088
6720 #define GEN6_RC_STATE 0xA094
6721 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
6722 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
6723 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
6724 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
6725 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
6726 #define GEN6_RC_SLEEP 0xA0B0
6727 #define GEN6_RCUBMABDTMR 0xA0B0
6728 #define GEN6_RC1e_THRESHOLD 0xA0B4
6729 #define GEN6_RC6_THRESHOLD 0xA0B8
6730 #define GEN6_RC6p_THRESHOLD 0xA0BC
6731 #define VLV_RCEDATA 0xA0BC
6732 #define GEN6_RC6pp_THRESHOLD 0xA0C0
6733 #define GEN6_PMINTRMSK 0xA168
6734 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6735 #define VLV_PWRDWNUPCTL 0xA294
6736 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
6737 #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
6738 #define GEN9_PG_ENABLE 0xA210
6739 #define GEN9_RENDER_PG_ENABLE (1<<0)
6740 #define GEN9_MEDIA_PG_ENABLE (1<<1)
6742 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6743 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6744 #define PIXEL_OVERLAP_CNT_SHIFT 30
6746 #define GEN6_PMISR 0x44020
6747 #define GEN6_PMIMR 0x44024 /* rps_lock */
6748 #define GEN6_PMIIR 0x44028
6749 #define GEN6_PMIER 0x4402C
6750 #define GEN6_PM_MBOX_EVENT (1<<25)
6751 #define GEN6_PM_THERMAL_EVENT (1<<24)
6752 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6753 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6754 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6755 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6756 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
6757 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
6758 GEN6_PM_RP_DOWN_THRESHOLD | \
6759 GEN6_PM_RP_DOWN_TIMEOUT)
6761 #define GEN7_GT_SCRATCH_BASE 0x4F100
6762 #define GEN7_GT_SCRATCH_REG_NUM 8
6764 #define VLV_GTLC_SURVIVABILITY_REG 0x130098
6765 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
6766 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6768 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
6769 #define VLV_COUNTER_CONTROL 0x138104
6770 #define VLV_COUNT_RANGE_HIGH (1<<15)
6771 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6772 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
6773 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6774 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
6775 #define GEN6_GT_GFX_RC6 0x138108
6776 #define VLV_GT_RENDER_RC6 0x138108
6777 #define VLV_GT_MEDIA_RC6 0x13810C
6779 #define GEN6_GT_GFX_RC6p 0x13810C
6780 #define GEN6_GT_GFX_RC6pp 0x138110
6781 #define VLV_RENDER_C0_COUNT 0x138118
6782 #define VLV_MEDIA_C0_COUNT 0x13811C
6784 #define GEN6_PCODE_MAILBOX 0x138124
6785 #define GEN6_PCODE_READY (1<<31)
6786 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6787 #define GEN6_PCODE_READ_RC6VIDS 0x5
6788 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6789 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6790 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
6791 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6792 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
6793 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
6794 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
6795 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
6796 #define SKL_PCODE_CDCLK_CONTROL 0x7
6797 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
6798 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
6799 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6800 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6801 #define GEN6_READ_OC_PARAMS 0xc
6802 #define GEN6_PCODE_READ_D_COMP 0x10
6803 #define GEN6_PCODE_WRITE_D_COMP 0x11
6804 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
6805 #define DISPLAY_IPS_CONTROL 0x19
6806 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6807 #define GEN6_PCODE_DATA 0x138128
6808 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6809 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6810 #define GEN6_PCODE_DATA1 0x13812C
6812 #define GEN6_GT_CORE_STATUS 0x138060
6813 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
6814 #define GEN6_RCn_MASK 7
6820 #define CHV_POWER_SS0_SIG1 0xa720
6821 #define CHV_POWER_SS1_SIG1 0xa728
6822 #define CHV_SS_PG_ENABLE (1<<1)
6823 #define CHV_EU08_PG_ENABLE (1<<9)
6824 #define CHV_EU19_PG_ENABLE (1<<17)
6825 #define CHV_EU210_PG_ENABLE (1<<25)
6827 #define CHV_POWER_SS0_SIG2 0xa724
6828 #define CHV_POWER_SS1_SIG2 0xa72c
6829 #define CHV_EU311_PG_ENABLE (1<<1)
6831 #define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)
6832 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
6833 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
6835 #define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)
6836 #define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)
6837 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
6838 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
6839 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
6840 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
6841 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
6842 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
6843 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
6844 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
6846 #define GEN7_MISCCPCTL (0x9424)
6847 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
6850 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
6851 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
6852 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
6853 #define GEN7_PARITY_ERROR_VALID (1<<13)
6854 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
6855 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
6856 #define GEN7_PARITY_ERROR_ROW(reg) \
6857 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6858 #define GEN7_PARITY_ERROR_BANK(reg) \
6859 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6860 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6861 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6862 #define GEN7_L3CDERRST1_ENABLE (1<<7)
6864 #define GEN7_L3LOG_BASE 0xB070
6865 #define HSW_L3LOG_BASE_SLICE1 0xB270
6866 #define GEN7_L3LOG_SIZE 0x80
6868 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
6869 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
6870 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
6871 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
6872 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
6873 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
6875 #define GEN9_HALF_SLICE_CHICKEN5 0xe188
6876 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
6877 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
6879 #define GEN8_ROW_CHICKEN 0xe4f0
6880 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
6881 #define STALL_DOP_GATING_DISABLE (1<<5)
6883 #define GEN7_ROW_CHICKEN2 0xe4f4
6884 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
6885 #define DOP_CLOCK_GATING_DISABLE (1<<0)
6887 #define HSW_ROW_CHICKEN3 0xe49c
6888 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
6890 #define HALF_SLICE_CHICKEN3 0xe184
6891 #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
6892 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
6893 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
6894 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
6896 #define GEN9_HALF_SLICE_CHICKEN7 0xe194
6897 #define GEN9_ENABLE_YV12_BUGFIX (1<<4)
6900 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
6901 #define INTEL_AUDIO_DEVCL 0x808629FB
6902 #define INTEL_AUDIO_DEVBLC 0x80862801
6903 #define INTEL_AUDIO_DEVCTG 0x80862802
6905 #define G4X_AUD_CNTL_ST 0x620B4
6906 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
6907 #define G4X_ELDV_DEVCTG (1 << 14)
6908 #define G4X_ELD_ADDR_MASK (0xf << 5)
6909 #define G4X_ELD_ACK (1 << 4)
6910 #define G4X_HDMIW_HDMIEDID 0x6210C
6912 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
6913 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
6914 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6915 _IBX_HDMIW_HDMIEDID_A, \
6916 _IBX_HDMIW_HDMIEDID_B)
6917 #define _IBX_AUD_CNTL_ST_A 0xE20B4
6918 #define _IBX_AUD_CNTL_ST_B 0xE21B4
6919 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6920 _IBX_AUD_CNTL_ST_A, \
6922 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
6923 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
6924 #define IBX_ELD_ACK (1 << 4)
6925 #define IBX_AUD_CNTL_ST2 0xE20C0
6926 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
6927 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
6929 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
6930 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
6931 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6932 _CPT_HDMIW_HDMIEDID_A, \
6933 _CPT_HDMIW_HDMIEDID_B)
6934 #define _CPT_AUD_CNTL_ST_A 0xE50B4
6935 #define _CPT_AUD_CNTL_ST_B 0xE51B4
6936 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6937 _CPT_AUD_CNTL_ST_A, \
6939 #define CPT_AUD_CNTRL_ST2 0xE50C0
6941 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
6942 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
6943 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
6944 _VLV_HDMIW_HDMIEDID_A, \
6945 _VLV_HDMIW_HDMIEDID_B)
6946 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
6947 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
6948 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
6949 _VLV_AUD_CNTL_ST_A, \
6951 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
6953 /* These are the 4 32-bit write offset registers for each stream
6954 * output buffer. It determines the offset from the
6955 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6957 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
6959 #define _IBX_AUD_CONFIG_A 0xe2000
6960 #define _IBX_AUD_CONFIG_B 0xe2100
6961 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
6962 _IBX_AUD_CONFIG_A, \
6964 #define _CPT_AUD_CONFIG_A 0xe5000
6965 #define _CPT_AUD_CONFIG_B 0xe5100
6966 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
6967 _CPT_AUD_CONFIG_A, \
6969 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
6970 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
6971 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
6972 _VLV_AUD_CONFIG_A, \
6975 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
6976 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
6977 #define AUD_CONFIG_UPPER_N_SHIFT 20
6978 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
6979 #define AUD_CONFIG_LOWER_N_SHIFT 4
6980 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
6981 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
6982 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
6983 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
6984 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
6985 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
6986 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
6987 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
6988 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
6989 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
6990 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
6991 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
6992 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
6993 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
6996 #define _HSW_AUD_CONFIG_A 0x65000
6997 #define _HSW_AUD_CONFIG_B 0x65100
6998 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
6999 _HSW_AUD_CONFIG_A, \
7002 #define _HSW_AUD_MISC_CTRL_A 0x65010
7003 #define _HSW_AUD_MISC_CTRL_B 0x65110
7004 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
7005 _HSW_AUD_MISC_CTRL_A, \
7006 _HSW_AUD_MISC_CTRL_B)
7008 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7009 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7010 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
7011 _HSW_AUD_DIP_ELD_CTRL_ST_A, \
7012 _HSW_AUD_DIP_ELD_CTRL_ST_B)
7014 /* Audio Digital Converter */
7015 #define _HSW_AUD_DIG_CNVT_1 0x65080
7016 #define _HSW_AUD_DIG_CNVT_2 0x65180
7017 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
7018 _HSW_AUD_DIG_CNVT_1, \
7019 _HSW_AUD_DIG_CNVT_2)
7020 #define DIP_PORT_SEL_MASK 0x3
7022 #define _HSW_AUD_EDID_DATA_A 0x65050
7023 #define _HSW_AUD_EDID_DATA_B 0x65150
7024 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
7025 _HSW_AUD_EDID_DATA_A, \
7026 _HSW_AUD_EDID_DATA_B)
7028 #define HSW_AUD_PIPE_CONV_CFG 0x6507c
7029 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0
7030 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7031 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7032 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7033 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
7035 #define HSW_AUD_CHICKENBIT 0x65f10
7036 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7038 /* HSW Power Wells */
7039 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
7040 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
7041 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
7042 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
7043 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7044 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
7045 #define HSW_PWR_WELL_CTL5 0x45410
7046 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7047 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
7048 #define HSW_PWR_WELL_FORCE_ON (1<<19)
7049 #define HSW_PWR_WELL_CTL6 0x45414
7051 /* SKL Fuse Status */
7052 #define SKL_FUSE_STATUS 0x42000
7053 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7054 #define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7055 #define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7056 #define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7058 /* Per-pipe DDI Function Control */
7059 #define TRANS_DDI_FUNC_CTL_A 0x60400
7060 #define TRANS_DDI_FUNC_CTL_B 0x61400
7061 #define TRANS_DDI_FUNC_CTL_C 0x62400
7062 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
7063 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
7065 #define TRANS_DDI_FUNC_ENABLE (1<<31)
7066 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
7067 #define TRANS_DDI_PORT_MASK (7<<28)
7068 #define TRANS_DDI_PORT_SHIFT 28
7069 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7070 #define TRANS_DDI_PORT_NONE (0<<28)
7071 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7072 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7073 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7074 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7075 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7076 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7077 #define TRANS_DDI_BPC_MASK (7<<20)
7078 #define TRANS_DDI_BPC_8 (0<<20)
7079 #define TRANS_DDI_BPC_10 (1<<20)
7080 #define TRANS_DDI_BPC_6 (2<<20)
7081 #define TRANS_DDI_BPC_12 (3<<20)
7082 #define TRANS_DDI_PVSYNC (1<<17)
7083 #define TRANS_DDI_PHSYNC (1<<16)
7084 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7085 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7086 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7087 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7088 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
7089 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
7090 #define TRANS_DDI_BFI_ENABLE (1<<4)
7092 /* DisplayPort Transport Control */
7093 #define DP_TP_CTL_A 0x64040
7094 #define DP_TP_CTL_B 0x64140
7095 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
7096 #define DP_TP_CTL_ENABLE (1<<31)
7097 #define DP_TP_CTL_MODE_SST (0<<27)
7098 #define DP_TP_CTL_MODE_MST (1<<27)
7099 #define DP_TP_CTL_FORCE_ACT (1<<25)
7100 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
7101 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
7102 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7103 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7104 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
7105 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7106 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
7107 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
7108 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
7110 /* DisplayPort Transport Status */
7111 #define DP_TP_STATUS_A 0x64044
7112 #define DP_TP_STATUS_B 0x64144
7113 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
7114 #define DP_TP_STATUS_IDLE_DONE (1<<25)
7115 #define DP_TP_STATUS_ACT_SENT (1<<24)
7116 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7117 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7118 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7119 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7120 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
7122 /* DDI Buffer Control */
7123 #define DDI_BUF_CTL_A 0x64000
7124 #define DDI_BUF_CTL_B 0x64100
7125 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
7126 #define DDI_BUF_CTL_ENABLE (1<<31)
7127 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
7128 #define DDI_BUF_EMP_MASK (0xf<<24)
7129 #define DDI_BUF_PORT_REVERSAL (1<<16)
7130 #define DDI_BUF_IS_IDLE (1<<7)
7131 #define DDI_A_4_LANES (1<<4)
7132 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
7133 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
7135 /* DDI Buffer Translations */
7136 #define DDI_BUF_TRANS_A 0x64E00
7137 #define DDI_BUF_TRANS_B 0x64E60
7138 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
7140 /* Sideband Interface (SBI) is programmed indirectly, via
7141 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7142 * which contains the payload */
7143 #define SBI_ADDR 0xC6000
7144 #define SBI_DATA 0xC6004
7145 #define SBI_CTL_STAT 0xC6008
7146 #define SBI_CTL_DEST_ICLK (0x0<<16)
7147 #define SBI_CTL_DEST_MPHY (0x1<<16)
7148 #define SBI_CTL_OP_IORD (0x2<<8)
7149 #define SBI_CTL_OP_IOWR (0x3<<8)
7150 #define SBI_CTL_OP_CRRD (0x6<<8)
7151 #define SBI_CTL_OP_CRWR (0x7<<8)
7152 #define SBI_RESPONSE_FAIL (0x1<<1)
7153 #define SBI_RESPONSE_SUCCESS (0x0<<1)
7154 #define SBI_BUSY (0x1<<0)
7155 #define SBI_READY (0x0<<0)
7158 #define SBI_SSCDIVINTPHASE6 0x0600
7159 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
7160 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
7161 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
7162 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
7163 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
7164 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
7165 #define SBI_SSCCTL 0x020c
7166 #define SBI_SSCCTL6 0x060C
7167 #define SBI_SSCCTL_PATHALT (1<<3)
7168 #define SBI_SSCCTL_DISABLE (1<<0)
7169 #define SBI_SSCAUXDIV6 0x0610
7170 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
7171 #define SBI_DBUFF0 0x2a00
7172 #define SBI_GEN0 0x1f00
7173 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
7175 /* LPT PIXCLK_GATE */
7176 #define PIXCLK_GATE 0xC6020
7177 #define PIXCLK_GATE_UNGATE (1<<0)
7178 #define PIXCLK_GATE_GATE (0<<0)
7181 #define SPLL_CTL 0x46020
7182 #define SPLL_PLL_ENABLE (1<<31)
7183 #define SPLL_PLL_SSC (1<<28)
7184 #define SPLL_PLL_NON_SSC (2<<28)
7185 #define SPLL_PLL_LCPLL (3<<28)
7186 #define SPLL_PLL_REF_MASK (3<<28)
7187 #define SPLL_PLL_FREQ_810MHz (0<<26)
7188 #define SPLL_PLL_FREQ_1350MHz (1<<26)
7189 #define SPLL_PLL_FREQ_2700MHz (2<<26)
7190 #define SPLL_PLL_FREQ_MASK (3<<26)
7193 #define WRPLL_CTL1 0x46040
7194 #define WRPLL_CTL2 0x46060
7195 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
7196 #define WRPLL_PLL_ENABLE (1<<31)
7197 #define WRPLL_PLL_SSC (1<<28)
7198 #define WRPLL_PLL_NON_SSC (2<<28)
7199 #define WRPLL_PLL_LCPLL (3<<28)
7200 #define WRPLL_PLL_REF_MASK (3<<28)
7201 /* WRPLL divider programming */
7202 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
7203 #define WRPLL_DIVIDER_REF_MASK (0xff)
7204 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
7205 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7206 #define WRPLL_DIVIDER_POST_SHIFT 8
7207 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
7208 #define WRPLL_DIVIDER_FB_SHIFT 16
7209 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
7211 /* Port clock selection */
7212 #define PORT_CLK_SEL_A 0x46100
7213 #define PORT_CLK_SEL_B 0x46104
7214 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
7215 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7216 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7217 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
7218 #define PORT_CLK_SEL_SPLL (3<<29)
7219 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
7220 #define PORT_CLK_SEL_WRPLL1 (4<<29)
7221 #define PORT_CLK_SEL_WRPLL2 (5<<29)
7222 #define PORT_CLK_SEL_NONE (7<<29)
7223 #define PORT_CLK_SEL_MASK (7<<29)
7225 /* Transcoder clock selection */
7226 #define TRANS_CLK_SEL_A 0x46140
7227 #define TRANS_CLK_SEL_B 0x46144
7228 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
7229 /* For each transcoder, we need to select the corresponding port clock */
7230 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
7231 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
7233 #define TRANSA_MSA_MISC 0x60410
7234 #define TRANSB_MSA_MISC 0x61410
7235 #define TRANSC_MSA_MISC 0x62410
7236 #define TRANS_EDP_MSA_MISC 0x6f410
7237 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
7239 #define TRANS_MSA_SYNC_CLK (1<<0)
7240 #define TRANS_MSA_6_BPC (0<<5)
7241 #define TRANS_MSA_8_BPC (1<<5)
7242 #define TRANS_MSA_10_BPC (2<<5)
7243 #define TRANS_MSA_12_BPC (3<<5)
7244 #define TRANS_MSA_16_BPC (4<<5)
7247 #define LCPLL_CTL 0x130040
7248 #define LCPLL_PLL_DISABLE (1<<31)
7249 #define LCPLL_PLL_LOCK (1<<30)
7250 #define LCPLL_CLK_FREQ_MASK (3<<26)
7251 #define LCPLL_CLK_FREQ_450 (0<<26)
7252 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7253 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7254 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
7255 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
7256 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
7257 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
7258 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
7259 #define LCPLL_CD_SOURCE_FCLK (1<<21)
7260 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7267 #define CDCLK_CTL 0x46000
7268 #define CDCLK_FREQ_SEL_MASK (3<<26)
7269 #define CDCLK_FREQ_450_432 (0<<26)
7270 #define CDCLK_FREQ_540 (1<<26)
7271 #define CDCLK_FREQ_337_308 (2<<26)
7272 #define CDCLK_FREQ_675_617 (3<<26)
7273 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7275 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7276 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7277 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7278 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7279 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
7280 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7283 #define LCPLL1_CTL 0x46010
7284 #define LCPLL2_CTL 0x46014
7285 #define LCPLL_PLL_ENABLE (1<<31)
7288 #define DPLL_CTRL1 0x6C058
7289 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7290 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
7291 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7292 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7293 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
7294 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
7295 #define DPLL_CTRL1_LINK_RATE_2700 0
7296 #define DPLL_CTRL1_LINK_RATE_1350 1
7297 #define DPLL_CTRL1_LINK_RATE_810 2
7298 #define DPLL_CTRL1_LINK_RATE_1620 3
7299 #define DPLL_CTRL1_LINK_RATE_1080 4
7300 #define DPLL_CTRL1_LINK_RATE_2160 5
7303 #define DPLL_CTRL2 0x6C05C
7304 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
7305 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
7306 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
7307 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
7308 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7311 #define DPLL_STATUS 0x6C060
7312 #define DPLL_LOCK(id) (1<<((id)*8))
7315 #define DPLL1_CFGCR1 0x6C040
7316 #define DPLL2_CFGCR1 0x6C048
7317 #define DPLL3_CFGCR1 0x6C050
7318 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7319 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7320 #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
7321 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7323 #define DPLL1_CFGCR2 0x6C044
7324 #define DPLL2_CFGCR2 0x6C04C
7325 #define DPLL3_CFGCR2 0x6C054
7326 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7327 #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
7328 #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
7329 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
7330 #define DPLL_CFGCR2_KDIV(x) (x<<5)
7331 #define DPLL_CFGCR2_KDIV_5 (0<<5)
7332 #define DPLL_CFGCR2_KDIV_2 (1<<5)
7333 #define DPLL_CFGCR2_KDIV_3 (2<<5)
7334 #define DPLL_CFGCR2_KDIV_1 (3<<5)
7335 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
7336 #define DPLL_CFGCR2_PDIV(x) (x<<2)
7337 #define DPLL_CFGCR2_PDIV_1 (0<<2)
7338 #define DPLL_CFGCR2_PDIV_2 (1<<2)
7339 #define DPLL_CFGCR2_PDIV_3 (2<<2)
7340 #define DPLL_CFGCR2_PDIV_7 (4<<2)
7341 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7343 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
7344 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
7346 /* BXT display engine PLL */
7347 #define BXT_DE_PLL_CTL 0x6d000
7348 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7349 #define BXT_DE_PLL_RATIO_MASK 0xff
7351 #define BXT_DE_PLL_ENABLE 0x46070
7352 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7353 #define BXT_DE_PLL_LOCK (1 << 30)
7356 #define DC_STATE_EN 0x45504
7357 #define DC_STATE_EN_UPTO_DC5 (1<<0)
7358 #define DC_STATE_EN_DC9 (1<<3)
7359 #define DC_STATE_EN_UPTO_DC6 (2<<0)
7360 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7362 #define DC_STATE_DEBUG 0x45520
7363 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7365 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7366 * since on HSW we can't write to it using I915_WRITE. */
7367 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7368 #define D_COMP_BDW 0x138144
7369 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7370 #define D_COMP_COMP_FORCE (1<<8)
7371 #define D_COMP_COMP_DISABLE (1<<0)
7373 /* Pipe WM_LINETIME - watermark line time */
7374 #define PIPE_WM_LINETIME_A 0x45270
7375 #define PIPE_WM_LINETIME_B 0x45274
7376 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
7378 #define PIPE_WM_LINETIME_MASK (0x1ff)
7379 #define PIPE_WM_LINETIME_TIME(x) ((x))
7380 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
7381 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
7384 #define SFUSE_STRAP 0xc2014
7385 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
7386 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
7387 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7388 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7389 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
7391 #define WM_MISC 0x45260
7392 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7394 #define WM_DBG 0x45280
7395 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7396 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7397 #define WM_DBG_DISALLOW_SPRITE (1<<2)
7400 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7401 #define _PIPE_A_CSC_COEFF_BY 0x49014
7402 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7403 #define _PIPE_A_CSC_COEFF_BU 0x4901c
7404 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7405 #define _PIPE_A_CSC_COEFF_BV 0x49024
7406 #define _PIPE_A_CSC_MODE 0x49028
7407 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7408 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7409 #define CSC_MODE_YUV_TO_RGB (1 << 0)
7410 #define _PIPE_A_CSC_PREOFF_HI 0x49030
7411 #define _PIPE_A_CSC_PREOFF_ME 0x49034
7412 #define _PIPE_A_CSC_PREOFF_LO 0x49038
7413 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
7414 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
7415 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
7417 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7418 #define _PIPE_B_CSC_COEFF_BY 0x49114
7419 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7420 #define _PIPE_B_CSC_COEFF_BU 0x4911c
7421 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7422 #define _PIPE_B_CSC_COEFF_BV 0x49124
7423 #define _PIPE_B_CSC_MODE 0x49128
7424 #define _PIPE_B_CSC_PREOFF_HI 0x49130
7425 #define _PIPE_B_CSC_PREOFF_ME 0x49134
7426 #define _PIPE_B_CSC_PREOFF_LO 0x49138
7427 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
7428 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
7429 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
7431 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7432 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7433 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7434 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7435 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7436 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7437 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7438 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7439 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7440 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7441 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7442 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7443 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7445 /* MIPI DSI registers */
7447 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
7449 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
7450 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7451 #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7452 #define DPI_ENABLE (1 << 31) /* A + C */
7453 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7454 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
7455 #define DUAL_LINK_MODE_SHIFT 26
7456 #define DUAL_LINK_MODE_MASK (1 << 26)
7457 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7458 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
7459 #define DITHERING_ENABLE (1 << 25) /* A + C */
7460 #define FLOPPED_HSTX (1 << 23)
7461 #define DE_INVERT (1 << 19) /* XXX */
7462 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7463 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7464 #define AFE_LATCHOUT (1 << 17)
7465 #define LP_OUTPUT_HOLD (1 << 16)
7466 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7467 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7468 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7469 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
7471 #define CSB_MASK (3 << 9)
7472 #define CSB_20MHZ (0 << 9)
7473 #define CSB_10MHZ (1 << 9)
7474 #define CSB_40MHZ (2 << 9)
7475 #define BANDGAP_MASK (1 << 8)
7476 #define BANDGAP_PNW_CIRCUIT (0 << 8)
7477 #define BANDGAP_LNC_CIRCUIT (1 << 8)
7478 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7479 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
7480 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
7481 #define TEARING_EFFECT_SHIFT 2 /* A + C */
7482 #define TEARING_EFFECT_MASK (3 << 2)
7483 #define TEARING_EFFECT_OFF (0 << 2)
7484 #define TEARING_EFFECT_DSI (1 << 2)
7485 #define TEARING_EFFECT_GPIO (2 << 2)
7486 #define LANE_CONFIGURATION_SHIFT 0
7487 #define LANE_CONFIGURATION_MASK (3 << 0)
7488 #define LANE_CONFIGURATION_4LANE (0 << 0)
7489 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
7490 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
7492 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
7493 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
7494 #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \
7495 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
7496 #define TEARING_EFFECT_DELAY_SHIFT 0
7497 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
7499 /* XXX: all bits reserved */
7500 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
7502 /* MIPI DSI Controller and D-PHY registers */
7504 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
7505 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
7506 #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \
7507 _MIPIC_DEVICE_READY)
7508 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
7509 #define ULPS_STATE_MASK (3 << 1)
7510 #define ULPS_STATE_ENTER (2 << 1)
7511 #define ULPS_STATE_EXIT (1 << 1)
7512 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
7513 #define DEVICE_READY (1 << 0)
7515 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
7516 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
7517 #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \
7519 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
7520 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
7521 #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \
7523 #define TEARING_EFFECT (1 << 31)
7524 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
7525 #define GEN_READ_DATA_AVAIL (1 << 29)
7526 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
7527 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
7528 #define RX_PROT_VIOLATION (1 << 26)
7529 #define RX_INVALID_TX_LENGTH (1 << 25)
7530 #define ACK_WITH_NO_ERROR (1 << 24)
7531 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
7532 #define LP_RX_TIMEOUT (1 << 22)
7533 #define HS_TX_TIMEOUT (1 << 21)
7534 #define DPI_FIFO_UNDERRUN (1 << 20)
7535 #define LOW_CONTENTION (1 << 19)
7536 #define HIGH_CONTENTION (1 << 18)
7537 #define TXDSI_VC_ID_INVALID (1 << 17)
7538 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
7539 #define TXCHECKSUM_ERROR (1 << 15)
7540 #define TXECC_MULTIBIT_ERROR (1 << 14)
7541 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
7542 #define TXFALSE_CONTROL_ERROR (1 << 12)
7543 #define RXDSI_VC_ID_INVALID (1 << 11)
7544 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
7545 #define RXCHECKSUM_ERROR (1 << 9)
7546 #define RXECC_MULTIBIT_ERROR (1 << 8)
7547 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
7548 #define RXFALSE_CONTROL_ERROR (1 << 6)
7549 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
7550 #define RX_LP_TX_SYNC_ERROR (1 << 4)
7551 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
7552 #define RXEOT_SYNC_ERROR (1 << 2)
7553 #define RXSOT_SYNC_ERROR (1 << 1)
7554 #define RXSOT_ERROR (1 << 0)
7556 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
7557 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7558 #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \
7559 _MIPIC_DSI_FUNC_PRG)
7560 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
7561 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
7562 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
7563 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
7564 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
7565 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
7566 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
7567 #define VID_MODE_FORMAT_MASK (0xf << 7)
7568 #define VID_MODE_NOT_SUPPORTED (0 << 7)
7569 #define VID_MODE_FORMAT_RGB565 (1 << 7)
7570 #define VID_MODE_FORMAT_RGB666 (2 << 7)
7571 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
7572 #define VID_MODE_FORMAT_RGB888 (4 << 7)
7573 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
7574 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
7575 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
7576 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
7577 #define DATA_LANES_PRG_REG_SHIFT 0
7578 #define DATA_LANES_PRG_REG_MASK (7 << 0)
7580 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
7581 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7582 #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \
7583 _MIPIC_HS_TX_TIMEOUT)
7584 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
7586 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
7587 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7588 #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \
7589 _MIPIC_LP_RX_TIMEOUT)
7590 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
7592 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
7593 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7594 #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \
7595 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
7596 #define TURN_AROUND_TIMEOUT_MASK 0x3f
7598 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
7599 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7600 #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \
7601 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
7602 #define DEVICE_RESET_TIMER_MASK 0xffff
7604 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
7605 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7606 #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \
7607 _MIPIC_DPI_RESOLUTION)
7608 #define VERTICAL_ADDRESS_SHIFT 16
7609 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
7610 #define HORIZONTAL_ADDRESS_SHIFT 0
7611 #define HORIZONTAL_ADDRESS_MASK 0xffff
7613 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
7614 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7615 #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \
7616 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
7617 #define DBI_FIFO_EMPTY_HALF (0 << 0)
7618 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
7619 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
7621 /* regs below are bits 15:0 */
7622 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
7623 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7624 #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7625 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
7627 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
7628 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7629 #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \
7632 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
7633 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7634 #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \
7637 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
7638 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7639 #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \
7640 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
7642 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
7643 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7644 #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \
7645 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
7647 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
7648 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7649 #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \
7652 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
7653 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7654 #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \
7657 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
7658 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7659 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \
7660 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
7662 /* regs above are bits 15:0 */
7664 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
7665 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7666 #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \
7668 #define DPI_LP_MODE (1 << 6)
7669 #define BACKLIGHT_OFF (1 << 5)
7670 #define BACKLIGHT_ON (1 << 4)
7671 #define COLOR_MODE_OFF (1 << 3)
7672 #define COLOR_MODE_ON (1 << 2)
7673 #define TURN_ON (1 << 1)
7674 #define SHUTDOWN (1 << 0)
7676 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
7677 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7678 #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \
7680 #define COMMAND_BYTE_SHIFT 0
7681 #define COMMAND_BYTE_MASK (0x3f << 0)
7683 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
7684 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7685 #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \
7687 #define MASTER_INIT_TIMER_SHIFT 0
7688 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
7690 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
7691 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7692 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \
7693 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
7694 #define MAX_RETURN_PKT_SIZE_SHIFT 0
7695 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
7697 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
7698 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7699 #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \
7700 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
7701 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
7702 #define DISABLE_VIDEO_BTA (1 << 3)
7703 #define IP_TG_CONFIG (1 << 2)
7704 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
7705 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
7706 #define VIDEO_MODE_BURST (3 << 0)
7708 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
7709 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7710 #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \
7712 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
7713 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
7714 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
7715 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
7716 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
7717 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
7718 #define CLOCKSTOP (1 << 1)
7719 #define EOT_DISABLE (1 << 0)
7721 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
7722 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7723 #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \
7725 #define LP_BYTECLK_SHIFT 0
7726 #define LP_BYTECLK_MASK (0xffff << 0)
7729 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
7730 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7731 #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \
7735 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
7736 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7737 #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \
7740 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
7741 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7742 #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \
7744 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
7745 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7746 #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \
7748 #define LONG_PACKET_WORD_COUNT_SHIFT 8
7749 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
7750 #define SHORT_PACKET_PARAM_SHIFT 8
7751 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
7752 #define VIRTUAL_CHANNEL_SHIFT 6
7753 #define VIRTUAL_CHANNEL_MASK (3 << 6)
7754 #define DATA_TYPE_SHIFT 0
7755 #define DATA_TYPE_MASK (3f << 0)
7756 /* data type values, see include/video/mipi_display.h */
7758 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
7759 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
7760 #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \
7761 _MIPIC_GEN_FIFO_STAT)
7762 #define DPI_FIFO_EMPTY (1 << 28)
7763 #define DBI_FIFO_EMPTY (1 << 27)
7764 #define LP_CTRL_FIFO_EMPTY (1 << 26)
7765 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
7766 #define LP_CTRL_FIFO_FULL (1 << 24)
7767 #define HS_CTRL_FIFO_EMPTY (1 << 18)
7768 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
7769 #define HS_CTRL_FIFO_FULL (1 << 16)
7770 #define LP_DATA_FIFO_EMPTY (1 << 10)
7771 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
7772 #define LP_DATA_FIFO_FULL (1 << 8)
7773 #define HS_DATA_FIFO_EMPTY (1 << 2)
7774 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
7775 #define HS_DATA_FIFO_FULL (1 << 0)
7777 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
7778 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
7779 #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \
7780 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
7781 #define DBI_HS_LP_MODE_MASK (1 << 0)
7782 #define DBI_LP_MODE (1 << 0)
7783 #define DBI_HS_MODE (0 << 0)
7785 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
7786 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
7787 #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \
7789 #define EXIT_ZERO_COUNT_SHIFT 24
7790 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
7791 #define TRAIL_COUNT_SHIFT 16
7792 #define TRAIL_COUNT_MASK (0x1f << 16)
7793 #define CLK_ZERO_COUNT_SHIFT 8
7794 #define CLK_ZERO_COUNT_MASK (0xff << 8)
7795 #define PREPARE_COUNT_SHIFT 0
7796 #define PREPARE_COUNT_MASK (0x3f << 0)
7799 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
7800 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
7801 #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \
7804 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7806 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7808 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \
7809 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
7810 #define LP_HS_SSW_CNT_SHIFT 16
7811 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
7812 #define HS_LP_PWR_SW_CNT_SHIFT 0
7813 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
7815 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
7816 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
7817 #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \
7818 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
7819 #define STOP_STATE_STALL_COUNTER_SHIFT 0
7820 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
7822 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
7823 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
7824 #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \
7825 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
7826 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
7827 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7828 #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \
7829 _MIPIC_INTR_EN_REG_1)
7830 #define RX_CONTENTION_DETECTED (1 << 0)
7832 /* XXX: only pipe A ?!? */
7833 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
7834 #define DBI_TYPEC_ENABLE (1 << 31)
7835 #define DBI_TYPEC_WIP (1 << 30)
7836 #define DBI_TYPEC_OPTION_SHIFT 28
7837 #define DBI_TYPEC_OPTION_MASK (3 << 28)
7838 #define DBI_TYPEC_FREQ_SHIFT 24
7839 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
7840 #define DBI_TYPEC_OVERRIDE (1 << 8)
7841 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
7842 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
7845 /* MIPI adapter registers */
7847 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
7848 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7849 #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \
7851 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
7852 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
7853 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
7854 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
7855 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
7856 #define READ_REQUEST_PRIORITY_SHIFT 3
7857 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
7858 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
7859 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
7860 #define RGB_FLIP_TO_BGR (1 << 2)
7862 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
7863 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7864 #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
7865 _MIPIC_DATA_ADDRESS)
7866 #define DATA_MEM_ADDRESS_SHIFT 5
7867 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
7868 #define DATA_VALID (1 << 0)
7870 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
7871 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7872 #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \
7874 #define DATA_LENGTH_SHIFT 0
7875 #define DATA_LENGTH_MASK (0xfffff << 0)
7877 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
7878 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7879 #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \
7880 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
7881 #define COMMAND_MEM_ADDRESS_SHIFT 5
7882 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
7883 #define AUTO_PWG_ENABLE (1 << 2)
7884 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
7885 #define COMMAND_VALID (1 << 0)
7887 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
7888 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7889 #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \
7890 _MIPIC_COMMAND_LENGTH)
7891 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
7892 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
7894 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
7895 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7896 #define MIPI_READ_DATA_RETURN(port, n) \
7897 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \
7898 + 4 * (n)) /* n: 0...7 */
7900 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
7901 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7902 #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \
7903 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
7904 #define READ_DATA_VALID(n) (1 << (n))
7906 /* For UMS only (deprecated): */
7907 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7908 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
7910 /* MOCS (Memory Object Control State) registers */
7911 #define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */
7913 #define GEN9_GFX_MOCS_0 0xc800 /* Graphics MOCS base register*/
7914 #define GEN9_MFX0_MOCS_0 0xc900 /* Media 0 MOCS base register*/
7915 #define GEN9_MFX1_MOCS_0 0xca00 /* Media 1 MOCS base register*/
7916 #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/
7917 #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/
7919 #endif /* _I915_REG_H_ */
projects / linux-drm-fsl-dcu.git / blob