drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_vgpu.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  71  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  72  * parameter encapsulating all metadata required to implement a view.
  73  *
  74  * As a helper for callers which are only interested in the normal view,
  75  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  76  * GEM API functions, the ones not taking the view parameter, are operating on,
  77  * or with the normal GGTT view.
  78  *
  79  * Code wanting to add or use a new GGTT view needs to:
  80  *
  81  * 1. Add a new enum with a suitable name.
  82  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  83  * 3. Add support to i915_get_vma_pages().
  84  *
  85  * New views are required to build a scatter-gather table from within the
  86  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  87  * exists for the lifetime of an VMA.
  88  *
  89  * Core API is designed to have copy semantics which means that passed in
  90  * struct i915_ggtt_view does not need to be persistent (left around after
  91  * calling the core API functions).
  92  *
  93  */
  94
  95 static int
  96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  97
  98 const struct i915_ggtt_view i915_ggtt_view_normal;
  99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 100         .type = I915_GGTT_VIEW_ROTATED
 101 };
 102
 103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 104 {
 105         bool has_aliasing_ppgtt;
 106         bool has_full_ppgtt;
 107
 108         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 109         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 110
 111         if (intel_vgpu_active(dev))
 112                 has_full_ppgtt = false; /* emulation is too hard */
 113
 114         /*
 115          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 116          * execlists, the sole mechanism available to submit work.
 117          */
 118         if (INTEL_INFO(dev)->gen < 9 &&
 119             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 120                 return 0;
 121
 122         if (enable_ppgtt == 1)
 123                 return 1;
 124
 125         if (enable_ppgtt == 2 && has_full_ppgtt)
 126                 return 2;
 127
 128 #ifdef CONFIG_INTEL_IOMMU
 129         /* Disable ppgtt on SNB if VT-d is on. */
 130         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 131                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 132                 return 0;
 133         }
 134 #endif
 135
 136         /* Early VLV doesn't have this */
 137         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 138             dev->pdev->revision < 0xb) {
 139                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 140                 return 0;
 141         }
 142
 143         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 144                 return 2;
 145         else
 146                 return has_aliasing_ppgtt ? 1 : 0;
 147 }
 148
 149 static int ppgtt_bind_vma(struct i915_vma *vma,
 150                           enum i915_cache_level cache_level,
 151                           u32 unused)
 152 {
 153         u32 pte_flags = 0;
 154
 155         /* Currently applicable only to VLV */
 156         if (vma->obj->gt_ro)
 157                 pte_flags |= PTE_READ_ONLY;
 158
 159         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 160                                 cache_level, pte_flags);
 161
 162         return 0;
 163 }
 164
 165 static void ppgtt_unbind_vma(struct i915_vma *vma)
 166 {
 167         vma->vm->clear_range(vma->vm,
 168                              vma->node.start,
 169                              vma->obj->base.size,
 170                              true);
 171 }
 172
 173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 174                                   enum i915_cache_level level,
 175                                   bool valid)
 176 {
 177         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 178         pte |= addr;
 179
 180         switch (level) {
 181         case I915_CACHE_NONE:
 182                 pte |= PPAT_UNCACHED_INDEX;
 183                 break;
 184         case I915_CACHE_WT:
 185                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 186                 break;
 187         default:
 188                 pte |= PPAT_CACHED_INDEX;
 189                 break;
 190         }
 191
 192         return pte;
 193 }
 194
 195 static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
 196                                   dma_addr_t addr,
 197                                   enum i915_cache_level level)
 198 {
 199         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 200         pde |= addr;
 201         if (level != I915_CACHE_NONE)
 202                 pde |= PPAT_CACHED_PDE_INDEX;
 203         else
 204                 pde |= PPAT_UNCACHED_INDEX;
 205         return pde;
 206 }
 207
 208 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 209                                  enum i915_cache_level level,
 210                                  bool valid, u32 unused)
 211 {
 212         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 213         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 214
 215         switch (level) {
 216         case I915_CACHE_L3_LLC:
 217         case I915_CACHE_LLC:
 218                 pte |= GEN6_PTE_CACHE_LLC;
 219                 break;
 220         case I915_CACHE_NONE:
 221                 pte |= GEN6_PTE_UNCACHED;
 222                 break;
 223         default:
 224                 MISSING_CASE(level);
 225         }
 226
 227         return pte;
 228 }
 229
 230 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 231                                  enum i915_cache_level level,
 232                                  bool valid, u32 unused)
 233 {
 234         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 235         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 236
 237         switch (level) {
 238         case I915_CACHE_L3_LLC:
 239                 pte |= GEN7_PTE_CACHE_L3_LLC;
 240                 break;
 241         case I915_CACHE_LLC:
 242                 pte |= GEN6_PTE_CACHE_LLC;
 243                 break;
 244         case I915_CACHE_NONE:
 245                 pte |= GEN6_PTE_UNCACHED;
 246                 break;
 247         default:
 248                 MISSING_CASE(level);
 249         }
 250
 251         return pte;
 252 }
 253
 254 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 255                                  enum i915_cache_level level,
 256                                  bool valid, u32 flags)
 257 {
 258         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 259         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 260
 261         if (!(flags & PTE_READ_ONLY))
 262                 pte |= BYT_PTE_WRITEABLE;
 263
 264         if (level != I915_CACHE_NONE)
 265                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 266
 267         return pte;
 268 }
 269
 270 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 271                                  enum i915_cache_level level,
 272                                  bool valid, u32 unused)
 273 {
 274         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 275         pte |= HSW_PTE_ADDR_ENCODE(addr);
 276
 277         if (level != I915_CACHE_NONE)
 278                 pte |= HSW_WB_LLC_AGE3;
 279
 280         return pte;
 281 }
 282
 283 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 284                                   enum i915_cache_level level,
 285                                   bool valid, u32 unused)
 286 {
 287         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 288         pte |= HSW_PTE_ADDR_ENCODE(addr);
 289
 290         switch (level) {
 291         case I915_CACHE_NONE:
 292                 break;
 293         case I915_CACHE_WT:
 294                 pte |= HSW_WT_ELLC_LLC_AGE3;
 295                 break;
 296         default:
 297                 pte |= HSW_WB_ELLC_LLC_AGE3;
 298                 break;
 299         }
 300
 301         return pte;
 302 }
 303
 304 #define i915_dma_unmap_single(px, dev) \
 305         __i915_dma_unmap_single((px)->daddr, dev)
 306
 307 static void __i915_dma_unmap_single(dma_addr_t daddr,
 308                                     struct drm_device *dev)
 309 {
 310         struct device *device = &dev->pdev->dev;
 311
 312         dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 313 }
 314
 315 /**
 316  * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
 317  * @px: Page table/dir/etc to get a DMA map for
 318  * @dev:        drm device
 319  *
 320  * Page table allocations are unified across all gens. They always require a
 321  * single 4k allocation, as well as a DMA mapping. If we keep the structs
 322  * symmetric here, the simple macro covers us for every page table type.
 323  *
 324  * Return: 0 if success.
 325  */
 326 #define i915_dma_map_single(px, dev) \
 327         i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
 328
 329 static int i915_dma_map_page_single(struct page *page,
 330                                     struct drm_device *dev,
 331                                     dma_addr_t *daddr)
 332 {
 333         struct device *device = &dev->pdev->dev;
 334
 335         *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 336         if (dma_mapping_error(device, *daddr))
 337                 return -ENOMEM;
 338
 339         return 0;
 340 }
 341
 342 static void unmap_and_free_pt(struct i915_page_table *pt,
 343                                struct drm_device *dev)
 344 {
 345         if (WARN_ON(!pt->page))
 346                 return;
 347
 348         i915_dma_unmap_single(pt, dev);
 349         __free_page(pt->page);
 350         kfree(pt->used_ptes);
 351         kfree(pt);
 352 }
 353
 354 static void gen8_initialize_pt(struct i915_address_space *vm,
 355                                struct i915_page_table *pt)
 356 {
 357         gen8_pte_t *pt_vaddr, scratch_pte;
 358         int i;
 359
 360         pt_vaddr = kmap_atomic(pt->page);
 361         scratch_pte = gen8_pte_encode(vm->scratch.addr,
 362                                       I915_CACHE_LLC, true);
 363
 364         for (i = 0; i < GEN8_PTES; i++)
 365                 pt_vaddr[i] = scratch_pte;
 366
 367         if (!HAS_LLC(vm->dev))
 368                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 369         kunmap_atomic(pt_vaddr);
 370 }
 371
 372 static struct i915_page_table *alloc_pt_single(struct drm_device *dev)
 373 {
 374         struct i915_page_table *pt;
 375         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 376                 GEN8_PTES : GEN6_PTES;
 377         int ret = -ENOMEM;
 378
 379         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 380         if (!pt)
 381                 return ERR_PTR(-ENOMEM);
 382
 383         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 384                                 GFP_KERNEL);
 385
 386         if (!pt->used_ptes)
 387                 goto fail_bitmap;
 388
 389         pt->page = alloc_page(GFP_KERNEL);
 390         if (!pt->page)
 391                 goto fail_page;
 392
 393         ret = i915_dma_map_single(pt, dev);
 394         if (ret)
 395                 goto fail_dma;
 396
 397         return pt;
 398
 399 fail_dma:
 400         __free_page(pt->page);
 401 fail_page:
 402         kfree(pt->used_ptes);
 403 fail_bitmap:
 404         kfree(pt);
 405
 406         return ERR_PTR(ret);
 407 }
 408
 409 static void unmap_and_free_pd(struct i915_page_directory *pd,
 410                               struct drm_device *dev)
 411 {
 412         if (pd->page) {
 413                 i915_dma_unmap_single(pd, dev);
 414                 __free_page(pd->page);
 415                 kfree(pd->used_pdes);
 416                 kfree(pd);
 417         }
 418 }
 419
 420 static struct i915_page_directory *alloc_pd_single(struct drm_device *dev)
 421 {
 422         struct i915_page_directory *pd;
 423         int ret = -ENOMEM;
 424
 425         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 426         if (!pd)
 427                 return ERR_PTR(-ENOMEM);
 428
 429         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 430                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 431         if (!pd->used_pdes)
 432                 goto free_pd;
 433
 434         pd->page = alloc_page(GFP_KERNEL);
 435         if (!pd->page)
 436                 goto free_bitmap;
 437
 438         ret = i915_dma_map_single(pd, dev);
 439         if (ret)
 440                 goto free_page;
 441
 442         return pd;
 443
 444 free_page:
 445         __free_page(pd->page);
 446 free_bitmap:
 447         kfree(pd->used_pdes);
 448 free_pd:
 449         kfree(pd);
 450
 451         return ERR_PTR(ret);
 452 }
 453
 454 /* Broadwell Page Directory Pointer Descriptors */
 455 static int gen8_write_pdp(struct intel_engine_cs *ring,
 456                           unsigned entry,
 457                           dma_addr_t addr)
 458 {
 459         int ret;
 460
 461         BUG_ON(entry >= 4);
 462
 463         ret = intel_ring_begin(ring, 6);
 464         if (ret)
 465                 return ret;
 466
 467         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 468         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 469         intel_ring_emit(ring, upper_32_bits(addr));
 470         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 471         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 472         intel_ring_emit(ring, lower_32_bits(addr));
 473         intel_ring_advance(ring);
 474
 475         return 0;
 476 }
 477
 478 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 479                           struct intel_engine_cs *ring)
 480 {
 481         int i, ret;
 482
 483         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 484                 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
 485                 dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
 486                 /* The page directory might be NULL, but we need to clear out
 487                  * whatever the previous context might have used. */
 488                 ret = gen8_write_pdp(ring, i, pd_daddr);
 489                 if (ret)
 490                         return ret;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 497                                    uint64_t start,
 498                                    uint64_t length,
 499                                    bool use_scratch)
 500 {
 501         struct i915_hw_ppgtt *ppgtt =
 502                 container_of(vm, struct i915_hw_ppgtt, base);
 503         gen8_pte_t *pt_vaddr, scratch_pte;
 504         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 505         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 506         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 507         unsigned num_entries = length >> PAGE_SHIFT;
 508         unsigned last_pte, i;
 509
 510         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 511                                       I915_CACHE_LLC, use_scratch);
 512
 513         while (num_entries) {
 514                 struct i915_page_directory *pd;
 515                 struct i915_page_table *pt;
 516                 struct page *page_table;
 517
 518                 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
 519                         continue;
 520
 521                 pd = ppgtt->pdp.page_directory[pdpe];
 522
 523                 if (WARN_ON(!pd->page_table[pde]))
 524                         continue;
 525
 526                 pt = pd->page_table[pde];
 527
 528                 if (WARN_ON(!pt->page))
 529                         continue;
 530
 531                 page_table = pt->page;
 532
 533                 last_pte = pte + num_entries;
 534                 if (last_pte > GEN8_PTES)
 535                         last_pte = GEN8_PTES;
 536
 537                 pt_vaddr = kmap_atomic(page_table);
 538
 539                 for (i = pte; i < last_pte; i++) {
 540                         pt_vaddr[i] = scratch_pte;
 541                         num_entries--;
 542                 }
 543
 544                 if (!HAS_LLC(ppgtt->base.dev))
 545                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 546                 kunmap_atomic(pt_vaddr);
 547
 548                 pte = 0;
 549                 if (++pde == I915_PDES) {
 550                         pdpe++;
 551                         pde = 0;
 552                 }
 553         }
 554 }
 555
 556 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 557                                       struct sg_table *pages,
 558                                       uint64_t start,
 559                                       enum i915_cache_level cache_level, u32 unused)
 560 {
 561         struct i915_hw_ppgtt *ppgtt =
 562                 container_of(vm, struct i915_hw_ppgtt, base);
 563         gen8_pte_t *pt_vaddr;
 564         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 565         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 566         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 567         struct sg_page_iter sg_iter;
 568
 569         pt_vaddr = NULL;
 570
 571         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 572                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
 573                         break;
 574
 575                 if (pt_vaddr == NULL) {
 576                         struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
 577                         struct i915_page_table *pt = pd->page_table[pde];
 578                         struct page *page_table = pt->page;
 579
 580                         pt_vaddr = kmap_atomic(page_table);
 581                 }
 582
 583                 pt_vaddr[pte] =
 584                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 585                                         cache_level, true);
 586                 if (++pte == GEN8_PTES) {
 587                         if (!HAS_LLC(ppgtt->base.dev))
 588                                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 589                         kunmap_atomic(pt_vaddr);
 590                         pt_vaddr = NULL;
 591                         if (++pde == I915_PDES) {
 592                                 pdpe++;
 593                                 pde = 0;
 594                         }
 595                         pte = 0;
 596                 }
 597         }
 598         if (pt_vaddr) {
 599                 if (!HAS_LLC(ppgtt->base.dev))
 600                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 601                 kunmap_atomic(pt_vaddr);
 602         }
 603 }
 604
 605 static void __gen8_do_map_pt(gen8_pde_t * const pde,
 606                              struct i915_page_table *pt,
 607                              struct drm_device *dev)
 608 {
 609         gen8_pde_t entry =
 610                 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
 611         *pde = entry;
 612 }
 613
 614 static void gen8_initialize_pd(struct i915_address_space *vm,
 615                                struct i915_page_directory *pd)
 616 {
 617         struct i915_hw_ppgtt *ppgtt =
 618                         container_of(vm, struct i915_hw_ppgtt, base);
 619         gen8_pde_t *page_directory;
 620         struct i915_page_table *pt;
 621         int i;
 622
 623         page_directory = kmap_atomic(pd->page);
 624         pt = ppgtt->scratch_pt;
 625         for (i = 0; i < I915_PDES; i++)
 626                 /* Map the PDE to the page table */
 627                 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
 628
 629         if (!HAS_LLC(vm->dev))
 630                 drm_clflush_virt_range(page_directory, PAGE_SIZE);
 631         kunmap_atomic(page_directory);
 632 }
 633
 634 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
 635 {
 636         int i;
 637
 638         if (!pd->page)
 639                 return;
 640
 641         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 642                 if (WARN_ON(!pd->page_table[i]))
 643                         continue;
 644
 645                 unmap_and_free_pt(pd->page_table[i], dev);
 646                 pd->page_table[i] = NULL;
 647         }
 648 }
 649
 650 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 651 {
 652         struct i915_hw_ppgtt *ppgtt =
 653                 container_of(vm, struct i915_hw_ppgtt, base);
 654         int i;
 655
 656         for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
 657                 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
 658                         continue;
 659
 660                 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 661                 unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 662         }
 663
 664         unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev);
 665         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
 666 }
 667
 668 /**
 669  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 670  * @ppgtt:      Master ppgtt structure.
 671  * @pd:         Page directory for this address range.
 672  * @start:      Starting virtual address to begin allocations.
 673  * @length      Size of the allocations.
 674  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 675  *              caller to free on error.
 676  *
 677  * Allocate the required number of page tables. Extremely similar to
 678  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
 679  * the page directory boundary (instead of the page directory pointer). That
 680  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
 681  * possible, and likely that the caller will need to use multiple calls of this
 682  * function to achieve the appropriate allocation.
 683  *
 684  * Return: 0 if success; negative error code otherwise.
 685  */
 686 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
 687                                      struct i915_page_directory *pd,
 688                                      uint64_t start,
 689                                      uint64_t length,
 690                                      unsigned long *new_pts)
 691 {
 692         struct drm_device *dev = ppgtt->base.dev;
 693         struct i915_page_table *pt;
 694         uint64_t temp;
 695         uint32_t pde;
 696
 697         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 698                 /* Don't reallocate page tables */
 699                 if (pt) {
 700                         /* Scratch is never allocated this way */
 701                         WARN_ON(pt == ppgtt->scratch_pt);
 702                         continue;
 703                 }
 704
 705                 pt = alloc_pt_single(dev);
 706                 if (IS_ERR(pt))
 707                         goto unwind_out;
 708
 709                 gen8_initialize_pt(&ppgtt->base, pt);
 710                 pd->page_table[pde] = pt;
 711                 set_bit(pde, new_pts);
 712         }
 713
 714         return 0;
 715
 716 unwind_out:
 717         for_each_set_bit(pde, new_pts, I915_PDES)
 718                 unmap_and_free_pt(pd->page_table[pde], dev);
 719
 720         return -ENOMEM;
 721 }
 722
 723 /**
 724  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
 725  * @ppgtt:      Master ppgtt structure.
 726  * @pdp:        Page directory pointer for this address range.
 727  * @start:      Starting virtual address to begin allocations.
 728  * @length      Size of the allocations.
 729  * @new_pds     Bitmap set by function with new allocations. Likely used by the
 730  *              caller to free on error.
 731  *
 732  * Allocate the required number of page directories starting at the pde index of
 733  * @start, and ending at the pde index @start + @length. This function will skip
 734  * over already allocated page directories within the range, and only allocate
 735  * new ones, setting the appropriate pointer within the pdp as well as the
 736  * correct position in the bitmap @new_pds.
 737  *
 738  * The function will only allocate the pages within the range for a give page
 739  * directory pointer. In other words, if @start + @length straddles a virtually
 740  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
 741  * required by the caller, This is not currently possible, and the BUG in the
 742  * code will prevent it.
 743  *
 744  * Return: 0 if success; negative error code otherwise.
 745  */
 746 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
 747                                      struct i915_page_directory_pointer *pdp,
 748                                      uint64_t start,
 749                                      uint64_t length,
 750                                      unsigned long *new_pds)
 751 {
 752         struct drm_device *dev = ppgtt->base.dev;
 753         struct i915_page_directory *pd;
 754         uint64_t temp;
 755         uint32_t pdpe;
 756
 757         WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
 758
 759         /* FIXME: upper bound must not overflow 32 bits  */
 760         WARN_ON((start + length) > (1ULL << 32));
 761
 762         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 763                 if (pd)
 764                         continue;
 765
 766                 pd = alloc_pd_single(dev);
 767                 if (IS_ERR(pd))
 768                         goto unwind_out;
 769
 770                 gen8_initialize_pd(&ppgtt->base, pd);
 771                 pdp->page_directory[pdpe] = pd;
 772                 set_bit(pdpe, new_pds);
 773         }
 774
 775         return 0;
 776
 777 unwind_out:
 778         for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
 779                 unmap_and_free_pd(pdp->page_directory[pdpe], dev);
 780
 781         return -ENOMEM;
 782 }
 783
 784 static void
 785 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 786 {
 787         int i;
 788
 789         for (i = 0; i < GEN8_LEGACY_PDPES; i++)
 790                 kfree(new_pts[i]);
 791         kfree(new_pts);
 792         kfree(new_pds);
 793 }
 794
 795 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
 796  * of these are based on the number of PDPEs in the system.
 797  */
 798 static
 799 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 800                                          unsigned long ***new_pts)
 801 {
 802         int i;
 803         unsigned long *pds;
 804         unsigned long **pts;
 805
 806         pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
 807         if (!pds)
 808                 return -ENOMEM;
 809
 810         pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
 811         if (!pts) {
 812                 kfree(pds);
 813                 return -ENOMEM;
 814         }
 815
 816         for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 817                 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
 818                                  sizeof(unsigned long), GFP_KERNEL);
 819                 if (!pts[i])
 820                         goto err_out;
 821         }
 822
 823         *new_pds = pds;
 824         *new_pts = pts;
 825
 826         return 0;
 827
 828 err_out:
 829         free_gen8_temp_bitmaps(pds, pts);
 830         return -ENOMEM;
 831 }
 832
 833 static int gen8_alloc_va_range(struct i915_address_space *vm,
 834                                uint64_t start,
 835                                uint64_t length)
 836 {
 837         struct i915_hw_ppgtt *ppgtt =
 838                 container_of(vm, struct i915_hw_ppgtt, base);
 839         unsigned long *new_page_dirs, **new_page_tables;
 840         struct i915_page_directory *pd;
 841         const uint64_t orig_start = start;
 842         const uint64_t orig_length = length;
 843         uint64_t temp;
 844         uint32_t pdpe;
 845         int ret;
 846
 847         /* Wrap is never okay since we can only represent 48b, and we don't
 848          * actually use the other side of the canonical address space.
 849          */
 850         if (WARN_ON(start + length < start))
 851                 return -ERANGE;
 852
 853         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
 854         if (ret)
 855                 return ret;
 856
 857         /* Do the allocations first so we can easily bail out */
 858         ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
 859                                         new_page_dirs);
 860         if (ret) {
 861                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 862                 return ret;
 863         }
 864
 865         /* For every page directory referenced, allocate page tables */
 866         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 867                 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
 868                                                 new_page_tables[pdpe]);
 869                 if (ret)
 870                         goto err_out;
 871         }
 872
 873         start = orig_start;
 874         length = orig_length;
 875
 876         /* Allocations have completed successfully, so set the bitmaps, and do
 877          * the mappings. */
 878         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 879                 gen8_pde_t *const page_directory = kmap_atomic(pd->page);
 880                 struct i915_page_table *pt;
 881                 uint64_t pd_len = gen8_clamp_pd(start, length);
 882                 uint64_t pd_start = start;
 883                 uint32_t pde;
 884
 885                 /* Every pd should be allocated, we just did that above. */
 886                 WARN_ON(!pd);
 887
 888                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 889                         /* Same reasoning as pd */
 890                         WARN_ON(!pt);
 891                         WARN_ON(!pd_len);
 892                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
 893
 894                         /* Set our used ptes within the page table */
 895                         bitmap_set(pt->used_ptes,
 896                                    gen8_pte_index(pd_start),
 897                                    gen8_pte_count(pd_start, pd_len));
 898
 899                         /* Our pde is now pointing to the pagetable, pt */
 900                         set_bit(pde, pd->used_pdes);
 901
 902                         /* Map the PDE to the page table */
 903                         __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
 904
 905                         /* NB: We haven't yet mapped ptes to pages. At this
 906                          * point we're still relying on insert_entries() */
 907                 }
 908
 909                 if (!HAS_LLC(vm->dev))
 910                         drm_clflush_virt_range(page_directory, PAGE_SIZE);
 911
 912                 kunmap_atomic(page_directory);
 913
 914                 set_bit(pdpe, ppgtt->pdp.used_pdpes);
 915         }
 916
 917         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 918         return 0;
 919
 920 err_out:
 921         while (pdpe--) {
 922                 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
 923                         unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev);
 924         }
 925
 926         for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
 927                 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev);
 928
 929         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 930         return ret;
 931 }
 932
 933 /*
 934  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 935  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 936  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 937  * space.
 938  *
 939  */
 940 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 941 {
 942         ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
 943         if (IS_ERR(ppgtt->scratch_pt))
 944                 return PTR_ERR(ppgtt->scratch_pt);
 945
 946         ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev);
 947         if (IS_ERR(ppgtt->scratch_pd))
 948                 return PTR_ERR(ppgtt->scratch_pd);
 949
 950         gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
 951         gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
 952
 953         ppgtt->base.start = 0;
 954         ppgtt->base.total = 1ULL << 32;
 955         if (IS_ENABLED(CONFIG_X86_32))
 956                 /* While we have a proliferation of size_t variables
 957                  * we cannot represent the full ppgtt size on 32bit,
 958                  * so limit it to the same size as the GGTT (currently
 959                  * 2GiB).
 960                  */
 961                 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
 962         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 963         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
 964         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 965         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 966         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
 967         ppgtt->base.bind_vma = ppgtt_bind_vma;
 968
 969         ppgtt->switch_mm = gen8_mm_switch;
 970
 971         return 0;
 972 }
 973
 974 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 975 {
 976         struct i915_address_space *vm = &ppgtt->base;
 977         struct i915_page_table *unused;
 978         gen6_pte_t scratch_pte;
 979         uint32_t pd_entry;
 980         uint32_t  pte, pde, temp;
 981         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
 982
 983         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 984
 985         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
 986                 u32 expected;
 987                 gen6_pte_t *pt_vaddr;
 988                 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
 989                 pd_entry = readl(ppgtt->pd_addr + pde);
 990                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 991
 992                 if (pd_entry != expected)
 993                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 994                                    pde,
 995                                    pd_entry,
 996                                    expected);
 997                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 998
 999                 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
1000                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1001                         unsigned long va =
1002                                 (pde * PAGE_SIZE * GEN6_PTES) +
1003                                 (pte * PAGE_SIZE);
1004                         int i;
1005                         bool found = false;
1006                         for (i = 0; i < 4; i++)
1007                                 if (pt_vaddr[pte + i] != scratch_pte)
1008                                         found = true;
1009                         if (!found)
1010                                 continue;
1011
1012                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1013                         for (i = 0; i < 4; i++) {
1014                                 if (pt_vaddr[pte + i] != scratch_pte)
1015                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1016                                 else
1017                                         seq_puts(m, "  SCRATCH ");
1018                         }
1019                         seq_puts(m, "\n");
1020                 }
1021                 kunmap_atomic(pt_vaddr);
1022         }
1023 }
1024
1025 /* Write pde (index) from the page directory @pd to the page table @pt */
1026 static void gen6_write_pde(struct i915_page_directory *pd,
1027                             const int pde, struct i915_page_table *pt)
1028 {
1029         /* Caller needs to make sure the write completes if necessary */
1030         struct i915_hw_ppgtt *ppgtt =
1031                 container_of(pd, struct i915_hw_ppgtt, pd);
1032         u32 pd_entry;
1033
1034         pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
1035         pd_entry |= GEN6_PDE_VALID;
1036
1037         writel(pd_entry, ppgtt->pd_addr + pde);
1038 }
1039
1040 /* Write all the page tables found in the ppgtt structure to incrementing page
1041  * directories. */
1042 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1043                                   struct i915_page_directory *pd,
1044                                   uint32_t start, uint32_t length)
1045 {
1046         struct i915_page_table *pt;
1047         uint32_t pde, temp;
1048
1049         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1050                 gen6_write_pde(pd, pde, pt);
1051
1052         /* Make sure write is complete before other code can use this page
1053          * table. Also require for WC mapped PTEs */
1054         readl(dev_priv->gtt.gsm);
1055 }
1056
1057 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1058 {
1059         BUG_ON(ppgtt->pd.pd_offset & 0x3f);
1060
1061         return (ppgtt->pd.pd_offset / 64) << 16;
1062 }
1063
1064 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1065                          struct intel_engine_cs *ring)
1066 {
1067         int ret;
1068
1069         /* NB: TLBs must be flushed and invalidated before a switch */
1070         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1071         if (ret)
1072                 return ret;
1073
1074         ret = intel_ring_begin(ring, 6);
1075         if (ret)
1076                 return ret;
1077
1078         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1079         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1080         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1081         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1082         intel_ring_emit(ring, get_pd_offset(ppgtt));
1083         intel_ring_emit(ring, MI_NOOP);
1084         intel_ring_advance(ring);
1085
1086         return 0;
1087 }
1088
1089 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1090                           struct intel_engine_cs *ring)
1091 {
1092         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1093
1094         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1095         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1096         return 0;
1097 }
1098
1099 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1100                           struct intel_engine_cs *ring)
1101 {
1102         int ret;
1103
1104         /* NB: TLBs must be flushed and invalidated before a switch */
1105         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1106         if (ret)
1107                 return ret;
1108
1109         ret = intel_ring_begin(ring, 6);
1110         if (ret)
1111                 return ret;
1112
1113         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1114         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1115         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1116         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1117         intel_ring_emit(ring, get_pd_offset(ppgtt));
1118         intel_ring_emit(ring, MI_NOOP);
1119         intel_ring_advance(ring);
1120
1121         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1122         if (ring->id != RCS) {
1123                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1124                 if (ret)
1125                         return ret;
1126         }
1127
1128         return 0;
1129 }
1130
1131 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1132                           struct intel_engine_cs *ring)
1133 {
1134         struct drm_device *dev = ppgtt->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136
1137
1138         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1139         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1140
1141         POSTING_READ(RING_PP_DIR_DCLV(ring));
1142
1143         return 0;
1144 }
1145
1146 static void gen8_ppgtt_enable(struct drm_device *dev)
1147 {
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         struct intel_engine_cs *ring;
1150         int j;
1151
1152         for_each_ring(ring, dev_priv, j) {
1153                 I915_WRITE(RING_MODE_GEN7(ring),
1154                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1155         }
1156 }
1157
1158 static void gen7_ppgtt_enable(struct drm_device *dev)
1159 {
1160         struct drm_i915_private *dev_priv = dev->dev_private;
1161         struct intel_engine_cs *ring;
1162         uint32_t ecochk, ecobits;
1163         int i;
1164
1165         ecobits = I915_READ(GAC_ECO_BITS);
1166         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1167
1168         ecochk = I915_READ(GAM_ECOCHK);
1169         if (IS_HASWELL(dev)) {
1170                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1171         } else {
1172                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1173                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1174         }
1175         I915_WRITE(GAM_ECOCHK, ecochk);
1176
1177         for_each_ring(ring, dev_priv, i) {
1178                 /* GFX_MODE is per-ring on gen7+ */
1179                 I915_WRITE(RING_MODE_GEN7(ring),
1180                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1181         }
1182 }
1183
1184 static void gen6_ppgtt_enable(struct drm_device *dev)
1185 {
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         uint32_t ecochk, gab_ctl, ecobits;
1188
1189         ecobits = I915_READ(GAC_ECO_BITS);
1190         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1191                    ECOBITS_PPGTT_CACHE64B);
1192
1193         gab_ctl = I915_READ(GAB_CTL);
1194         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1195
1196         ecochk = I915_READ(GAM_ECOCHK);
1197         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1198
1199         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1200 }
1201
1202 /* PPGTT support for Sandybdrige/Gen6 and later */
1203 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1204                                    uint64_t start,
1205                                    uint64_t length,
1206                                    bool use_scratch)
1207 {
1208         struct i915_hw_ppgtt *ppgtt =
1209                 container_of(vm, struct i915_hw_ppgtt, base);
1210         gen6_pte_t *pt_vaddr, scratch_pte;
1211         unsigned first_entry = start >> PAGE_SHIFT;
1212         unsigned num_entries = length >> PAGE_SHIFT;
1213         unsigned act_pt = first_entry / GEN6_PTES;
1214         unsigned first_pte = first_entry % GEN6_PTES;
1215         unsigned last_pte, i;
1216
1217         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1218
1219         while (num_entries) {
1220                 last_pte = first_pte + num_entries;
1221                 if (last_pte > GEN6_PTES)
1222                         last_pte = GEN6_PTES;
1223
1224                 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1225
1226                 for (i = first_pte; i < last_pte; i++)
1227                         pt_vaddr[i] = scratch_pte;
1228
1229                 kunmap_atomic(pt_vaddr);
1230
1231                 num_entries -= last_pte - first_pte;
1232                 first_pte = 0;
1233                 act_pt++;
1234         }
1235 }
1236
1237 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1238                                       struct sg_table *pages,
1239                                       uint64_t start,
1240                                       enum i915_cache_level cache_level, u32 flags)
1241 {
1242         struct i915_hw_ppgtt *ppgtt =
1243                 container_of(vm, struct i915_hw_ppgtt, base);
1244         gen6_pte_t *pt_vaddr;
1245         unsigned first_entry = start >> PAGE_SHIFT;
1246         unsigned act_pt = first_entry / GEN6_PTES;
1247         unsigned act_pte = first_entry % GEN6_PTES;
1248         struct sg_page_iter sg_iter;
1249
1250         pt_vaddr = NULL;
1251         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1252                 if (pt_vaddr == NULL)
1253                         pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1254
1255                 pt_vaddr[act_pte] =
1256                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1257                                        cache_level, true, flags);
1258
1259                 if (++act_pte == GEN6_PTES) {
1260                         kunmap_atomic(pt_vaddr);
1261                         pt_vaddr = NULL;
1262                         act_pt++;
1263                         act_pte = 0;
1264                 }
1265         }
1266         if (pt_vaddr)
1267                 kunmap_atomic(pt_vaddr);
1268 }
1269
1270 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1271  * are switching between contexts with the same LRCA, we also must do a force
1272  * restore.
1273  */
1274 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1275 {
1276         /* If current vm != vm, */
1277         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1278 }
1279
1280 static void gen6_initialize_pt(struct i915_address_space *vm,
1281                 struct i915_page_table *pt)
1282 {
1283         gen6_pte_t *pt_vaddr, scratch_pte;
1284         int i;
1285
1286         WARN_ON(vm->scratch.addr == 0);
1287
1288         scratch_pte = vm->pte_encode(vm->scratch.addr,
1289                         I915_CACHE_LLC, true, 0);
1290
1291         pt_vaddr = kmap_atomic(pt->page);
1292
1293         for (i = 0; i < GEN6_PTES; i++)
1294                 pt_vaddr[i] = scratch_pte;
1295
1296         kunmap_atomic(pt_vaddr);
1297 }
1298
1299 static int gen6_alloc_va_range(struct i915_address_space *vm,
1300                                uint64_t start, uint64_t length)
1301 {
1302         DECLARE_BITMAP(new_page_tables, I915_PDES);
1303         struct drm_device *dev = vm->dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         struct i915_hw_ppgtt *ppgtt =
1306                                 container_of(vm, struct i915_hw_ppgtt, base);
1307         struct i915_page_table *pt;
1308         const uint32_t start_save = start, length_save = length;
1309         uint32_t pde, temp;
1310         int ret;
1311
1312         WARN_ON(upper_32_bits(start));
1313
1314         bitmap_zero(new_page_tables, I915_PDES);
1315
1316         /* The allocation is done in two stages so that we can bail out with
1317          * minimal amount of pain. The first stage finds new page tables that
1318          * need allocation. The second stage marks use ptes within the page
1319          * tables.
1320          */
1321         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1322                 if (pt != ppgtt->scratch_pt) {
1323                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1324                         continue;
1325                 }
1326
1327                 /* We've already allocated a page table */
1328                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1329
1330                 pt = alloc_pt_single(dev);
1331                 if (IS_ERR(pt)) {
1332                         ret = PTR_ERR(pt);
1333                         goto unwind_out;
1334                 }
1335
1336                 gen6_initialize_pt(vm, pt);
1337
1338                 ppgtt->pd.page_table[pde] = pt;
1339                 set_bit(pde, new_page_tables);
1340                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1341         }
1342
1343         start = start_save;
1344         length = length_save;
1345
1346         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1347                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1348
1349                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1350                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1351                            gen6_pte_count(start, length));
1352
1353                 if (test_and_clear_bit(pde, new_page_tables))
1354                         gen6_write_pde(&ppgtt->pd, pde, pt);
1355
1356                 trace_i915_page_table_entry_map(vm, pde, pt,
1357                                          gen6_pte_index(start),
1358                                          gen6_pte_count(start, length),
1359                                          GEN6_PTES);
1360                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1361                                 GEN6_PTES);
1362         }
1363
1364         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1365
1366         /* Make sure write is complete before other code can use this page
1367          * table. Also require for WC mapped PTEs */
1368         readl(dev_priv->gtt.gsm);
1369
1370         mark_tlbs_dirty(ppgtt);
1371         return 0;
1372
1373 unwind_out:
1374         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1375                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1376
1377                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1378                 unmap_and_free_pt(pt, vm->dev);
1379         }
1380
1381         mark_tlbs_dirty(ppgtt);
1382         return ret;
1383 }
1384
1385 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1386 {
1387         struct i915_hw_ppgtt *ppgtt =
1388                 container_of(vm, struct i915_hw_ppgtt, base);
1389         struct i915_page_table *pt;
1390         uint32_t pde;
1391
1392
1393         drm_mm_remove_node(&ppgtt->node);
1394
1395         gen6_for_all_pdes(pt, ppgtt, pde) {
1396                 if (pt != ppgtt->scratch_pt)
1397                         unmap_and_free_pt(pt, ppgtt->base.dev);
1398         }
1399
1400         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1401         unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev);
1402 }
1403
1404 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1405 {
1406         struct drm_device *dev = ppgtt->base.dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         bool retried = false;
1409         int ret;
1410
1411         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1412          * allocator works in address space sizes, so it's multiplied by page
1413          * size. We allocate at the top of the GTT to avoid fragmentation.
1414          */
1415         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1416         ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
1417         if (IS_ERR(ppgtt->scratch_pt))
1418                 return PTR_ERR(ppgtt->scratch_pt);
1419
1420         gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1421
1422 alloc:
1423         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1424                                                   &ppgtt->node, GEN6_PD_SIZE,
1425                                                   GEN6_PD_ALIGN, 0,
1426                                                   0, dev_priv->gtt.base.total,
1427                                                   DRM_MM_TOPDOWN);
1428         if (ret == -ENOSPC && !retried) {
1429                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1430                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1431                                                I915_CACHE_NONE,
1432                                                0, dev_priv->gtt.base.total,
1433                                                0);
1434                 if (ret)
1435                         goto err_out;
1436
1437                 retried = true;
1438                 goto alloc;
1439         }
1440
1441         if (ret)
1442                 goto err_out;
1443
1444
1445         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1446                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1447
1448         return 0;
1449
1450 err_out:
1451         unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1452         return ret;
1453 }
1454
1455 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1456 {
1457         return gen6_ppgtt_allocate_page_directories(ppgtt);
1458 }
1459
1460 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1461                                   uint64_t start, uint64_t length)
1462 {
1463         struct i915_page_table *unused;
1464         uint32_t pde, temp;
1465
1466         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1467                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1468 }
1469
1470 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1471 {
1472         struct drm_device *dev = ppgtt->base.dev;
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         int ret;
1475
1476         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1477         if (IS_GEN6(dev)) {
1478                 ppgtt->switch_mm = gen6_mm_switch;
1479         } else if (IS_HASWELL(dev)) {
1480                 ppgtt->switch_mm = hsw_mm_switch;
1481         } else if (IS_GEN7(dev)) {
1482                 ppgtt->switch_mm = gen7_mm_switch;
1483         } else
1484                 BUG();
1485
1486         if (intel_vgpu_active(dev))
1487                 ppgtt->switch_mm = vgpu_mm_switch;
1488
1489         ret = gen6_ppgtt_alloc(ppgtt);
1490         if (ret)
1491                 return ret;
1492
1493         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1494         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1495         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1496         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1497         ppgtt->base.bind_vma = ppgtt_bind_vma;
1498         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1499         ppgtt->base.start = 0;
1500         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1501         ppgtt->debug_dump = gen6_dump_ppgtt;
1502
1503         ppgtt->pd.pd_offset =
1504                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1505
1506         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1507                 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1508
1509         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1510
1511         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1512
1513         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1514                          ppgtt->node.size >> 20,
1515                          ppgtt->node.start / PAGE_SIZE);
1516
1517         DRM_DEBUG("Adding PPGTT at offset %x\n",
1518                   ppgtt->pd.pd_offset << 10);
1519
1520         return 0;
1521 }
1522
1523 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1524 {
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526
1527         ppgtt->base.dev = dev;
1528         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1529
1530         if (INTEL_INFO(dev)->gen < 8)
1531                 return gen6_ppgtt_init(ppgtt);
1532         else
1533                 return gen8_ppgtt_init(ppgtt);
1534 }
1535 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1536 {
1537         struct drm_i915_private *dev_priv = dev->dev_private;
1538         int ret = 0;
1539
1540         ret = __hw_ppgtt_init(dev, ppgtt);
1541         if (ret == 0) {
1542                 kref_init(&ppgtt->ref);
1543                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1544                             ppgtt->base.total);
1545                 i915_init_vm(dev_priv, &ppgtt->base);
1546         }
1547
1548         return ret;
1549 }
1550
1551 int i915_ppgtt_init_hw(struct drm_device *dev)
1552 {
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         struct intel_engine_cs *ring;
1555         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1556         int i, ret = 0;
1557
1558         /* In the case of execlists, PPGTT is enabled by the context descriptor
1559          * and the PDPs are contained within the context itself.  We don't
1560          * need to do anything here. */
1561         if (i915.enable_execlists)
1562                 return 0;
1563
1564         if (!USES_PPGTT(dev))
1565                 return 0;
1566
1567         if (IS_GEN6(dev))
1568                 gen6_ppgtt_enable(dev);
1569         else if (IS_GEN7(dev))
1570                 gen7_ppgtt_enable(dev);
1571         else if (INTEL_INFO(dev)->gen >= 8)
1572                 gen8_ppgtt_enable(dev);
1573         else
1574                 MISSING_CASE(INTEL_INFO(dev)->gen);
1575
1576         if (ppgtt) {
1577                 for_each_ring(ring, dev_priv, i) {
1578                         ret = ppgtt->switch_mm(ppgtt, ring);
1579                         if (ret != 0)
1580                                 return ret;
1581                 }
1582         }
1583
1584         return ret;
1585 }
1586 struct i915_hw_ppgtt *
1587 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1588 {
1589         struct i915_hw_ppgtt *ppgtt;
1590         int ret;
1591
1592         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1593         if (!ppgtt)
1594                 return ERR_PTR(-ENOMEM);
1595
1596         ret = i915_ppgtt_init(dev, ppgtt);
1597         if (ret) {
1598                 kfree(ppgtt);
1599                 return ERR_PTR(ret);
1600         }
1601
1602         ppgtt->file_priv = fpriv;
1603
1604         trace_i915_ppgtt_create(&ppgtt->base);
1605
1606         return ppgtt;
1607 }
1608
1609 void  i915_ppgtt_release(struct kref *kref)
1610 {
1611         struct i915_hw_ppgtt *ppgtt =
1612                 container_of(kref, struct i915_hw_ppgtt, ref);
1613
1614         trace_i915_ppgtt_release(&ppgtt->base);
1615
1616         /* vmas should already be unbound */
1617         WARN_ON(!list_empty(&ppgtt->base.active_list));
1618         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1619
1620         list_del(&ppgtt->base.global_link);
1621         drm_mm_takedown(&ppgtt->base.mm);
1622
1623         ppgtt->base.cleanup(&ppgtt->base);
1624         kfree(ppgtt);
1625 }
1626
1627 extern int intel_iommu_gfx_mapped;
1628 /* Certain Gen5 chipsets require require idling the GPU before
1629  * unmapping anything from the GTT when VT-d is enabled.
1630  */
1631 static bool needs_idle_maps(struct drm_device *dev)
1632 {
1633 #ifdef CONFIG_INTEL_IOMMU
1634         /* Query intel_iommu to see if we need the workaround. Presumably that
1635          * was loaded first.
1636          */
1637         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1638                 return true;
1639 #endif
1640         return false;
1641 }
1642
1643 static bool do_idling(struct drm_i915_private *dev_priv)
1644 {
1645         bool ret = dev_priv->mm.interruptible;
1646
1647         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1648                 dev_priv->mm.interruptible = false;
1649                 if (i915_gpu_idle(dev_priv->dev)) {
1650                         DRM_ERROR("Couldn't idle GPU\n");
1651                         /* Wait a bit, in hopes it avoids the hang */
1652                         udelay(10);
1653                 }
1654         }
1655
1656         return ret;
1657 }
1658
1659 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1660 {
1661         if (unlikely(dev_priv->gtt.do_idle_maps))
1662                 dev_priv->mm.interruptible = interruptible;
1663 }
1664
1665 void i915_check_and_clear_faults(struct drm_device *dev)
1666 {
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668         struct intel_engine_cs *ring;
1669         int i;
1670
1671         if (INTEL_INFO(dev)->gen < 6)
1672                 return;
1673
1674         for_each_ring(ring, dev_priv, i) {
1675                 u32 fault_reg;
1676                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1677                 if (fault_reg & RING_FAULT_VALID) {
1678                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1679                                          "\tAddr: 0x%08lx\n"
1680                                          "\tAddress space: %s\n"
1681                                          "\tSource ID: %d\n"
1682                                          "\tType: %d\n",
1683                                          fault_reg & PAGE_MASK,
1684                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1685                                          RING_FAULT_SRCID(fault_reg),
1686                                          RING_FAULT_FAULT_TYPE(fault_reg));
1687                         I915_WRITE(RING_FAULT_REG(ring),
1688                                    fault_reg & ~RING_FAULT_VALID);
1689                 }
1690         }
1691         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1692 }
1693
1694 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1695 {
1696         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1697                 intel_gtt_chipset_flush();
1698         } else {
1699                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1700                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1701         }
1702 }
1703
1704 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1705 {
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707
1708         /* Don't bother messing with faults pre GEN6 as we have little
1709          * documentation supporting that it's a good idea.
1710          */
1711         if (INTEL_INFO(dev)->gen < 6)
1712                 return;
1713
1714         i915_check_and_clear_faults(dev);
1715
1716         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1717                                        dev_priv->gtt.base.start,
1718                                        dev_priv->gtt.base.total,
1719                                        true);
1720
1721         i915_ggtt_flush(dev_priv);
1722 }
1723
1724 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1725 {
1726         if (obj->has_dma_mapping)
1727                 return 0;
1728
1729         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1730                         obj->pages->sgl, obj->pages->nents,
1731                         PCI_DMA_BIDIRECTIONAL))
1732                 return -ENOSPC;
1733
1734         return 0;
1735 }
1736
1737 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1738 {
1739 #ifdef writeq
1740         writeq(pte, addr);
1741 #else
1742         iowrite32((u32)pte, addr);
1743         iowrite32(pte >> 32, addr + 4);
1744 #endif
1745 }
1746
1747 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1748                                      struct sg_table *st,
1749                                      uint64_t start,
1750                                      enum i915_cache_level level, u32 unused)
1751 {
1752         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1753         unsigned first_entry = start >> PAGE_SHIFT;
1754         gen8_pte_t __iomem *gtt_entries =
1755                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1756         int i = 0;
1757         struct sg_page_iter sg_iter;
1758         dma_addr_t addr = 0; /* shut up gcc */
1759
1760         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1761                 addr = sg_dma_address(sg_iter.sg) +
1762                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1763                 gen8_set_pte(&gtt_entries[i],
1764                              gen8_pte_encode(addr, level, true));
1765                 i++;
1766         }
1767
1768         /*
1769          * XXX: This serves as a posting read to make sure that the PTE has
1770          * actually been updated. There is some concern that even though
1771          * registers and PTEs are within the same BAR that they are potentially
1772          * of NUMA access patterns. Therefore, even with the way we assume
1773          * hardware should work, we must keep this posting read for paranoia.
1774          */
1775         if (i != 0)
1776                 WARN_ON(readq(&gtt_entries[i-1])
1777                         != gen8_pte_encode(addr, level, true));
1778
1779         /* This next bit makes the above posting read even more important. We
1780          * want to flush the TLBs only after we're certain all the PTE updates
1781          * have finished.
1782          */
1783         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1784         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1785 }
1786
1787 /*
1788  * Binds an object into the global gtt with the specified cache level. The object
1789  * will be accessible to the GPU via commands whose operands reference offsets
1790  * within the global GTT as well as accessible by the GPU through the GMADR
1791  * mapped BAR (dev_priv->mm.gtt->gtt).
1792  */
1793 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1794                                      struct sg_table *st,
1795                                      uint64_t start,
1796                                      enum i915_cache_level level, u32 flags)
1797 {
1798         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1799         unsigned first_entry = start >> PAGE_SHIFT;
1800         gen6_pte_t __iomem *gtt_entries =
1801                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1802         int i = 0;
1803         struct sg_page_iter sg_iter;
1804         dma_addr_t addr = 0;
1805
1806         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1807                 addr = sg_page_iter_dma_address(&sg_iter);
1808                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1809                 i++;
1810         }
1811
1812         /* XXX: This serves as a posting read to make sure that the PTE has
1813          * actually been updated. There is some concern that even though
1814          * registers and PTEs are within the same BAR that they are potentially
1815          * of NUMA access patterns. Therefore, even with the way we assume
1816          * hardware should work, we must keep this posting read for paranoia.
1817          */
1818         if (i != 0) {
1819                 unsigned long gtt = readl(&gtt_entries[i-1]);
1820                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1821         }
1822
1823         /* This next bit makes the above posting read even more important. We
1824          * want to flush the TLBs only after we're certain all the PTE updates
1825          * have finished.
1826          */
1827         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1828         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1829 }
1830
1831 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1832                                   uint64_t start,
1833                                   uint64_t length,
1834                                   bool use_scratch)
1835 {
1836         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1837         unsigned first_entry = start >> PAGE_SHIFT;
1838         unsigned num_entries = length >> PAGE_SHIFT;
1839         gen8_pte_t scratch_pte, __iomem *gtt_base =
1840                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1841         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1842         int i;
1843
1844         if (WARN(num_entries > max_entries,
1845                  "First entry = %d; Num entries = %d (max=%d)\n",
1846                  first_entry, num_entries, max_entries))
1847                 num_entries = max_entries;
1848
1849         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1850                                       I915_CACHE_LLC,
1851                                       use_scratch);
1852         for (i = 0; i < num_entries; i++)
1853                 gen8_set_pte(&gtt_base[i], scratch_pte);
1854         readl(gtt_base);
1855 }
1856
1857 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1858                                   uint64_t start,
1859                                   uint64_t length,
1860                                   bool use_scratch)
1861 {
1862         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1863         unsigned first_entry = start >> PAGE_SHIFT;
1864         unsigned num_entries = length >> PAGE_SHIFT;
1865         gen6_pte_t scratch_pte, __iomem *gtt_base =
1866                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1867         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1868         int i;
1869
1870         if (WARN(num_entries > max_entries,
1871                  "First entry = %d; Num entries = %d (max=%d)\n",
1872                  first_entry, num_entries, max_entries))
1873                 num_entries = max_entries;
1874
1875         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1876
1877         for (i = 0; i < num_entries; i++)
1878                 iowrite32(scratch_pte, &gtt_base[i]);
1879         readl(gtt_base);
1880 }
1881
1882 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1883                                      struct sg_table *pages,
1884                                      uint64_t start,
1885                                      enum i915_cache_level cache_level, u32 unused)
1886 {
1887         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1888                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1889
1890         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1891
1892 }
1893
1894 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1895                                   uint64_t start,
1896                                   uint64_t length,
1897                                   bool unused)
1898 {
1899         unsigned first_entry = start >> PAGE_SHIFT;
1900         unsigned num_entries = length >> PAGE_SHIFT;
1901         intel_gtt_clear_range(first_entry, num_entries);
1902 }
1903
1904 static int ggtt_bind_vma(struct i915_vma *vma,
1905                          enum i915_cache_level cache_level,
1906                          u32 flags)
1907 {
1908         struct drm_device *dev = vma->vm->dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct drm_i915_gem_object *obj = vma->obj;
1911         struct sg_table *pages = obj->pages;
1912         u32 pte_flags = 0;
1913         int ret;
1914
1915         ret = i915_get_ggtt_vma_pages(vma);
1916         if (ret)
1917                 return ret;
1918         pages = vma->ggtt_view.pages;
1919
1920         /* Currently applicable only to VLV */
1921         if (obj->gt_ro)
1922                 pte_flags |= PTE_READ_ONLY;
1923
1924
1925         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1926                 vma->vm->insert_entries(vma->vm, pages,
1927                                         vma->node.start,
1928                                         cache_level, pte_flags);
1929         }
1930
1931         if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1932                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1933                 appgtt->base.insert_entries(&appgtt->base, pages,
1934                                             vma->node.start,
1935                                             cache_level, pte_flags);
1936         }
1937
1938         return 0;
1939 }
1940
1941 static void ggtt_unbind_vma(struct i915_vma *vma)
1942 {
1943         struct drm_device *dev = vma->vm->dev;
1944         struct drm_i915_private *dev_priv = dev->dev_private;
1945         struct drm_i915_gem_object *obj = vma->obj;
1946         const uint64_t size = min_t(uint64_t,
1947                                     obj->base.size,
1948                                     vma->node.size);
1949
1950         if (vma->bound & GLOBAL_BIND) {
1951                 vma->vm->clear_range(vma->vm,
1952                                      vma->node.start,
1953                                      size,
1954                                      true);
1955         }
1956
1957         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1958                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1959
1960                 appgtt->base.clear_range(&appgtt->base,
1961                                          vma->node.start,
1962                                          size,
1963                                          true);
1964         }
1965 }
1966
1967 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1968 {
1969         struct drm_device *dev = obj->base.dev;
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971         bool interruptible;
1972
1973         interruptible = do_idling(dev_priv);
1974
1975         if (!obj->has_dma_mapping)
1976                 dma_unmap_sg(&dev->pdev->dev,
1977                              obj->pages->sgl, obj->pages->nents,
1978                              PCI_DMA_BIDIRECTIONAL);
1979
1980         undo_idling(dev_priv, interruptible);
1981 }
1982
1983 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1984                                   unsigned long color,
1985                                   u64 *start,
1986                                   u64 *end)
1987 {
1988         if (node->color != color)
1989                 *start += 4096;
1990
1991         if (!list_empty(&node->node_list)) {
1992                 node = list_entry(node->node_list.next,
1993                                   struct drm_mm_node,
1994                                   node_list);
1995                 if (node->allocated && node->color != color)
1996                         *end -= 4096;
1997         }
1998 }
1999
2000 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2001                                      unsigned long start,
2002                                      unsigned long mappable_end,
2003                                      unsigned long end)
2004 {
2005         /* Let GEM Manage all of the aperture.
2006          *
2007          * However, leave one page at the end still bound to the scratch page.
2008          * There are a number of places where the hardware apparently prefetches
2009          * past the end of the object, and we've seen multiple hangs with the
2010          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2011          * aperture.  One page should be enough to keep any prefetching inside
2012          * of the aperture.
2013          */
2014         struct drm_i915_private *dev_priv = dev->dev_private;
2015         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2016         struct drm_mm_node *entry;
2017         struct drm_i915_gem_object *obj;
2018         unsigned long hole_start, hole_end;
2019         int ret;
2020
2021         BUG_ON(mappable_end > end);
2022
2023         /* Subtract the guard page ... */
2024         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2025
2026         dev_priv->gtt.base.start = start;
2027         dev_priv->gtt.base.total = end - start;
2028
2029         if (intel_vgpu_active(dev)) {
2030                 ret = intel_vgt_balloon(dev);
2031                 if (ret)
2032                         return ret;
2033         }
2034
2035         if (!HAS_LLC(dev))
2036                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2037
2038         /* Mark any preallocated objects as occupied */
2039         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2040                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2041
2042                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2043                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2044
2045                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2046                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2047                 if (ret) {
2048                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2049                         return ret;
2050                 }
2051                 vma->bound |= GLOBAL_BIND;
2052         }
2053
2054         /* Clear any non-preallocated blocks */
2055         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2056                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2057                               hole_start, hole_end);
2058                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2059                                      hole_end - hole_start, true);
2060         }
2061
2062         /* And finally clear the reserved guard page */
2063         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2064
2065         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2066                 struct i915_hw_ppgtt *ppgtt;
2067
2068                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2069                 if (!ppgtt)
2070                         return -ENOMEM;
2071
2072                 ret = __hw_ppgtt_init(dev, ppgtt);
2073                 if (ret) {
2074                         ppgtt->base.cleanup(&ppgtt->base);
2075                         kfree(ppgtt);
2076                         return ret;
2077                 }
2078
2079                 if (ppgtt->base.allocate_va_range)
2080                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2081                                                             ppgtt->base.total);
2082                 if (ret) {
2083                         ppgtt->base.cleanup(&ppgtt->base);
2084                         kfree(ppgtt);
2085                         return ret;
2086                 }
2087
2088                 ppgtt->base.clear_range(&ppgtt->base,
2089                                         ppgtt->base.start,
2090                                         ppgtt->base.total,
2091                                         true);
2092
2093                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2094         }
2095
2096         return 0;
2097 }
2098
2099 void i915_gem_init_global_gtt(struct drm_device *dev)
2100 {
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         unsigned long gtt_size, mappable_size;
2103
2104         gtt_size = dev_priv->gtt.base.total;
2105         mappable_size = dev_priv->gtt.mappable_end;
2106
2107         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2108 }
2109
2110 void i915_global_gtt_cleanup(struct drm_device *dev)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         struct i915_address_space *vm = &dev_priv->gtt.base;
2114
2115         if (dev_priv->mm.aliasing_ppgtt) {
2116                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2117
2118                 ppgtt->base.cleanup(&ppgtt->base);
2119         }
2120
2121         if (drm_mm_initialized(&vm->mm)) {
2122                 if (intel_vgpu_active(dev))
2123                         intel_vgt_deballoon();
2124
2125                 drm_mm_takedown(&vm->mm);
2126                 list_del(&vm->global_link);
2127         }
2128
2129         vm->cleanup(vm);
2130 }
2131
2132 static int setup_scratch_page(struct drm_device *dev)
2133 {
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct page *page;
2136         dma_addr_t dma_addr;
2137
2138         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2139         if (page == NULL)
2140                 return -ENOMEM;
2141         set_pages_uc(page, 1);
2142
2143 #ifdef CONFIG_INTEL_IOMMU
2144         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2145                                 PCI_DMA_BIDIRECTIONAL);
2146         if (pci_dma_mapping_error(dev->pdev, dma_addr))
2147                 return -EINVAL;
2148 #else
2149         dma_addr = page_to_phys(page);
2150 #endif
2151         dev_priv->gtt.base.scratch.page = page;
2152         dev_priv->gtt.base.scratch.addr = dma_addr;
2153
2154         return 0;
2155 }
2156
2157 static void teardown_scratch_page(struct drm_device *dev)
2158 {
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160         struct page *page = dev_priv->gtt.base.scratch.page;
2161
2162         set_pages_wb(page, 1);
2163         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2164                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2165         __free_page(page);
2166 }
2167
2168 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2169 {
2170         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2171         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2172         return snb_gmch_ctl << 20;
2173 }
2174
2175 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2176 {
2177         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2178         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2179         if (bdw_gmch_ctl)
2180                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2181
2182 #ifdef CONFIG_X86_32
2183         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2184         if (bdw_gmch_ctl > 4)
2185                 bdw_gmch_ctl = 4;
2186 #endif
2187
2188         return bdw_gmch_ctl << 20;
2189 }
2190
2191 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2192 {
2193         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2194         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2195
2196         if (gmch_ctrl)
2197                 return 1 << (20 + gmch_ctrl);
2198
2199         return 0;
2200 }
2201
2202 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2203 {
2204         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2205         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2206         return snb_gmch_ctl << 25; /* 32 MB units */
2207 }
2208
2209 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2210 {
2211         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2212         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2213         return bdw_gmch_ctl << 25; /* 32 MB units */
2214 }
2215
2216 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2217 {
2218         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2219         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2220
2221         /*
2222          * 0x0  to 0x10: 32MB increments starting at 0MB
2223          * 0x11 to 0x16: 4MB increments starting at 8MB
2224          * 0x17 to 0x1d: 4MB increments start at 36MB
2225          */
2226         if (gmch_ctrl < 0x11)
2227                 return gmch_ctrl << 25;
2228         else if (gmch_ctrl < 0x17)
2229                 return (gmch_ctrl - 0x11 + 2) << 22;
2230         else
2231                 return (gmch_ctrl - 0x17 + 9) << 22;
2232 }
2233
2234 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2235 {
2236         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2237         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2238
2239         if (gen9_gmch_ctl < 0xf0)
2240                 return gen9_gmch_ctl << 25; /* 32 MB units */
2241         else
2242                 /* 4MB increments starting at 0xf0 for 4MB */
2243                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2244 }
2245
2246 static int ggtt_probe_common(struct drm_device *dev,
2247                              size_t gtt_size)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         phys_addr_t gtt_phys_addr;
2251         int ret;
2252
2253         /* For Modern GENs the PTEs and register space are split in the BAR */
2254         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2255                 (pci_resource_len(dev->pdev, 0) / 2);
2256
2257         /*
2258          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2259          * dropped. For WC mappings in general we have 64 byte burst writes
2260          * when the WC buffer is flushed, so we can't use it, but have to
2261          * resort to an uncached mapping. The WC issue is easily caught by the
2262          * readback check when writing GTT PTE entries.
2263          */
2264         if (IS_BROXTON(dev))
2265                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2266         else
2267                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2268         if (!dev_priv->gtt.gsm) {
2269                 DRM_ERROR("Failed to map the gtt page table\n");
2270                 return -ENOMEM;
2271         }
2272
2273         ret = setup_scratch_page(dev);
2274         if (ret) {
2275                 DRM_ERROR("Scratch setup failed\n");
2276                 /* iounmap will also get called at remove, but meh */
2277                 iounmap(dev_priv->gtt.gsm);
2278         }
2279
2280         return ret;
2281 }
2282
2283 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2284  * bits. When using advanced contexts each context stores its own PAT, but
2285  * writing this data shouldn't be harmful even in those cases. */
2286 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2287 {
2288         uint64_t pat;
2289
2290         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2291               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2292               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2293               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2294               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2295               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2296               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2297               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2298
2299         if (!USES_PPGTT(dev_priv->dev))
2300                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2301                  * so RTL will always use the value corresponding to
2302                  * pat_sel = 000".
2303                  * So let's disable cache for GGTT to avoid screen corruptions.
2304                  * MOCS still can be used though.
2305                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2306                  * before this patch, i.e. the same uncached + snooping access
2307                  * like on gen6/7 seems to be in effect.
2308                  * - So this just fixes blitter/render access. Again it looks
2309                  * like it's not just uncached access, but uncached + snooping.
2310                  * So we can still hold onto all our assumptions wrt cpu
2311                  * clflushing on LLC machines.
2312                  */
2313                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2314
2315         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2316          * write would work. */
2317         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2318         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2319 }
2320
2321 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2322 {
2323         uint64_t pat;
2324
2325         /*
2326          * Map WB on BDW to snooped on CHV.
2327          *
2328          * Only the snoop bit has meaning for CHV, the rest is
2329          * ignored.
2330          *
2331          * The hardware will never snoop for certain types of accesses:
2332          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2333          * - PPGTT page tables
2334          * - some other special cycles
2335          *
2336          * As with BDW, we also need to consider the following for GT accesses:
2337          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2338          * so RTL will always use the value corresponding to
2339          * pat_sel = 000".
2340          * Which means we must set the snoop bit in PAT entry 0
2341          * in order to keep the global status page working.
2342          */
2343         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2344               GEN8_PPAT(1, 0) |
2345               GEN8_PPAT(2, 0) |
2346               GEN8_PPAT(3, 0) |
2347               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2348               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2349               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2350               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2351
2352         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2353         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2354 }
2355
2356 static int gen8_gmch_probe(struct drm_device *dev,
2357                            size_t *gtt_total,
2358                            size_t *stolen,
2359                            phys_addr_t *mappable_base,
2360                            unsigned long *mappable_end)
2361 {
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         unsigned int gtt_size;
2364         u16 snb_gmch_ctl;
2365         int ret;
2366
2367         /* TODO: We're not aware of mappable constraints on gen8 yet */
2368         *mappable_base = pci_resource_start(dev->pdev, 2);
2369         *mappable_end = pci_resource_len(dev->pdev, 2);
2370
2371         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2372                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2373
2374         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2375
2376         if (INTEL_INFO(dev)->gen >= 9) {
2377                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2378                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2379         } else if (IS_CHERRYVIEW(dev)) {
2380                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2381                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2382         } else {
2383                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2384                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2385         }
2386
2387         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2388
2389         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2390                 chv_setup_private_ppat(dev_priv);
2391         else
2392                 bdw_setup_private_ppat(dev_priv);
2393
2394         ret = ggtt_probe_common(dev, gtt_size);
2395
2396         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2397         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2398         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2399         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2400
2401         return ret;
2402 }
2403
2404 static int gen6_gmch_probe(struct drm_device *dev,
2405                            size_t *gtt_total,
2406                            size_t *stolen,
2407                            phys_addr_t *mappable_base,
2408                            unsigned long *mappable_end)
2409 {
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         unsigned int gtt_size;
2412         u16 snb_gmch_ctl;
2413         int ret;
2414
2415         *mappable_base = pci_resource_start(dev->pdev, 2);
2416         *mappable_end = pci_resource_len(dev->pdev, 2);
2417
2418         /* 64/512MB is the current min/max we actually know of, but this is just
2419          * a coarse sanity check.
2420          */
2421         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2422                 DRM_ERROR("Unknown GMADR size (%lx)\n",
2423                           dev_priv->gtt.mappable_end);
2424                 return -ENXIO;
2425         }
2426
2427         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2428                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2429         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2430
2431         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2432
2433         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2434         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2435
2436         ret = ggtt_probe_common(dev, gtt_size);
2437
2438         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2439         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2440         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2441         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2442
2443         return ret;
2444 }
2445
2446 static void gen6_gmch_remove(struct i915_address_space *vm)
2447 {
2448
2449         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2450
2451         iounmap(gtt->gsm);
2452         teardown_scratch_page(vm->dev);
2453 }
2454
2455 static int i915_gmch_probe(struct drm_device *dev,
2456                            size_t *gtt_total,
2457                            size_t *stolen,
2458                            phys_addr_t *mappable_base,
2459                            unsigned long *mappable_end)
2460 {
2461         struct drm_i915_private *dev_priv = dev->dev_private;
2462         int ret;
2463
2464         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2465         if (!ret) {
2466                 DRM_ERROR("failed to set up gmch\n");
2467                 return -EIO;
2468         }
2469
2470         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2471
2472         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2473         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2474         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2475         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2476         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2477
2478         if (unlikely(dev_priv->gtt.do_idle_maps))
2479                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2480
2481         return 0;
2482 }
2483
2484 static void i915_gmch_remove(struct i915_address_space *vm)
2485 {
2486         intel_gmch_remove();
2487 }
2488
2489 int i915_gem_gtt_init(struct drm_device *dev)
2490 {
2491         struct drm_i915_private *dev_priv = dev->dev_private;
2492         struct i915_gtt *gtt = &dev_priv->gtt;
2493         int ret;
2494
2495         if (INTEL_INFO(dev)->gen <= 5) {
2496                 gtt->gtt_probe = i915_gmch_probe;
2497                 gtt->base.cleanup = i915_gmch_remove;
2498         } else if (INTEL_INFO(dev)->gen < 8) {
2499                 gtt->gtt_probe = gen6_gmch_probe;
2500                 gtt->base.cleanup = gen6_gmch_remove;
2501                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2502                         gtt->base.pte_encode = iris_pte_encode;
2503                 else if (IS_HASWELL(dev))
2504                         gtt->base.pte_encode = hsw_pte_encode;
2505                 else if (IS_VALLEYVIEW(dev))
2506                         gtt->base.pte_encode = byt_pte_encode;
2507                 else if (INTEL_INFO(dev)->gen >= 7)
2508                         gtt->base.pte_encode = ivb_pte_encode;
2509                 else
2510                         gtt->base.pte_encode = snb_pte_encode;
2511         } else {
2512                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2513                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2514         }
2515
2516         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2517                              &gtt->mappable_base, &gtt->mappable_end);
2518         if (ret)
2519                 return ret;
2520
2521         gtt->base.dev = dev;
2522
2523         /* GMADR is the PCI mmio aperture into the global GTT. */
2524         DRM_INFO("Memory usable by graphics device = %zdM\n",
2525                  gtt->base.total >> 20);
2526         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2527         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2528 #ifdef CONFIG_INTEL_IOMMU
2529         if (intel_iommu_gfx_mapped)
2530                 DRM_INFO("VT-d active for gfx access\n");
2531 #endif
2532         /*
2533          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2534          * user's requested state against the hardware/driver capabilities.  We
2535          * do this now so that we can print out any log messages once rather
2536          * than every time we check intel_enable_ppgtt().
2537          */
2538         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2539         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2540
2541         return 0;
2542 }
2543
2544 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct drm_i915_gem_object *obj;
2548         struct i915_address_space *vm;
2549
2550         i915_check_and_clear_faults(dev);
2551
2552         /* First fill our portion of the GTT with scratch pages */
2553         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2554                                        dev_priv->gtt.base.start,
2555                                        dev_priv->gtt.base.total,
2556                                        true);
2557
2558         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2559                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2560                                                            &dev_priv->gtt.base);
2561                 if (!vma)
2562                         continue;
2563
2564                 i915_gem_clflush_object(obj, obj->pin_display);
2565                 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2566         }
2567
2568
2569         if (INTEL_INFO(dev)->gen >= 8) {
2570                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2571                         chv_setup_private_ppat(dev_priv);
2572                 else
2573                         bdw_setup_private_ppat(dev_priv);
2574
2575                 return;
2576         }
2577
2578         if (USES_PPGTT(dev)) {
2579                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2580                         /* TODO: Perhaps it shouldn't be gen6 specific */
2581
2582                         struct i915_hw_ppgtt *ppgtt =
2583                                         container_of(vm, struct i915_hw_ppgtt,
2584                                                      base);
2585
2586                         if (i915_is_ggtt(vm))
2587                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
2588
2589                         gen6_write_page_range(dev_priv, &ppgtt->pd,
2590                                               0, ppgtt->base.total);
2591                 }
2592         }
2593
2594         i915_ggtt_flush(dev_priv);
2595 }
2596
2597 static struct i915_vma *
2598 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2599                       struct i915_address_space *vm,
2600                       const struct i915_ggtt_view *ggtt_view)
2601 {
2602         struct i915_vma *vma;
2603
2604         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2605                 return ERR_PTR(-EINVAL);
2606
2607         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2608         if (vma == NULL)
2609                 return ERR_PTR(-ENOMEM);
2610
2611         INIT_LIST_HEAD(&vma->vma_link);
2612         INIT_LIST_HEAD(&vma->mm_list);
2613         INIT_LIST_HEAD(&vma->exec_list);
2614         vma->vm = vm;
2615         vma->obj = obj;
2616
2617         if (i915_is_ggtt(vm))
2618                 vma->ggtt_view = *ggtt_view;
2619
2620         list_add_tail(&vma->vma_link, &obj->vma_list);
2621         if (!i915_is_ggtt(vm))
2622                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2623
2624         return vma;
2625 }
2626
2627 struct i915_vma *
2628 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2629                                   struct i915_address_space *vm)
2630 {
2631         struct i915_vma *vma;
2632
2633         vma = i915_gem_obj_to_vma(obj, vm);
2634         if (!vma)
2635                 vma = __i915_gem_vma_create(obj, vm,
2636                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2637
2638         return vma;
2639 }
2640
2641 struct i915_vma *
2642 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2643                                        const struct i915_ggtt_view *view)
2644 {
2645         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2646         struct i915_vma *vma;
2647
2648         if (WARN_ON(!view))
2649                 return ERR_PTR(-EINVAL);
2650
2651         vma = i915_gem_obj_to_ggtt_view(obj, view);
2652
2653         if (IS_ERR(vma))
2654                 return vma;
2655
2656         if (!vma)
2657                 vma = __i915_gem_vma_create(obj, ggtt, view);
2658
2659         return vma;
2660
2661 }
2662
2663 static void
2664 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2665              struct sg_table *st)
2666 {
2667         unsigned int column, row;
2668         unsigned int src_idx;
2669         struct scatterlist *sg = st->sgl;
2670
2671         st->nents = 0;
2672
2673         for (column = 0; column < width; column++) {
2674                 src_idx = width * (height - 1) + column;
2675                 for (row = 0; row < height; row++) {
2676                         st->nents++;
2677                         /* We don't need the pages, but need to initialize
2678                          * the entries so the sg list can be happily traversed.
2679                          * The only thing we need are DMA addresses.
2680                          */
2681                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
2682                         sg_dma_address(sg) = in[src_idx];
2683                         sg_dma_len(sg) = PAGE_SIZE;
2684                         sg = sg_next(sg);
2685                         src_idx -= width;
2686                 }
2687         }
2688 }
2689
2690 static struct sg_table *
2691 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2692                           struct drm_i915_gem_object *obj)
2693 {
2694         struct drm_device *dev = obj->base.dev;
2695         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2696         unsigned long size, pages, rot_pages;
2697         struct sg_page_iter sg_iter;
2698         unsigned long i;
2699         dma_addr_t *page_addr_list;
2700         struct sg_table *st;
2701         unsigned int tile_pitch, tile_height;
2702         unsigned int width_pages, height_pages;
2703         int ret = -ENOMEM;
2704
2705         pages = obj->base.size / PAGE_SIZE;
2706
2707         /* Calculate tiling geometry. */
2708         tile_height = intel_tile_height(dev, rot_info->pixel_format,
2709                                         rot_info->fb_modifier);
2710         tile_pitch = PAGE_SIZE / tile_height;
2711         width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2712         height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2713         rot_pages = width_pages * height_pages;
2714         size = rot_pages * PAGE_SIZE;
2715
2716         /* Allocate a temporary list of source pages for random access. */
2717         page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2718         if (!page_addr_list)
2719                 return ERR_PTR(ret);
2720
2721         /* Allocate target SG list. */
2722         st = kmalloc(sizeof(*st), GFP_KERNEL);
2723         if (!st)
2724                 goto err_st_alloc;
2725
2726         ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2727         if (ret)
2728                 goto err_sg_alloc;
2729
2730         /* Populate source page list from the object. */
2731         i = 0;
2732         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2733                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2734                 i++;
2735         }
2736
2737         /* Rotate the pages. */
2738         rotate_pages(page_addr_list, width_pages, height_pages, st);
2739
2740         DRM_DEBUG_KMS(
2741                       "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2742                       size, rot_info->pitch, rot_info->height,
2743                       rot_info->pixel_format, width_pages, height_pages,
2744                       rot_pages);
2745
2746         drm_free_large(page_addr_list);
2747
2748         return st;
2749
2750 err_sg_alloc:
2751         kfree(st);
2752 err_st_alloc:
2753         drm_free_large(page_addr_list);
2754
2755         DRM_DEBUG_KMS(
2756                       "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2757                       size, ret, rot_info->pitch, rot_info->height,
2758                       rot_info->pixel_format, width_pages, height_pages,
2759                       rot_pages);
2760         return ERR_PTR(ret);
2761 }
2762
2763 static struct sg_table *
2764 intel_partial_pages(const struct i915_ggtt_view *view,
2765                     struct drm_i915_gem_object *obj)
2766 {
2767         struct sg_table *st;
2768         struct scatterlist *sg;
2769         struct sg_page_iter obj_sg_iter;
2770         int ret = -ENOMEM;
2771
2772         st = kmalloc(sizeof(*st), GFP_KERNEL);
2773         if (!st)
2774                 goto err_st_alloc;
2775
2776         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2777         if (ret)
2778                 goto err_sg_alloc;
2779
2780         sg = st->sgl;
2781         st->nents = 0;
2782         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2783                 view->params.partial.offset)
2784         {
2785                 if (st->nents >= view->params.partial.size)
2786                         break;
2787
2788                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2789                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2790                 sg_dma_len(sg) = PAGE_SIZE;
2791
2792                 sg = sg_next(sg);
2793                 st->nents++;
2794         }
2795
2796         return st;
2797
2798 err_sg_alloc:
2799         kfree(st);
2800 err_st_alloc:
2801         return ERR_PTR(ret);
2802 }
2803
2804 static int
2805 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2806 {
2807         int ret = 0;
2808
2809         if (vma->ggtt_view.pages)
2810                 return 0;
2811
2812         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2813                 vma->ggtt_view.pages = vma->obj->pages;
2814         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2815                 vma->ggtt_view.pages =
2816                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2817         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2818                 vma->ggtt_view.pages =
2819                         intel_partial_pages(&vma->ggtt_view, vma->obj);
2820         else
2821                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2822                           vma->ggtt_view.type);
2823
2824         if (!vma->ggtt_view.pages) {
2825                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2826                           vma->ggtt_view.type);
2827                 ret = -EINVAL;
2828         } else if (IS_ERR(vma->ggtt_view.pages)) {
2829                 ret = PTR_ERR(vma->ggtt_view.pages);
2830                 vma->ggtt_view.pages = NULL;
2831                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2832                           vma->ggtt_view.type, ret);
2833         }
2834
2835         return ret;
2836 }
2837
2838 /**
2839  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2840  * @vma: VMA to map
2841  * @cache_level: mapping cache level
2842  * @flags: flags like global or local mapping
2843  *
2844  * DMA addresses are taken from the scatter-gather table of this object (or of
2845  * this VMA in case of non-default GGTT views) and PTE entries set up.
2846  * Note that DMA addresses are also the only part of the SG table we care about.
2847  */
2848 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2849                   u32 flags)
2850 {
2851         int ret;
2852         u32 bind_flags;
2853
2854         if (WARN_ON(flags == 0))
2855                 return -EINVAL;
2856
2857         bind_flags = 0;
2858         if (flags & PIN_GLOBAL)
2859                 bind_flags |= GLOBAL_BIND;
2860         if (flags & PIN_USER)
2861                 bind_flags |= LOCAL_BIND;
2862
2863         if (flags & PIN_UPDATE)
2864                 bind_flags |= vma->bound;
2865         else
2866                 bind_flags &= ~vma->bound;
2867
2868         if (bind_flags == 0)
2869                 return 0;
2870
2871         if (vma->bound == 0 && vma->vm->allocate_va_range) {
2872                 trace_i915_va_alloc(vma->vm,
2873                                     vma->node.start,
2874                                     vma->node.size,
2875                                     VM_TO_TRACE_NAME(vma->vm));
2876
2877                 ret = vma->vm->allocate_va_range(vma->vm,
2878                                                  vma->node.start,
2879                                                  vma->node.size);
2880                 if (ret)
2881                         return ret;
2882         }
2883
2884         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2885         if (ret)
2886                 return ret;
2887
2888         vma->bound |= bind_flags;
2889
2890         return 0;
2891 }
2892
2893 /**
2894  * i915_ggtt_view_size - Get the size of a GGTT view.
2895  * @obj: Object the view is of.
2896  * @view: The view in question.
2897  *
2898  * @return The size of the GGTT view in bytes.
2899  */
2900 size_t
2901 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2902                     const struct i915_ggtt_view *view)
2903 {
2904         if (view->type == I915_GGTT_VIEW_NORMAL ||
2905             view->type == I915_GGTT_VIEW_ROTATED) {
2906                 return obj->base.size;
2907         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2908                 return view->params.partial.size << PAGE_SHIFT;
2909         } else {
2910                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2911                 return obj->base.size;
2912         }
2913 }