drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33 typedef uint64_t gen8_gtt_pte_t;
  34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  35
  36 /* PPGTT stuff */
  37 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  38 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  39
  40 #define GEN6_PDE_VALID                  (1 << 0)
  41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  42 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  43
  44 #define GEN6_PTE_VALID                  (1 << 0)
  45 #define GEN6_PTE_UNCACHED               (1 << 1)
  46 #define HSW_PTE_UNCACHED                (0)
  47 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  48 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  49 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  50 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  51
  52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  53  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  54  */
  55 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  56                                          (((bits) & 0x8) << (11 - 3)))
  57 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  58 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  59 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  60 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  61
  62 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  63 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  64 #define GEN8_LEGACY_PDPS                4
  65
  66 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  67 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  68 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  69 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  70
  71 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  72                                              enum i915_cache_level level,
  73                                              bool valid)
  74 {
  75         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  76         pte |= addr;
  77         if (level != I915_CACHE_NONE)
  78                 pte |= PPAT_CACHED_INDEX;
  79         else
  80                 pte |= PPAT_UNCACHED_INDEX;
  81         return pte;
  82 }
  83
  84 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
  85                                              dma_addr_t addr,
  86                                              enum i915_cache_level level)
  87 {
  88         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  89         pde |= addr;
  90         if (level != I915_CACHE_NONE)
  91                 pde |= PPAT_CACHED_PDE_INDEX;
  92         else
  93                 pde |= PPAT_UNCACHED_INDEX;
  94         return pde;
  95 }
  96
  97 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
  98                                      enum i915_cache_level level,
  99                                      bool valid)
 100 {
 101         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 102         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 103
 104         switch (level) {
 105         case I915_CACHE_L3_LLC:
 106         case I915_CACHE_LLC:
 107                 pte |= GEN6_PTE_CACHE_LLC;
 108                 break;
 109         case I915_CACHE_NONE:
 110                 pte |= GEN6_PTE_UNCACHED;
 111                 break;
 112         default:
 113                 WARN_ON(1);
 114         }
 115
 116         return pte;
 117 }
 118
 119 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 120                                      enum i915_cache_level level,
 121                                      bool valid)
 122 {
 123         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 124         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 125
 126         switch (level) {
 127         case I915_CACHE_L3_LLC:
 128                 pte |= GEN7_PTE_CACHE_L3_LLC;
 129                 break;
 130         case I915_CACHE_LLC:
 131                 pte |= GEN6_PTE_CACHE_LLC;
 132                 break;
 133         case I915_CACHE_NONE:
 134                 pte |= GEN6_PTE_UNCACHED;
 135                 break;
 136         default:
 137                 WARN_ON(1);
 138         }
 139
 140         return pte;
 141 }
 142
 143 #define BYT_PTE_WRITEABLE               (1 << 1)
 144 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 145
 146 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 147                                      enum i915_cache_level level,
 148                                      bool valid)
 149 {
 150         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 151         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 152
 153         /* Mark the page as writeable.  Other platforms don't have a
 154          * setting for read-only/writable, so this matches that behavior.
 155          */
 156         pte |= BYT_PTE_WRITEABLE;
 157
 158         if (level != I915_CACHE_NONE)
 159                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 160
 161         return pte;
 162 }
 163
 164 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 165                                      enum i915_cache_level level,
 166                                      bool valid)
 167 {
 168         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 169         pte |= HSW_PTE_ADDR_ENCODE(addr);
 170
 171         if (level != I915_CACHE_NONE)
 172                 pte |= HSW_WB_LLC_AGE3;
 173
 174         return pte;
 175 }
 176
 177 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 178                                       enum i915_cache_level level,
 179                                       bool valid)
 180 {
 181         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 182         pte |= HSW_PTE_ADDR_ENCODE(addr);
 183
 184         switch (level) {
 185         case I915_CACHE_NONE:
 186                 break;
 187         case I915_CACHE_WT:
 188                 pte |= HSW_WT_ELLC_LLC_AGE0;
 189                 break;
 190         default:
 191                 pte |= HSW_WB_ELLC_LLC_AGE0;
 192                 break;
 193         }
 194
 195         return pte;
 196 }
 197
 198 /* Broadwell Page Directory Pointer Descriptors */
 199 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 200                            uint64_t val)
 201 {
 202         int ret;
 203
 204         BUG_ON(entry >= 4);
 205
 206         ret = intel_ring_begin(ring, 6);
 207         if (ret)
 208                 return ret;
 209
 210         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 211         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 212         intel_ring_emit(ring, (u32)(val >> 32));
 213         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 214         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 215         intel_ring_emit(ring, (u32)(val));
 216         intel_ring_advance(ring);
 217
 218         return 0;
 219 }
 220
 221 static int gen8_ppgtt_enable(struct drm_device *dev)
 222 {
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct intel_ring_buffer *ring;
 225         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 226         int i, j, ret;
 227
 228         /* bit of a hack to find the actual last used pd */
 229         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 230
 231         for_each_ring(ring, dev_priv, j) {
 232                 I915_WRITE(RING_MODE_GEN7(ring),
 233                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 234         }
 235
 236         for (i = used_pd - 1; i >= 0; i--) {
 237                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 238                 for_each_ring(ring, dev_priv, j) {
 239                         ret = gen8_write_pdp(ring, i, addr);
 240                         if (ret)
 241                                 return ret;
 242                 }
 243         }
 244         return 0;
 245 }
 246
 247 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 248                                    unsigned first_entry,
 249                                    unsigned num_entries,
 250                                    bool use_scratch)
 251 {
 252         struct i915_hw_ppgtt *ppgtt =
 253                 container_of(vm, struct i915_hw_ppgtt, base);
 254         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 255         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 256         unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
 257         unsigned last_pte, i;
 258
 259         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 260                                       I915_CACHE_LLC, use_scratch);
 261
 262         while (num_entries) {
 263                 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
 264
 265                 last_pte = first_pte + num_entries;
 266                 if (last_pte > GEN8_PTES_PER_PAGE)
 267                         last_pte = GEN8_PTES_PER_PAGE;
 268
 269                 pt_vaddr = kmap_atomic(page_table);
 270
 271                 for (i = first_pte; i < last_pte; i++)
 272                         pt_vaddr[i] = scratch_pte;
 273
 274                 kunmap_atomic(pt_vaddr);
 275
 276                 num_entries -= last_pte - first_pte;
 277                 first_pte = 0;
 278                 act_pt++;
 279         }
 280 }
 281
 282 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 283                                       struct sg_table *pages,
 284                                       unsigned first_entry,
 285                                       enum i915_cache_level cache_level)
 286 {
 287         struct i915_hw_ppgtt *ppgtt =
 288                 container_of(vm, struct i915_hw_ppgtt, base);
 289         gen8_gtt_pte_t *pt_vaddr;
 290         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 291         unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
 292         struct sg_page_iter sg_iter;
 293
 294         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 295         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 296                 dma_addr_t page_addr;
 297
 298                 page_addr = sg_dma_address(sg_iter.sg) +
 299                                 (sg_iter.sg_pgoffset << PAGE_SHIFT);
 300                 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
 301                                                     true);
 302                 if (++act_pte == GEN8_PTES_PER_PAGE) {
 303                         kunmap_atomic(pt_vaddr);
 304                         act_pt++;
 305                         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 306                         act_pte = 0;
 307
 308                 }
 309         }
 310         kunmap_atomic(pt_vaddr);
 311 }
 312
 313 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 314 {
 315         struct i915_hw_ppgtt *ppgtt =
 316                 container_of(vm, struct i915_hw_ppgtt, base);
 317         int i, j;
 318
 319         for (i = 0; i < ppgtt->num_pd_pages ; i++) {
 320                 if (ppgtt->pd_dma_addr[i]) {
 321                         pci_unmap_page(ppgtt->base.dev->pdev,
 322                                        ppgtt->pd_dma_addr[i],
 323                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 324
 325                         for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 326                                 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 327                                 if (addr)
 328                                         pci_unmap_page(ppgtt->base.dev->pdev,
 329                                                        addr,
 330                                                        PAGE_SIZE,
 331                                                        PCI_DMA_BIDIRECTIONAL);
 332
 333                         }
 334                 }
 335                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 336         }
 337
 338         __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);
 339         __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);
 340 }
 341
 342 /**
 343  * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
 344  * net effect resembling a 2-level page table in normal x86 terms. Each PDP
 345  * represents 1GB of memory
 346  * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
 347  *
 348  * TODO: Do something with the size parameter
 349  **/
 350 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 351 {
 352         struct page *pt_pages;
 353         int i, j, ret = -ENOMEM;
 354         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 355         const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 356
 357         if (size % (1<<30))
 358                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 359
 360         /* FIXME: split allocation into smaller pieces. For now we only ever do
 361          * this once, but with full PPGTT, the multiple contiguous allocations
 362          * will be bad.
 363          */
 364         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 365         if (!ppgtt->pd_pages)
 366                 return -ENOMEM;
 367
 368         pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
 369         if (!pt_pages) {
 370                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 371                 return -ENOMEM;
 372         }
 373
 374         ppgtt->gen8_pt_pages = pt_pages;
 375         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 376         ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 377         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 378         ppgtt->enable = gen8_ppgtt_enable;
 379         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 380         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 381         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 382
 383         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 384
 385         /*
 386          * - Create a mapping for the page directories.
 387          * - For each page directory:
 388          *      allocate space for page table mappings.
 389          *      map each page table
 390          */
 391         for (i = 0; i < max_pdp; i++) {
 392                 dma_addr_t temp;
 393                 temp = pci_map_page(ppgtt->base.dev->pdev,
 394                                     &ppgtt->pd_pages[i], 0,
 395                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 396                 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 397                         goto err_out;
 398
 399                 ppgtt->pd_dma_addr[i] = temp;
 400
 401                 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
 402                 if (!ppgtt->gen8_pt_dma_addr[i])
 403                         goto err_out;
 404
 405                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 406                         struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
 407                         temp = pci_map_page(ppgtt->base.dev->pdev,
 408                                             p, 0, PAGE_SIZE,
 409                                             PCI_DMA_BIDIRECTIONAL);
 410
 411                         if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 412                                 goto err_out;
 413
 414                         ppgtt->gen8_pt_dma_addr[i][j] = temp;
 415                 }
 416         }
 417
 418         /* For now, the PPGTT helper functions all require that the PDEs are
 419          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 420          * will never need to touch the PDEs again */
 421         for (i = 0; i < max_pdp; i++) {
 422                 gen8_ppgtt_pde_t *pd_vaddr;
 423                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 424                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 425                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 426                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 427                                                       I915_CACHE_LLC);
 428                 }
 429                 kunmap_atomic(pd_vaddr);
 430         }
 431
 432         ppgtt->base.clear_range(&ppgtt->base, 0,
 433                                 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
 434                                 true);
 435
 436         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 437                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 438         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 439                          ppgtt->num_pt_pages,
 440                          (ppgtt->num_pt_pages - num_pt_pages) +
 441                          size % (1<<30));
 442         return 0;
 443
 444 err_out:
 445         ppgtt->base.cleanup(&ppgtt->base);
 446         return ret;
 447 }
 448
 449 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 450 {
 451         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 452         gen6_gtt_pte_t __iomem *pd_addr;
 453         uint32_t pd_entry;
 454         int i;
 455
 456         WARN_ON(ppgtt->pd_offset & 0x3f);
 457         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 458                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 459         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 460                 dma_addr_t pt_addr;
 461
 462                 pt_addr = ppgtt->pt_dma_addr[i];
 463                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 464                 pd_entry |= GEN6_PDE_VALID;
 465
 466                 writel(pd_entry, pd_addr + i);
 467         }
 468         readl(pd_addr);
 469 }
 470
 471 static int gen6_ppgtt_enable(struct drm_device *dev)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474         uint32_t pd_offset;
 475         struct intel_ring_buffer *ring;
 476         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 477         int i;
 478
 479         BUG_ON(ppgtt->pd_offset & 0x3f);
 480
 481         gen6_write_pdes(ppgtt);
 482
 483         pd_offset = ppgtt->pd_offset;
 484         pd_offset /= 64; /* in cachelines, */
 485         pd_offset <<= 16;
 486
 487         if (INTEL_INFO(dev)->gen == 6) {
 488                 uint32_t ecochk, gab_ctl, ecobits;
 489
 490                 ecobits = I915_READ(GAC_ECO_BITS);
 491                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 492                                          ECOBITS_PPGTT_CACHE64B);
 493
 494                 gab_ctl = I915_READ(GAB_CTL);
 495                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 496
 497                 ecochk = I915_READ(GAM_ECOCHK);
 498                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 499                                        ECOCHK_PPGTT_CACHE64B);
 500                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 501         } else if (INTEL_INFO(dev)->gen >= 7) {
 502                 uint32_t ecochk, ecobits;
 503
 504                 ecobits = I915_READ(GAC_ECO_BITS);
 505                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 506
 507                 ecochk = I915_READ(GAM_ECOCHK);
 508                 if (IS_HASWELL(dev)) {
 509                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 510                 } else {
 511                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 512                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 513                 }
 514                 I915_WRITE(GAM_ECOCHK, ecochk);
 515                 /* GFX_MODE is per-ring on gen7+ */
 516         }
 517
 518         for_each_ring(ring, dev_priv, i) {
 519                 if (INTEL_INFO(dev)->gen >= 7)
 520                         I915_WRITE(RING_MODE_GEN7(ring),
 521                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 522
 523                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 524                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 525         }
 526         return 0;
 527 }
 528
 529 /* PPGTT support for Sandybdrige/Gen6 and later */
 530 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 531                                    unsigned first_entry,
 532                                    unsigned num_entries,
 533                                    bool use_scratch)
 534 {
 535         struct i915_hw_ppgtt *ppgtt =
 536                 container_of(vm, struct i915_hw_ppgtt, base);
 537         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 538         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 539         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 540         unsigned last_pte, i;
 541
 542         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 543
 544         while (num_entries) {
 545                 last_pte = first_pte + num_entries;
 546                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 547                         last_pte = I915_PPGTT_PT_ENTRIES;
 548
 549                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 550
 551                 for (i = first_pte; i < last_pte; i++)
 552                         pt_vaddr[i] = scratch_pte;
 553
 554                 kunmap_atomic(pt_vaddr);
 555
 556                 num_entries -= last_pte - first_pte;
 557                 first_pte = 0;
 558                 act_pt++;
 559         }
 560 }
 561
 562 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 563                                       struct sg_table *pages,
 564                                       unsigned first_entry,
 565                                       enum i915_cache_level cache_level)
 566 {
 567         struct i915_hw_ppgtt *ppgtt =
 568                 container_of(vm, struct i915_hw_ppgtt, base);
 569         gen6_gtt_pte_t *pt_vaddr;
 570         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 571         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 572         struct sg_page_iter sg_iter;
 573
 574         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 575         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 576                 dma_addr_t page_addr;
 577
 578                 page_addr = sg_page_iter_dma_address(&sg_iter);
 579                 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
 580                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 581                         kunmap_atomic(pt_vaddr);
 582                         act_pt++;
 583                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 584                         act_pte = 0;
 585
 586                 }
 587         }
 588         kunmap_atomic(pt_vaddr);
 589 }
 590
 591 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 592 {
 593         struct i915_hw_ppgtt *ppgtt =
 594                 container_of(vm, struct i915_hw_ppgtt, base);
 595         int i;
 596
 597         drm_mm_takedown(&ppgtt->base.mm);
 598
 599         if (ppgtt->pt_dma_addr) {
 600                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 601                         pci_unmap_page(ppgtt->base.dev->pdev,
 602                                        ppgtt->pt_dma_addr[i],
 603                                        4096, PCI_DMA_BIDIRECTIONAL);
 604         }
 605
 606         kfree(ppgtt->pt_dma_addr);
 607         for (i = 0; i < ppgtt->num_pd_entries; i++)
 608                 __free_page(ppgtt->pt_pages[i]);
 609         kfree(ppgtt->pt_pages);
 610         kfree(ppgtt);
 611 }
 612
 613 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 614 {
 615         struct drm_device *dev = ppgtt->base.dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         unsigned first_pd_entry_in_global_pt;
 618         int i;
 619         int ret = -ENOMEM;
 620
 621         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 622          * entries. For aliasing ppgtt support we just steal them at the end for
 623          * now. */
 624         first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 625
 626         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 627         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 628         ppgtt->enable = gen6_ppgtt_enable;
 629         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 630         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 631         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 632         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 633         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 634                                   GFP_KERNEL);
 635         if (!ppgtt->pt_pages)
 636                 return -ENOMEM;
 637
 638         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 639                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 640                 if (!ppgtt->pt_pages[i])
 641                         goto err_pt_alloc;
 642         }
 643
 644         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
 645                                      GFP_KERNEL);
 646         if (!ppgtt->pt_dma_addr)
 647                 goto err_pt_alloc;
 648
 649         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 650                 dma_addr_t pt_addr;
 651
 652                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 653                                        PCI_DMA_BIDIRECTIONAL);
 654
 655                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 656                         ret = -EIO;
 657                         goto err_pd_pin;
 658
 659                 }
 660                 ppgtt->pt_dma_addr[i] = pt_addr;
 661         }
 662
 663         ppgtt->base.clear_range(&ppgtt->base, 0,
 664                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
 665
 666         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 667
 668         return 0;
 669
 670 err_pd_pin:
 671         if (ppgtt->pt_dma_addr) {
 672                 for (i--; i >= 0; i--)
 673                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 674                                        4096, PCI_DMA_BIDIRECTIONAL);
 675         }
 676 err_pt_alloc:
 677         kfree(ppgtt->pt_dma_addr);
 678         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 679                 if (ppgtt->pt_pages[i])
 680                         __free_page(ppgtt->pt_pages[i]);
 681         }
 682         kfree(ppgtt->pt_pages);
 683
 684         return ret;
 685 }
 686
 687 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 688 {
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         struct i915_hw_ppgtt *ppgtt;
 691         int ret;
 692
 693         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 694         if (!ppgtt)
 695                 return -ENOMEM;
 696
 697         ppgtt->base.dev = dev;
 698
 699         if (INTEL_INFO(dev)->gen < 8)
 700                 ret = gen6_ppgtt_init(ppgtt);
 701         else if (IS_GEN8(dev))
 702                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 703         else
 704                 BUG();
 705
 706         if (ret)
 707                 kfree(ppgtt);
 708         else {
 709                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 710                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
 711                             ppgtt->base.total);
 712         }
 713
 714         return ret;
 715 }
 716
 717 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 718 {
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 721
 722         if (!ppgtt)
 723                 return;
 724
 725         ppgtt->base.cleanup(&ppgtt->base);
 726         dev_priv->mm.aliasing_ppgtt = NULL;
 727 }
 728
 729 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 730                             struct drm_i915_gem_object *obj,
 731                             enum i915_cache_level cache_level)
 732 {
 733         ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
 734                                    i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 735                                    cache_level);
 736 }
 737
 738 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 739                               struct drm_i915_gem_object *obj)
 740 {
 741         ppgtt->base.clear_range(&ppgtt->base,
 742                                 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
 743                                 obj->base.size >> PAGE_SHIFT,
 744                                 true);
 745 }
 746
 747 extern int intel_iommu_gfx_mapped;
 748 /* Certain Gen5 chipsets require require idling the GPU before
 749  * unmapping anything from the GTT when VT-d is enabled.
 750  */
 751 static inline bool needs_idle_maps(struct drm_device *dev)
 752 {
 753 #ifdef CONFIG_INTEL_IOMMU
 754         /* Query intel_iommu to see if we need the workaround. Presumably that
 755          * was loaded first.
 756          */
 757         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 758                 return true;
 759 #endif
 760         return false;
 761 }
 762
 763 static bool do_idling(struct drm_i915_private *dev_priv)
 764 {
 765         bool ret = dev_priv->mm.interruptible;
 766
 767         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 768                 dev_priv->mm.interruptible = false;
 769                 if (i915_gpu_idle(dev_priv->dev)) {
 770                         DRM_ERROR("Couldn't idle GPU\n");
 771                         /* Wait a bit, in hopes it avoids the hang */
 772                         udelay(10);
 773                 }
 774         }
 775
 776         return ret;
 777 }
 778
 779 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 780 {
 781         if (unlikely(dev_priv->gtt.do_idle_maps))
 782                 dev_priv->mm.interruptible = interruptible;
 783 }
 784
 785 void i915_check_and_clear_faults(struct drm_device *dev)
 786 {
 787         struct drm_i915_private *dev_priv = dev->dev_private;
 788         struct intel_ring_buffer *ring;
 789         int i;
 790
 791         if (INTEL_INFO(dev)->gen < 6)
 792                 return;
 793
 794         for_each_ring(ring, dev_priv, i) {
 795                 u32 fault_reg;
 796                 fault_reg = I915_READ(RING_FAULT_REG(ring));
 797                 if (fault_reg & RING_FAULT_VALID) {
 798                         DRM_DEBUG_DRIVER("Unexpected fault\n"
 799                                          "\tAddr: 0x%08lx\\n"
 800                                          "\tAddress space: %s\n"
 801                                          "\tSource ID: %d\n"
 802                                          "\tType: %d\n",
 803                                          fault_reg & PAGE_MASK,
 804                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
 805                                          RING_FAULT_SRCID(fault_reg),
 806                                          RING_FAULT_FAULT_TYPE(fault_reg));
 807                         I915_WRITE(RING_FAULT_REG(ring),
 808                                    fault_reg & ~RING_FAULT_VALID);
 809                 }
 810         }
 811         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
 812 }
 813
 814 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817
 818         /* Don't bother messing with faults pre GEN6 as we have little
 819          * documentation supporting that it's a good idea.
 820          */
 821         if (INTEL_INFO(dev)->gen < 6)
 822                 return;
 823
 824         i915_check_and_clear_faults(dev);
 825
 826         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 827                                        dev_priv->gtt.base.start / PAGE_SIZE,
 828                                        dev_priv->gtt.base.total / PAGE_SIZE,
 829                                        false);
 830 }
 831
 832 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         struct drm_i915_gem_object *obj;
 836
 837         i915_check_and_clear_faults(dev);
 838
 839         /* First fill our portion of the GTT with scratch pages */
 840         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 841                                        dev_priv->gtt.base.start / PAGE_SIZE,
 842                                        dev_priv->gtt.base.total / PAGE_SIZE,
 843                                        true);
 844
 845         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 846                 i915_gem_clflush_object(obj, obj->pin_display);
 847                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 848         }
 849
 850         i915_gem_chipset_flush(dev);
 851 }
 852
 853 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 854 {
 855         if (obj->has_dma_mapping)
 856                 return 0;
 857
 858         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 859                         obj->pages->sgl, obj->pages->nents,
 860                         PCI_DMA_BIDIRECTIONAL))
 861                 return -ENOSPC;
 862
 863         return 0;
 864 }
 865
 866 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
 867 {
 868 #ifdef writeq
 869         writeq(pte, addr);
 870 #else
 871         iowrite32((u32)pte, addr);
 872         iowrite32(pte >> 32, addr + 4);
 873 #endif
 874 }
 875
 876 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 877                                      struct sg_table *st,
 878                                      unsigned int first_entry,
 879                                      enum i915_cache_level level)
 880 {
 881         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 882         gen8_gtt_pte_t __iomem *gtt_entries =
 883                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 884         int i = 0;
 885         struct sg_page_iter sg_iter;
 886         dma_addr_t addr;
 887
 888         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 889                 addr = sg_dma_address(sg_iter.sg) +
 890                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
 891                 gen8_set_pte(&gtt_entries[i],
 892                              gen8_pte_encode(addr, level, true));
 893                 i++;
 894         }
 895
 896         /*
 897          * XXX: This serves as a posting read to make sure that the PTE has
 898          * actually been updated. There is some concern that even though
 899          * registers and PTEs are within the same BAR that they are potentially
 900          * of NUMA access patterns. Therefore, even with the way we assume
 901          * hardware should work, we must keep this posting read for paranoia.
 902          */
 903         if (i != 0)
 904                 WARN_ON(readq(&gtt_entries[i-1])
 905                         != gen8_pte_encode(addr, level, true));
 906
 907 #if 0 /* TODO: Still needed on GEN8? */
 908         /* This next bit makes the above posting read even more important. We
 909          * want to flush the TLBs only after we're certain all the PTE updates
 910          * have finished.
 911          */
 912         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 913         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 914 #endif
 915 }
 916
 917 /*
 918  * Binds an object into the global gtt with the specified cache level. The object
 919  * will be accessible to the GPU via commands whose operands reference offsets
 920  * within the global GTT as well as accessible by the GPU through the GMADR
 921  * mapped BAR (dev_priv->mm.gtt->gtt).
 922  */
 923 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 924                                      struct sg_table *st,
 925                                      unsigned int first_entry,
 926                                      enum i915_cache_level level)
 927 {
 928         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 929         gen6_gtt_pte_t __iomem *gtt_entries =
 930                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 931         int i = 0;
 932         struct sg_page_iter sg_iter;
 933         dma_addr_t addr;
 934
 935         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 936                 addr = sg_page_iter_dma_address(&sg_iter);
 937                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
 938                 i++;
 939         }
 940
 941         /* XXX: This serves as a posting read to make sure that the PTE has
 942          * actually been updated. There is some concern that even though
 943          * registers and PTEs are within the same BAR that they are potentially
 944          * of NUMA access patterns. Therefore, even with the way we assume
 945          * hardware should work, we must keep this posting read for paranoia.
 946          */
 947         if (i != 0)
 948                 WARN_ON(readl(&gtt_entries[i-1]) !=
 949                         vm->pte_encode(addr, level, true));
 950
 951         /* This next bit makes the above posting read even more important. We
 952          * want to flush the TLBs only after we're certain all the PTE updates
 953          * have finished.
 954          */
 955         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 956         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 957 }
 958
 959 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 960                                   unsigned int first_entry,
 961                                   unsigned int num_entries,
 962                                   bool use_scratch)
 963 {
 964         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 965         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
 966                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 967         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 968         int i;
 969
 970         if (WARN(num_entries > max_entries,
 971                  "First entry = %d; Num entries = %d (max=%d)\n",
 972                  first_entry, num_entries, max_entries))
 973                 num_entries = max_entries;
 974
 975         scratch_pte = gen8_pte_encode(vm->scratch.addr,
 976                                       I915_CACHE_LLC,
 977                                       use_scratch);
 978         for (i = 0; i < num_entries; i++)
 979                 gen8_set_pte(&gtt_base[i], scratch_pte);
 980         readl(gtt_base);
 981 }
 982
 983 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 984                                   unsigned int first_entry,
 985                                   unsigned int num_entries,
 986                                   bool use_scratch)
 987 {
 988         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 989         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 990                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 991         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 992         int i;
 993
 994         if (WARN(num_entries > max_entries,
 995                  "First entry = %d; Num entries = %d (max=%d)\n",
 996                  first_entry, num_entries, max_entries))
 997                 num_entries = max_entries;
 998
 999         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1000
1001         for (i = 0; i < num_entries; i++)
1002                 iowrite32(scratch_pte, &gtt_base[i]);
1003         readl(gtt_base);
1004 }
1005
1006 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1007                                      struct sg_table *st,
1008                                      unsigned int pg_start,
1009                                      enum i915_cache_level cache_level)
1010 {
1011         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1012                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1013
1014         intel_gtt_insert_sg_entries(st, pg_start, flags);
1015
1016 }
1017
1018 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1019                                   unsigned int first_entry,
1020                                   unsigned int num_entries,
1021                                   bool unused)
1022 {
1023         intel_gtt_clear_range(first_entry, num_entries);
1024 }
1025
1026
1027 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1028                               enum i915_cache_level cache_level)
1029 {
1030         struct drm_device *dev = obj->base.dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1033
1034         dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
1035                                           entry,
1036                                           cache_level);
1037
1038         obj->has_global_gtt_mapping = 1;
1039 }
1040
1041 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
1042 {
1043         struct drm_device *dev = obj->base.dev;
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1046
1047         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1048                                        entry,
1049                                        obj->base.size >> PAGE_SHIFT,
1050                                        true);
1051
1052         obj->has_global_gtt_mapping = 0;
1053 }
1054
1055 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1056 {
1057         struct drm_device *dev = obj->base.dev;
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         bool interruptible;
1060
1061         interruptible = do_idling(dev_priv);
1062
1063         if (!obj->has_dma_mapping)
1064                 dma_unmap_sg(&dev->pdev->dev,
1065                              obj->pages->sgl, obj->pages->nents,
1066                              PCI_DMA_BIDIRECTIONAL);
1067
1068         undo_idling(dev_priv, interruptible);
1069 }
1070
1071 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1072                                   unsigned long color,
1073                                   unsigned long *start,
1074                                   unsigned long *end)
1075 {
1076         if (node->color != color)
1077                 *start += 4096;
1078
1079         if (!list_empty(&node->node_list)) {
1080                 node = list_entry(node->node_list.next,
1081                                   struct drm_mm_node,
1082                                   node_list);
1083                 if (node->allocated && node->color != color)
1084                         *end -= 4096;
1085         }
1086 }
1087
1088 void i915_gem_setup_global_gtt(struct drm_device *dev,
1089                                unsigned long start,
1090                                unsigned long mappable_end,
1091                                unsigned long end)
1092 {
1093         /* Let GEM Manage all of the aperture.
1094          *
1095          * However, leave one page at the end still bound to the scratch page.
1096          * There are a number of places where the hardware apparently prefetches
1097          * past the end of the object, and we've seen multiple hangs with the
1098          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1099          * aperture.  One page should be enough to keep any prefetching inside
1100          * of the aperture.
1101          */
1102         struct drm_i915_private *dev_priv = dev->dev_private;
1103         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1104         struct drm_mm_node *entry;
1105         struct drm_i915_gem_object *obj;
1106         unsigned long hole_start, hole_end;
1107
1108         BUG_ON(mappable_end > end);
1109
1110         /* Subtract the guard page ... */
1111         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1112         if (!HAS_LLC(dev))
1113                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1114
1115         /* Mark any preallocated objects as occupied */
1116         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1117                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1118                 int ret;
1119                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1120                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1121
1122                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1123                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1124                 if (ret)
1125                         DRM_DEBUG_KMS("Reservation failed\n");
1126                 obj->has_global_gtt_mapping = 1;
1127                 list_add(&vma->vma_link, &obj->vma_list);
1128         }
1129
1130         dev_priv->gtt.base.start = start;
1131         dev_priv->gtt.base.total = end - start;
1132
1133         /* Clear any non-preallocated blocks */
1134         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1135                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1136                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1137                               hole_start, hole_end);
1138                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1139         }
1140
1141         /* And finally clear the reserved guard page */
1142         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1143 }
1144
1145 static bool
1146 intel_enable_ppgtt(struct drm_device *dev)
1147 {
1148         if (i915_enable_ppgtt >= 0)
1149                 return i915_enable_ppgtt;
1150
1151 #ifdef CONFIG_INTEL_IOMMU
1152         /* Disable ppgtt on SNB if VT-d is on. */
1153         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1154                 return false;
1155 #endif
1156
1157         return true;
1158 }
1159
1160 void i915_gem_init_global_gtt(struct drm_device *dev)
1161 {
1162         struct drm_i915_private *dev_priv = dev->dev_private;
1163         unsigned long gtt_size, mappable_size;
1164
1165         gtt_size = dev_priv->gtt.base.total;
1166         mappable_size = dev_priv->gtt.mappable_end;
1167
1168         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1169                 int ret;
1170
1171                 if (INTEL_INFO(dev)->gen <= 7) {
1172                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1173                          * aperture accordingly when using aliasing ppgtt. */
1174                         gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
1175                 }
1176
1177                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1178
1179                 ret = i915_gem_init_aliasing_ppgtt(dev);
1180                 if (!ret)
1181                         return;
1182
1183                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
1184                 drm_mm_takedown(&dev_priv->gtt.base.mm);
1185                 if (INTEL_INFO(dev)->gen < 8)
1186                         gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE;
1187         }
1188         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1189 }
1190
1191 static int setup_scratch_page(struct drm_device *dev)
1192 {
1193         struct drm_i915_private *dev_priv = dev->dev_private;
1194         struct page *page;
1195         dma_addr_t dma_addr;
1196
1197         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1198         if (page == NULL)
1199                 return -ENOMEM;
1200         get_page(page);
1201         set_pages_uc(page, 1);
1202
1203 #ifdef CONFIG_INTEL_IOMMU
1204         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1205                                 PCI_DMA_BIDIRECTIONAL);
1206         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1207                 return -EINVAL;
1208 #else
1209         dma_addr = page_to_phys(page);
1210 #endif
1211         dev_priv->gtt.base.scratch.page = page;
1212         dev_priv->gtt.base.scratch.addr = dma_addr;
1213
1214         return 0;
1215 }
1216
1217 static void teardown_scratch_page(struct drm_device *dev)
1218 {
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220         struct page *page = dev_priv->gtt.base.scratch.page;
1221
1222         set_pages_wb(page, 1);
1223         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1224                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1225         put_page(page);
1226         __free_page(page);
1227 }
1228
1229 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1230 {
1231         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1232         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1233         return snb_gmch_ctl << 20;
1234 }
1235
1236 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1237 {
1238         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1239         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1240         if (bdw_gmch_ctl)
1241                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1242         return bdw_gmch_ctl << 20;
1243 }
1244
1245 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1246 {
1247         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1248         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1249         return snb_gmch_ctl << 25; /* 32 MB units */
1250 }
1251
1252 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1253 {
1254         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1255         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1256         return bdw_gmch_ctl << 25; /* 32 MB units */
1257 }
1258
1259 static int ggtt_probe_common(struct drm_device *dev,
1260                              size_t gtt_size)
1261 {
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         phys_addr_t gtt_bus_addr;
1264         int ret;
1265
1266         /* For Modern GENs the PTEs and register space are split in the BAR */
1267         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1268                 (pci_resource_len(dev->pdev, 0) / 2);
1269
1270         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1271         if (!dev_priv->gtt.gsm) {
1272                 DRM_ERROR("Failed to map the gtt page table\n");
1273                 return -ENOMEM;
1274         }
1275
1276         ret = setup_scratch_page(dev);
1277         if (ret) {
1278                 DRM_ERROR("Scratch setup failed\n");
1279                 /* iounmap will also get called at remove, but meh */
1280                 iounmap(dev_priv->gtt.gsm);
1281         }
1282
1283         return ret;
1284 }
1285
1286 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1287  * bits. When using advanced contexts each context stores its own PAT, but
1288  * writing this data shouldn't be harmful even in those cases. */
1289 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1290 {
1291 #define GEN8_PPAT_UC            (0<<0)
1292 #define GEN8_PPAT_WC            (1<<0)
1293 #define GEN8_PPAT_WT            (2<<0)
1294 #define GEN8_PPAT_WB            (3<<0)
1295 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1296 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1297 #define GEN8_PPAT_LLC           (1<<2)
1298 #define GEN8_PPAT_LLCELLC       (2<<2)
1299 #define GEN8_PPAT_LLCeLLC       (3<<2)
1300 #define GEN8_PPAT_AGE(x)        (x<<4)
1301 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1302         uint64_t pat;
1303
1304         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1305               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1306               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1307               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1308               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1309               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1310               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1311               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1312
1313         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1314          * write would work. */
1315         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1316         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1317 }
1318
1319 static int gen8_gmch_probe(struct drm_device *dev,
1320                            size_t *gtt_total,
1321                            size_t *stolen,
1322                            phys_addr_t *mappable_base,
1323                            unsigned long *mappable_end)
1324 {
1325         struct drm_i915_private *dev_priv = dev->dev_private;
1326         unsigned int gtt_size;
1327         u16 snb_gmch_ctl;
1328         int ret;
1329
1330         /* TODO: We're not aware of mappable constraints on gen8 yet */
1331         *mappable_base = pci_resource_start(dev->pdev, 2);
1332         *mappable_end = pci_resource_len(dev->pdev, 2);
1333
1334         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1335                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1336
1337         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1338
1339         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1340
1341         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1342         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1343
1344         gen8_setup_private_ppat(dev_priv);
1345
1346         ret = ggtt_probe_common(dev, gtt_size);
1347
1348         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1349         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1350
1351         return ret;
1352 }
1353
1354 static int gen6_gmch_probe(struct drm_device *dev,
1355                            size_t *gtt_total,
1356                            size_t *stolen,
1357                            phys_addr_t *mappable_base,
1358                            unsigned long *mappable_end)
1359 {
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         unsigned int gtt_size;
1362         u16 snb_gmch_ctl;
1363         int ret;
1364
1365         *mappable_base = pci_resource_start(dev->pdev, 2);
1366         *mappable_end = pci_resource_len(dev->pdev, 2);
1367
1368         /* 64/512MB is the current min/max we actually know of, but this is just
1369          * a coarse sanity check.
1370          */
1371         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1372                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1373                           dev_priv->gtt.mappable_end);
1374                 return -ENXIO;
1375         }
1376
1377         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1378                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1379         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1380
1381         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1382
1383         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1384         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1385
1386         ret = ggtt_probe_common(dev, gtt_size);
1387
1388         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1389         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1390
1391         return ret;
1392 }
1393
1394 static void gen6_gmch_remove(struct i915_address_space *vm)
1395 {
1396
1397         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1398         iounmap(gtt->gsm);
1399         teardown_scratch_page(vm->dev);
1400 }
1401
1402 static int i915_gmch_probe(struct drm_device *dev,
1403                            size_t *gtt_total,
1404                            size_t *stolen,
1405                            phys_addr_t *mappable_base,
1406                            unsigned long *mappable_end)
1407 {
1408         struct drm_i915_private *dev_priv = dev->dev_private;
1409         int ret;
1410
1411         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1412         if (!ret) {
1413                 DRM_ERROR("failed to set up gmch\n");
1414                 return -EIO;
1415         }
1416
1417         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1418
1419         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1420         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1421         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
1422
1423         return 0;
1424 }
1425
1426 static void i915_gmch_remove(struct i915_address_space *vm)
1427 {
1428         intel_gmch_remove();
1429 }
1430
1431 int i915_gem_gtt_init(struct drm_device *dev)
1432 {
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         struct i915_gtt *gtt = &dev_priv->gtt;
1435         int ret;
1436
1437         if (INTEL_INFO(dev)->gen <= 5) {
1438                 gtt->gtt_probe = i915_gmch_probe;
1439                 gtt->base.cleanup = i915_gmch_remove;
1440         } else if (INTEL_INFO(dev)->gen < 8) {
1441                 gtt->gtt_probe = gen6_gmch_probe;
1442                 gtt->base.cleanup = gen6_gmch_remove;
1443                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1444                         gtt->base.pte_encode = iris_pte_encode;
1445                 else if (IS_HASWELL(dev))
1446                         gtt->base.pte_encode = hsw_pte_encode;
1447                 else if (IS_VALLEYVIEW(dev))
1448                         gtt->base.pte_encode = byt_pte_encode;
1449                 else if (INTEL_INFO(dev)->gen >= 7)
1450                         gtt->base.pte_encode = ivb_pte_encode;
1451                 else
1452                         gtt->base.pte_encode = snb_pte_encode;
1453         } else {
1454                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1455                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1456         }
1457
1458         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1459                              &gtt->mappable_base, &gtt->mappable_end);
1460         if (ret)
1461                 return ret;
1462
1463         gtt->base.dev = dev;
1464
1465         /* GMADR is the PCI mmio aperture into the global GTT. */
1466         DRM_INFO("Memory usable by graphics device = %zdM\n",
1467                  gtt->base.total >> 20);
1468         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1469         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1470
1471         return 0;
1472 }