drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 static const struct intel_device_info intel_skylake_info = {
 360         .is_preliminary = 1,
 361         .is_skylake = 1,
 362         .gen = 9, .num_pipes = 3,
 363         .need_gfx_hws = 1, .has_hotplug = 1,
 364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 365         .has_llc = 1,
 366         .has_ddi = 1,
 367         .has_fbc = 1,
 368         GEN_DEFAULT_PIPEOFFSETS,
 369         IVB_CURSOR_OFFSETS,
 370 };
 371
 372 /*
 373  * Make sure any device matches here are from most specific to most
 374  * general.  For example, since the Quanta match is based on the subsystem
 375  * and subvendor IDs, we need it to come before the more general IVB
 376  * PCI ID matches, otherwise we'll use the wrong info struct above.
 377  */
 378 #define INTEL_PCI_IDS \
 379         INTEL_I830_IDS(&intel_i830_info),       \
 380         INTEL_I845G_IDS(&intel_845g_info),      \
 381         INTEL_I85X_IDS(&intel_i85x_info),       \
 382         INTEL_I865G_IDS(&intel_i865g_info),     \
 383         INTEL_I915G_IDS(&intel_i915g_info),     \
 384         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 385         INTEL_I945G_IDS(&intel_i945g_info),     \
 386         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 387         INTEL_I965G_IDS(&intel_i965g_info),     \
 388         INTEL_G33_IDS(&intel_g33_info),         \
 389         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 390         INTEL_GM45_IDS(&intel_gm45_info),       \
 391         INTEL_G45_IDS(&intel_g45_info),         \
 392         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 393         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 394         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 395         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 396         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 397         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 398         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 399         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 400         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 401         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 402         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 403         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 404         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 405         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 406         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 407         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 408         INTEL_CHV_IDS(&intel_cherryview_info),  \
 409         INTEL_SKL_IDS(&intel_skylake_info)
 410
 411 static const struct pci_device_id pciidlist[] = {               /* aka */
 412         INTEL_PCI_IDS,
 413         {0, 0, 0}
 414 };
 415
 416 #if defined(CONFIG_DRM_I915_KMS)
 417 MODULE_DEVICE_TABLE(pci, pciidlist);
 418 #endif
 419
 420 void intel_detect_pch(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = dev->dev_private;
 423         struct pci_dev *pch = NULL;
 424
 425         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 426          * (which really amounts to a PCH but no South Display).
 427          */
 428         if (INTEL_INFO(dev)->num_pipes == 0) {
 429                 dev_priv->pch_type = PCH_NOP;
 430                 return;
 431         }
 432
 433         /*
 434          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 435          * make graphics device passthrough work easy for VMM, that only
 436          * need to expose ISA bridge to let driver know the real hardware
 437          * underneath. This is a requirement from virtualization team.
 438          *
 439          * In some virtualized environments (e.g. XEN), there is irrelevant
 440          * ISA bridge in the system. To work reliably, we should scan trhough
 441          * all the ISA bridge devices and check for the first match, instead
 442          * of only checking the first one.
 443          */
 444         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 445                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 446                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 447                         dev_priv->pch_id = id;
 448
 449                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_IBX;
 451                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 452                                 WARN_ON(!IS_GEN5(dev));
 453                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 454                                 dev_priv->pch_type = PCH_CPT;
 455                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 456                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 457                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 458                                 /* PantherPoint is CPT compatible */
 459                                 dev_priv->pch_type = PCH_CPT;
 460                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 461                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 462                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 463                                 dev_priv->pch_type = PCH_LPT;
 464                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 465                                 WARN_ON(!IS_HASWELL(dev));
 466                                 WARN_ON(IS_HSW_ULT(dev));
 467                         } else if (IS_BROADWELL(dev)) {
 468                                 dev_priv->pch_type = PCH_LPT;
 469                                 dev_priv->pch_id =
 470                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 471                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 472                                               "LynxPoint LP PCH\n");
 473                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 474                                 dev_priv->pch_type = PCH_LPT;
 475                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 476                                 WARN_ON(!IS_HASWELL(dev));
 477                                 WARN_ON(!IS_HSW_ULT(dev));
 478                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 479                                 dev_priv->pch_type = PCH_SPT;
 480                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 481                                 WARN_ON(!IS_SKYLAKE(dev));
 482                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 483                                 dev_priv->pch_type = PCH_SPT;
 484                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 485                                 WARN_ON(!IS_SKYLAKE(dev));
 486                         } else
 487                                 continue;
 488
 489                         break;
 490                 }
 491         }
 492         if (!pch)
 493                 DRM_DEBUG_KMS("No PCH found.\n");
 494
 495         pci_dev_put(pch);
 496 }
 497
 498 bool i915_semaphore_is_enabled(struct drm_device *dev)
 499 {
 500         if (INTEL_INFO(dev)->gen < 6)
 501                 return false;
 502
 503         if (i915.semaphores >= 0)
 504                 return i915.semaphores;
 505
 506         /* TODO: make semaphores and Execlists play nicely together */
 507         if (i915.enable_execlists)
 508                 return false;
 509
 510         /* Until we get further testing... */
 511         if (IS_GEN8(dev))
 512                 return false;
 513
 514 #ifdef CONFIG_INTEL_IOMMU
 515         /* Enable semaphores on SNB when IO remapping is off */
 516         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 517                 return false;
 518 #endif
 519
 520         return true;
 521 }
 522
 523 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 524 {
 525         spin_lock_irq(&dev_priv->irq_lock);
 526
 527         dev_priv->long_hpd_port_mask = 0;
 528         dev_priv->short_hpd_port_mask = 0;
 529         dev_priv->hpd_event_bits = 0;
 530
 531         spin_unlock_irq(&dev_priv->irq_lock);
 532
 533         cancel_work_sync(&dev_priv->dig_port_work);
 534         cancel_work_sync(&dev_priv->hotplug_work);
 535         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 536 }
 537
 538 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 539 {
 540         struct drm_device *dev = dev_priv->dev;
 541         struct drm_encoder *encoder;
 542
 543         drm_modeset_lock_all(dev);
 544         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 545                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 546
 547                 if (intel_encoder->suspend)
 548                         intel_encoder->suspend(intel_encoder);
 549         }
 550         drm_modeset_unlock_all(dev);
 551 }
 552
 553 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 554 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 555                               bool rpm_resume);
 556
 557 static int i915_drm_suspend(struct drm_device *dev)
 558 {
 559         struct drm_i915_private *dev_priv = dev->dev_private;
 560         struct drm_crtc *crtc;
 561         pci_power_t opregion_target_state;
 562
 563         /* ignore lid events during suspend */
 564         mutex_lock(&dev_priv->modeset_restore_lock);
 565         dev_priv->modeset_restore = MODESET_SUSPENDED;
 566         mutex_unlock(&dev_priv->modeset_restore_lock);
 567
 568         /* We do a lot of poking in a lot of registers, make sure they work
 569          * properly. */
 570         intel_display_set_init_power(dev_priv, true);
 571
 572         drm_kms_helper_poll_disable(dev);
 573
 574         pci_save_state(dev->pdev);
 575
 576         /* If KMS is active, we do the leavevt stuff here */
 577         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 578                 int error;
 579
 580                 error = i915_gem_suspend(dev);
 581                 if (error) {
 582                         dev_err(&dev->pdev->dev,
 583                                 "GEM idle failed, resume might fail\n");
 584                         return error;
 585                 }
 586
 587                 intel_suspend_gt_powersave(dev);
 588
 589                 /*
 590                  * Disable CRTCs directly since we want to preserve sw state
 591                  * for _thaw. Also, power gate the CRTC power wells.
 592                  */
 593                 drm_modeset_lock_all(dev);
 594                 for_each_crtc(dev, crtc)
 595                         intel_crtc_control(crtc, false);
 596                 drm_modeset_unlock_all(dev);
 597
 598                 intel_dp_mst_suspend(dev);
 599
 600                 intel_runtime_pm_disable_interrupts(dev_priv);
 601                 intel_hpd_cancel_work(dev_priv);
 602
 603                 intel_suspend_encoders(dev_priv);
 604
 605                 intel_suspend_hw(dev);
 606         }
 607
 608         i915_gem_suspend_gtt_mappings(dev);
 609
 610         i915_save_state(dev);
 611
 612         opregion_target_state = PCI_D3cold;
 613 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 614         if (acpi_target_system_state() < ACPI_STATE_S3)
 615                 opregion_target_state = PCI_D1;
 616 #endif
 617         intel_opregion_notify_adapter(dev, opregion_target_state);
 618
 619         intel_uncore_forcewake_reset(dev, false);
 620         intel_opregion_fini(dev);
 621
 622         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 623
 624         dev_priv->suspend_count++;
 625
 626         intel_display_set_init_power(dev_priv, false);
 627
 628         return 0;
 629 }
 630
 631 static int i915_drm_suspend_late(struct drm_device *drm_dev)
 632 {
 633         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 634         int ret;
 635
 636         ret = intel_suspend_complete(dev_priv);
 637
 638         if (ret) {
 639                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 640
 641                 return ret;
 642         }
 643
 644         pci_disable_device(drm_dev->pdev);
 645         pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 646
 647         return 0;
 648 }
 649
 650 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 651 {
 652         int error;
 653
 654         if (!dev || !dev->dev_private) {
 655                 DRM_ERROR("dev: %p\n", dev);
 656                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 657                 return -ENODEV;
 658         }
 659
 660         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 661                          state.event != PM_EVENT_FREEZE))
 662                 return -EINVAL;
 663
 664         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 665                 return 0;
 666
 667         error = i915_drm_suspend(dev);
 668         if (error)
 669                 return error;
 670
 671         return i915_drm_suspend_late(dev);
 672 }
 673
 674 static int i915_drm_resume(struct drm_device *dev)
 675 {
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677
 678         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 679                 mutex_lock(&dev->struct_mutex);
 680                 i915_gem_restore_gtt_mappings(dev);
 681                 mutex_unlock(&dev->struct_mutex);
 682         }
 683
 684         i915_restore_state(dev);
 685         intel_opregion_setup(dev);
 686
 687         /* KMS EnterVT equivalent */
 688         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 689                 intel_init_pch_refclk(dev);
 690                 drm_mode_config_reset(dev);
 691
 692                 mutex_lock(&dev->struct_mutex);
 693                 if (i915_gem_init_hw(dev)) {
 694                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 695                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 696                 }
 697                 mutex_unlock(&dev->struct_mutex);
 698
 699                 /* We need working interrupts for modeset enabling ... */
 700                 intel_runtime_pm_enable_interrupts(dev_priv);
 701
 702                 intel_modeset_init_hw(dev);
 703
 704                 spin_lock_irq(&dev_priv->irq_lock);
 705                 if (dev_priv->display.hpd_irq_setup)
 706                         dev_priv->display.hpd_irq_setup(dev);
 707                 spin_unlock_irq(&dev_priv->irq_lock);
 708
 709                 drm_modeset_lock_all(dev);
 710                 intel_modeset_setup_hw_state(dev, true);
 711                 drm_modeset_unlock_all(dev);
 712
 713                 intel_dp_mst_resume(dev);
 714
 715                 /*
 716                  * ... but also need to make sure that hotplug processing
 717                  * doesn't cause havoc. Like in the driver load code we don't
 718                  * bother with the tiny race here where we might loose hotplug
 719                  * notifications.
 720                  * */
 721                 intel_hpd_init(dev_priv);
 722                 /* Config may have changed between suspend and resume */
 723                 drm_helper_hpd_irq_event(dev);
 724         }
 725
 726         intel_opregion_init(dev);
 727
 728         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 729
 730         mutex_lock(&dev_priv->modeset_restore_lock);
 731         dev_priv->modeset_restore = MODESET_DONE;
 732         mutex_unlock(&dev_priv->modeset_restore_lock);
 733
 734         intel_opregion_notify_adapter(dev, PCI_D0);
 735
 736         drm_kms_helper_poll_enable(dev);
 737
 738         return 0;
 739 }
 740
 741 static int i915_drm_resume_early(struct drm_device *dev)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         int ret = 0;
 745
 746         /*
 747          * We have a resume ordering issue with the snd-hda driver also
 748          * requiring our device to be power up. Due to the lack of a
 749          * parent/child relationship we currently solve this with an early
 750          * resume hook.
 751          *
 752          * FIXME: This should be solved with a special hdmi sink device or
 753          * similar so that power domains can be employed.
 754          */
 755         if (pci_enable_device(dev->pdev))
 756                 return -EIO;
 757
 758         pci_set_master(dev->pdev);
 759
 760         if (IS_VALLEYVIEW(dev_priv))
 761                 ret = vlv_resume_prepare(dev_priv, false);
 762         if (ret)
 763                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 764
 765         intel_uncore_early_sanitize(dev, true);
 766
 767         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 768                 hsw_disable_pc8(dev_priv);
 769
 770         intel_uncore_sanitize(dev);
 771         intel_power_domains_init_hw(dev_priv);
 772
 773         return ret;
 774 }
 775
 776 int i915_resume_legacy(struct drm_device *dev)
 777 {
 778         int ret;
 779
 780         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 781                 return 0;
 782
 783         ret = i915_drm_resume_early(dev);
 784         if (ret)
 785                 return ret;
 786
 787         return i915_drm_resume(dev);
 788 }
 789
 790 /**
 791  * i915_reset - reset chip after a hang
 792  * @dev: drm device to reset
 793  *
 794  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 795  * reset or otherwise an error code.
 796  *
 797  * Procedure is fairly simple:
 798  *   - reset the chip using the reset reg
 799  *   - re-init context state
 800  *   - re-init hardware status page
 801  *   - re-init ring buffer
 802  *   - re-init interrupt state
 803  *   - re-init display
 804  */
 805 int i915_reset(struct drm_device *dev)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         bool simulated;
 809         int ret;
 810
 811         if (!i915.reset)
 812                 return 0;
 813
 814         intel_reset_gt_powersave(dev);
 815
 816         mutex_lock(&dev->struct_mutex);
 817
 818         i915_gem_reset(dev);
 819
 820         simulated = dev_priv->gpu_error.stop_rings != 0;
 821
 822         ret = intel_gpu_reset(dev);
 823
 824         /* Also reset the gpu hangman. */
 825         if (simulated) {
 826                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 827                 dev_priv->gpu_error.stop_rings = 0;
 828                 if (ret == -ENODEV) {
 829                         DRM_INFO("Reset not implemented, but ignoring "
 830                                  "error for simulated gpu hangs\n");
 831                         ret = 0;
 832                 }
 833         }
 834
 835         if (i915_stop_ring_allow_warn(dev_priv))
 836                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 837
 838         if (ret) {
 839                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 840                 mutex_unlock(&dev->struct_mutex);
 841                 return ret;
 842         }
 843
 844         /* Ok, now get things going again... */
 845
 846         /*
 847          * Everything depends on having the GTT running, so we need to start
 848          * there.  Fortunately we don't need to do this unless we reset the
 849          * chip at a PCI level.
 850          *
 851          * Next we need to restore the context, but we don't use those
 852          * yet either...
 853          *
 854          * Ring buffer needs to be re-initialized in the KMS case, or if X
 855          * was running at the time of the reset (i.e. we weren't VT
 856          * switched away).
 857          */
 858         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 859                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 860                 dev_priv->gpu_error.reload_in_reset = true;
 861
 862                 ret = i915_gem_init_hw(dev);
 863
 864                 dev_priv->gpu_error.reload_in_reset = false;
 865
 866                 mutex_unlock(&dev->struct_mutex);
 867                 if (ret) {
 868                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 869                         return ret;
 870                 }
 871
 872                 /*
 873                  * FIXME: This races pretty badly against concurrent holders of
 874                  * ring interrupts. This is possible since we've started to drop
 875                  * dev->struct_mutex in select places when waiting for the gpu.
 876                  */
 877
 878                 /*
 879                  * rps/rc6 re-init is necessary to restore state lost after the
 880                  * reset and the re-install of gt irqs. Skip for ironlake per
 881                  * previous concerns that it doesn't respond well to some forms
 882                  * of re-init after reset.
 883                  */
 884                 if (INTEL_INFO(dev)->gen > 5)
 885                         intel_enable_gt_powersave(dev);
 886         } else {
 887                 mutex_unlock(&dev->struct_mutex);
 888         }
 889
 890         return 0;
 891 }
 892
 893 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 894 {
 895         struct intel_device_info *intel_info =
 896                 (struct intel_device_info *) ent->driver_data;
 897
 898         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 899                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 900                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 901                 return -ENODEV;
 902         }
 903
 904         /* Only bind to function 0 of the device. Early generations
 905          * used function 1 as a placeholder for multi-head. This causes
 906          * us confusion instead, especially on the systems where both
 907          * functions have the same PCI-ID!
 908          */
 909         if (PCI_FUNC(pdev->devfn))
 910                 return -ENODEV;
 911
 912         driver.driver_features &= ~(DRIVER_USE_AGP);
 913
 914         return drm_get_pci_dev(pdev, ent, &driver);
 915 }
 916
 917 static void
 918 i915_pci_remove(struct pci_dev *pdev)
 919 {
 920         struct drm_device *dev = pci_get_drvdata(pdev);
 921
 922         drm_put_dev(dev);
 923 }
 924
 925 static int i915_pm_suspend(struct device *dev)
 926 {
 927         struct pci_dev *pdev = to_pci_dev(dev);
 928         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 929
 930         if (!drm_dev || !drm_dev->dev_private) {
 931                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 932                 return -ENODEV;
 933         }
 934
 935         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 936                 return 0;
 937
 938         return i915_drm_suspend(drm_dev);
 939 }
 940
 941 static int i915_pm_suspend_late(struct device *dev)
 942 {
 943         struct pci_dev *pdev = to_pci_dev(dev);
 944         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 945
 946         /*
 947          * We have a suspedn ordering issue with the snd-hda driver also
 948          * requiring our device to be power up. Due to the lack of a
 949          * parent/child relationship we currently solve this with an late
 950          * suspend hook.
 951          *
 952          * FIXME: This should be solved with a special hdmi sink device or
 953          * similar so that power domains can be employed.
 954          */
 955         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 956                 return 0;
 957
 958         return i915_drm_suspend_late(drm_dev);
 959 }
 960
 961 static int i915_pm_resume_early(struct device *dev)
 962 {
 963         struct pci_dev *pdev = to_pci_dev(dev);
 964         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 965
 966         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 967                 return 0;
 968
 969         return i915_drm_resume_early(drm_dev);
 970 }
 971
 972 static int i915_pm_resume(struct device *dev)
 973 {
 974         struct pci_dev *pdev = to_pci_dev(dev);
 975         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 976
 977         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 978                 return 0;
 979
 980         return i915_drm_resume(drm_dev);
 981 }
 982
 983 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 984 {
 985         hsw_enable_pc8(dev_priv);
 986
 987         return 0;
 988 }
 989
 990 /*
 991  * Save all Gunit registers that may be lost after a D3 and a subsequent
 992  * S0i[R123] transition. The list of registers needing a save/restore is
 993  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 994  * registers in the following way:
 995  * - Driver: saved/restored by the driver
 996  * - Punit : saved/restored by the Punit firmware
 997  * - No, w/o marking: no need to save/restore, since the register is R/O or
 998  *                    used internally by the HW in a way that doesn't depend
 999  *                    keeping the content across a suspend/resume.
1000  * - Debug : used for debugging
1001  *
1002  * We save/restore all registers marked with 'Driver', with the following
1003  * exceptions:
1004  * - Registers out of use, including also registers marked with 'Debug'.
1005  *   These have no effect on the driver's operation, so we don't save/restore
1006  *   them to reduce the overhead.
1007  * - Registers that are fully setup by an initialization function called from
1008  *   the resume path. For example many clock gating and RPS/RC6 registers.
1009  * - Registers that provide the right functionality with their reset defaults.
1010  *
1011  * TODO: Except for registers that based on the above 3 criteria can be safely
1012  * ignored, we save/restore all others, practically treating the HW context as
1013  * a black-box for the driver. Further investigation is needed to reduce the
1014  * saved/restored registers even further, by following the same 3 criteria.
1015  */
1016 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1017 {
1018         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1019         int i;
1020
1021         /* GAM 0x4000-0x4770 */
1022         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1023         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1024         s->arb_mode             = I915_READ(ARB_MODE);
1025         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1026         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1027
1028         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1029                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1030
1031         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1032         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1033
1034         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1035         s->ecochk               = I915_READ(GAM_ECOCHK);
1036         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1037         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1038
1039         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1040
1041         /* MBC 0x9024-0x91D0, 0x8500 */
1042         s->g3dctl               = I915_READ(VLV_G3DCTL);
1043         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1044         s->mbctl                = I915_READ(GEN6_MBCTL);
1045
1046         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1047         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1048         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1049         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1050         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1051         s->rstctl               = I915_READ(GEN6_RSTCTL);
1052         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1053
1054         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1055         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1056         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1057         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1058         s->ecobus               = I915_READ(ECOBUS);
1059         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1060         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1061         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1062         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1063         s->rcedata              = I915_READ(VLV_RCEDATA);
1064         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1065
1066         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1067         s->gt_imr               = I915_READ(GTIMR);
1068         s->gt_ier               = I915_READ(GTIER);
1069         s->pm_imr               = I915_READ(GEN6_PMIMR);
1070         s->pm_ier               = I915_READ(GEN6_PMIER);
1071
1072         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1073                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1074
1075         /* GT SA CZ domain, 0x100000-0x138124 */
1076         s->tilectl              = I915_READ(TILECTL);
1077         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1078         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1079         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1080         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1081
1082         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1083         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1084         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1085         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1086
1087         /*
1088          * Not saving any of:
1089          * DFT,         0x9800-0x9EC0
1090          * SARB,        0xB000-0xB1FC
1091          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1092          * PCI CFG
1093          */
1094 }
1095
1096 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1097 {
1098         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1099         u32 val;
1100         int i;
1101
1102         /* GAM 0x4000-0x4770 */
1103         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1104         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1105         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1106         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1107         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1108
1109         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1110                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1111
1112         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1113         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1114
1115         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1116         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1117         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1118         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1119
1120         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1121
1122         /* MBC 0x9024-0x91D0, 0x8500 */
1123         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1124         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1125         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1126
1127         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1128         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1129         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1130         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1131         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1132         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1133         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1134
1135         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1136         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1137         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1138         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1139         I915_WRITE(ECOBUS,              s->ecobus);
1140         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1141         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1142         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1143         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1144         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1145         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1146
1147         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1148         I915_WRITE(GTIMR,               s->gt_imr);
1149         I915_WRITE(GTIER,               s->gt_ier);
1150         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1151         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1152
1153         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1154                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1155
1156         /* GT SA CZ domain, 0x100000-0x138124 */
1157         I915_WRITE(TILECTL,                     s->tilectl);
1158         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1159         /*
1160          * Preserve the GT allow wake and GFX force clock bit, they are not
1161          * be restored, as they are used to control the s0ix suspend/resume
1162          * sequence by the caller.
1163          */
1164         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1165         val &= VLV_GTLC_ALLOWWAKEREQ;
1166         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1167         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1168
1169         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1170         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1171         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1172         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1173
1174         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1175
1176         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1177         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1178         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1179         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1180 }
1181
1182 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1183 {
1184         u32 val;
1185         int err;
1186
1187         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1188         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1189
1190 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1191         /* Wait for a previous force-off to settle */
1192         if (force_on) {
1193                 err = wait_for(!COND, 20);
1194                 if (err) {
1195                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1196                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1197                         return err;
1198                 }
1199         }
1200
1201         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1202         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1203         if (force_on)
1204                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1205         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1206
1207         if (!force_on)
1208                 return 0;
1209
1210         err = wait_for(COND, 20);
1211         if (err)
1212                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1213                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1214
1215         return err;
1216 #undef COND
1217 }
1218
1219 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1220 {
1221         u32 val;
1222         int err = 0;
1223
1224         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1225         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1226         if (allow)
1227                 val |= VLV_GTLC_ALLOWWAKEREQ;
1228         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1229         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1230
1231 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1232               allow)
1233         err = wait_for(COND, 1);
1234         if (err)
1235                 DRM_ERROR("timeout disabling GT waking\n");
1236         return err;
1237 #undef COND
1238 }
1239
1240 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1241                                  bool wait_for_on)
1242 {
1243         u32 mask;
1244         u32 val;
1245         int err;
1246
1247         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1248         val = wait_for_on ? mask : 0;
1249 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1250         if (COND)
1251                 return 0;
1252
1253         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1254                         wait_for_on ? "on" : "off",
1255                         I915_READ(VLV_GTLC_PW_STATUS));
1256
1257         /*
1258          * RC6 transitioning can be delayed up to 2 msec (see
1259          * valleyview_enable_rps), use 3 msec for safety.
1260          */
1261         err = wait_for(COND, 3);
1262         if (err)
1263                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1264                           wait_for_on ? "on" : "off");
1265
1266         return err;
1267 #undef COND
1268 }
1269
1270 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1271 {
1272         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1273                 return;
1274
1275         DRM_ERROR("GT register access while GT waking disabled\n");
1276         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1277 }
1278
1279 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1280 {
1281         u32 mask;
1282         int err;
1283
1284         /*
1285          * Bspec defines the following GT well on flags as debug only, so
1286          * don't treat them as hard failures.
1287          */
1288         (void)vlv_wait_for_gt_wells(dev_priv, false);
1289
1290         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1291         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1292
1293         vlv_check_no_gt_access(dev_priv);
1294
1295         err = vlv_force_gfx_clock(dev_priv, true);
1296         if (err)
1297                 goto err1;
1298
1299         err = vlv_allow_gt_wake(dev_priv, false);
1300         if (err)
1301                 goto err2;
1302         vlv_save_gunit_s0ix_state(dev_priv);
1303
1304         err = vlv_force_gfx_clock(dev_priv, false);
1305         if (err)
1306                 goto err2;
1307
1308         return 0;
1309
1310 err2:
1311         /* For safety always re-enable waking and disable gfx clock forcing */
1312         vlv_allow_gt_wake(dev_priv, true);
1313 err1:
1314         vlv_force_gfx_clock(dev_priv, false);
1315
1316         return err;
1317 }
1318
1319 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1320                                 bool rpm_resume)
1321 {
1322         struct drm_device *dev = dev_priv->dev;
1323         int err;
1324         int ret;
1325
1326         /*
1327          * If any of the steps fail just try to continue, that's the best we
1328          * can do at this point. Return the first error code (which will also
1329          * leave RPM permanently disabled).
1330          */
1331         ret = vlv_force_gfx_clock(dev_priv, true);
1332
1333         vlv_restore_gunit_s0ix_state(dev_priv);
1334
1335         err = vlv_allow_gt_wake(dev_priv, true);
1336         if (!ret)
1337                 ret = err;
1338
1339         err = vlv_force_gfx_clock(dev_priv, false);
1340         if (!ret)
1341                 ret = err;
1342
1343         vlv_check_no_gt_access(dev_priv);
1344
1345         if (rpm_resume) {
1346                 intel_init_clock_gating(dev);
1347                 i915_gem_restore_fences(dev);
1348         }
1349
1350         return ret;
1351 }
1352
1353 static int intel_runtime_suspend(struct device *device)
1354 {
1355         struct pci_dev *pdev = to_pci_dev(device);
1356         struct drm_device *dev = pci_get_drvdata(pdev);
1357         struct drm_i915_private *dev_priv = dev->dev_private;
1358         int ret;
1359
1360         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1361                 return -ENODEV;
1362
1363         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1364                 return -ENODEV;
1365
1366         assert_force_wake_inactive(dev_priv);
1367
1368         DRM_DEBUG_KMS("Suspending device\n");
1369
1370         /*
1371          * We could deadlock here in case another thread holding struct_mutex
1372          * calls RPM suspend concurrently, since the RPM suspend will wait
1373          * first for this RPM suspend to finish. In this case the concurrent
1374          * RPM resume will be followed by its RPM suspend counterpart. Still
1375          * for consistency return -EAGAIN, which will reschedule this suspend.
1376          */
1377         if (!mutex_trylock(&dev->struct_mutex)) {
1378                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1379                 /*
1380                  * Bump the expiration timestamp, otherwise the suspend won't
1381                  * be rescheduled.
1382                  */
1383                 pm_runtime_mark_last_busy(device);
1384
1385                 return -EAGAIN;
1386         }
1387         /*
1388          * We are safe here against re-faults, since the fault handler takes
1389          * an RPM reference.
1390          */
1391         i915_gem_release_all_mmaps(dev_priv);
1392         mutex_unlock(&dev->struct_mutex);
1393
1394         intel_suspend_gt_powersave(dev);
1395         intel_runtime_pm_disable_interrupts(dev_priv);
1396
1397         ret = intel_suspend_complete(dev_priv);
1398         if (ret) {
1399                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1400                 intel_runtime_pm_enable_interrupts(dev_priv);
1401
1402                 return ret;
1403         }
1404
1405         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1406         dev_priv->pm.suspended = true;
1407
1408         /*
1409          * FIXME: We really should find a document that references the arguments
1410          * used below!
1411          */
1412         if (IS_HASWELL(dev)) {
1413                 /*
1414                  * current versions of firmware which depend on this opregion
1415                  * notification have repurposed the D1 definition to mean
1416                  * "runtime suspended" vs. what you would normally expect (D3)
1417                  * to distinguish it from notifications that might be sent via
1418                  * the suspend path.
1419                  */
1420                 intel_opregion_notify_adapter(dev, PCI_D1);
1421         } else {
1422                 /*
1423                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1424                  * being detected, and the call we do at intel_runtime_resume()
1425                  * won't be able to restore them. Since PCI_D3hot matches the
1426                  * actual specification and appears to be working, use it. Let's
1427                  * assume the other non-Haswell platforms will stay the same as
1428                  * Broadwell.
1429                  */
1430                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1431         }
1432
1433         DRM_DEBUG_KMS("Device suspended\n");
1434         return 0;
1435 }
1436
1437 static int intel_runtime_resume(struct device *device)
1438 {
1439         struct pci_dev *pdev = to_pci_dev(device);
1440         struct drm_device *dev = pci_get_drvdata(pdev);
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         int ret = 0;
1443
1444         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1445                 return -ENODEV;
1446
1447         DRM_DEBUG_KMS("Resuming device\n");
1448
1449         intel_opregion_notify_adapter(dev, PCI_D0);
1450         dev_priv->pm.suspended = false;
1451
1452         if (IS_GEN6(dev_priv))
1453                 intel_init_pch_refclk(dev);
1454         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1455                 hsw_disable_pc8(dev_priv);
1456         else if (IS_VALLEYVIEW(dev_priv))
1457                 ret = vlv_resume_prepare(dev_priv, true);
1458
1459         /*
1460          * No point of rolling back things in case of an error, as the best
1461          * we can do is to hope that things will still work (and disable RPM).
1462          */
1463         i915_gem_init_swizzling(dev);
1464         gen6_update_ring_freq(dev);
1465
1466         intel_runtime_pm_enable_interrupts(dev_priv);
1467         intel_enable_gt_powersave(dev);
1468
1469         if (ret)
1470                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1471         else
1472                 DRM_DEBUG_KMS("Device resumed\n");
1473
1474         return ret;
1475 }
1476
1477 /*
1478  * This function implements common functionality of runtime and system
1479  * suspend sequence.
1480  */
1481 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1482 {
1483         struct drm_device *dev = dev_priv->dev;
1484         int ret;
1485
1486         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1487                 ret = hsw_suspend_complete(dev_priv);
1488         else if (IS_VALLEYVIEW(dev))
1489                 ret = vlv_suspend_complete(dev_priv);
1490         else
1491                 ret = 0;
1492
1493         return ret;
1494 }
1495
1496 static const struct dev_pm_ops i915_pm_ops = {
1497         /*
1498          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1499          * PMSG_RESUME]
1500          */
1501         .suspend = i915_pm_suspend,
1502         .suspend_late = i915_pm_suspend_late,
1503         .resume_early = i915_pm_resume_early,
1504         .resume = i915_pm_resume,
1505
1506         /*
1507          * S4 event handlers
1508          * @freeze, @freeze_late    : called (1) before creating the
1509          *                            hibernation image [PMSG_FREEZE] and
1510          *                            (2) after rebooting, before restoring
1511          *                            the image [PMSG_QUIESCE]
1512          * @thaw, @thaw_early       : called (1) after creating the hibernation
1513          *                            image, before writing it [PMSG_THAW]
1514          *                            and (2) after failing to create or
1515          *                            restore the image [PMSG_RECOVER]
1516          * @poweroff, @poweroff_late: called after writing the hibernation
1517          *                            image, before rebooting [PMSG_HIBERNATE]
1518          * @restore, @restore_early : called after rebooting and restoring the
1519          *                            hibernation image [PMSG_RESTORE]
1520          */
1521         .freeze = i915_pm_suspend,
1522         .freeze_late = i915_pm_suspend_late,
1523         .thaw_early = i915_pm_resume_early,
1524         .thaw = i915_pm_resume,
1525         .poweroff = i915_pm_suspend,
1526         .poweroff_late = i915_pm_suspend_late,
1527         .restore_early = i915_pm_resume_early,
1528         .restore = i915_pm_resume,
1529
1530         /* S0ix (via runtime suspend) event handlers */
1531         .runtime_suspend = intel_runtime_suspend,
1532         .runtime_resume = intel_runtime_resume,
1533 };
1534
1535 static const struct vm_operations_struct i915_gem_vm_ops = {
1536         .fault = i915_gem_fault,
1537         .open = drm_gem_vm_open,
1538         .close = drm_gem_vm_close,
1539 };
1540
1541 static const struct file_operations i915_driver_fops = {
1542         .owner = THIS_MODULE,
1543         .open = drm_open,
1544         .release = drm_release,
1545         .unlocked_ioctl = drm_ioctl,
1546         .mmap = drm_gem_mmap,
1547         .poll = drm_poll,
1548         .read = drm_read,
1549 #ifdef CONFIG_COMPAT
1550         .compat_ioctl = i915_compat_ioctl,
1551 #endif
1552         .llseek = noop_llseek,
1553 };
1554
1555 static struct drm_driver driver = {
1556         /* Don't use MTRRs here; the Xserver or userspace app should
1557          * deal with them for Intel hardware.
1558          */
1559         .driver_features =
1560             DRIVER_USE_AGP |
1561             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1562             DRIVER_RENDER,
1563         .load = i915_driver_load,
1564         .unload = i915_driver_unload,
1565         .open = i915_driver_open,
1566         .lastclose = i915_driver_lastclose,
1567         .preclose = i915_driver_preclose,
1568         .postclose = i915_driver_postclose,
1569         .set_busid = drm_pci_set_busid,
1570
1571         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1572         .suspend = i915_suspend_legacy,
1573         .resume = i915_resume_legacy,
1574
1575         .device_is_agp = i915_driver_device_is_agp,
1576 #if defined(CONFIG_DEBUG_FS)
1577         .debugfs_init = i915_debugfs_init,
1578         .debugfs_cleanup = i915_debugfs_cleanup,
1579 #endif
1580         .gem_free_object = i915_gem_free_object,
1581         .gem_vm_ops = &i915_gem_vm_ops,
1582
1583         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1584         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1585         .gem_prime_export = i915_gem_prime_export,
1586         .gem_prime_import = i915_gem_prime_import,
1587
1588         .dumb_create = i915_gem_dumb_create,
1589         .dumb_map_offset = i915_gem_mmap_gtt,
1590         .dumb_destroy = drm_gem_dumb_destroy,
1591         .ioctls = i915_ioctls,
1592         .fops = &i915_driver_fops,
1593         .name = DRIVER_NAME,
1594         .desc = DRIVER_DESC,
1595         .date = DRIVER_DATE,
1596         .major = DRIVER_MAJOR,
1597         .minor = DRIVER_MINOR,
1598         .patchlevel = DRIVER_PATCHLEVEL,
1599 };
1600
1601 static struct pci_driver i915_pci_driver = {
1602         .name = DRIVER_NAME,
1603         .id_table = pciidlist,
1604         .probe = i915_pci_probe,
1605         .remove = i915_pci_remove,
1606         .driver.pm = &i915_pm_ops,
1607 };
1608
1609 static int __init i915_init(void)
1610 {
1611         driver.num_ioctls = i915_max_ioctl;
1612
1613         /*
1614          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1615          * explicitly disabled with the module pararmeter.
1616          *
1617          * Otherwise, just follow the parameter (defaulting to off).
1618          *
1619          * Allow optional vga_text_mode_force boot option to override
1620          * the default behavior.
1621          */
1622 #if defined(CONFIG_DRM_I915_KMS)
1623         if (i915.modeset != 0)
1624                 driver.driver_features |= DRIVER_MODESET;
1625 #endif
1626         if (i915.modeset == 1)
1627                 driver.driver_features |= DRIVER_MODESET;
1628
1629 #ifdef CONFIG_VGA_CONSOLE
1630         if (vgacon_text_force() && i915.modeset == -1)
1631                 driver.driver_features &= ~DRIVER_MODESET;
1632 #endif
1633
1634         if (!(driver.driver_features & DRIVER_MODESET)) {
1635                 driver.get_vblank_timestamp = NULL;
1636 #ifndef CONFIG_DRM_I915_UMS
1637                 /* Silently fail loading to not upset userspace. */
1638                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1639                 return 0;
1640 #endif
1641         }
1642
1643         return drm_pci_init(&driver, &i915_pci_driver);
1644 }
1645
1646 static void __exit i915_exit(void)
1647 {
1648 #ifndef CONFIG_DRM_I915_UMS
1649         if (!(driver.driver_features & DRIVER_MODESET))
1650                 return; /* Never loaded a driver. */
1651 #endif
1652
1653         drm_pci_exit(&driver, &i915_pci_driver);
1654 }
1655
1656 module_init(i915_init);
1657 module_exit(i915_exit);
1658
1659 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1660 MODULE_AUTHOR("Intel Corporation");
1661
1662 MODULE_DESCRIPTION(DRIVER_DESC);
1663 MODULE_LICENSE("GPL and additional rights");