drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158 extern int intel_agp_enabled;
 159
 160 static const struct intel_device_info intel_i830_info = {
 161         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163         .ring_mask = RENDER_RING,
 164 };
 165
 166 static const struct intel_device_info intel_845g_info = {
 167         .gen = 2, .num_pipes = 1,
 168         .has_overlay = 1, .overlay_needs_physical = 1,
 169         .ring_mask = RENDER_RING,
 170 };
 171
 172 static const struct intel_device_info intel_i85x_info = {
 173         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 174         .cursor_needs_physical = 1,
 175         .has_overlay = 1, .overlay_needs_physical = 1,
 176         .ring_mask = RENDER_RING,
 177 };
 178
 179 static const struct intel_device_info intel_i865g_info = {
 180         .gen = 2, .num_pipes = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .ring_mask = RENDER_RING,
 183 };
 184
 185 static const struct intel_device_info intel_i915g_info = {
 186         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 187         .has_overlay = 1, .overlay_needs_physical = 1,
 188         .ring_mask = RENDER_RING,
 189 };
 190 static const struct intel_device_info intel_i915gm_info = {
 191         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 192         .cursor_needs_physical = 1,
 193         .has_overlay = 1, .overlay_needs_physical = 1,
 194         .supports_tv = 1,
 195         .ring_mask = RENDER_RING,
 196 };
 197 static const struct intel_device_info intel_i945g_info = {
 198         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 199         .has_overlay = 1, .overlay_needs_physical = 1,
 200         .ring_mask = RENDER_RING,
 201 };
 202 static const struct intel_device_info intel_i945gm_info = {
 203         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 204         .has_hotplug = 1, .cursor_needs_physical = 1,
 205         .has_overlay = 1, .overlay_needs_physical = 1,
 206         .supports_tv = 1,
 207         .ring_mask = RENDER_RING,
 208 };
 209
 210 static const struct intel_device_info intel_i965g_info = {
 211         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 212         .has_hotplug = 1,
 213         .has_overlay = 1,
 214         .ring_mask = RENDER_RING,
 215 };
 216
 217 static const struct intel_device_info intel_i965gm_info = {
 218         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 219         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 220         .has_overlay = 1,
 221         .supports_tv = 1,
 222         .ring_mask = RENDER_RING,
 223 };
 224
 225 static const struct intel_device_info intel_g33_info = {
 226         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_overlay = 1,
 229         .ring_mask = RENDER_RING,
 230 };
 231
 232 static const struct intel_device_info intel_g45_info = {
 233         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 234         .has_pipe_cxsr = 1, .has_hotplug = 1,
 235         .ring_mask = RENDER_RING | BSD_RING,
 236 };
 237
 238 static const struct intel_device_info intel_gm45_info = {
 239         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 240         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 241         .has_pipe_cxsr = 1, .has_hotplug = 1,
 242         .supports_tv = 1,
 243         .ring_mask = RENDER_RING | BSD_RING,
 244 };
 245
 246 static const struct intel_device_info intel_pineview_info = {
 247         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 248         .need_gfx_hws = 1, .has_hotplug = 1,
 249         .has_overlay = 1,
 250 };
 251
 252 static const struct intel_device_info intel_ironlake_d_info = {
 253         .gen = 5, .num_pipes = 2,
 254         .need_gfx_hws = 1, .has_hotplug = 1,
 255         .ring_mask = RENDER_RING | BSD_RING,
 256 };
 257
 258 static const struct intel_device_info intel_ironlake_m_info = {
 259         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 260         .need_gfx_hws = 1, .has_hotplug = 1,
 261         .has_fbc = 1,
 262         .ring_mask = RENDER_RING | BSD_RING,
 263 };
 264
 265 static const struct intel_device_info intel_sandybridge_d_info = {
 266         .gen = 6, .num_pipes = 2,
 267         .need_gfx_hws = 1, .has_hotplug = 1,
 268         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 269         .has_llc = 1,
 270 };
 271
 272 static const struct intel_device_info intel_sandybridge_m_info = {
 273         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 1,
 276         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 277         .has_llc = 1,
 278 };
 279
 280 #define GEN7_FEATURES  \
 281         .gen = 7, .num_pipes = 3, \
 282         .need_gfx_hws = 1, .has_hotplug = 1, \
 283         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 284         .has_llc = 1
 285
 286 static const struct intel_device_info intel_ivybridge_d_info = {
 287         GEN7_FEATURES,
 288         .is_ivybridge = 1,
 289 };
 290
 291 static const struct intel_device_info intel_ivybridge_m_info = {
 292         GEN7_FEATURES,
 293         .is_ivybridge = 1,
 294         .is_mobile = 1,
 295         .has_fbc = 1,
 296 };
 297
 298 static const struct intel_device_info intel_ivybridge_q_info = {
 299         GEN7_FEATURES,
 300         .is_ivybridge = 1,
 301         .num_pipes = 0, /* legal, last one wins */
 302 };
 303
 304 static const struct intel_device_info intel_valleyview_m_info = {
 305         GEN7_FEATURES,
 306         .is_mobile = 1,
 307         .num_pipes = 2,
 308         .is_valleyview = 1,
 309         .display_mmio_offset = VLV_DISPLAY_BASE,
 310         .has_llc = 0, /* legal, last one wins */
 311 };
 312
 313 static const struct intel_device_info intel_valleyview_d_info = {
 314         GEN7_FEATURES,
 315         .num_pipes = 2,
 316         .is_valleyview = 1,
 317         .display_mmio_offset = VLV_DISPLAY_BASE,
 318         .has_llc = 0, /* legal, last one wins */
 319 };
 320
 321 static const struct intel_device_info intel_haswell_d_info = {
 322         GEN7_FEATURES,
 323         .is_haswell = 1,
 324         .has_ddi = 1,
 325         .has_fpga_dbg = 1,
 326         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 327 };
 328
 329 static const struct intel_device_info intel_haswell_m_info = {
 330         GEN7_FEATURES,
 331         .is_haswell = 1,
 332         .is_mobile = 1,
 333         .has_ddi = 1,
 334         .has_fpga_dbg = 1,
 335         .has_fbc = 1,
 336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 337 };
 338
 339 static const struct intel_device_info intel_broadwell_d_info = {
 340         .is_preliminary = 1,
 341         .gen = 8, .num_pipes = 3,
 342         .need_gfx_hws = 1, .has_hotplug = 1,
 343         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 344         .has_llc = 1,
 345         .has_ddi = 1,
 346 };
 347
 348 static const struct intel_device_info intel_broadwell_m_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .has_llc = 1,
 354         .has_ddi = 1,
 355 };
 356
 357 /*
 358  * Make sure any device matches here are from most specific to most
 359  * general.  For example, since the Quanta match is based on the subsystem
 360  * and subvendor IDs, we need it to come before the more general IVB
 361  * PCI ID matches, otherwise we'll use the wrong info struct above.
 362  */
 363 #define INTEL_PCI_IDS \
 364         INTEL_I830_IDS(&intel_i830_info),       \
 365         INTEL_I845G_IDS(&intel_845g_info),      \
 366         INTEL_I85X_IDS(&intel_i85x_info),       \
 367         INTEL_I865G_IDS(&intel_i865g_info),     \
 368         INTEL_I915G_IDS(&intel_i915g_info),     \
 369         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 370         INTEL_I945G_IDS(&intel_i945g_info),     \
 371         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 372         INTEL_I965G_IDS(&intel_i965g_info),     \
 373         INTEL_G33_IDS(&intel_g33_info),         \
 374         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 375         INTEL_GM45_IDS(&intel_gm45_info),       \
 376         INTEL_G45_IDS(&intel_g45_info),         \
 377         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 378         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 379         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 380         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 381         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 382         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 383         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 384         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 385         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 386         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 387         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 388         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 389         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 390         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 391
 392 static const struct pci_device_id pciidlist[] = {               /* aka */
 393         INTEL_PCI_IDS,
 394         {0, 0, 0}
 395 };
 396
 397 #if defined(CONFIG_DRM_I915_KMS)
 398 MODULE_DEVICE_TABLE(pci, pciidlist);
 399 #endif
 400
 401 void intel_detect_pch(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct pci_dev *pch;
 405
 406         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 407          * (which really amounts to a PCH but no South Display).
 408          */
 409         if (INTEL_INFO(dev)->num_pipes == 0) {
 410                 dev_priv->pch_type = PCH_NOP;
 411                 return;
 412         }
 413
 414         /*
 415          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 416          * make graphics device passthrough work easy for VMM, that only
 417          * need to expose ISA bridge to let driver know the real hardware
 418          * underneath. This is a requirement from virtualization team.
 419          *
 420          * In some virtualized environments (e.g. XEN), there is irrelevant
 421          * ISA bridge in the system. To work reliably, we should scan trhough
 422          * all the ISA bridge devices and check for the first match, instead
 423          * of only checking the first one.
 424          */
 425         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 426         while (pch) {
 427                 struct pci_dev *curr = pch;
 428                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 429                         unsigned short id;
 430                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 431                         dev_priv->pch_id = id;
 432
 433                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 434                                 dev_priv->pch_type = PCH_IBX;
 435                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 436                                 WARN_ON(!IS_GEN5(dev));
 437                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 438                                 dev_priv->pch_type = PCH_CPT;
 439                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 440                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 441                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 442                                 /* PantherPoint is CPT compatible */
 443                                 dev_priv->pch_type = PCH_CPT;
 444                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 445                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 446                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 447                                 dev_priv->pch_type = PCH_LPT;
 448                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 449                                 WARN_ON(!IS_HASWELL(dev));
 450                                 WARN_ON(IS_ULT(dev));
 451                         } else if (IS_BROADWELL(dev)) {
 452                                 dev_priv->pch_type = PCH_LPT;
 453                                 dev_priv->pch_id =
 454                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 455                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 456                                               "LynxPoint LP PCH\n");
 457                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 458                                 dev_priv->pch_type = PCH_LPT;
 459                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 460                                 WARN_ON(!IS_HASWELL(dev));
 461                                 WARN_ON(!IS_ULT(dev));
 462                         } else {
 463                                 goto check_next;
 464                         }
 465                         pci_dev_put(pch);
 466                         break;
 467                 }
 468 check_next:
 469                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 470                 pci_dev_put(curr);
 471         }
 472         if (!pch)
 473                 DRM_DEBUG_KMS("No PCH found?\n");
 474 }
 475
 476 bool i915_semaphore_is_enabled(struct drm_device *dev)
 477 {
 478         if (INTEL_INFO(dev)->gen < 6)
 479                 return 0;
 480
 481         /* Until we get further testing... */
 482         if (IS_GEN8(dev)) {
 483                 WARN_ON(!i915_preliminary_hw_support);
 484                 return 0;
 485         }
 486
 487         if (i915_semaphores >= 0)
 488                 return i915_semaphores;
 489
 490 #ifdef CONFIG_INTEL_IOMMU
 491         /* Enable semaphores on SNB when IO remapping is off */
 492         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 493                 return false;
 494 #endif
 495
 496         return 1;
 497 }
 498
 499 static int i915_drm_freeze(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         struct drm_crtc *crtc;
 503
 504         /* ignore lid events during suspend */
 505         mutex_lock(&dev_priv->modeset_restore_lock);
 506         dev_priv->modeset_restore = MODESET_SUSPENDED;
 507         mutex_unlock(&dev_priv->modeset_restore_lock);
 508
 509         /* We do a lot of poking in a lot of registers, make sure they work
 510          * properly. */
 511         hsw_disable_package_c8(dev_priv);
 512         intel_display_set_init_power(dev, true);
 513
 514         drm_kms_helper_poll_disable(dev);
 515
 516         pci_save_state(dev->pdev);
 517
 518         /* If KMS is active, we do the leavevt stuff here */
 519         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 520                 int error;
 521
 522                 error = i915_gem_suspend(dev);
 523                 if (error) {
 524                         dev_err(&dev->pdev->dev,
 525                                 "GEM idle failed, resume might fail\n");
 526                         return error;
 527                 }
 528
 529                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 530
 531                 drm_irq_uninstall(dev);
 532                 dev_priv->enable_hotplug_processing = false;
 533                 /*
 534                  * Disable CRTCs directly since we want to preserve sw state
 535                  * for _thaw.
 536                  */
 537                 mutex_lock(&dev->mode_config.mutex);
 538                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 539                         dev_priv->display.crtc_disable(crtc);
 540                 mutex_unlock(&dev->mode_config.mutex);
 541
 542                 intel_modeset_suspend_hw(dev);
 543         }
 544
 545         i915_gem_suspend_gtt_mappings(dev);
 546
 547         i915_save_state(dev);
 548
 549         intel_opregion_fini(dev);
 550
 551         console_lock();
 552         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 553         console_unlock();
 554
 555         return 0;
 556 }
 557
 558 int i915_suspend(struct drm_device *dev, pm_message_t state)
 559 {
 560         int error;
 561
 562         if (!dev || !dev->dev_private) {
 563                 DRM_ERROR("dev: %p\n", dev);
 564                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 565                 return -ENODEV;
 566         }
 567
 568         if (state.event == PM_EVENT_PRETHAW)
 569                 return 0;
 570
 571
 572         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 573                 return 0;
 574
 575         error = i915_drm_freeze(dev);
 576         if (error)
 577                 return error;
 578
 579         if (state.event == PM_EVENT_SUSPEND) {
 580                 /* Shut down the device */
 581                 pci_disable_device(dev->pdev);
 582                 pci_set_power_state(dev->pdev, PCI_D3hot);
 583         }
 584
 585         return 0;
 586 }
 587
 588 void intel_console_resume(struct work_struct *work)
 589 {
 590         struct drm_i915_private *dev_priv =
 591                 container_of(work, struct drm_i915_private,
 592                              console_resume_work);
 593         struct drm_device *dev = dev_priv->dev;
 594
 595         console_lock();
 596         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 597         console_unlock();
 598 }
 599
 600 static void intel_resume_hotplug(struct drm_device *dev)
 601 {
 602         struct drm_mode_config *mode_config = &dev->mode_config;
 603         struct intel_encoder *encoder;
 604
 605         mutex_lock(&mode_config->mutex);
 606         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 607
 608         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 609                 if (encoder->hot_plug)
 610                         encoder->hot_plug(encoder);
 611
 612         mutex_unlock(&mode_config->mutex);
 613
 614         /* Just fire off a uevent and let userspace tell us what to do */
 615         drm_helper_hpd_irq_event(dev);
 616 }
 617
 618 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 619 {
 620         struct drm_i915_private *dev_priv = dev->dev_private;
 621         int error = 0;
 622
 623         intel_uncore_early_sanitize(dev);
 624
 625         intel_uncore_sanitize(dev);
 626
 627         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 628             restore_gtt_mappings) {
 629                 mutex_lock(&dev->struct_mutex);
 630                 i915_gem_restore_gtt_mappings(dev);
 631                 mutex_unlock(&dev->struct_mutex);
 632         }
 633
 634         intel_power_domains_init_hw(dev);
 635
 636         i915_restore_state(dev);
 637         intel_opregion_setup(dev);
 638
 639         /* KMS EnterVT equivalent */
 640         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 641                 intel_init_pch_refclk(dev);
 642
 643                 mutex_lock(&dev->struct_mutex);
 644
 645                 error = i915_gem_init_hw(dev);
 646                 mutex_unlock(&dev->struct_mutex);
 647
 648                 /* We need working interrupts for modeset enabling ... */
 649                 drm_irq_install(dev);
 650
 651                 intel_modeset_init_hw(dev);
 652
 653                 drm_modeset_lock_all(dev);
 654                 intel_modeset_setup_hw_state(dev, true);
 655                 drm_modeset_unlock_all(dev);
 656
 657                 /*
 658                  * ... but also need to make sure that hotplug processing
 659                  * doesn't cause havoc. Like in the driver load code we don't
 660                  * bother with the tiny race here where we might loose hotplug
 661                  * notifications.
 662                  * */
 663                 intel_hpd_init(dev);
 664                 dev_priv->enable_hotplug_processing = true;
 665                 /* Config may have changed between suspend and resume */
 666                 intel_resume_hotplug(dev);
 667         }
 668
 669         intel_opregion_init(dev);
 670
 671         /*
 672          * The console lock can be pretty contented on resume due
 673          * to all the printk activity.  Try to keep it out of the hot
 674          * path of resume if possible.
 675          */
 676         if (console_trylock()) {
 677                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 678                 console_unlock();
 679         } else {
 680                 schedule_work(&dev_priv->console_resume_work);
 681         }
 682
 683         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 684          * expected level. */
 685         hsw_enable_package_c8(dev_priv);
 686
 687         mutex_lock(&dev_priv->modeset_restore_lock);
 688         dev_priv->modeset_restore = MODESET_DONE;
 689         mutex_unlock(&dev_priv->modeset_restore_lock);
 690         return error;
 691 }
 692
 693 static int i915_drm_thaw(struct drm_device *dev)
 694 {
 695         if (drm_core_check_feature(dev, DRIVER_MODESET))
 696                 i915_check_and_clear_faults(dev);
 697
 698         return __i915_drm_thaw(dev, true);
 699 }
 700
 701 int i915_resume(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int ret;
 705
 706         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 707                 return 0;
 708
 709         if (pci_enable_device(dev->pdev))
 710                 return -EIO;
 711
 712         pci_set_master(dev->pdev);
 713
 714         /*
 715          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 716          * earlier) need to restore the GTT mappings since the BIOS might clear
 717          * all our scratch PTEs.
 718          */
 719         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 720         if (ret)
 721                 return ret;
 722
 723         drm_kms_helper_poll_enable(dev);
 724         return 0;
 725 }
 726
 727 /**
 728  * i915_reset - reset chip after a hang
 729  * @dev: drm device to reset
 730  *
 731  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 732  * reset or otherwise an error code.
 733  *
 734  * Procedure is fairly simple:
 735  *   - reset the chip using the reset reg
 736  *   - re-init context state
 737  *   - re-init hardware status page
 738  *   - re-init ring buffer
 739  *   - re-init interrupt state
 740  *   - re-init display
 741  */
 742 int i915_reset(struct drm_device *dev)
 743 {
 744         drm_i915_private_t *dev_priv = dev->dev_private;
 745         bool simulated;
 746         int ret;
 747
 748         if (!i915_try_reset)
 749                 return 0;
 750
 751         mutex_lock(&dev->struct_mutex);
 752
 753         i915_gem_reset(dev);
 754
 755         simulated = dev_priv->gpu_error.stop_rings != 0;
 756
 757         ret = intel_gpu_reset(dev);
 758
 759         /* Also reset the gpu hangman. */
 760         if (simulated) {
 761                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 762                 dev_priv->gpu_error.stop_rings = 0;
 763                 if (ret == -ENODEV) {
 764                         DRM_ERROR("Reset not implemented, but ignoring "
 765                                   "error for simulated gpu hangs\n");
 766                         ret = 0;
 767                 }
 768         }
 769
 770         if (ret) {
 771                 DRM_ERROR("Failed to reset chip.\n");
 772                 mutex_unlock(&dev->struct_mutex);
 773                 return ret;
 774         }
 775
 776         /* Ok, now get things going again... */
 777
 778         /*
 779          * Everything depends on having the GTT running, so we need to start
 780          * there.  Fortunately we don't need to do this unless we reset the
 781          * chip at a PCI level.
 782          *
 783          * Next we need to restore the context, but we don't use those
 784          * yet either...
 785          *
 786          * Ring buffer needs to be re-initialized in the KMS case, or if X
 787          * was running at the time of the reset (i.e. we weren't VT
 788          * switched away).
 789          */
 790         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 791                         !dev_priv->ums.mm_suspended) {
 792                 bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
 793                 dev_priv->ums.mm_suspended = 0;
 794
 795                 ret = i915_gem_init_hw(dev);
 796                 if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
 797                         DRM_ERROR("HW contexts didn't survive reset\n");
 798                 mutex_unlock(&dev->struct_mutex);
 799                 if (ret) {
 800                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 801                         return ret;
 802                 }
 803
 804                 drm_irq_uninstall(dev);
 805                 drm_irq_install(dev);
 806                 intel_hpd_init(dev);
 807         } else {
 808                 mutex_unlock(&dev->struct_mutex);
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 815 {
 816         struct intel_device_info *intel_info =
 817                 (struct intel_device_info *) ent->driver_data;
 818
 819         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 820                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 821                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 822                 return -ENODEV;
 823         }
 824
 825         /* Only bind to function 0 of the device. Early generations
 826          * used function 1 as a placeholder for multi-head. This causes
 827          * us confusion instead, especially on the systems where both
 828          * functions have the same PCI-ID!
 829          */
 830         if (PCI_FUNC(pdev->devfn))
 831                 return -ENODEV;
 832
 833         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 834          * implementation for gen3 (and only gen3) that used legacy drm maps
 835          * (gasp!) to share buffers between X and the client. Hence we need to
 836          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 837         if (intel_info->gen != 3) {
 838                 driver.driver_features &=
 839                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 840         } else if (!intel_agp_enabled) {
 841                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 842                 return -ENODEV;
 843         }
 844
 845         return drm_get_pci_dev(pdev, ent, &driver);
 846 }
 847
 848 static void
 849 i915_pci_remove(struct pci_dev *pdev)
 850 {
 851         struct drm_device *dev = pci_get_drvdata(pdev);
 852
 853         drm_put_dev(dev);
 854 }
 855
 856 static int i915_pm_suspend(struct device *dev)
 857 {
 858         struct pci_dev *pdev = to_pci_dev(dev);
 859         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 860         int error;
 861
 862         if (!drm_dev || !drm_dev->dev_private) {
 863                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 864                 return -ENODEV;
 865         }
 866
 867         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 868                 return 0;
 869
 870         error = i915_drm_freeze(drm_dev);
 871         if (error)
 872                 return error;
 873
 874         pci_disable_device(pdev);
 875         pci_set_power_state(pdev, PCI_D3hot);
 876
 877         return 0;
 878 }
 879
 880 static int i915_pm_resume(struct device *dev)
 881 {
 882         struct pci_dev *pdev = to_pci_dev(dev);
 883         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 884
 885         return i915_resume(drm_dev);
 886 }
 887
 888 static int i915_pm_freeze(struct device *dev)
 889 {
 890         struct pci_dev *pdev = to_pci_dev(dev);
 891         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 892
 893         if (!drm_dev || !drm_dev->dev_private) {
 894                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 895                 return -ENODEV;
 896         }
 897
 898         return i915_drm_freeze(drm_dev);
 899 }
 900
 901 static int i915_pm_thaw(struct device *dev)
 902 {
 903         struct pci_dev *pdev = to_pci_dev(dev);
 904         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 905
 906         return i915_drm_thaw(drm_dev);
 907 }
 908
 909 static int i915_pm_poweroff(struct device *dev)
 910 {
 911         struct pci_dev *pdev = to_pci_dev(dev);
 912         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 913
 914         return i915_drm_freeze(drm_dev);
 915 }
 916
 917 static const struct dev_pm_ops i915_pm_ops = {
 918         .suspend = i915_pm_suspend,
 919         .resume = i915_pm_resume,
 920         .freeze = i915_pm_freeze,
 921         .thaw = i915_pm_thaw,
 922         .poweroff = i915_pm_poweroff,
 923         .restore = i915_pm_resume,
 924 };
 925
 926 static const struct vm_operations_struct i915_gem_vm_ops = {
 927         .fault = i915_gem_fault,
 928         .open = drm_gem_vm_open,
 929         .close = drm_gem_vm_close,
 930 };
 931
 932 static const struct file_operations i915_driver_fops = {
 933         .owner = THIS_MODULE,
 934         .open = drm_open,
 935         .release = drm_release,
 936         .unlocked_ioctl = drm_ioctl,
 937         .mmap = drm_gem_mmap,
 938         .poll = drm_poll,
 939         .read = drm_read,
 940 #ifdef CONFIG_COMPAT
 941         .compat_ioctl = i915_compat_ioctl,
 942 #endif
 943         .llseek = noop_llseek,
 944 };
 945
 946 static struct drm_driver driver = {
 947         /* Don't use MTRRs here; the Xserver or userspace app should
 948          * deal with them for Intel hardware.
 949          */
 950         .driver_features =
 951             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 952             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 953             DRIVER_RENDER,
 954         .load = i915_driver_load,
 955         .unload = i915_driver_unload,
 956         .open = i915_driver_open,
 957         .lastclose = i915_driver_lastclose,
 958         .preclose = i915_driver_preclose,
 959         .postclose = i915_driver_postclose,
 960
 961         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 962         .suspend = i915_suspend,
 963         .resume = i915_resume,
 964
 965         .device_is_agp = i915_driver_device_is_agp,
 966         .master_create = i915_master_create,
 967         .master_destroy = i915_master_destroy,
 968 #if defined(CONFIG_DEBUG_FS)
 969         .debugfs_init = i915_debugfs_init,
 970         .debugfs_cleanup = i915_debugfs_cleanup,
 971 #endif
 972         .gem_free_object = i915_gem_free_object,
 973         .gem_vm_ops = &i915_gem_vm_ops,
 974
 975         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 976         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 977         .gem_prime_export = i915_gem_prime_export,
 978         .gem_prime_import = i915_gem_prime_import,
 979
 980         .dumb_create = i915_gem_dumb_create,
 981         .dumb_map_offset = i915_gem_mmap_gtt,
 982         .dumb_destroy = drm_gem_dumb_destroy,
 983         .ioctls = i915_ioctls,
 984         .fops = &i915_driver_fops,
 985         .name = DRIVER_NAME,
 986         .desc = DRIVER_DESC,
 987         .date = DRIVER_DATE,
 988         .major = DRIVER_MAJOR,
 989         .minor = DRIVER_MINOR,
 990         .patchlevel = DRIVER_PATCHLEVEL,
 991 };
 992
 993 static struct pci_driver i915_pci_driver = {
 994         .name = DRIVER_NAME,
 995         .id_table = pciidlist,
 996         .probe = i915_pci_probe,
 997         .remove = i915_pci_remove,
 998         .driver.pm = &i915_pm_ops,
 999 };
1000
1001 static int __init i915_init(void)
1002 {
1003         driver.num_ioctls = i915_max_ioctl;
1004
1005         /*
1006          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1007          * explicitly disabled with the module pararmeter.
1008          *
1009          * Otherwise, just follow the parameter (defaulting to off).
1010          *
1011          * Allow optional vga_text_mode_force boot option to override
1012          * the default behavior.
1013          */
1014 #if defined(CONFIG_DRM_I915_KMS)
1015         if (i915_modeset != 0)
1016                 driver.driver_features |= DRIVER_MODESET;
1017 #endif
1018         if (i915_modeset == 1)
1019                 driver.driver_features |= DRIVER_MODESET;
1020
1021 #ifdef CONFIG_VGA_CONSOLE
1022         if (vgacon_text_force() && i915_modeset == -1)
1023                 driver.driver_features &= ~DRIVER_MODESET;
1024 #endif
1025
1026         if (!(driver.driver_features & DRIVER_MODESET))
1027                 driver.get_vblank_timestamp = NULL;
1028
1029         return drm_pci_init(&driver, &i915_pci_driver);
1030 }
1031
1032 static void __exit i915_exit(void)
1033 {
1034         drm_pci_exit(&driver, &i915_pci_driver);
1035 }
1036
1037 module_init(i915_init);
1038 module_exit(i915_exit);
1039
1040 MODULE_AUTHOR(DRIVER_AUTHOR);
1041 MODULE_DESCRIPTION(DRIVER_DESC);
1042 MODULE_LICENSE("GPL and additional rights");