drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT_MS     1000
  44
  45 /* Firmware Names */
  46 #ifdef CONFIG_DRM_AMDGPU_CIK
  47 #define FIRMWARE_BONAIRE        "radeon/bonaire_uvd.bin"
  48 #define FIRMWARE_KABINI         "radeon/kabini_uvd.bin"
  49 #define FIRMWARE_KAVERI         "radeon/kaveri_uvd.bin"
  50 #define FIRMWARE_HAWAII         "radeon/hawaii_uvd.bin"
  51 #define FIRMWARE_MULLINS        "radeon/mullins_uvd.bin"
  52 #endif
  53 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  54 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  55
  56 /**
  57  * amdgpu_uvd_cs_ctx - Command submission parser context
  58  *
  59  * Used for emulating virtual memory support on UVD 4.2.
  60  */
  61 struct amdgpu_uvd_cs_ctx {
  62         struct amdgpu_cs_parser *parser;
  63         unsigned reg, count;
  64         unsigned data0, data1;
  65         unsigned idx;
  66         unsigned ib_idx;
  67
  68         /* does the IB has a msg command */
  69         bool has_msg_cmd;
  70
  71         /* minimum buffer sizes */
  72         unsigned *buf_sizes;
  73 };
  74
  75 #ifdef CONFIG_DRM_AMDGPU_CIK
  76 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  77 MODULE_FIRMWARE(FIRMWARE_KABINI);
  78 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  79 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  80 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  81 #endif
  82 MODULE_FIRMWARE(FIRMWARE_TONGA);
  83 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  84
  85 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
  86 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
  87
  88 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
  89 {
  90         unsigned long bo_size;
  91         const char *fw_name;
  92         const struct common_firmware_header *hdr;
  93         unsigned version_major, version_minor, family_id;
  94         int i, r;
  95
  96         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
  97
  98         switch (adev->asic_type) {
  99 #ifdef CONFIG_DRM_AMDGPU_CIK
 100         case CHIP_BONAIRE:
 101                 fw_name = FIRMWARE_BONAIRE;
 102                 break;
 103         case CHIP_KABINI:
 104                 fw_name = FIRMWARE_KABINI;
 105                 break;
 106         case CHIP_KAVERI:
 107                 fw_name = FIRMWARE_KAVERI;
 108                 break;
 109         case CHIP_HAWAII:
 110                 fw_name = FIRMWARE_HAWAII;
 111                 break;
 112         case CHIP_MULLINS:
 113                 fw_name = FIRMWARE_MULLINS;
 114                 break;
 115 #endif
 116         case CHIP_TONGA:
 117                 fw_name = FIRMWARE_TONGA;
 118                 break;
 119         case CHIP_CARRIZO:
 120                 fw_name = FIRMWARE_CARRIZO;
 121                 break;
 122         default:
 123                 return -EINVAL;
 124         }
 125
 126         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 127         if (r) {
 128                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 129                         fw_name);
 130                 return r;
 131         }
 132
 133         r = amdgpu_ucode_validate(adev->uvd.fw);
 134         if (r) {
 135                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 136                         fw_name);
 137                 release_firmware(adev->uvd.fw);
 138                 adev->uvd.fw = NULL;
 139                 return r;
 140         }
 141
 142         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 143         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 144         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 145         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 146         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 147                 version_major, version_minor, family_id);
 148
 149         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 150                  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
 151         r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
 152                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
 153         if (r) {
 154                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 155                 return r;
 156         }
 157
 158         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 159         if (r) {
 160                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 161                 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
 162                 return r;
 163         }
 164
 165         r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 166                           &adev->uvd.gpu_addr);
 167         if (r) {
 168                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 169                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 170                 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
 171                 return r;
 172         }
 173
 174         r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
 175         if (r) {
 176                 dev_err(adev->dev, "(%d) UVD map failed\n", r);
 177                 return r;
 178         }
 179
 180         amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 181
 182         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 183                 atomic_set(&adev->uvd.handles[i], 0);
 184                 adev->uvd.filp[i] = NULL;
 185         }
 186
 187         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 188         if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 189                 adev->uvd.address_64_bit = true;
 190
 191         return 0;
 192 }
 193
 194 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 195 {
 196         int r;
 197
 198         if (adev->uvd.vcpu_bo == NULL)
 199                 return 0;
 200
 201         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 202         if (!r) {
 203                 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
 204                 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
 205                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 206         }
 207
 208         amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 209
 210         amdgpu_ring_fini(&adev->uvd.ring);
 211
 212         release_firmware(adev->uvd.fw);
 213
 214         return 0;
 215 }
 216
 217 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 218 {
 219         unsigned size;
 220         void *ptr;
 221         const struct common_firmware_header *hdr;
 222         int i;
 223
 224         if (adev->uvd.vcpu_bo == NULL)
 225                 return 0;
 226
 227         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 228                 if (atomic_read(&adev->uvd.handles[i]))
 229                         break;
 230
 231         if (i == AMDGPU_MAX_UVD_HANDLES)
 232                 return 0;
 233
 234         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 235
 236         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 237         size -= le32_to_cpu(hdr->ucode_size_bytes);
 238
 239         ptr = adev->uvd.cpu_addr;
 240         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 241
 242         adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 243         memcpy(adev->uvd.saved_bo, ptr, size);
 244
 245         return 0;
 246 }
 247
 248 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 249 {
 250         unsigned size;
 251         void *ptr;
 252         const struct common_firmware_header *hdr;
 253         unsigned offset;
 254
 255         if (adev->uvd.vcpu_bo == NULL)
 256                 return -EINVAL;
 257
 258         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 259         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 260         memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
 261                 (adev->uvd.fw->size) - offset);
 262
 263         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 264         size -= le32_to_cpu(hdr->ucode_size_bytes);
 265         ptr = adev->uvd.cpu_addr;
 266         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 267
 268         if (adev->uvd.saved_bo != NULL) {
 269                 memcpy(ptr, adev->uvd.saved_bo, size);
 270                 kfree(adev->uvd.saved_bo);
 271                 adev->uvd.saved_bo = NULL;
 272         } else
 273                 memset(ptr, 0, size);
 274
 275         return 0;
 276 }
 277
 278 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 279 {
 280         struct amdgpu_ring *ring = &adev->uvd.ring;
 281         int i, r;
 282
 283         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 284                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 285                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 286                         struct amdgpu_fence *fence;
 287
 288                         amdgpu_uvd_note_usage(adev);
 289
 290                         r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
 291                         if (r) {
 292                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 293                                 continue;
 294                         }
 295
 296                         amdgpu_fence_wait(fence, false);
 297                         amdgpu_fence_unref(&fence);
 298
 299                         adev->uvd.filp[i] = NULL;
 300                         atomic_set(&adev->uvd.handles[i], 0);
 301                 }
 302         }
 303 }
 304
 305 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
 306 {
 307         int i;
 308         for (i = 0; i < rbo->placement.num_placement; ++i) {
 309                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 310                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 311         }
 312 }
 313
 314 /**
 315  * amdgpu_uvd_cs_pass1 - first parsing round
 316  *
 317  * @ctx: UVD parser context
 318  *
 319  * Make sure UVD message and feedback buffers are in VRAM and
 320  * nobody is violating an 256MB boundary.
 321  */
 322 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 323 {
 324         struct amdgpu_bo_va_mapping *mapping;
 325         struct amdgpu_bo *bo;
 326         uint32_t cmd, lo, hi;
 327         uint64_t addr;
 328         int r = 0;
 329
 330         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 331         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 332         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 333
 334         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 335         if (mapping == NULL) {
 336                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 337                 return -EINVAL;
 338         }
 339
 340         if (!ctx->parser->adev->uvd.address_64_bit) {
 341                 /* check if it's a message or feedback command */
 342                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 343                 if (cmd == 0x0 || cmd == 0x3) {
 344                         /* yes, force it into VRAM */
 345                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 346                         amdgpu_ttm_placement_from_domain(bo, domain);
 347                 }
 348                 amdgpu_uvd_force_into_uvd_segment(bo);
 349
 350                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 351         }
 352
 353         return r;
 354 }
 355
 356 /**
 357  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 358  *
 359  * @msg: pointer to message structure
 360  * @buf_sizes: returned buffer sizes
 361  *
 362  * Peek into the decode message and calculate the necessary buffer sizes.
 363  */
 364 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 365 {
 366         unsigned stream_type = msg[4];
 367         unsigned width = msg[6];
 368         unsigned height = msg[7];
 369         unsigned dpb_size = msg[9];
 370         unsigned pitch = msg[28];
 371         unsigned level = msg[57];
 372
 373         unsigned width_in_mb = width / 16;
 374         unsigned height_in_mb = ALIGN(height / 16, 2);
 375         unsigned fs_in_mb = width_in_mb * height_in_mb;
 376
 377         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
 378
 379         image_size = width * height;
 380         image_size += image_size / 2;
 381         image_size = ALIGN(image_size, 1024);
 382
 383         switch (stream_type) {
 384         case 0: /* H264 */
 385         case 7: /* H264 Perf */
 386                 switch(level) {
 387                 case 30:
 388                         num_dpb_buffer = 8100 / fs_in_mb;
 389                         break;
 390                 case 31:
 391                         num_dpb_buffer = 18000 / fs_in_mb;
 392                         break;
 393                 case 32:
 394                         num_dpb_buffer = 20480 / fs_in_mb;
 395                         break;
 396                 case 41:
 397                         num_dpb_buffer = 32768 / fs_in_mb;
 398                         break;
 399                 case 42:
 400                         num_dpb_buffer = 34816 / fs_in_mb;
 401                         break;
 402                 case 50:
 403                         num_dpb_buffer = 110400 / fs_in_mb;
 404                         break;
 405                 case 51:
 406                         num_dpb_buffer = 184320 / fs_in_mb;
 407                         break;
 408                 default:
 409                         num_dpb_buffer = 184320 / fs_in_mb;
 410                         break;
 411                 }
 412                 num_dpb_buffer++;
 413                 if (num_dpb_buffer > 17)
 414                         num_dpb_buffer = 17;
 415
 416                 /* reference picture buffer */
 417                 min_dpb_size = image_size * num_dpb_buffer;
 418
 419                 /* macroblock context buffer */
 420                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 421
 422                 /* IT surface buffer */
 423                 min_dpb_size += width_in_mb * height_in_mb * 32;
 424                 break;
 425
 426         case 1: /* VC1 */
 427
 428                 /* reference picture buffer */
 429                 min_dpb_size = image_size * 3;
 430
 431                 /* CONTEXT_BUFFER */
 432                 min_dpb_size += width_in_mb * height_in_mb * 128;
 433
 434                 /* IT surface buffer */
 435                 min_dpb_size += width_in_mb * 64;
 436
 437                 /* DB surface buffer */
 438                 min_dpb_size += width_in_mb * 128;
 439
 440                 /* BP */
 441                 tmp = max(width_in_mb, height_in_mb);
 442                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 443                 break;
 444
 445         case 3: /* MPEG2 */
 446
 447                 /* reference picture buffer */
 448                 min_dpb_size = image_size * 3;
 449                 break;
 450
 451         case 4: /* MPEG4 */
 452
 453                 /* reference picture buffer */
 454                 min_dpb_size = image_size * 3;
 455
 456                 /* CM */
 457                 min_dpb_size += width_in_mb * height_in_mb * 64;
 458
 459                 /* IT surface buffer */
 460                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 461                 break;
 462
 463         case 16: /* H265 */
 464                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 465                 image_size = ALIGN(image_size, 256);
 466
 467                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 468                 min_dpb_size = image_size * num_dpb_buffer;
 469                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 470                                            * 16 * num_dpb_buffer + 52 * 1024;
 471                 break;
 472
 473         default:
 474                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 475                 return -EINVAL;
 476         }
 477
 478         if (width > pitch) {
 479                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 480                 return -EINVAL;
 481         }
 482
 483         if (dpb_size < min_dpb_size) {
 484                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 485                           dpb_size, min_dpb_size);
 486                 return -EINVAL;
 487         }
 488
 489         buf_sizes[0x1] = dpb_size;
 490         buf_sizes[0x2] = image_size;
 491         buf_sizes[0x4] = min_ctx_size;
 492         return 0;
 493 }
 494
 495 /**
 496  * amdgpu_uvd_cs_msg - handle UVD message
 497  *
 498  * @ctx: UVD parser context
 499  * @bo: buffer object containing the message
 500  * @offset: offset into the buffer object
 501  *
 502  * Peek into the UVD message and extract the session id.
 503  * Make sure that we don't open up to many sessions.
 504  */
 505 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 506                              struct amdgpu_bo *bo, unsigned offset)
 507 {
 508         struct amdgpu_device *adev = ctx->parser->adev;
 509         int32_t *msg, msg_type, handle;
 510         struct fence *f;
 511         void *ptr;
 512
 513         int i, r;
 514
 515         if (offset & 0x3F) {
 516                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 517                 return -EINVAL;
 518         }
 519
 520         f = reservation_object_get_excl(bo->tbo.resv);
 521         if (f) {
 522                 r = amdgpu_fence_wait((struct amdgpu_fence *)f, false);
 523                 if (r) {
 524                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 525                         return r;
 526                 }
 527         }
 528
 529         r = amdgpu_bo_kmap(bo, &ptr);
 530         if (r) {
 531                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 532                 return r;
 533         }
 534
 535         msg = ptr + offset;
 536
 537         msg_type = msg[1];
 538         handle = msg[2];
 539
 540         if (handle == 0) {
 541                 DRM_ERROR("Invalid UVD handle!\n");
 542                 return -EINVAL;
 543         }
 544
 545         if (msg_type == 1) {
 546                 /* it's a decode msg, calc buffer sizes */
 547                 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
 548                 amdgpu_bo_kunmap(bo);
 549                 if (r)
 550                         return r;
 551
 552         } else if (msg_type == 2) {
 553                 /* it's a destroy msg, free the handle */
 554                 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 555                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 556                 amdgpu_bo_kunmap(bo);
 557                 return 0;
 558         } else {
 559                 /* it's a create msg */
 560                 amdgpu_bo_kunmap(bo);
 561
 562                 if (msg_type != 0) {
 563                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 564                         return -EINVAL;
 565                 }
 566
 567                 /* it's a create msg, no special handling needed */
 568         }
 569
 570         /* create or decode, validate the handle */
 571         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 572                 if (atomic_read(&adev->uvd.handles[i]) == handle)
 573                         return 0;
 574         }
 575
 576         /* handle not found try to alloc a new one */
 577         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 578                 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 579                         adev->uvd.filp[i] = ctx->parser->filp;
 580                         return 0;
 581                 }
 582         }
 583
 584         DRM_ERROR("No more free UVD handles!\n");
 585         return -EINVAL;
 586 }
 587
 588 /**
 589  * amdgpu_uvd_cs_pass2 - second parsing round
 590  *
 591  * @ctx: UVD parser context
 592  *
 593  * Patch buffer addresses, make sure buffer sizes are correct.
 594  */
 595 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 596 {
 597         struct amdgpu_bo_va_mapping *mapping;
 598         struct amdgpu_bo *bo;
 599         struct amdgpu_ib *ib;
 600         uint32_t cmd, lo, hi;
 601         uint64_t start, end;
 602         uint64_t addr;
 603         int r;
 604
 605         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 606         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 607         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 608
 609         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 610         if (mapping == NULL)
 611                 return -EINVAL;
 612
 613         start = amdgpu_bo_gpu_offset(bo);
 614
 615         end = (mapping->it.last + 1 - mapping->it.start);
 616         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 617
 618         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 619         start += addr;
 620
 621         ib = &ctx->parser->ibs[ctx->ib_idx];
 622         ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
 623         ib->ptr[ctx->data1] = start >> 32;
 624
 625         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 626         if (cmd < 0x4) {
 627                 if ((end - start) < ctx->buf_sizes[cmd]) {
 628                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 629                                   (unsigned)(end - start),
 630                                   ctx->buf_sizes[cmd]);
 631                         return -EINVAL;
 632                 }
 633
 634         } else if (cmd == 0x206) {
 635                 if ((end - start) < ctx->buf_sizes[4]) {
 636                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 637                                           (unsigned)(end - start),
 638                                           ctx->buf_sizes[4]);
 639                         return -EINVAL;
 640                 }
 641         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 642                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 643                 return -EINVAL;
 644         }
 645
 646         if (!ctx->parser->adev->uvd.address_64_bit) {
 647                 if ((start >> 28) != ((end - 1) >> 28)) {
 648                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 649                                   start, end);
 650                         return -EINVAL;
 651                 }
 652
 653                 if ((cmd == 0 || cmd == 0x3) &&
 654                     (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
 655                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 656                                   start, end);
 657                         return -EINVAL;
 658                 }
 659         }
 660
 661         if (cmd == 0) {
 662                 ctx->has_msg_cmd = true;
 663                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 664                 if (r)
 665                         return r;
 666         } else if (!ctx->has_msg_cmd) {
 667                 DRM_ERROR("Message needed before other commands are send!\n");
 668                 return -EINVAL;
 669         }
 670
 671         return 0;
 672 }
 673
 674 /**
 675  * amdgpu_uvd_cs_reg - parse register writes
 676  *
 677  * @ctx: UVD parser context
 678  * @cb: callback function
 679  *
 680  * Parse the register writes, call cb on each complete command.
 681  */
 682 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 683                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 684 {
 685         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 686         int i, r;
 687
 688         ctx->idx++;
 689         for (i = 0; i <= ctx->count; ++i) {
 690                 unsigned reg = ctx->reg + i;
 691
 692                 if (ctx->idx >= ib->length_dw) {
 693                         DRM_ERROR("Register command after end of CS!\n");
 694                         return -EINVAL;
 695                 }
 696
 697                 switch (reg) {
 698                 case mmUVD_GPCOM_VCPU_DATA0:
 699                         ctx->data0 = ctx->idx;
 700                         break;
 701                 case mmUVD_GPCOM_VCPU_DATA1:
 702                         ctx->data1 = ctx->idx;
 703                         break;
 704                 case mmUVD_GPCOM_VCPU_CMD:
 705                         r = cb(ctx);
 706                         if (r)
 707                                 return r;
 708                         break;
 709                 case mmUVD_ENGINE_CNTL:
 710                         break;
 711                 default:
 712                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 713                         return -EINVAL;
 714                 }
 715                 ctx->idx++;
 716         }
 717         return 0;
 718 }
 719
 720 /**
 721  * amdgpu_uvd_cs_packets - parse UVD packets
 722  *
 723  * @ctx: UVD parser context
 724  * @cb: callback function
 725  *
 726  * Parse the command stream packets.
 727  */
 728 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 729                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 730 {
 731         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 732         int r;
 733
 734         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 735                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 736                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 737                 switch (type) {
 738                 case PACKET_TYPE0:
 739                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 740                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 741                         r = amdgpu_uvd_cs_reg(ctx, cb);
 742                         if (r)
 743                                 return r;
 744                         break;
 745                 case PACKET_TYPE2:
 746                         ++ctx->idx;
 747                         break;
 748                 default:
 749                         DRM_ERROR("Unknown packet type %d !\n", type);
 750                         return -EINVAL;
 751                 }
 752         }
 753         return 0;
 754 }
 755
 756 /**
 757  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 758  *
 759  * @parser: Command submission parser context
 760  *
 761  * Parse the command stream, patch in addresses as necessary.
 762  */
 763 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 764 {
 765         struct amdgpu_uvd_cs_ctx ctx = {};
 766         unsigned buf_sizes[] = {
 767                 [0x00000000]    =       2048,
 768                 [0x00000001]    =       0xFFFFFFFF,
 769                 [0x00000002]    =       0xFFFFFFFF,
 770                 [0x00000003]    =       2048,
 771                 [0x00000004]    =       0xFFFFFFFF,
 772         };
 773         struct amdgpu_ib *ib = &parser->ibs[ib_idx];
 774         int r;
 775
 776         if (ib->length_dw % 16) {
 777                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 778                           ib->length_dw);
 779                 return -EINVAL;
 780         }
 781
 782         ctx.parser = parser;
 783         ctx.buf_sizes = buf_sizes;
 784         ctx.ib_idx = ib_idx;
 785
 786         /* first round, make sure the buffers are actually in the UVD segment */
 787         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 788         if (r)
 789                 return r;
 790
 791         /* second round, patch buffer addresses into the command stream */
 792         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 793         if (r)
 794                 return r;
 795
 796         if (!ctx.has_msg_cmd) {
 797                 DRM_ERROR("UVD-IBs need a msg command!\n");
 798                 return -EINVAL;
 799         }
 800
 801         amdgpu_uvd_note_usage(ctx.parser->adev);
 802
 803         return 0;
 804 }
 805
 806 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
 807                                struct amdgpu_bo *bo,
 808                                struct amdgpu_fence **fence)
 809 {
 810         struct ttm_validate_buffer tv;
 811         struct ww_acquire_ctx ticket;
 812         struct list_head head;
 813         struct amdgpu_ib ib;
 814         uint64_t addr;
 815         int i, r;
 816
 817         memset(&tv, 0, sizeof(tv));
 818         tv.bo = &bo->tbo;
 819
 820         INIT_LIST_HEAD(&head);
 821         list_add(&tv.head, &head);
 822
 823         r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
 824         if (r)
 825                 return r;
 826
 827         if (!bo->adev->uvd.address_64_bit) {
 828                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 829                 amdgpu_uvd_force_into_uvd_segment(bo);
 830         }
 831
 832         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 833         if (r)
 834                 goto err;
 835
 836         r = amdgpu_ib_get(ring, NULL, 64, &ib);
 837         if (r)
 838                 goto err;
 839
 840         addr = amdgpu_bo_gpu_offset(bo);
 841         ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
 842         ib.ptr[1] = addr;
 843         ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
 844         ib.ptr[3] = addr >> 32;
 845         ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
 846         ib.ptr[5] = 0;
 847         for (i = 6; i < 16; ++i)
 848                 ib.ptr[i] = PACKET2(0);
 849         ib.length_dw = 16;
 850
 851         r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
 852         if (r)
 853                 goto err;
 854         ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base);
 855
 856         if (fence)
 857                 *fence = amdgpu_fence_ref(ib.fence);
 858
 859         amdgpu_ib_free(ring->adev, &ib);
 860         amdgpu_bo_unref(&bo);
 861         return 0;
 862
 863 err:
 864         ttm_eu_backoff_reservation(&ticket, &head);
 865         return r;
 866 }
 867
 868 /* multiple fence commands without any stream commands in between can
 869    crash the vcpu so just try to emmit a dummy create/destroy msg to
 870    avoid this */
 871 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 872                               struct amdgpu_fence **fence)
 873 {
 874         struct amdgpu_device *adev = ring->adev;
 875         struct amdgpu_bo *bo;
 876         uint32_t *msg;
 877         int r, i;
 878
 879         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 880                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 881         if (r)
 882                 return r;
 883
 884         r = amdgpu_bo_reserve(bo, false);
 885         if (r) {
 886                 amdgpu_bo_unref(&bo);
 887                 return r;
 888         }
 889
 890         r = amdgpu_bo_kmap(bo, (void **)&msg);
 891         if (r) {
 892                 amdgpu_bo_unreserve(bo);
 893                 amdgpu_bo_unref(&bo);
 894                 return r;
 895         }
 896
 897         /* stitch together an UVD create msg */
 898         msg[0] = cpu_to_le32(0x00000de4);
 899         msg[1] = cpu_to_le32(0x00000000);
 900         msg[2] = cpu_to_le32(handle);
 901         msg[3] = cpu_to_le32(0x00000000);
 902         msg[4] = cpu_to_le32(0x00000000);
 903         msg[5] = cpu_to_le32(0x00000000);
 904         msg[6] = cpu_to_le32(0x00000000);
 905         msg[7] = cpu_to_le32(0x00000780);
 906         msg[8] = cpu_to_le32(0x00000440);
 907         msg[9] = cpu_to_le32(0x00000000);
 908         msg[10] = cpu_to_le32(0x01b37000);
 909         for (i = 11; i < 1024; ++i)
 910                 msg[i] = cpu_to_le32(0x0);
 911
 912         amdgpu_bo_kunmap(bo);
 913         amdgpu_bo_unreserve(bo);
 914
 915         return amdgpu_uvd_send_msg(ring, bo, fence);
 916 }
 917
 918 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 919                                struct amdgpu_fence **fence)
 920 {
 921         struct amdgpu_device *adev = ring->adev;
 922         struct amdgpu_bo *bo;
 923         uint32_t *msg;
 924         int r, i;
 925
 926         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 927                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 928         if (r)
 929                 return r;
 930
 931         r = amdgpu_bo_reserve(bo, false);
 932         if (r) {
 933                 amdgpu_bo_unref(&bo);
 934                 return r;
 935         }
 936
 937         r = amdgpu_bo_kmap(bo, (void **)&msg);
 938         if (r) {
 939                 amdgpu_bo_unreserve(bo);
 940                 amdgpu_bo_unref(&bo);
 941                 return r;
 942         }
 943
 944         /* stitch together an UVD destroy msg */
 945         msg[0] = cpu_to_le32(0x00000de4);
 946         msg[1] = cpu_to_le32(0x00000002);
 947         msg[2] = cpu_to_le32(handle);
 948         msg[3] = cpu_to_le32(0x00000000);
 949         for (i = 4; i < 1024; ++i)
 950                 msg[i] = cpu_to_le32(0x0);
 951
 952         amdgpu_bo_kunmap(bo);
 953         amdgpu_bo_unreserve(bo);
 954
 955         return amdgpu_uvd_send_msg(ring, bo, fence);
 956 }
 957
 958 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
 959 {
 960         struct amdgpu_device *adev =
 961                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
 962         unsigned i, fences, handles = 0;
 963
 964         fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
 965
 966         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 967                 if (atomic_read(&adev->uvd.handles[i]))
 968                         ++handles;
 969
 970         if (fences == 0 && handles == 0) {
 971                 if (adev->pm.dpm_enabled) {
 972                         amdgpu_dpm_enable_uvd(adev, false);
 973                 } else {
 974                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 975                 }
 976         } else {
 977                 schedule_delayed_work(&adev->uvd.idle_work,
 978                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 979         }
 980 }
 981
 982 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
 983 {
 984         bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
 985         set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
 986                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 987
 988         if (set_clocks) {
 989                 if (adev->pm.dpm_enabled) {
 990                         amdgpu_dpm_enable_uvd(adev, true);
 991                 } else {
 992                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
 993                 }
 994         }
 995 }