drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #ifdef CONFIG_DRM_AMDGPU_CIK
  42 #include "cik.h"
  43 #endif
  44 #include "vi.h"
  45 #include "bif/bif_4_1_d.h"
  46
  47 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  49
  50 static const char *amdgpu_asic_name[] = {
  51         "BONAIRE",
  52         "KAVERI",
  53         "KABINI",
  54         "HAWAII",
  55         "MULLINS",
  56         "TOPAZ",
  57         "TONGA",
  58         "CARRIZO",
  59         "LAST",
  60 };
  61
  62 bool amdgpu_device_is_px(struct drm_device *dev)
  63 {
  64         struct amdgpu_device *adev = dev->dev_private;
  65
  66         if (adev->flags & AMDGPU_IS_PX)
  67                 return true;
  68         return false;
  69 }
  70
  71 /*
  72  * MMIO register access helper functions.
  73  */
  74 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  75                         bool always_indirect)
  76 {
  77         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  78                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  79         else {
  80                 unsigned long flags;
  81                 uint32_t ret;
  82
  83                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  84                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  85                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  86                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  87
  88                 return ret;
  89         }
  90 }
  91
  92 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  93                     bool always_indirect)
  94 {
  95         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  96                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  97         else {
  98                 unsigned long flags;
  99
 100                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 101                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 102                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 103                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 104         }
 105 }
 106
 107 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 108 {
 109         if ((reg * 4) < adev->rio_mem_size)
 110                 return ioread32(adev->rio_mem + (reg * 4));
 111         else {
 112                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 113                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 114         }
 115 }
 116
 117 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 118 {
 119
 120         if ((reg * 4) < adev->rio_mem_size)
 121                 iowrite32(v, adev->rio_mem + (reg * 4));
 122         else {
 123                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 124                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 125         }
 126 }
 127
 128 /**
 129  * amdgpu_mm_rdoorbell - read a doorbell dword
 130  *
 131  * @adev: amdgpu_device pointer
 132  * @index: doorbell index
 133  *
 134  * Returns the value in the doorbell aperture at the
 135  * requested doorbell index (CIK).
 136  */
 137 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 138 {
 139         if (index < adev->doorbell.num_doorbells) {
 140                 return readl(adev->doorbell.ptr + index);
 141         } else {
 142                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 143                 return 0;
 144         }
 145 }
 146
 147 /**
 148  * amdgpu_mm_wdoorbell - write a doorbell dword
 149  *
 150  * @adev: amdgpu_device pointer
 151  * @index: doorbell index
 152  * @v: value to write
 153  *
 154  * Writes @v to the doorbell aperture at the
 155  * requested doorbell index (CIK).
 156  */
 157 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 158 {
 159         if (index < adev->doorbell.num_doorbells) {
 160                 writel(v, adev->doorbell.ptr + index);
 161         } else {
 162                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 163         }
 164 }
 165
 166 /**
 167  * amdgpu_invalid_rreg - dummy reg read function
 168  *
 169  * @adev: amdgpu device pointer
 170  * @reg: offset of register
 171  *
 172  * Dummy register read function.  Used for register blocks
 173  * that certain asics don't have (all asics).
 174  * Returns the value in the register.
 175  */
 176 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 177 {
 178         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 179         BUG();
 180         return 0;
 181 }
 182
 183 /**
 184  * amdgpu_invalid_wreg - dummy reg write function
 185  *
 186  * @adev: amdgpu device pointer
 187  * @reg: offset of register
 188  * @v: value to write to the register
 189  *
 190  * Dummy register read function.  Used for register blocks
 191  * that certain asics don't have (all asics).
 192  */
 193 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 194 {
 195         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 196                   reg, v);
 197         BUG();
 198 }
 199
 200 /**
 201  * amdgpu_block_invalid_rreg - dummy reg read function
 202  *
 203  * @adev: amdgpu device pointer
 204  * @block: offset of instance
 205  * @reg: offset of register
 206  *
 207  * Dummy register read function.  Used for register blocks
 208  * that certain asics don't have (all asics).
 209  * Returns the value in the register.
 210  */
 211 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 212                                           uint32_t block, uint32_t reg)
 213 {
 214         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 215                   reg, block);
 216         BUG();
 217         return 0;
 218 }
 219
 220 /**
 221  * amdgpu_block_invalid_wreg - dummy reg write function
 222  *
 223  * @adev: amdgpu device pointer
 224  * @block: offset of instance
 225  * @reg: offset of register
 226  * @v: value to write to the register
 227  *
 228  * Dummy register read function.  Used for register blocks
 229  * that certain asics don't have (all asics).
 230  */
 231 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 232                                       uint32_t block,
 233                                       uint32_t reg, uint32_t v)
 234 {
 235         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 236                   reg, block, v);
 237         BUG();
 238 }
 239
 240 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 241 {
 242         int r;
 243
 244         if (adev->vram_scratch.robj == NULL) {
 245                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 246                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
 247                                      NULL, &adev->vram_scratch.robj);
 248                 if (r) {
 249                         return r;
 250                 }
 251         }
 252
 253         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 254         if (unlikely(r != 0))
 255                 return r;
 256         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 257                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 258         if (r) {
 259                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 260                 return r;
 261         }
 262         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 263                                 (void **)&adev->vram_scratch.ptr);
 264         if (r)
 265                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 266         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 267
 268         return r;
 269 }
 270
 271 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 272 {
 273         int r;
 274
 275         if (adev->vram_scratch.robj == NULL) {
 276                 return;
 277         }
 278         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 279         if (likely(r == 0)) {
 280                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 281                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 282                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 283         }
 284         amdgpu_bo_unref(&adev->vram_scratch.robj);
 285 }
 286
 287 /**
 288  * amdgpu_program_register_sequence - program an array of registers.
 289  *
 290  * @adev: amdgpu_device pointer
 291  * @registers: pointer to the register array
 292  * @array_size: size of the register array
 293  *
 294  * Programs an array or registers with and and or masks.
 295  * This is a helper for setting golden registers.
 296  */
 297 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 298                                       const u32 *registers,
 299                                       const u32 array_size)
 300 {
 301         u32 tmp, reg, and_mask, or_mask;
 302         int i;
 303
 304         if (array_size % 3)
 305                 return;
 306
 307         for (i = 0; i < array_size; i +=3) {
 308                 reg = registers[i + 0];
 309                 and_mask = registers[i + 1];
 310                 or_mask = registers[i + 2];
 311
 312                 if (and_mask == 0xffffffff) {
 313                         tmp = or_mask;
 314                 } else {
 315                         tmp = RREG32(reg);
 316                         tmp &= ~and_mask;
 317                         tmp |= or_mask;
 318                 }
 319                 WREG32(reg, tmp);
 320         }
 321 }
 322
 323 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 324 {
 325         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 326 }
 327
 328 /*
 329  * GPU doorbell aperture helpers function.
 330  */
 331 /**
 332  * amdgpu_doorbell_init - Init doorbell driver information.
 333  *
 334  * @adev: amdgpu_device pointer
 335  *
 336  * Init doorbell driver information (CIK)
 337  * Returns 0 on success, error on failure.
 338  */
 339 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 340 {
 341         /* doorbell bar mapping */
 342         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 343         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 344
 345         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 346                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 347         if (adev->doorbell.num_doorbells == 0)
 348                 return -EINVAL;
 349
 350         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 351         if (adev->doorbell.ptr == NULL) {
 352                 return -ENOMEM;
 353         }
 354         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 355         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 362  *
 363  * @adev: amdgpu_device pointer
 364  *
 365  * Tear down doorbell driver information (CIK)
 366  */
 367 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 368 {
 369         iounmap(adev->doorbell.ptr);
 370         adev->doorbell.ptr = NULL;
 371 }
 372
 373 /**
 374  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 375  *                                setup amdkfd
 376  *
 377  * @adev: amdgpu_device pointer
 378  * @aperture_base: output returning doorbell aperture base physical address
 379  * @aperture_size: output returning doorbell aperture size in bytes
 380  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 381  *
 382  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 383  * takes doorbells required for its own rings and reports the setup to amdkfd.
 384  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 385  */
 386 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 387                                 phys_addr_t *aperture_base,
 388                                 size_t *aperture_size,
 389                                 size_t *start_offset)
 390 {
 391         /*
 392          * The first num_doorbells are used by amdgpu.
 393          * amdkfd takes whatever's left in the aperture.
 394          */
 395         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 396                 *aperture_base = adev->doorbell.base;
 397                 *aperture_size = adev->doorbell.size;
 398                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 399         } else {
 400                 *aperture_base = 0;
 401                 *aperture_size = 0;
 402                 *start_offset = 0;
 403         }
 404 }
 405
 406 /*
 407  * amdgpu_wb_*()
 408  * Writeback is the the method by which the the GPU updates special pages
 409  * in memory with the status of certain GPU events (fences, ring pointers,
 410  * etc.).
 411  */
 412
 413 /**
 414  * amdgpu_wb_fini - Disable Writeback and free memory
 415  *
 416  * @adev: amdgpu_device pointer
 417  *
 418  * Disables Writeback and frees the Writeback memory (all asics).
 419  * Used at driver shutdown.
 420  */
 421 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 422 {
 423         if (adev->wb.wb_obj) {
 424                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 425                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 426                         amdgpu_bo_unpin(adev->wb.wb_obj);
 427                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 428                 }
 429                 amdgpu_bo_unref(&adev->wb.wb_obj);
 430                 adev->wb.wb = NULL;
 431                 adev->wb.wb_obj = NULL;
 432         }
 433 }
 434
 435 /**
 436  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 437  *
 438  * @adev: amdgpu_device pointer
 439  *
 440  * Disables Writeback and frees the Writeback memory (all asics).
 441  * Used at driver startup.
 442  * Returns 0 on success or an -error on failure.
 443  */
 444 static int amdgpu_wb_init(struct amdgpu_device *adev)
 445 {
 446         int r;
 447
 448         if (adev->wb.wb_obj == NULL) {
 449                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 450                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, &adev->wb.wb_obj);
 451                 if (r) {
 452                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 453                         return r;
 454                 }
 455                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 456                 if (unlikely(r != 0)) {
 457                         amdgpu_wb_fini(adev);
 458                         return r;
 459                 }
 460                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 461                                 &adev->wb.gpu_addr);
 462                 if (r) {
 463                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 464                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 465                         amdgpu_wb_fini(adev);
 466                         return r;
 467                 }
 468                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 469                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 470                 if (r) {
 471                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 472                         amdgpu_wb_fini(adev);
 473                         return r;
 474                 }
 475
 476                 adev->wb.num_wb = AMDGPU_MAX_WB;
 477                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 478
 479                 /* clear wb memory */
 480                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 481         }
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * amdgpu_wb_get - Allocate a wb entry
 488  *
 489  * @adev: amdgpu_device pointer
 490  * @wb: wb index
 491  *
 492  * Allocate a wb slot for use by the driver (all asics).
 493  * Returns 0 on success or -EINVAL on failure.
 494  */
 495 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 496 {
 497         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 498         if (offset < adev->wb.num_wb) {
 499                 __set_bit(offset, adev->wb.used);
 500                 *wb = offset;
 501                 return 0;
 502         } else {
 503                 return -EINVAL;
 504         }
 505 }
 506
 507 /**
 508  * amdgpu_wb_free - Free a wb entry
 509  *
 510  * @adev: amdgpu_device pointer
 511  * @wb: wb index
 512  *
 513  * Free a wb slot allocated for use by the driver (all asics)
 514  */
 515 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 516 {
 517         if (wb < adev->wb.num_wb)
 518                 __clear_bit(wb, adev->wb.used);
 519 }
 520
 521 /**
 522  * amdgpu_vram_location - try to find VRAM location
 523  * @adev: amdgpu device structure holding all necessary informations
 524  * @mc: memory controller structure holding memory informations
 525  * @base: base address at which to put VRAM
 526  *
 527  * Function will place try to place VRAM at base address provided
 528  * as parameter (which is so far either PCI aperture address or
 529  * for IGP TOM base address).
 530  *
 531  * If there is not enough space to fit the unvisible VRAM in the 32bits
 532  * address space then we limit the VRAM size to the aperture.
 533  *
 534  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 535  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 536  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 537  * not IGP.
 538  *
 539  * Note: we use mc_vram_size as on some board we need to program the mc to
 540  * cover the whole aperture even if VRAM size is inferior to aperture size
 541  * Novell bug 204882 + along with lots of ubuntu ones
 542  *
 543  * Note: when limiting vram it's safe to overwritte real_vram_size because
 544  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 545  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 546  * ones)
 547  *
 548  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 549  * explicitly check for that thought.
 550  *
 551  * FIXME: when reducing VRAM size align new size on power of 2.
 552  */
 553 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 554 {
 555         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 556
 557         mc->vram_start = base;
 558         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 559                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 560                 mc->real_vram_size = mc->aper_size;
 561                 mc->mc_vram_size = mc->aper_size;
 562         }
 563         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 564         if (limit && limit < mc->real_vram_size)
 565                 mc->real_vram_size = limit;
 566         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 567                         mc->mc_vram_size >> 20, mc->vram_start,
 568                         mc->vram_end, mc->real_vram_size >> 20);
 569 }
 570
 571 /**
 572  * amdgpu_gtt_location - try to find GTT location
 573  * @adev: amdgpu device structure holding all necessary informations
 574  * @mc: memory controller structure holding memory informations
 575  *
 576  * Function will place try to place GTT before or after VRAM.
 577  *
 578  * If GTT size is bigger than space left then we ajust GTT size.
 579  * Thus function will never fails.
 580  *
 581  * FIXME: when reducing GTT size align new size on power of 2.
 582  */
 583 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 584 {
 585         u64 size_af, size_bf;
 586
 587         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 588         size_bf = mc->vram_start & ~mc->gtt_base_align;
 589         if (size_bf > size_af) {
 590                 if (mc->gtt_size > size_bf) {
 591                         dev_warn(adev->dev, "limiting GTT\n");
 592                         mc->gtt_size = size_bf;
 593                 }
 594                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 595         } else {
 596                 if (mc->gtt_size > size_af) {
 597                         dev_warn(adev->dev, "limiting GTT\n");
 598                         mc->gtt_size = size_af;
 599                 }
 600                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 601         }
 602         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 603         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 604                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 605 }
 606
 607 /*
 608  * GPU helpers function.
 609  */
 610 /**
 611  * amdgpu_card_posted - check if the hw has already been initialized
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Check if the asic has been initialized (all asics).
 616  * Used at driver startup.
 617  * Returns true if initialized or false if not.
 618  */
 619 bool amdgpu_card_posted(struct amdgpu_device *adev)
 620 {
 621         uint32_t reg;
 622
 623         /* then check MEM_SIZE, in case the crtcs are off */
 624         reg = RREG32(mmCONFIG_MEMSIZE);
 625
 626         if (reg)
 627                 return true;
 628
 629         return false;
 630
 631 }
 632
 633 /**
 634  * amdgpu_boot_test_post_card - check and possibly initialize the hw
 635  *
 636  * @adev: amdgpu_device pointer
 637  *
 638  * Check if the asic is initialized and if not, attempt to initialize
 639  * it (all asics).
 640  * Returns true if initialized or false if not.
 641  */
 642 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
 643 {
 644         if (amdgpu_card_posted(adev))
 645                 return true;
 646
 647         if (adev->bios) {
 648                 DRM_INFO("GPU not posted. posting now...\n");
 649                 if (adev->is_atom_bios)
 650                         amdgpu_atom_asic_init(adev->mode_info.atom_context);
 651                 return true;
 652         } else {
 653                 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
 654                 return false;
 655         }
 656 }
 657
 658 /**
 659  * amdgpu_dummy_page_init - init dummy page used by the driver
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Allocate the dummy page used by the driver (all asics).
 664  * This dummy page is used by the driver as a filler for gart entries
 665  * when pages are taken out of the GART
 666  * Returns 0 on sucess, -ENOMEM on failure.
 667  */
 668 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 669 {
 670         if (adev->dummy_page.page)
 671                 return 0;
 672         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 673         if (adev->dummy_page.page == NULL)
 674                 return -ENOMEM;
 675         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 676                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 677         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 678                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 679                 __free_page(adev->dummy_page.page);
 680                 adev->dummy_page.page = NULL;
 681                 return -ENOMEM;
 682         }
 683         return 0;
 684 }
 685
 686 /**
 687  * amdgpu_dummy_page_fini - free dummy page used by the driver
 688  *
 689  * @adev: amdgpu_device pointer
 690  *
 691  * Frees the dummy page used by the driver (all asics).
 692  */
 693 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 694 {
 695         if (adev->dummy_page.page == NULL)
 696                 return;
 697         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 698                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 699         __free_page(adev->dummy_page.page);
 700         adev->dummy_page.page = NULL;
 701 }
 702
 703
 704 /* ATOM accessor methods */
 705 /*
 706  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 707  * driver registers callbacks to access registers and the interpreter
 708  * in the driver parses the tables and executes then to program specific
 709  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 710  * atombios.h, and atom.c
 711  */
 712
 713 /**
 714  * cail_pll_read - read PLL register
 715  *
 716  * @info: atom card_info pointer
 717  * @reg: PLL register offset
 718  *
 719  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 720  * Returns the value of the PLL register.
 721  */
 722 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 723 {
 724         return 0;
 725 }
 726
 727 /**
 728  * cail_pll_write - write PLL register
 729  *
 730  * @info: atom card_info pointer
 731  * @reg: PLL register offset
 732  * @val: value to write to the pll register
 733  *
 734  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 735  */
 736 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 737 {
 738
 739 }
 740
 741 /**
 742  * cail_mc_read - read MC (Memory Controller) register
 743  *
 744  * @info: atom card_info pointer
 745  * @reg: MC register offset
 746  *
 747  * Provides an MC register accessor for the atom interpreter (r4xx+).
 748  * Returns the value of the MC register.
 749  */
 750 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 751 {
 752         return 0;
 753 }
 754
 755 /**
 756  * cail_mc_write - write MC (Memory Controller) register
 757  *
 758  * @info: atom card_info pointer
 759  * @reg: MC register offset
 760  * @val: value to write to the pll register
 761  *
 762  * Provides a MC register accessor for the atom interpreter (r4xx+).
 763  */
 764 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 765 {
 766
 767 }
 768
 769 /**
 770  * cail_reg_write - write MMIO register
 771  *
 772  * @info: atom card_info pointer
 773  * @reg: MMIO register offset
 774  * @val: value to write to the pll register
 775  *
 776  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 777  */
 778 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 779 {
 780         struct amdgpu_device *adev = info->dev->dev_private;
 781
 782         WREG32(reg, val);
 783 }
 784
 785 /**
 786  * cail_reg_read - read MMIO register
 787  *
 788  * @info: atom card_info pointer
 789  * @reg: MMIO register offset
 790  *
 791  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 792  * Returns the value of the MMIO register.
 793  */
 794 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 795 {
 796         struct amdgpu_device *adev = info->dev->dev_private;
 797         uint32_t r;
 798
 799         r = RREG32(reg);
 800         return r;
 801 }
 802
 803 /**
 804  * cail_ioreg_write - write IO register
 805  *
 806  * @info: atom card_info pointer
 807  * @reg: IO register offset
 808  * @val: value to write to the pll register
 809  *
 810  * Provides a IO register accessor for the atom interpreter (r4xx+).
 811  */
 812 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 813 {
 814         struct amdgpu_device *adev = info->dev->dev_private;
 815
 816         WREG32_IO(reg, val);
 817 }
 818
 819 /**
 820  * cail_ioreg_read - read IO register
 821  *
 822  * @info: atom card_info pointer
 823  * @reg: IO register offset
 824  *
 825  * Provides an IO register accessor for the atom interpreter (r4xx+).
 826  * Returns the value of the IO register.
 827  */
 828 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 829 {
 830         struct amdgpu_device *adev = info->dev->dev_private;
 831         uint32_t r;
 832
 833         r = RREG32_IO(reg);
 834         return r;
 835 }
 836
 837 /**
 838  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 839  *
 840  * @adev: amdgpu_device pointer
 841  *
 842  * Frees the driver info and register access callbacks for the ATOM
 843  * interpreter (r4xx+).
 844  * Called at driver shutdown.
 845  */
 846 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 847 {
 848         if (adev->mode_info.atom_context)
 849                 kfree(adev->mode_info.atom_context->scratch);
 850         kfree(adev->mode_info.atom_context);
 851         adev->mode_info.atom_context = NULL;
 852         kfree(adev->mode_info.atom_card_info);
 853         adev->mode_info.atom_card_info = NULL;
 854 }
 855
 856 /**
 857  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 858  *
 859  * @adev: amdgpu_device pointer
 860  *
 861  * Initializes the driver info and register access callbacks for the
 862  * ATOM interpreter (r4xx+).
 863  * Returns 0 on sucess, -ENOMEM on failure.
 864  * Called at driver startup.
 865  */
 866 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 867 {
 868         struct card_info *atom_card_info =
 869             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 870
 871         if (!atom_card_info)
 872                 return -ENOMEM;
 873
 874         adev->mode_info.atom_card_info = atom_card_info;
 875         atom_card_info->dev = adev->ddev;
 876         atom_card_info->reg_read = cail_reg_read;
 877         atom_card_info->reg_write = cail_reg_write;
 878         /* needed for iio ops */
 879         if (adev->rio_mem) {
 880                 atom_card_info->ioreg_read = cail_ioreg_read;
 881                 atom_card_info->ioreg_write = cail_ioreg_write;
 882         } else {
 883                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 884                 atom_card_info->ioreg_read = cail_reg_read;
 885                 atom_card_info->ioreg_write = cail_reg_write;
 886         }
 887         atom_card_info->mc_read = cail_mc_read;
 888         atom_card_info->mc_write = cail_mc_write;
 889         atom_card_info->pll_read = cail_pll_read;
 890         atom_card_info->pll_write = cail_pll_write;
 891
 892         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 893         if (!adev->mode_info.atom_context) {
 894                 amdgpu_atombios_fini(adev);
 895                 return -ENOMEM;
 896         }
 897
 898         mutex_init(&adev->mode_info.atom_context->mutex);
 899         amdgpu_atombios_scratch_regs_init(adev);
 900         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 901         return 0;
 902 }
 903
 904 /* if we get transitioned to only one device, take VGA back */
 905 /**
 906  * amdgpu_vga_set_decode - enable/disable vga decode
 907  *
 908  * @cookie: amdgpu_device pointer
 909  * @state: enable/disable vga decode
 910  *
 911  * Enable/disable vga decode (all asics).
 912  * Returns VGA resource flags.
 913  */
 914 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 915 {
 916         struct amdgpu_device *adev = cookie;
 917         amdgpu_asic_set_vga_state(adev, state);
 918         if (state)
 919                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 920                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 921         else
 922                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 923 }
 924
 925 /**
 926  * amdgpu_check_pot_argument - check that argument is a power of two
 927  *
 928  * @arg: value to check
 929  *
 930  * Validates that a certain argument is a power of two (all asics).
 931  * Returns true if argument is valid.
 932  */
 933 static bool amdgpu_check_pot_argument(int arg)
 934 {
 935         return (arg & (arg - 1)) == 0;
 936 }
 937
 938 /**
 939  * amdgpu_check_arguments - validate module params
 940  *
 941  * @adev: amdgpu_device pointer
 942  *
 943  * Validates certain module parameters and updates
 944  * the associated values used by the driver (all asics).
 945  */
 946 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 947 {
 948         /* vramlimit must be a power of two */
 949         if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
 950                 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
 951                                 amdgpu_vram_limit);
 952                 amdgpu_vram_limit = 0;
 953         }
 954
 955         if (amdgpu_gart_size != -1) {
 956                 /* gtt size must be power of two and greater or equal to 32M */
 957                 if (amdgpu_gart_size < 32) {
 958                         dev_warn(adev->dev, "gart size (%d) too small\n",
 959                                  amdgpu_gart_size);
 960                         amdgpu_gart_size = -1;
 961                 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
 962                         dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
 963                                  amdgpu_gart_size);
 964                         amdgpu_gart_size = -1;
 965                 }
 966         }
 967
 968         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 969                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 970                          amdgpu_vm_size);
 971                 amdgpu_vm_size = 8;
 972         }
 973
 974         if (amdgpu_vm_size < 1) {
 975                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 976                          amdgpu_vm_size);
 977                 amdgpu_vm_size = 8;
 978         }
 979
 980         /*
 981          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 982          */
 983         if (amdgpu_vm_size > 1024) {
 984                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 985                          amdgpu_vm_size);
 986                 amdgpu_vm_size = 8;
 987         }
 988
 989         /* defines number of bits in page table versus page directory,
 990          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 991          * page table and the remaining bits are in the page directory */
 992         if (amdgpu_vm_block_size == -1) {
 993
 994                 /* Total bits covered by PD + PTs */
 995                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 996
 997                 /* Make sure the PD is 4K in size up to 8GB address space.
 998                    Above that split equal between PD and PTs */
 999                 if (amdgpu_vm_size <= 8)
1000                         amdgpu_vm_block_size = bits - 9;
1001                 else
1002                         amdgpu_vm_block_size = (bits + 3) / 2;
1003
1004         } else if (amdgpu_vm_block_size < 9) {
1005                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1006                          amdgpu_vm_block_size);
1007                 amdgpu_vm_block_size = 9;
1008         }
1009
1010         if (amdgpu_vm_block_size > 24 ||
1011             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1012                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1013                          amdgpu_vm_block_size);
1014                 amdgpu_vm_block_size = 9;
1015         }
1016 }
1017
1018 /**
1019  * amdgpu_switcheroo_set_state - set switcheroo state
1020  *
1021  * @pdev: pci dev pointer
1022  * @state: vga switcheroo state
1023  *
1024  * Callback for the switcheroo driver.  Suspends or resumes the
1025  * the asics before or after it is powered up using ACPI methods.
1026  */
1027 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1028 {
1029         struct drm_device *dev = pci_get_drvdata(pdev);
1030
1031         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1032                 return;
1033
1034         if (state == VGA_SWITCHEROO_ON) {
1035                 unsigned d3_delay = dev->pdev->d3_delay;
1036
1037                 printk(KERN_INFO "amdgpu: switched on\n");
1038                 /* don't suspend or resume card normally */
1039                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1040
1041                 amdgpu_resume_kms(dev, true, true);
1042
1043                 dev->pdev->d3_delay = d3_delay;
1044
1045                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1046                 drm_kms_helper_poll_enable(dev);
1047         } else {
1048                 printk(KERN_INFO "amdgpu: switched off\n");
1049                 drm_kms_helper_poll_disable(dev);
1050                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1051                 amdgpu_suspend_kms(dev, true, true);
1052                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1053         }
1054 }
1055
1056 /**
1057  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1058  *
1059  * @pdev: pci dev pointer
1060  *
1061  * Callback for the switcheroo driver.  Check of the switcheroo
1062  * state can be changed.
1063  * Returns true if the state can be changed, false if not.
1064  */
1065 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1066 {
1067         struct drm_device *dev = pci_get_drvdata(pdev);
1068
1069         /*
1070         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1071         * locking inversion with the driver load path. And the access here is
1072         * completely racy anyway. So don't bother with locking for now.
1073         */
1074         return dev->open_count == 0;
1075 }
1076
1077 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1078         .set_gpu_state = amdgpu_switcheroo_set_state,
1079         .reprobe = NULL,
1080         .can_switch = amdgpu_switcheroo_can_switch,
1081 };
1082
1083 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1084                                   enum amd_ip_block_type block_type,
1085                                   enum amd_clockgating_state state)
1086 {
1087         int i, r = 0;
1088
1089         for (i = 0; i < adev->num_ip_blocks; i++) {
1090                 if (adev->ip_blocks[i].type == block_type) {
1091                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1092                                                                             state);
1093                         if (r)
1094                                 return r;
1095                 }
1096         }
1097         return r;
1098 }
1099
1100 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1101                                   enum amd_ip_block_type block_type,
1102                                   enum amd_powergating_state state)
1103 {
1104         int i, r = 0;
1105
1106         for (i = 0; i < adev->num_ip_blocks; i++) {
1107                 if (adev->ip_blocks[i].type == block_type) {
1108                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1109                                                                             state);
1110                         if (r)
1111                                 return r;
1112                 }
1113         }
1114         return r;
1115 }
1116
1117 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1118                                         struct amdgpu_device *adev,
1119                                         enum amd_ip_block_type type)
1120 {
1121         int i;
1122
1123         for (i = 0; i < adev->num_ip_blocks; i++)
1124                 if (adev->ip_blocks[i].type == type)
1125                         return &adev->ip_blocks[i];
1126
1127         return NULL;
1128 }
1129
1130 /**
1131  * amdgpu_ip_block_version_cmp
1132  *
1133  * @adev: amdgpu_device pointer
1134  * @type: enum amd_ip_block_type
1135  * @major: major version
1136  * @minor: minor version
1137  *
1138  * return 0 if equal or greater
1139  * return 1 if smaller or the ip_block doesn't exist
1140  */
1141 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1142                                 enum amd_ip_block_type type,
1143                                 u32 major, u32 minor)
1144 {
1145         const struct amdgpu_ip_block_version *ip_block;
1146         ip_block = amdgpu_get_ip_block(adev, type);
1147
1148         if (ip_block && ((ip_block->major > major) ||
1149                         ((ip_block->major == major) &&
1150                         (ip_block->minor >= minor))))
1151                 return 0;
1152
1153         return 1;
1154 }
1155
1156 static int amdgpu_early_init(struct amdgpu_device *adev)
1157 {
1158         int i, r;
1159
1160         switch (adev->asic_type) {
1161         case CHIP_TOPAZ:
1162         case CHIP_TONGA:
1163         case CHIP_CARRIZO:
1164                 if (adev->asic_type == CHIP_CARRIZO)
1165                         adev->family = AMDGPU_FAMILY_CZ;
1166                 else
1167                         adev->family = AMDGPU_FAMILY_VI;
1168
1169                 r = vi_set_ip_blocks(adev);
1170                 if (r)
1171                         return r;
1172                 break;
1173 #ifdef CONFIG_DRM_AMDGPU_CIK
1174         case CHIP_BONAIRE:
1175         case CHIP_HAWAII:
1176         case CHIP_KAVERI:
1177         case CHIP_KABINI:
1178         case CHIP_MULLINS:
1179                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1180                         adev->family = AMDGPU_FAMILY_CI;
1181                 else
1182                         adev->family = AMDGPU_FAMILY_KV;
1183
1184                 r = cik_set_ip_blocks(adev);
1185                 if (r)
1186                         return r;
1187                 break;
1188 #endif
1189         default:
1190                 /* FIXME: not supported yet */
1191                 return -EINVAL;
1192         }
1193
1194         adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL);
1195         if (adev->ip_block_enabled == NULL)
1196                 return -ENOMEM;
1197
1198         if (adev->ip_blocks == NULL) {
1199                 DRM_ERROR("No IP blocks found!\n");
1200                 return r;
1201         }
1202
1203         for (i = 0; i < adev->num_ip_blocks; i++) {
1204                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1205                         DRM_ERROR("disabled ip block: %d\n", i);
1206                         adev->ip_block_enabled[i] = false;
1207                 } else {
1208                         if (adev->ip_blocks[i].funcs->early_init) {
1209                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1210                                 if (r)
1211                                         return r;
1212                         }
1213                         adev->ip_block_enabled[i] = true;
1214                 }
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int amdgpu_init(struct amdgpu_device *adev)
1221 {
1222         int i, r;
1223
1224         for (i = 0; i < adev->num_ip_blocks; i++) {
1225                 if (!adev->ip_block_enabled[i])
1226                         continue;
1227                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1228                 if (r)
1229                         return r;
1230                 /* need to do gmc hw init early so we can allocate gpu mem */
1231                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1232                         r = amdgpu_vram_scratch_init(adev);
1233                         if (r)
1234                                 return r;
1235                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1236                         if (r)
1237                                 return r;
1238                         r = amdgpu_wb_init(adev);
1239                         if (r)
1240                                 return r;
1241                 }
1242         }
1243
1244         for (i = 0; i < adev->num_ip_blocks; i++) {
1245                 if (!adev->ip_block_enabled[i])
1246                         continue;
1247                 /* gmc hw init is done early */
1248                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1249                         continue;
1250                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1251                 if (r)
1252                         return r;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int amdgpu_late_init(struct amdgpu_device *adev)
1259 {
1260         int i = 0, r;
1261
1262         for (i = 0; i < adev->num_ip_blocks; i++) {
1263                 if (!adev->ip_block_enabled[i])
1264                         continue;
1265                 /* enable clockgating to save power */
1266                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1267                                                                     AMD_CG_STATE_GATE);
1268                 if (r)
1269                         return r;
1270                 if (adev->ip_blocks[i].funcs->late_init) {
1271                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1272                         if (r)
1273                                 return r;
1274                 }
1275         }
1276
1277         return 0;
1278 }
1279
1280 static int amdgpu_fini(struct amdgpu_device *adev)
1281 {
1282         int i, r;
1283
1284         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1285                 if (!adev->ip_block_enabled[i])
1286                         continue;
1287                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1288                         amdgpu_wb_fini(adev);
1289                         amdgpu_vram_scratch_fini(adev);
1290                 }
1291                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1292                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1293                                                                     AMD_CG_STATE_UNGATE);
1294                 if (r)
1295                         return r;
1296                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1297                 /* XXX handle errors */
1298         }
1299
1300         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1301                 if (!adev->ip_block_enabled[i])
1302                         continue;
1303                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1304                 /* XXX handle errors */
1305                 adev->ip_block_enabled[i] = false;
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int amdgpu_suspend(struct amdgpu_device *adev)
1312 {
1313         int i, r;
1314
1315         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1316                 if (!adev->ip_block_enabled[i])
1317                         continue;
1318                 /* ungate blocks so that suspend can properly shut them down */
1319                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1320                                                                     AMD_CG_STATE_UNGATE);
1321                 /* XXX handle errors */
1322                 r = adev->ip_blocks[i].funcs->suspend(adev);
1323                 /* XXX handle errors */
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int amdgpu_resume(struct amdgpu_device *adev)
1330 {
1331         int i, r;
1332
1333         for (i = 0; i < adev->num_ip_blocks; i++) {
1334                 if (!adev->ip_block_enabled[i])
1335                         continue;
1336                 r = adev->ip_blocks[i].funcs->resume(adev);
1337                 if (r)
1338                         return r;
1339         }
1340
1341         return 0;
1342 }
1343
1344 /**
1345  * amdgpu_device_init - initialize the driver
1346  *
1347  * @adev: amdgpu_device pointer
1348  * @pdev: drm dev pointer
1349  * @pdev: pci dev pointer
1350  * @flags: driver flags
1351  *
1352  * Initializes the driver info and hw (all asics).
1353  * Returns 0 for success or an error on failure.
1354  * Called at driver startup.
1355  */
1356 int amdgpu_device_init(struct amdgpu_device *adev,
1357                        struct drm_device *ddev,
1358                        struct pci_dev *pdev,
1359                        uint32_t flags)
1360 {
1361         int r, i;
1362         bool runtime = false;
1363
1364         adev->shutdown = false;
1365         adev->dev = &pdev->dev;
1366         adev->ddev = ddev;
1367         adev->pdev = pdev;
1368         adev->flags = flags;
1369         adev->asic_type = flags & AMDGPU_ASIC_MASK;
1370         adev->is_atom_bios = false;
1371         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1372         adev->mc.gtt_size = 512 * 1024 * 1024;
1373         adev->accel_working = false;
1374         adev->num_rings = 0;
1375         adev->mman.buffer_funcs = NULL;
1376         adev->mman.buffer_funcs_ring = NULL;
1377         adev->vm_manager.vm_pte_funcs = NULL;
1378         adev->vm_manager.vm_pte_funcs_ring = NULL;
1379         adev->gart.gart_funcs = NULL;
1380         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1381
1382         adev->smc_rreg = &amdgpu_invalid_rreg;
1383         adev->smc_wreg = &amdgpu_invalid_wreg;
1384         adev->pcie_rreg = &amdgpu_invalid_rreg;
1385         adev->pcie_wreg = &amdgpu_invalid_wreg;
1386         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1387         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1388         adev->didt_rreg = &amdgpu_invalid_rreg;
1389         adev->didt_wreg = &amdgpu_invalid_wreg;
1390         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1391         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1392
1393         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1394                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1395                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1396
1397         /* mutex initialization are all done here so we
1398          * can recall function without having locking issues */
1399         mutex_init(&adev->ring_lock);
1400         atomic_set(&adev->irq.ih.lock, 0);
1401         mutex_init(&adev->gem.mutex);
1402         mutex_init(&adev->pm.mutex);
1403         mutex_init(&adev->gfx.gpu_clock_mutex);
1404         mutex_init(&adev->srbm_mutex);
1405         mutex_init(&adev->grbm_idx_mutex);
1406         init_rwsem(&adev->exclusive_lock);
1407         mutex_init(&adev->mn_lock);
1408         hash_init(adev->mn_hash);
1409
1410         amdgpu_check_arguments(adev);
1411
1412         /* Registers mapping */
1413         /* TODO: block userspace mapping of io register */
1414         spin_lock_init(&adev->mmio_idx_lock);
1415         spin_lock_init(&adev->smc_idx_lock);
1416         spin_lock_init(&adev->pcie_idx_lock);
1417         spin_lock_init(&adev->uvd_ctx_idx_lock);
1418         spin_lock_init(&adev->didt_idx_lock);
1419         spin_lock_init(&adev->audio_endpt_idx_lock);
1420
1421         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1422         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1423         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1424         if (adev->rmmio == NULL) {
1425                 return -ENOMEM;
1426         }
1427         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1428         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1429
1430         /* doorbell bar mapping */
1431         amdgpu_doorbell_init(adev);
1432
1433         /* io port mapping */
1434         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1435                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1436                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1437                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1438                         break;
1439                 }
1440         }
1441         if (adev->rio_mem == NULL)
1442                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1443
1444         /* early init functions */
1445         r = amdgpu_early_init(adev);
1446         if (r)
1447                 return r;
1448
1449         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1450         /* this will fail for cards that aren't VGA class devices, just
1451          * ignore it */
1452         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1453
1454         if (amdgpu_runtime_pm == 1)
1455                 runtime = true;
1456         if (amdgpu_device_is_px(ddev))
1457                 runtime = true;
1458         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1459         if (runtime)
1460                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1461
1462         /* Read BIOS */
1463         if (!amdgpu_get_bios(adev))
1464                 return -EINVAL;
1465         /* Must be an ATOMBIOS */
1466         if (!adev->is_atom_bios) {
1467                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1468                 return -EINVAL;
1469         }
1470         r = amdgpu_atombios_init(adev);
1471         if (r)
1472                 return r;
1473
1474         /* Post card if necessary */
1475         if (!amdgpu_card_posted(adev)) {
1476                 if (!adev->bios) {
1477                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1478                         return -EINVAL;
1479                 }
1480                 DRM_INFO("GPU not posted. posting now...\n");
1481                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1482         }
1483
1484         /* Initialize clocks */
1485         r = amdgpu_atombios_get_clock_info(adev);
1486         if (r)
1487                 return r;
1488         /* init i2c buses */
1489         amdgpu_atombios_i2c_init(adev);
1490
1491         /* Fence driver */
1492         r = amdgpu_fence_driver_init(adev);
1493         if (r)
1494                 return r;
1495
1496         /* init the mode config */
1497         drm_mode_config_init(adev->ddev);
1498
1499         r = amdgpu_init(adev);
1500         if (r) {
1501                 amdgpu_fini(adev);
1502                 return r;
1503         }
1504
1505         adev->accel_working = true;
1506
1507         amdgpu_fbdev_init(adev);
1508
1509         r = amdgpu_ib_pool_init(adev);
1510         if (r) {
1511                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1512                 return r;
1513         }
1514
1515         r = amdgpu_ib_ring_tests(adev);
1516         if (r)
1517                 DRM_ERROR("ib ring test failed (%d).\n", r);
1518
1519         r = amdgpu_gem_debugfs_init(adev);
1520         if (r) {
1521                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1522         }
1523
1524         r = amdgpu_debugfs_regs_init(adev);
1525         if (r) {
1526                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1527         }
1528
1529         if ((amdgpu_testing & 1)) {
1530                 if (adev->accel_working)
1531                         amdgpu_test_moves(adev);
1532                 else
1533                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1534         }
1535         if ((amdgpu_testing & 2)) {
1536                 if (adev->accel_working)
1537                         amdgpu_test_syncing(adev);
1538                 else
1539                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1540         }
1541         if (amdgpu_benchmarking) {
1542                 if (adev->accel_working)
1543                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1544                 else
1545                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1546         }
1547
1548         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1549          * explicit gating rather than handling it automatically.
1550          */
1551         r = amdgpu_late_init(adev);
1552         if (r)
1553                 return r;
1554
1555         return 0;
1556 }
1557
1558 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1559
1560 /**
1561  * amdgpu_device_fini - tear down the driver
1562  *
1563  * @adev: amdgpu_device pointer
1564  *
1565  * Tear down the driver info (all asics).
1566  * Called at driver shutdown.
1567  */
1568 void amdgpu_device_fini(struct amdgpu_device *adev)
1569 {
1570         int r;
1571
1572         DRM_INFO("amdgpu: finishing device.\n");
1573         adev->shutdown = true;
1574         /* evict vram memory */
1575         amdgpu_bo_evict_vram(adev);
1576         amdgpu_ib_pool_fini(adev);
1577         amdgpu_fence_driver_fini(adev);
1578         amdgpu_fbdev_fini(adev);
1579         r = amdgpu_fini(adev);
1580         kfree(adev->ip_block_enabled);
1581         adev->ip_block_enabled = NULL;
1582         adev->accel_working = false;
1583         /* free i2c buses */
1584         amdgpu_i2c_fini(adev);
1585         amdgpu_atombios_fini(adev);
1586         kfree(adev->bios);
1587         adev->bios = NULL;
1588         vga_switcheroo_unregister_client(adev->pdev);
1589         vga_client_register(adev->pdev, NULL, NULL, NULL);
1590         if (adev->rio_mem)
1591                 pci_iounmap(adev->pdev, adev->rio_mem);
1592         adev->rio_mem = NULL;
1593         iounmap(adev->rmmio);
1594         adev->rmmio = NULL;
1595         amdgpu_doorbell_fini(adev);
1596         amdgpu_debugfs_regs_cleanup(adev);
1597         amdgpu_debugfs_remove_files(adev);
1598 }
1599
1600
1601 /*
1602  * Suspend & resume.
1603  */
1604 /**
1605  * amdgpu_suspend_kms - initiate device suspend
1606  *
1607  * @pdev: drm dev pointer
1608  * @state: suspend state
1609  *
1610  * Puts the hw in the suspend state (all asics).
1611  * Returns 0 for success or an error on failure.
1612  * Called at driver suspend.
1613  */
1614 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1615 {
1616         struct amdgpu_device *adev;
1617         struct drm_crtc *crtc;
1618         struct drm_connector *connector;
1619         int i, r;
1620         bool force_completion = false;
1621
1622         if (dev == NULL || dev->dev_private == NULL) {
1623                 return -ENODEV;
1624         }
1625
1626         adev = dev->dev_private;
1627
1628         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1629                 return 0;
1630
1631         drm_kms_helper_poll_disable(dev);
1632
1633         /* turn off display hw */
1634         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1635                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1636         }
1637
1638         /* unpin the front buffers */
1639         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1640                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1641                 struct amdgpu_bo *robj;
1642
1643                 if (rfb == NULL || rfb->obj == NULL) {
1644                         continue;
1645                 }
1646                 robj = gem_to_amdgpu_bo(rfb->obj);
1647                 /* don't unpin kernel fb objects */
1648                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1649                         r = amdgpu_bo_reserve(robj, false);
1650                         if (r == 0) {
1651                                 amdgpu_bo_unpin(robj);
1652                                 amdgpu_bo_unreserve(robj);
1653                         }
1654                 }
1655         }
1656         /* evict vram memory */
1657         amdgpu_bo_evict_vram(adev);
1658
1659         /* wait for gpu to finish processing current batch */
1660         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1661                 struct amdgpu_ring *ring = adev->rings[i];
1662                 if (!ring)
1663                         continue;
1664
1665                 r = amdgpu_fence_wait_empty(ring);
1666                 if (r) {
1667                         /* delay GPU reset to resume */
1668                         force_completion = true;
1669                 }
1670         }
1671         if (force_completion) {
1672                 amdgpu_fence_driver_force_completion(adev);
1673         }
1674
1675         r = amdgpu_suspend(adev);
1676
1677         /* evict remaining vram memory */
1678         amdgpu_bo_evict_vram(adev);
1679
1680         pci_save_state(dev->pdev);
1681         if (suspend) {
1682                 /* Shut down the device */
1683                 pci_disable_device(dev->pdev);
1684                 pci_set_power_state(dev->pdev, PCI_D3hot);
1685         }
1686
1687         if (fbcon) {
1688                 console_lock();
1689                 amdgpu_fbdev_set_suspend(adev, 1);
1690                 console_unlock();
1691         }
1692         return 0;
1693 }
1694
1695 /**
1696  * amdgpu_resume_kms - initiate device resume
1697  *
1698  * @pdev: drm dev pointer
1699  *
1700  * Bring the hw back to operating state (all asics).
1701  * Returns 0 for success or an error on failure.
1702  * Called at driver resume.
1703  */
1704 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1705 {
1706         struct drm_connector *connector;
1707         struct amdgpu_device *adev = dev->dev_private;
1708         int r;
1709
1710         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1711                 return 0;
1712
1713         if (fbcon) {
1714                 console_lock();
1715         }
1716         if (resume) {
1717                 pci_set_power_state(dev->pdev, PCI_D0);
1718                 pci_restore_state(dev->pdev);
1719                 if (pci_enable_device(dev->pdev)) {
1720                         if (fbcon)
1721                                 console_unlock();
1722                         return -1;
1723                 }
1724         }
1725
1726         /* post card */
1727         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1728
1729         r = amdgpu_resume(adev);
1730
1731         r = amdgpu_ib_ring_tests(adev);
1732         if (r)
1733                 DRM_ERROR("ib ring test failed (%d).\n", r);
1734
1735         r = amdgpu_late_init(adev);
1736         if (r)
1737                 return r;
1738
1739         /* blat the mode back in */
1740         if (fbcon) {
1741                 drm_helper_resume_force_mode(dev);
1742                 /* turn on display hw */
1743                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1744                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1745                 }
1746         }
1747
1748         drm_kms_helper_poll_enable(dev);
1749
1750         if (fbcon) {
1751                 amdgpu_fbdev_set_suspend(adev, 0);
1752                 console_unlock();
1753         }
1754
1755         return 0;
1756 }
1757
1758 /**
1759  * amdgpu_gpu_reset - reset the asic
1760  *
1761  * @adev: amdgpu device pointer
1762  *
1763  * Attempt the reset the GPU if it has hung (all asics).
1764  * Returns 0 for success or an error on failure.
1765  */
1766 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1767 {
1768         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1769         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1770
1771         bool saved = false;
1772
1773         int i, r;
1774         int resched;
1775
1776         down_write(&adev->exclusive_lock);
1777
1778         if (!adev->needs_reset) {
1779                 up_write(&adev->exclusive_lock);
1780                 return 0;
1781         }
1782
1783         adev->needs_reset = false;
1784         atomic_inc(&adev->gpu_reset_counter);
1785
1786         /* block TTM */
1787         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1788
1789         r = amdgpu_suspend(adev);
1790
1791         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1792                 struct amdgpu_ring *ring = adev->rings[i];
1793                 if (!ring)
1794                         continue;
1795
1796                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1797                 if (ring_sizes[i]) {
1798                         saved = true;
1799                         dev_info(adev->dev, "Saved %d dwords of commands "
1800                                  "on ring %d.\n", ring_sizes[i], i);
1801                 }
1802         }
1803
1804 retry:
1805         r = amdgpu_asic_reset(adev);
1806         if (!r) {
1807                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1808                 r = amdgpu_resume(adev);
1809         }
1810
1811         if (!r) {
1812                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1813                         struct amdgpu_ring *ring = adev->rings[i];
1814                         if (!ring)
1815                                 continue;
1816
1817                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1818                         ring_sizes[i] = 0;
1819                         ring_data[i] = NULL;
1820                 }
1821
1822                 r = amdgpu_ib_ring_tests(adev);
1823                 if (r) {
1824                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1825                         if (saved) {
1826                                 saved = false;
1827                                 r = amdgpu_suspend(adev);
1828                                 goto retry;
1829                         }
1830                 }
1831         } else {
1832                 amdgpu_fence_driver_force_completion(adev);
1833                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1834                         if (adev->rings[i])
1835                                 kfree(ring_data[i]);
1836                 }
1837         }
1838
1839         drm_helper_resume_force_mode(adev->ddev);
1840
1841         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1842         if (r) {
1843                 /* bad news, how to tell it to userspace ? */
1844                 dev_info(adev->dev, "GPU reset failed\n");
1845         }
1846
1847         up_write(&adev->exclusive_lock);
1848         return r;
1849 }
1850
1851
1852 /*
1853  * Debugfs
1854  */
1855 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1856                              struct drm_info_list *files,
1857                              unsigned nfiles)
1858 {
1859         unsigned i;
1860
1861         for (i = 0; i < adev->debugfs_count; i++) {
1862                 if (adev->debugfs[i].files == files) {
1863                         /* Already registered */
1864                         return 0;
1865                 }
1866         }
1867
1868         i = adev->debugfs_count + 1;
1869         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
1870                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1871                 DRM_ERROR("Report so we increase "
1872                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1873                 return -EINVAL;
1874         }
1875         adev->debugfs[adev->debugfs_count].files = files;
1876         adev->debugfs[adev->debugfs_count].num_files = nfiles;
1877         adev->debugfs_count = i;
1878 #if defined(CONFIG_DEBUG_FS)
1879         drm_debugfs_create_files(files, nfiles,
1880                                  adev->ddev->control->debugfs_root,
1881                                  adev->ddev->control);
1882         drm_debugfs_create_files(files, nfiles,
1883                                  adev->ddev->primary->debugfs_root,
1884                                  adev->ddev->primary);
1885 #endif
1886         return 0;
1887 }
1888
1889 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
1890 {
1891 #if defined(CONFIG_DEBUG_FS)
1892         unsigned i;
1893
1894         for (i = 0; i < adev->debugfs_count; i++) {
1895                 drm_debugfs_remove_files(adev->debugfs[i].files,
1896                                          adev->debugfs[i].num_files,
1897                                          adev->ddev->control);
1898                 drm_debugfs_remove_files(adev->debugfs[i].files,
1899                                          adev->debugfs[i].num_files,
1900                                          adev->ddev->primary);
1901         }
1902 #endif
1903 }
1904
1905 #if defined(CONFIG_DEBUG_FS)
1906
1907 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
1908                                         size_t size, loff_t *pos)
1909 {
1910         struct amdgpu_device *adev = f->f_inode->i_private;
1911         ssize_t result = 0;
1912         int r;
1913
1914         if (size & 0x3 || *pos & 0x3)
1915                 return -EINVAL;
1916
1917         while (size) {
1918                 uint32_t value;
1919
1920                 if (*pos > adev->rmmio_size)
1921                         return result;
1922
1923                 value = RREG32(*pos >> 2);
1924                 r = put_user(value, (uint32_t *)buf);
1925                 if (r)
1926                         return r;
1927
1928                 result += 4;
1929                 buf += 4;
1930                 *pos += 4;
1931                 size -= 4;
1932         }
1933
1934         return result;
1935 }
1936
1937 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
1938                                          size_t size, loff_t *pos)
1939 {
1940         struct amdgpu_device *adev = f->f_inode->i_private;
1941         ssize_t result = 0;
1942         int r;
1943
1944         if (size & 0x3 || *pos & 0x3)
1945                 return -EINVAL;
1946
1947         while (size) {
1948                 uint32_t value;
1949
1950                 if (*pos > adev->rmmio_size)
1951                         return result;
1952
1953                 r = get_user(value, (uint32_t *)buf);
1954                 if (r)
1955                         return r;
1956
1957                 WREG32(*pos >> 2, value);
1958
1959                 result += 4;
1960                 buf += 4;
1961                 *pos += 4;
1962                 size -= 4;
1963         }
1964
1965         return result;
1966 }
1967
1968 static const struct file_operations amdgpu_debugfs_regs_fops = {
1969         .owner = THIS_MODULE,
1970         .read = amdgpu_debugfs_regs_read,
1971         .write = amdgpu_debugfs_regs_write,
1972         .llseek = default_llseek
1973 };
1974
1975 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1976 {
1977         struct drm_minor *minor = adev->ddev->primary;
1978         struct dentry *ent, *root = minor->debugfs_root;
1979
1980         ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
1981                                   adev, &amdgpu_debugfs_regs_fops);
1982         if (IS_ERR(ent))
1983                 return PTR_ERR(ent);
1984         i_size_write(ent->d_inode, adev->rmmio_size);
1985         adev->debugfs_regs = ent;
1986
1987         return 0;
1988 }
1989
1990 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
1991 {
1992         debugfs_remove(adev->debugfs_regs);
1993         adev->debugfs_regs = NULL;
1994 }
1995
1996 int amdgpu_debugfs_init(struct drm_minor *minor)
1997 {
1998         return 0;
1999 }
2000
2001 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2002 {
2003 }
2004 #else
2005 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2006 {
2007         return 0;
2008 }
2009 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2010 #endif