drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < adev->sdma.num_instances) {
 108                         *out_ring = &adev->sdma.instance[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only %d SDMA rings are supported\n",
 111                                   adev->sdma.num_instances);
 112                         return -EINVAL;
 113                 }
 114                 break;
 115         case AMDGPU_HW_IP_UVD:
 116                 *out_ring = &adev->uvd.ring;
 117                 break;
 118         case AMDGPU_HW_IP_VCE:
 119                 if (ring < 2){
 120                         *out_ring = &adev->vce.ring[ring];
 121                 } else {
 122                         DRM_ERROR("only two VCE rings are supported\n");
 123                         return -EINVAL;
 124                 }
 125                 break;
 126         }
 127         return 0;
 128 }
 129
 130 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 131 {
 132         union drm_amdgpu_cs *cs = data;
 133         uint64_t *chunk_array_user;
 134         uint64_t *chunk_array;
 135         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 136         unsigned size;
 137         int i;
 138         int ret;
 139
 140         if (cs->in.num_chunks == 0)
 141                 return 0;
 142
 143         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 144         if (!chunk_array)
 145                 return -ENOMEM;
 146
 147         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 148         if (!p->ctx) {
 149                 ret = -EINVAL;
 150                 goto free_chunk;
 151         }
 152
 153         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 154
 155         /* get chunks */
 156         INIT_LIST_HEAD(&p->validated);
 157         chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
 158         if (copy_from_user(chunk_array, chunk_array_user,
 159                            sizeof(uint64_t)*cs->in.num_chunks)) {
 160                 ret = -EFAULT;
 161                 goto put_bo_list;
 162         }
 163
 164         p->nchunks = cs->in.num_chunks;
 165         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 166                             GFP_KERNEL);
 167         if (!p->chunks) {
 168                 ret = -ENOMEM;
 169                 goto put_bo_list;
 170         }
 171
 172         for (i = 0; i < p->nchunks; i++) {
 173                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 174                 struct drm_amdgpu_cs_chunk user_chunk;
 175                 uint32_t __user *cdata;
 176
 177                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 178                 if (copy_from_user(&user_chunk, chunk_ptr,
 179                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 180                         ret = -EFAULT;
 181                         i--;
 182                         goto free_partial_kdata;
 183                 }
 184                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 185                 p->chunks[i].length_dw = user_chunk.length_dw;
 186
 187                 size = p->chunks[i].length_dw;
 188                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 189                 p->chunks[i].user_ptr = cdata;
 190
 191                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 192                 if (p->chunks[i].kdata == NULL) {
 193                         ret = -ENOMEM;
 194                         i--;
 195                         goto free_partial_kdata;
 196                 }
 197                 size *= sizeof(uint32_t);
 198                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 199                         ret = -EFAULT;
 200                         goto free_partial_kdata;
 201                 }
 202
 203                 switch (p->chunks[i].chunk_id) {
 204                 case AMDGPU_CHUNK_ID_IB:
 205                         p->num_ibs++;
 206                         break;
 207
 208                 case AMDGPU_CHUNK_ID_FENCE:
 209                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 210                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 211                                 uint32_t handle;
 212                                 struct drm_gem_object *gobj;
 213                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 214
 215                                 fence_data = (void *)p->chunks[i].kdata;
 216                                 handle = fence_data->handle;
 217                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 218                                                              p->filp, handle);
 219                                 if (gobj == NULL) {
 220                                         ret = -EINVAL;
 221                                         goto free_partial_kdata;
 222                                 }
 223
 224                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 225                                 amdgpu_bo_ref(p->uf.bo);
 226                                 drm_gem_object_unreference_unlocked(gobj);
 227                                 p->uf.offset = fence_data->offset;
 228                         } else {
 229                                 ret = -EINVAL;
 230                                 goto free_partial_kdata;
 231                         }
 232                         break;
 233
 234                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 235                         break;
 236
 237                 default:
 238                         ret = -EINVAL;
 239                         goto free_partial_kdata;
 240                 }
 241         }
 242
 243
 244         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 245         if (!p->ibs) {
 246                 ret = -ENOMEM;
 247                 goto free_all_kdata;
 248         }
 249
 250         kfree(chunk_array);
 251         return 0;
 252
 253 free_all_kdata:
 254         i = p->nchunks - 1;
 255 free_partial_kdata:
 256         for (; i >= 0; i--)
 257                 drm_free_large(p->chunks[i].kdata);
 258         kfree(p->chunks);
 259 put_bo_list:
 260         if (p->bo_list)
 261                 amdgpu_bo_list_put(p->bo_list);
 262         amdgpu_ctx_put(p->ctx);
 263 free_chunk:
 264         kfree(chunk_array);
 265
 266         return ret;
 267 }
 268
 269 /* Returns how many bytes TTM can move per IB.
 270  */
 271 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 272 {
 273         u64 real_vram_size = adev->mc.real_vram_size;
 274         u64 vram_usage = atomic64_read(&adev->vram_usage);
 275
 276         /* This function is based on the current VRAM usage.
 277          *
 278          * - If all of VRAM is free, allow relocating the number of bytes that
 279          *   is equal to 1/4 of the size of VRAM for this IB.
 280
 281          * - If more than one half of VRAM is occupied, only allow relocating
 282          *   1 MB of data for this IB.
 283          *
 284          * - From 0 to one half of used VRAM, the threshold decreases
 285          *   linearly.
 286          *         __________________
 287          * 1/4 of -|\               |
 288          * VRAM    | \              |
 289          *         |  \             |
 290          *         |   \            |
 291          *         |    \           |
 292          *         |     \          |
 293          *         |      \         |
 294          *         |       \________|1 MB
 295          *         |----------------|
 296          *    VRAM 0 %             100 %
 297          *         used            used
 298          *
 299          * Note: It's a threshold, not a limit. The threshold must be crossed
 300          * for buffer relocations to stop, so any buffer of an arbitrary size
 301          * can be moved as long as the threshold isn't crossed before
 302          * the relocation takes place. We don't want to disable buffer
 303          * relocations completely.
 304          *
 305          * The idea is that buffers should be placed in VRAM at creation time
 306          * and TTM should only do a minimum number of relocations during
 307          * command submission. In practice, you need to submit at least
 308          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 309          *
 310          * Also, things can get pretty crazy under memory pressure and actual
 311          * VRAM usage can change a lot, so playing safe even at 50% does
 312          * consistently increase performance.
 313          */
 314
 315         u64 half_vram = real_vram_size >> 1;
 316         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 317         u64 bytes_moved_threshold = half_free_vram >> 1;
 318         return max(bytes_moved_threshold, 1024*1024ull);
 319 }
 320
 321 int amdgpu_cs_list_validate(struct amdgpu_device *adev,
 322                             struct amdgpu_vm *vm,
 323                             struct list_head *validated)
 324 {
 325         struct amdgpu_bo_list_entry *lobj;
 326         struct amdgpu_bo *bo;
 327         u64 bytes_moved = 0, initial_bytes_moved;
 328         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 329         int r;
 330
 331         list_for_each_entry(lobj, validated, tv.head) {
 332                 bo = lobj->robj;
 333                 if (!bo->pin_count) {
 334                         u32 domain = lobj->prefered_domains;
 335                         u32 current_domain =
 336                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 337
 338                         /* Check if this buffer will be moved and don't move it
 339                          * if we have moved too many buffers for this IB already.
 340                          *
 341                          * Note that this allows moving at least one buffer of
 342                          * any size, because it doesn't take the current "bo"
 343                          * into account. We don't want to disallow buffer moves
 344                          * completely.
 345                          */
 346                         if ((lobj->allowed_domains & current_domain) != 0 &&
 347                             (domain & current_domain) == 0 && /* will be moved */
 348                             bytes_moved > bytes_moved_threshold) {
 349                                 /* don't move it */
 350                                 domain = current_domain;
 351                         }
 352
 353                 retry:
 354                         amdgpu_ttm_placement_from_domain(bo, domain);
 355                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 356                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 357                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 358                                        initial_bytes_moved;
 359
 360                         if (unlikely(r)) {
 361                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 362                                         domain = lobj->allowed_domains;
 363                                         goto retry;
 364                                 }
 365                                 return r;
 366                         }
 367                 }
 368                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 369         }
 370         return 0;
 371 }
 372
 373 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 374 {
 375         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 376         struct amdgpu_cs_buckets buckets;
 377         struct list_head duplicates;
 378         bool need_mmap_lock = false;
 379         int i, r;
 380
 381         if (p->bo_list) {
 382                 need_mmap_lock = p->bo_list->has_userptr;
 383                 amdgpu_cs_buckets_init(&buckets);
 384                 for (i = 0; i < p->bo_list->num_entries; i++)
 385                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 386                                                                   p->bo_list->array[i].priority);
 387
 388                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 389         }
 390
 391         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 392                                       &p->validated);
 393
 394         if (need_mmap_lock)
 395                 down_read(&current->mm->mmap_sem);
 396
 397         INIT_LIST_HEAD(&duplicates);
 398         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 399         if (unlikely(r != 0))
 400                 goto error_reserve;
 401
 402         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
 403         if (r)
 404                 goto error_validate;
 405
 406         r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
 407
 408 error_validate:
 409         if (r)
 410                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 411
 412 error_reserve:
 413         if (need_mmap_lock)
 414                 up_read(&current->mm->mmap_sem);
 415
 416         return r;
 417 }
 418
 419 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 420 {
 421         struct amdgpu_bo_list_entry *e;
 422         int r;
 423
 424         list_for_each_entry(e, &p->validated, tv.head) {
 425                 struct reservation_object *resv = e->robj->tbo.resv;
 426                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 427
 428                 if (r)
 429                         return r;
 430         }
 431         return 0;
 432 }
 433
 434 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 435                                   struct list_head *b)
 436 {
 437         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 438         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 439
 440         /* Sort A before B if A is smaller. */
 441         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 442 }
 443
 444 /**
 445  * cs_parser_fini() - clean parser states
 446  * @parser:     parser structure holding parsing context.
 447  * @error:      error number
 448  *
 449  * If error is set than unvalidate buffer, otherwise just free memory
 450  * used by parsing context.
 451  **/
 452 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 453 {
 454         unsigned i;
 455
 456         if (!error) {
 457                 /* Sort the buffer list from the smallest to largest buffer,
 458                  * which affects the order of buffers in the LRU list.
 459                  * This assures that the smallest buffers are added first
 460                  * to the LRU list, so they are likely to be later evicted
 461                  * first, instead of large buffers whose eviction is more
 462                  * expensive.
 463                  *
 464                  * This slightly lowers the number of bytes moved by TTM
 465                  * per frame under memory pressure.
 466                  */
 467                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 468
 469                 ttm_eu_fence_buffer_objects(&parser->ticket,
 470                                             &parser->validated,
 471                                             parser->fence);
 472         } else if (backoff) {
 473                 ttm_eu_backoff_reservation(&parser->ticket,
 474                                            &parser->validated);
 475         }
 476         fence_put(parser->fence);
 477
 478         if (parser->ctx)
 479                 amdgpu_ctx_put(parser->ctx);
 480         if (parser->bo_list)
 481                 amdgpu_bo_list_put(parser->bo_list);
 482
 483         drm_free_large(parser->vm_bos);
 484         for (i = 0; i < parser->nchunks; i++)
 485                 drm_free_large(parser->chunks[i].kdata);
 486         kfree(parser->chunks);
 487         if (parser->ibs)
 488                 for (i = 0; i < parser->num_ibs; i++)
 489                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 490         kfree(parser->ibs);
 491         if (parser->uf.bo)
 492                 amdgpu_bo_unref(&parser->uf.bo);
 493 }
 494
 495 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 496                                    struct amdgpu_vm *vm)
 497 {
 498         struct amdgpu_device *adev = p->adev;
 499         struct amdgpu_bo_va *bo_va;
 500         struct amdgpu_bo *bo;
 501         int i, r;
 502
 503         r = amdgpu_vm_update_page_directory(adev, vm);
 504         if (r)
 505                 return r;
 506
 507         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
 508         if (r)
 509                 return r;
 510
 511         r = amdgpu_vm_clear_freed(adev, vm);
 512         if (r)
 513                 return r;
 514
 515         if (p->bo_list) {
 516                 for (i = 0; i < p->bo_list->num_entries; i++) {
 517                         struct fence *f;
 518
 519                         /* ignore duplicates */
 520                         bo = p->bo_list->array[i].robj;
 521                         if (!bo)
 522                                 continue;
 523
 524                         bo_va = p->bo_list->array[i].bo_va;
 525                         if (bo_va == NULL)
 526                                 continue;
 527
 528                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 529                         if (r)
 530                                 return r;
 531
 532                         f = bo_va->last_pt_update;
 533                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 534                         if (r)
 535                                 return r;
 536                 }
 537
 538         }
 539
 540         r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 541
 542         if (amdgpu_vm_debug && p->bo_list) {
 543                 /* Invalidate all BOs to test for userspace bugs */
 544                 for (i = 0; i < p->bo_list->num_entries; i++) {
 545                         /* ignore duplicates */
 546                         bo = p->bo_list->array[i].robj;
 547                         if (!bo)
 548                                 continue;
 549
 550                         amdgpu_vm_bo_invalidate(adev, bo);
 551                 }
 552         }
 553
 554         return r;
 555 }
 556
 557 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 558                                  struct amdgpu_cs_parser *parser)
 559 {
 560         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 561         struct amdgpu_vm *vm = &fpriv->vm;
 562         struct amdgpu_ring *ring;
 563         int i, r;
 564
 565         if (parser->num_ibs == 0)
 566                 return 0;
 567
 568         /* Only for UVD/VCE VM emulation */
 569         for (i = 0; i < parser->num_ibs; i++) {
 570                 ring = parser->ibs[i].ring;
 571                 if (ring->funcs->parse_cs) {
 572                         r = amdgpu_ring_parse_cs(ring, parser, i);
 573                         if (r)
 574                                 return r;
 575                 }
 576         }
 577
 578         r = amdgpu_bo_vm_update_pte(parser, vm);
 579         if (!r)
 580                 amdgpu_cs_sync_rings(parser);
 581
 582         return r;
 583 }
 584
 585 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 586 {
 587         if (r == -EDEADLK) {
 588                 r = amdgpu_gpu_reset(adev);
 589                 if (!r)
 590                         r = -EAGAIN;
 591         }
 592         return r;
 593 }
 594
 595 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 596                              struct amdgpu_cs_parser *parser)
 597 {
 598         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 599         struct amdgpu_vm *vm = &fpriv->vm;
 600         int i, j;
 601         int r;
 602
 603         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 604                 struct amdgpu_cs_chunk *chunk;
 605                 struct amdgpu_ib *ib;
 606                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 607                 struct amdgpu_ring *ring;
 608
 609                 chunk = &parser->chunks[i];
 610                 ib = &parser->ibs[j];
 611                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 612
 613                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 614                         continue;
 615
 616                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 617                                        chunk_ib->ip_instance, chunk_ib->ring,
 618                                        &ring);
 619                 if (r)
 620                         return r;
 621
 622                 if (ring->funcs->parse_cs) {
 623                         struct amdgpu_bo_va_mapping *m;
 624                         struct amdgpu_bo *aobj = NULL;
 625                         uint64_t offset;
 626                         uint8_t *kptr;
 627
 628                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 629                                                    &aobj);
 630                         if (!aobj) {
 631                                 DRM_ERROR("IB va_start is invalid\n");
 632                                 return -EINVAL;
 633                         }
 634
 635                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 636                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 637                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 638                                 return -EINVAL;
 639                         }
 640
 641                         /* the IB should be reserved at this point */
 642                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 643                         if (r) {
 644                                 return r;
 645                         }
 646
 647                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 648                         kptr += chunk_ib->va_start - offset;
 649
 650                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 651                         if (r) {
 652                                 DRM_ERROR("Failed to get ib !\n");
 653                                 return r;
 654                         }
 655
 656                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 657                         amdgpu_bo_kunmap(aobj);
 658                 } else {
 659                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 660                         if (r) {
 661                                 DRM_ERROR("Failed to get ib !\n");
 662                                 return r;
 663                         }
 664
 665                         ib->gpu_addr = chunk_ib->va_start;
 666                 }
 667
 668                 ib->length_dw = chunk_ib->ib_bytes / 4;
 669                 ib->flags = chunk_ib->flags;
 670                 ib->ctx = parser->ctx;
 671                 j++;
 672         }
 673
 674         if (!parser->num_ibs)
 675                 return 0;
 676
 677         /* add GDS resources to first IB */
 678         if (parser->bo_list) {
 679                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 680                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 681                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 682                 struct amdgpu_ib *ib = &parser->ibs[0];
 683
 684                 if (gds) {
 685                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 686                         ib->gds_size = amdgpu_bo_size(gds);
 687                 }
 688                 if (gws) {
 689                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 690                         ib->gws_size = amdgpu_bo_size(gws);
 691                 }
 692                 if (oa) {
 693                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 694                         ib->oa_size = amdgpu_bo_size(oa);
 695                 }
 696         }
 697         /* wrap the last IB with user fence */
 698         if (parser->uf.bo) {
 699                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 700
 701                 /* UVD & VCE fw doesn't support user fences */
 702                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 703                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 704                         return -EINVAL;
 705
 706                 ib->user = &parser->uf;
 707         }
 708
 709         return 0;
 710 }
 711
 712 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 713                                   struct amdgpu_cs_parser *p)
 714 {
 715         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 716         struct amdgpu_ib *ib;
 717         int i, j, r;
 718
 719         if (!p->num_ibs)
 720                 return 0;
 721
 722         /* Add dependencies to first IB */
 723         ib = &p->ibs[0];
 724         for (i = 0; i < p->nchunks; ++i) {
 725                 struct drm_amdgpu_cs_chunk_dep *deps;
 726                 struct amdgpu_cs_chunk *chunk;
 727                 unsigned num_deps;
 728
 729                 chunk = &p->chunks[i];
 730
 731                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 732                         continue;
 733
 734                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 735                 num_deps = chunk->length_dw * 4 /
 736                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 737
 738                 for (j = 0; j < num_deps; ++j) {
 739                         struct amdgpu_ring *ring;
 740                         struct amdgpu_ctx *ctx;
 741                         struct fence *fence;
 742
 743                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 744                                                deps[j].ip_instance,
 745                                                deps[j].ring, &ring);
 746                         if (r)
 747                                 return r;
 748
 749                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 750                         if (ctx == NULL)
 751                                 return -EINVAL;
 752
 753                         fence = amdgpu_ctx_get_fence(ctx, ring,
 754                                                      deps[j].handle);
 755                         if (IS_ERR(fence)) {
 756                                 r = PTR_ERR(fence);
 757                                 amdgpu_ctx_put(ctx);
 758                                 return r;
 759
 760                         } else if (fence) {
 761                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 762                                 fence_put(fence);
 763                                 amdgpu_ctx_put(ctx);
 764                                 if (r)
 765                                         return r;
 766                         }
 767                 }
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int amdgpu_cs_free_job(struct amdgpu_job *job)
 774 {
 775         int i;
 776         if (job->ibs)
 777                 for (i = 0; i < job->num_ibs; i++)
 778                         amdgpu_ib_free(job->adev, &job->ibs[i]);
 779         kfree(job->ibs);
 780         if (job->uf.bo)
 781                 amdgpu_bo_unref(&job->uf.bo);
 782         return 0;
 783 }
 784
 785 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 786 {
 787         struct amdgpu_device *adev = dev->dev_private;
 788         union drm_amdgpu_cs *cs = data;
 789         struct amdgpu_cs_parser parser = {};
 790         bool reserved_buffers = false;
 791         int i, r;
 792
 793         if (!adev->accel_working)
 794                 return -EBUSY;
 795
 796         parser.adev = adev;
 797         parser.filp = filp;
 798
 799         r = amdgpu_cs_parser_init(&parser, data);
 800         if (r) {
 801                 DRM_ERROR("Failed to initialize parser !\n");
 802                 amdgpu_cs_parser_fini(&parser, r, false);
 803                 r = amdgpu_cs_handle_lockup(adev, r);
 804                 return r;
 805         }
 806         r = amdgpu_cs_parser_relocs(&parser);
 807         if (r == -ENOMEM)
 808                 DRM_ERROR("Not enough memory for command submission!\n");
 809         else if (r && r != -ERESTARTSYS)
 810                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 811         else if (!r) {
 812                 reserved_buffers = true;
 813                 r = amdgpu_cs_ib_fill(adev, &parser);
 814         }
 815
 816         if (!r) {
 817                 r = amdgpu_cs_dependencies(adev, &parser);
 818                 if (r)
 819                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 820         }
 821
 822         if (r)
 823                 goto out;
 824
 825         for (i = 0; i < parser.num_ibs; i++)
 826                 trace_amdgpu_cs(&parser, i);
 827
 828         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 829         if (r)
 830                 goto out;
 831
 832         if (amdgpu_enable_scheduler && parser.num_ibs) {
 833                 struct amdgpu_ring * ring = parser.ibs->ring;
 834                 struct amd_sched_fence *fence;
 835                 struct amdgpu_job *job;
 836
 837                 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
 838                 if (!job) {
 839                         r = -ENOMEM;
 840                         goto out;
 841                 }
 842
 843                 job->base.sched = &ring->sched;
 844                 job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
 845                 job->adev = parser.adev;
 846                 job->owner = parser.filp;
 847                 job->free_job = amdgpu_cs_free_job;
 848
 849                 job->ibs = parser.ibs;
 850                 job->num_ibs = parser.num_ibs;
 851                 parser.ibs = NULL;
 852                 parser.num_ibs = 0;
 853
 854                 if (job->ibs[job->num_ibs - 1].user) {
 855                         job->uf = parser.uf;
 856                         job->ibs[job->num_ibs - 1].user = &job->uf;
 857                         parser.uf.bo = NULL;
 858                 }
 859
 860                 fence = amd_sched_fence_create(job->base.s_entity,
 861                                                parser.filp);
 862                 if (!fence) {
 863                         r = -ENOMEM;
 864                         amdgpu_cs_free_job(job);
 865                         kfree(job);
 866                         goto out;
 867                 }
 868                 job->base.s_fence = fence;
 869                 parser.fence = fence_get(&fence->base);
 870
 871                 cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring,
 872                                                       &fence->base);
 873                 job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
 874
 875                 trace_amdgpu_cs_ioctl(job);
 876                 amd_sched_entity_push_job(&job->base);
 877
 878         } else {
 879                 struct amdgpu_fence *fence;
 880
 881                 r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs,
 882                                        parser.filp);
 883                 fence = parser.ibs[parser.num_ibs - 1].fence;
 884                 parser.fence = fence_get(&fence->base);
 885                 cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
 886         }
 887
 888 out:
 889         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 890         r = amdgpu_cs_handle_lockup(adev, r);
 891         return r;
 892 }
 893
 894 /**
 895  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 896  *
 897  * @dev: drm device
 898  * @data: data from userspace
 899  * @filp: file private
 900  *
 901  * Wait for the command submission identified by handle to finish.
 902  */
 903 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 904                          struct drm_file *filp)
 905 {
 906         union drm_amdgpu_wait_cs *wait = data;
 907         struct amdgpu_device *adev = dev->dev_private;
 908         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 909         struct amdgpu_ring *ring = NULL;
 910         struct amdgpu_ctx *ctx;
 911         struct fence *fence;
 912         long r;
 913
 914         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 915                                wait->in.ring, &ring);
 916         if (r)
 917                 return r;
 918
 919         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 920         if (ctx == NULL)
 921                 return -EINVAL;
 922
 923         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 924         if (IS_ERR(fence))
 925                 r = PTR_ERR(fence);
 926         else if (fence) {
 927                 r = fence_wait_timeout(fence, true, timeout);
 928                 fence_put(fence);
 929         } else
 930                 r = 1;
 931
 932         amdgpu_ctx_put(ctx);
 933         if (r < 0)
 934                 return r;
 935
 936         memset(wait, 0, sizeof(*wait));
 937         wait->out.status = (r == 0);
 938
 939         return 0;
 940 }
 941
 942 /**
 943  * amdgpu_cs_find_bo_va - find bo_va for VM address
 944  *
 945  * @parser: command submission parser context
 946  * @addr: VM address
 947  * @bo: resulting BO of the mapping found
 948  *
 949  * Search the buffer objects in the command submission context for a certain
 950  * virtual memory address. Returns allocation structure when found, NULL
 951  * otherwise.
 952  */
 953 struct amdgpu_bo_va_mapping *
 954 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 955                        uint64_t addr, struct amdgpu_bo **bo)
 956 {
 957         struct amdgpu_bo_list_entry *reloc;
 958         struct amdgpu_bo_va_mapping *mapping;
 959
 960         addr /= AMDGPU_GPU_PAGE_SIZE;
 961
 962         list_for_each_entry(reloc, &parser->validated, tv.head) {
 963                 if (!reloc->bo_va)
 964                         continue;
 965
 966                 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
 967                         if (mapping->it.start > addr ||
 968                             addr > mapping->it.last)
 969                                 continue;
 970
 971                         *bo = reloc->bo_va->bo;
 972                         return mapping;
 973                 }
 974
 975                 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
 976                         if (mapping->it.start > addr ||
 977                             addr > mapping->it.last)
 978                                 continue;
 979
 980                         *bo = reloc->bo_va->bo;
 981                         return mapping;
 982                 }
 983         }
 984
 985         return NULL;
 986 }