2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/clk/sunxi.h>
21 #include <linux/of_address.h>
23 #include "clk-factors.h"
25 static DEFINE_SPINLOCK(clk_lock);
28 * sunxi_osc_clk_setup() - Setup function for gatable oscillator
31 #define SUNXI_OSC24M_GATE 0
33 static void __init sunxi_osc_clk_setup(struct device_node *node)
36 struct clk_fixed_rate *fixed;
37 struct clk_gate *gate;
38 const char *clk_name = node->name;
41 /* allocate fixed-rate and gate clock structs */
42 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
45 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
51 if (of_property_read_u32(node, "clock-frequency", &rate))
54 /* set up gate and fixed rate properties */
55 gate->reg = of_iomap(node, 0);
56 gate->bit_idx = SUNXI_OSC24M_GATE;
57 gate->lock = &clk_lock;
58 fixed->fixed_rate = rate;
60 clk = clk_register_composite(NULL, clk_name,
63 &fixed->hw, &clk_fixed_rate_ops,
64 &gate->hw, &clk_gate_ops,
68 of_clk_add_provider(node, of_clk_src_simple_get, clk);
69 clk_register_clkdev(clk, clk_name, NULL);
76 * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
77 * PLL1 rate is calculated as follows
78 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
79 * parent_rate is always 24Mhz
82 static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
83 u8 *n, u8 *k, u8 *m, u8 *p)
87 /* Normalize value to a 6M multiple */
88 div = *freq / 6000000;
89 *freq = 6000000 * div;
91 /* we were called to round the frequency, we can now return */
95 /* m is always zero for pll1 */
98 /* k is 1 only on these cases */
99 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
104 /* p will be 3 for divs under 10 */
108 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
109 else if (div < 20 || (div < 32 && (div & 1)))
112 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
113 * of divs between 40-62 */
114 else if (div < 40 || (div < 64 && (div & 2)))
117 /* any other entries have p = 0 */
121 /* calculate a suitable n based on k and p */
130 * sunxi_get_apb1_factors() - calculates m, p factors for APB1
131 * APB1 rate is calculated as follows
132 * rate = (parent_rate >> p) / (m + 1);
135 static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate,
136 u8 *n, u8 *k, u8 *m, u8 *p)
140 if (parent_rate < *freq)
143 parent_rate = (parent_rate + (*freq - 1)) / *freq;
146 if (parent_rate > 32)
149 if (parent_rate <= 4)
151 else if (parent_rate <= 8)
153 else if (parent_rate <= 16)
158 calcm = (parent_rate >> calcp) - 1;
160 *freq = (parent_rate >> calcp) / (calcm + 1);
162 /* we were called to round the frequency, we can now return */
173 * sunxi_factors_clk_setup() - Setup function for factor clocks
176 struct factors_data {
177 struct clk_factors_config *table;
178 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
181 static struct clk_factors_config pll1_config = {
192 static struct clk_factors_config apb1_config = {
199 static const __initconst struct factors_data pll1_data = {
200 .table = &pll1_config,
201 .getter = sunxi_get_pll1_factors,
204 static const __initconst struct factors_data apb1_data = {
205 .table = &apb1_config,
206 .getter = sunxi_get_apb1_factors,
209 static void __init sunxi_factors_clk_setup(struct device_node *node,
210 struct factors_data *data)
213 const char *clk_name = node->name;
217 reg = of_iomap(node, 0);
219 parent = of_clk_get_parent_name(node, 0);
221 clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
222 data->table, data->getter, &clk_lock);
225 of_clk_add_provider(node, of_clk_src_simple_get, clk);
226 clk_register_clkdev(clk, clk_name, NULL);
233 * sunxi_mux_clk_setup() - Setup function for muxes
236 #define SUNXI_MUX_GATE_WIDTH 2
242 static const __initconst struct mux_data cpu_mux_data = {
246 static const __initconst struct mux_data apb1_mux_data = {
250 static void __init sunxi_mux_clk_setup(struct device_node *node,
251 struct mux_data *data)
254 const char *clk_name = node->name;
255 const char *parents[5];
259 reg = of_iomap(node, 0);
261 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
264 clk = clk_register_mux(NULL, clk_name, parents, i,
265 CLK_SET_RATE_NO_REPARENT, reg,
266 data->shift, SUNXI_MUX_GATE_WIDTH,
270 of_clk_add_provider(node, of_clk_src_simple_get, clk);
271 clk_register_clkdev(clk, clk_name, NULL);
278 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
281 #define SUNXI_DIVISOR_WIDTH 2
288 static const __initconst struct div_data axi_data = {
293 static const __initconst struct div_data ahb_data = {
298 static const __initconst struct div_data apb0_data = {
303 static void __init sunxi_divider_clk_setup(struct device_node *node,
304 struct div_data *data)
307 const char *clk_name = node->name;
308 const char *clk_parent;
311 reg = of_iomap(node, 0);
313 clk_parent = of_clk_get_parent_name(node, 0);
315 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
316 reg, data->shift, SUNXI_DIVISOR_WIDTH,
317 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
320 of_clk_add_provider(node, of_clk_src_simple_get, clk);
321 clk_register_clkdev(clk, clk_name, NULL);
328 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
331 #define SUNXI_GATES_MAX_SIZE 64
334 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
337 static const __initconst struct gates_data sun4i_axi_gates_data = {
341 static const __initconst struct gates_data sun4i_ahb_gates_data = {
342 .mask = {0x7F77FFF, 0x14FB3F},
345 static const __initconst struct gates_data sun5i_a10s_ahb_gates_data = {
346 .mask = {0x147667e7, 0x185915},
349 static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
350 .mask = {0x107067e7, 0x185111},
353 static const __initconst struct gates_data sun4i_apb0_gates_data = {
357 static const __initconst struct gates_data sun5i_a10s_apb0_gates_data = {
361 static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
365 static const __initconst struct gates_data sun4i_apb1_gates_data = {
369 static const __initconst struct gates_data sun5i_a10s_apb1_gates_data = {
373 static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
377 static void __init sunxi_gates_clk_setup(struct device_node *node,
378 struct gates_data *data)
380 struct clk_onecell_data *clk_data;
381 const char *clk_parent;
382 const char *clk_name;
389 reg = of_iomap(node, 0);
391 clk_parent = of_clk_get_parent_name(node, 0);
393 /* Worst-case size approximation and memory allocation */
394 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
395 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
398 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
399 if (!clk_data->clks) {
404 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
405 of_property_read_string_index(node, "clock-output-names",
408 /* No driver claims this clock, but it should remain gated */
409 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
411 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
413 reg + 4 * (i/32), i % 32,
415 WARN_ON(IS_ERR(clk_data->clks[i]));
420 /* Adjust to the real max */
421 clk_data->clk_num = i;
423 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
426 /* Matches for of_clk_init */
427 static const __initconst struct of_device_id clk_match[] = {
428 {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
432 /* Matches for factors clocks */
433 static const __initconst struct of_device_id clk_factors_match[] = {
434 {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
435 {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
439 /* Matches for divider clocks */
440 static const __initconst struct of_device_id clk_div_match[] = {
441 {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
442 {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
443 {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
447 /* Matches for mux clocks */
448 static const __initconst struct of_device_id clk_mux_match[] = {
449 {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,},
450 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
454 /* Matches for gate clocks */
455 static const __initconst struct of_device_id clk_gates_match[] = {
456 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
457 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
458 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
459 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
460 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
461 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
462 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
463 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
464 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
465 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
469 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
472 struct device_node *np;
473 const struct div_data *data;
474 const struct of_device_id *match;
475 void (*setup_function)(struct device_node *, const void *) = function;
477 for_each_matching_node(np, clk_match) {
478 match = of_match_node(clk_match, np);
480 setup_function(np, data);
484 void __init sunxi_init_clocks(void)
486 /* Register all the simple sunxi clocks on DT */
487 of_clk_init(clk_match);
489 /* Register factor clocks */
490 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
492 /* Register divider clocks */
493 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
495 /* Register mux clocks */
496 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
498 /* Register gate clocks */
499 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);