drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #include "linux/synclink.h"
  85
  86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  87 #define SYNCLINK_GENERIC_HDLC 1
  88 #else
  89 #define SYNCLINK_GENERIC_HDLC 0
  90 #endif
  91
  92 /*
  93  * module identification
  94  */
  95 static char *driver_name     = "SyncLink GT";
  96 static char *driver_version  = "$Revision: 4.36 $";
  97 static char *tty_driver_name = "synclink_gt";
  98 static char *tty_dev_prefix  = "ttySLG";
  99 MODULE_LICENSE("GPL");
 100 #define MGSL_MAGIC 0x5401
 101 #define MAX_DEVICES 32
 102
 103 static struct pci_device_id pci_table[] = {
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 108         {0,}, /* terminate list */
 109 };
 110 MODULE_DEVICE_TABLE(pci, pci_table);
 111
 112 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 113 static void remove_one(struct pci_dev *dev);
 114 static struct pci_driver pci_driver = {
 115         .name           = "synclink_gt",
 116         .id_table       = pci_table,
 117         .probe          = init_one,
 118         .remove         = __devexit_p(remove_one),
 119 };
 120
 121 static int pci_registered;
 122
 123 /*
 124  * module configuration and status
 125  */
 126 static struct slgt_info *slgt_device_list;
 127 static int slgt_device_count;
 128
 129 static int ttymajor;
 130 static int debug_level;
 131 static int maxframe[MAX_DEVICES];
 132 static int dosyncppp[MAX_DEVICES];
 133
 134 module_param(ttymajor, int, 0);
 135 module_param(debug_level, int, 0);
 136 module_param_array(maxframe, int, NULL, 0);
 137 module_param_array(dosyncppp, int, NULL, 0);
 138
 139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 143
 144 /*
 145  * tty support and callbacks
 146  */
 147 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 148
 149 static struct tty_driver *serial_driver;
 150
 151 static int  open(struct tty_struct *tty, struct file * filp);
 152 static void close(struct tty_struct *tty, struct file * filp);
 153 static void hangup(struct tty_struct *tty);
 154 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 155
 156 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 157 static void put_char(struct tty_struct *tty, unsigned char ch);
 158 static void send_xchar(struct tty_struct *tty, char ch);
 159 static void wait_until_sent(struct tty_struct *tty, int timeout);
 160 static int  write_room(struct tty_struct *tty);
 161 static void flush_chars(struct tty_struct *tty);
 162 static void flush_buffer(struct tty_struct *tty);
 163 static void tx_hold(struct tty_struct *tty);
 164 static void tx_release(struct tty_struct *tty);
 165
 166 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 167 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 168 static int  chars_in_buffer(struct tty_struct *tty);
 169 static void throttle(struct tty_struct * tty);
 170 static void unthrottle(struct tty_struct * tty);
 171 static void set_break(struct tty_struct *tty, int break_state);
 172
 173 /*
 174  * generic HDLC support and callbacks
 175  */
 176 #if SYNCLINK_GENERIC_HDLC
 177 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 178 static void hdlcdev_tx_done(struct slgt_info *info);
 179 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 180 static int  hdlcdev_init(struct slgt_info *info);
 181 static void hdlcdev_exit(struct slgt_info *info);
 182 #endif
 183
 184
 185 /*
 186  * device specific structures, macros and functions
 187  */
 188
 189 #define SLGT_MAX_PORTS 4
 190 #define SLGT_REG_SIZE  256
 191
 192 /*
 193  * conditional wait facility
 194  */
 195 struct cond_wait {
 196         struct cond_wait *next;
 197         wait_queue_head_t q;
 198         wait_queue_t wait;
 199         unsigned int data;
 200 };
 201 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 202 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 203 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 204 static void flush_cond_wait(struct cond_wait **head);
 205
 206 /*
 207  * DMA buffer descriptor and access macros
 208  */
 209 struct slgt_desc
 210 {
 211         unsigned short count;
 212         unsigned short status;
 213         unsigned int pbuf;  /* physical address of data buffer */
 214         unsigned int next;  /* physical address of next descriptor */
 215
 216         /* driver book keeping */
 217         char *buf;          /* virtual  address of data buffer */
 218         unsigned int pdesc; /* physical address of this descriptor */
 219         dma_addr_t buf_dma_addr;
 220 };
 221
 222 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 223 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 224 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 225 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 226 #define desc_count(a)      (le16_to_cpu((a).count))
 227 #define desc_status(a)     (le16_to_cpu((a).status))
 228 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 229 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 230 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 231 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 232 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 233
 234 struct _input_signal_events {
 235         int ri_up;
 236         int ri_down;
 237         int dsr_up;
 238         int dsr_down;
 239         int dcd_up;
 240         int dcd_down;
 241         int cts_up;
 242         int cts_down;
 243 };
 244
 245 /*
 246  * device instance data structure
 247  */
 248 struct slgt_info {
 249         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 250
 251         struct slgt_info *next_device;  /* device list link */
 252
 253         int magic;
 254         int flags;
 255
 256         char device_name[25];
 257         struct pci_dev *pdev;
 258
 259         int port_count;  /* count of ports on adapter */
 260         int adapter_num; /* adapter instance number */
 261         int port_num;    /* port instance number */
 262
 263         /* array of pointers to port contexts on this adapter */
 264         struct slgt_info *port_array[SLGT_MAX_PORTS];
 265
 266         int                     count;          /* count of opens */
 267         int                     line;           /* tty line instance number */
 268         unsigned short          close_delay;
 269         unsigned short          closing_wait;   /* time to wait before closing */
 270
 271         struct mgsl_icount      icount;
 272
 273         struct tty_struct       *tty;
 274         int                     timeout;
 275         int                     x_char;         /* xon/xoff character */
 276         int                     blocked_open;   /* # of blocked opens */
 277         unsigned int            read_status_mask;
 278         unsigned int            ignore_status_mask;
 279
 280         wait_queue_head_t       open_wait;
 281         wait_queue_head_t       close_wait;
 282
 283         wait_queue_head_t       status_event_wait_q;
 284         wait_queue_head_t       event_wait_q;
 285         struct timer_list       tx_timer;
 286         struct timer_list       rx_timer;
 287
 288         unsigned int            gpio_present;
 289         struct cond_wait        *gpio_wait_q;
 290
 291         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 292
 293         struct work_struct task;
 294         u32 pending_bh;
 295         int bh_requested;
 296         int bh_running;
 297
 298         int isr_overflow;
 299         int irq_requested;      /* nonzero if IRQ requested */
 300         int irq_occurred;       /* for diagnostics use */
 301
 302         /* device configuration */
 303
 304         unsigned int bus_type;
 305         unsigned int irq_level;
 306         unsigned long irq_flags;
 307
 308         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 309         u32 phys_reg_addr;
 310         int reg_addr_requested;
 311
 312         MGSL_PARAMS params;       /* communications parameters */
 313         u32 idle_mode;
 314         u32 max_frame_size;       /* as set by device config */
 315
 316         unsigned int raw_rx_size;
 317         unsigned int if_mode;
 318
 319         /* device status */
 320
 321         int rx_enabled;
 322         int rx_restart;
 323
 324         int tx_enabled;
 325         int tx_active;
 326
 327         unsigned char signals;    /* serial signal states */
 328         int init_error;  /* initialization error */
 329
 330         unsigned char *tx_buf;
 331         int tx_count;
 332
 333         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 334         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 335         BOOLEAN drop_rts_on_tx_done;
 336         struct  _input_signal_events    input_signal_events;
 337
 338         int dcd_chkcount;       /* check counts to prevent */
 339         int cts_chkcount;       /* too many IRQs if a signal */
 340         int dsr_chkcount;       /* is floating */
 341         int ri_chkcount;
 342
 343         char *bufs;             /* virtual address of DMA buffer lists */
 344         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 345
 346         unsigned int rbuf_count;
 347         struct slgt_desc *rbufs;
 348         unsigned int rbuf_current;
 349         unsigned int rbuf_index;
 350
 351         unsigned int tbuf_count;
 352         struct slgt_desc *tbufs;
 353         unsigned int tbuf_current;
 354         unsigned int tbuf_start;
 355
 356         unsigned char *tmp_rbuf;
 357         unsigned int tmp_rbuf_count;
 358
 359         /* SPPP/Cisco HDLC device parts */
 360
 361         int netcount;
 362         int dosyncppp;
 363         spinlock_t netlock;
 364 #if SYNCLINK_GENERIC_HDLC
 365         struct net_device *netdev;
 366 #endif
 367
 368 };
 369
 370 static MGSL_PARAMS default_params = {
 371         .mode            = MGSL_MODE_HDLC,
 372         .loopback        = 0,
 373         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 374         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 375         .clock_speed     = 0,
 376         .addr_filter     = 0xff,
 377         .crc_type        = HDLC_CRC_16_CCITT,
 378         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 379         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 380         .data_rate       = 9600,
 381         .data_bits       = 8,
 382         .stop_bits       = 1,
 383         .parity          = ASYNC_PARITY_NONE
 384 };
 385
 386
 387 #define BH_RECEIVE  1
 388 #define BH_TRANSMIT 2
 389 #define BH_STATUS   4
 390 #define IO_PIN_SHUTDOWN_LIMIT 100
 391
 392 #define DMABUFSIZE 256
 393 #define DESC_LIST_SIZE 4096
 394
 395 #define MASK_PARITY  BIT1
 396 #define MASK_FRAMING BIT0
 397 #define MASK_BREAK   BIT14
 398 #define MASK_OVERRUN BIT4
 399
 400 #define GSR   0x00 /* global status */
 401 #define JCR   0x04 /* JTAG control */
 402 #define IODR  0x08 /* GPIO direction */
 403 #define IOER  0x0c /* GPIO interrupt enable */
 404 #define IOVR  0x10 /* GPIO value */
 405 #define IOSR  0x14 /* GPIO interrupt status */
 406 #define TDR   0x80 /* tx data */
 407 #define RDR   0x80 /* rx data */
 408 #define TCR   0x82 /* tx control */
 409 #define TIR   0x84 /* tx idle */
 410 #define TPR   0x85 /* tx preamble */
 411 #define RCR   0x86 /* rx control */
 412 #define VCR   0x88 /* V.24 control */
 413 #define CCR   0x89 /* clock control */
 414 #define BDR   0x8a /* baud divisor */
 415 #define SCR   0x8c /* serial control */
 416 #define SSR   0x8e /* serial status */
 417 #define RDCSR 0x90 /* rx DMA control/status */
 418 #define TDCSR 0x94 /* tx DMA control/status */
 419 #define RDDAR 0x98 /* rx DMA descriptor address */
 420 #define TDDAR 0x9c /* tx DMA descriptor address */
 421
 422 #define RXIDLE      BIT14
 423 #define RXBREAK     BIT14
 424 #define IRQ_TXDATA  BIT13
 425 #define IRQ_TXIDLE  BIT12
 426 #define IRQ_TXUNDER BIT11 /* HDLC */
 427 #define IRQ_RXDATA  BIT10
 428 #define IRQ_RXIDLE  BIT9  /* HDLC */
 429 #define IRQ_RXBREAK BIT9  /* async */
 430 #define IRQ_RXOVER  BIT8
 431 #define IRQ_DSR     BIT7
 432 #define IRQ_CTS     BIT6
 433 #define IRQ_DCD     BIT5
 434 #define IRQ_RI      BIT4
 435 #define IRQ_ALL     0x3ff0
 436 #define IRQ_MASTER  BIT0
 437
 438 #define slgt_irq_on(info, mask) \
 439         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 440 #define slgt_irq_off(info, mask) \
 441         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 442
 443 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 444 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 445 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 446 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 447 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 448 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 449
 450 static void  msc_set_vcr(struct slgt_info *info);
 451
 452 static int  startup(struct slgt_info *info);
 453 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 454 static void shutdown(struct slgt_info *info);
 455 static void program_hw(struct slgt_info *info);
 456 static void change_params(struct slgt_info *info);
 457
 458 static int  register_test(struct slgt_info *info);
 459 static int  irq_test(struct slgt_info *info);
 460 static int  loopback_test(struct slgt_info *info);
 461 static int  adapter_test(struct slgt_info *info);
 462
 463 static void reset_adapter(struct slgt_info *info);
 464 static void reset_port(struct slgt_info *info);
 465 static void async_mode(struct slgt_info *info);
 466 static void sync_mode(struct slgt_info *info);
 467
 468 static void rx_stop(struct slgt_info *info);
 469 static void rx_start(struct slgt_info *info);
 470 static void reset_rbufs(struct slgt_info *info);
 471 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 472 static void rdma_reset(struct slgt_info *info);
 473 static int  rx_get_frame(struct slgt_info *info);
 474 static int  rx_get_buf(struct slgt_info *info);
 475
 476 static void tx_start(struct slgt_info *info);
 477 static void tx_stop(struct slgt_info *info);
 478 static void tx_set_idle(struct slgt_info *info);
 479 static unsigned int free_tbuf_count(struct slgt_info *info);
 480 static void reset_tbufs(struct slgt_info *info);
 481 static void tdma_reset(struct slgt_info *info);
 482 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 483
 484 static void get_signals(struct slgt_info *info);
 485 static void set_signals(struct slgt_info *info);
 486 static void enable_loopback(struct slgt_info *info);
 487 static void set_rate(struct slgt_info *info, u32 data_rate);
 488
 489 static int  bh_action(struct slgt_info *info);
 490 static void bh_handler(struct work_struct *work);
 491 static void bh_transmit(struct slgt_info *info);
 492 static void isr_serial(struct slgt_info *info);
 493 static void isr_rdma(struct slgt_info *info);
 494 static void isr_txeom(struct slgt_info *info, unsigned short status);
 495 static void isr_tdma(struct slgt_info *info);
 496 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
 497
 498 static int  alloc_dma_bufs(struct slgt_info *info);
 499 static void free_dma_bufs(struct slgt_info *info);
 500 static int  alloc_desc(struct slgt_info *info);
 501 static void free_desc(struct slgt_info *info);
 502 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 503 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 504
 505 static int  alloc_tmp_rbuf(struct slgt_info *info);
 506 static void free_tmp_rbuf(struct slgt_info *info);
 507
 508 static void tx_timeout(unsigned long context);
 509 static void rx_timeout(unsigned long context);
 510
 511 /*
 512  * ioctl handlers
 513  */
 514 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 515 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 516 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 517 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 518 static int  set_txidle(struct slgt_info *info, int idle_mode);
 519 static int  tx_enable(struct slgt_info *info, int enable);
 520 static int  tx_abort(struct slgt_info *info);
 521 static int  rx_enable(struct slgt_info *info, int enable);
 522 static int  modem_input_wait(struct slgt_info *info,int arg);
 523 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 524 static int  tiocmget(struct tty_struct *tty, struct file *file);
 525 static int  tiocmset(struct tty_struct *tty, struct file *file,
 526                      unsigned int set, unsigned int clear);
 527 static void set_break(struct tty_struct *tty, int break_state);
 528 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 529 static int  set_interface(struct slgt_info *info, int if_mode);
 530 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 531 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 532 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 533
 534 /*
 535  * driver functions
 536  */
 537 static void add_device(struct slgt_info *info);
 538 static void device_init(int adapter_num, struct pci_dev *pdev);
 539 static int  claim_resources(struct slgt_info *info);
 540 static void release_resources(struct slgt_info *info);
 541
 542 /*
 543  * DEBUG OUTPUT CODE
 544  */
 545 #ifndef DBGINFO
 546 #define DBGINFO(fmt)
 547 #endif
 548 #ifndef DBGERR
 549 #define DBGERR(fmt)
 550 #endif
 551 #ifndef DBGBH
 552 #define DBGBH(fmt)
 553 #endif
 554 #ifndef DBGISR
 555 #define DBGISR(fmt)
 556 #endif
 557
 558 #ifdef DBGDATA
 559 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 560 {
 561         int i;
 562         int linecount;
 563         printk("%s %s data:\n",info->device_name, label);
 564         while(count) {
 565                 linecount = (count > 16) ? 16 : count;
 566                 for(i=0; i < linecount; i++)
 567                         printk("%02X ",(unsigned char)data[i]);
 568                 for(;i<17;i++)
 569                         printk("   ");
 570                 for(i=0;i<linecount;i++) {
 571                         if (data[i]>=040 && data[i]<=0176)
 572                                 printk("%c",data[i]);
 573                         else
 574                                 printk(".");
 575                 }
 576                 printk("\n");
 577                 data  += linecount;
 578                 count -= linecount;
 579         }
 580 }
 581 #else
 582 #define DBGDATA(info, buf, size, label)
 583 #endif
 584
 585 #ifdef DBGTBUF
 586 static void dump_tbufs(struct slgt_info *info)
 587 {
 588         int i;
 589         printk("tbuf_current=%d\n", info->tbuf_current);
 590         for (i=0 ; i < info->tbuf_count ; i++) {
 591                 printk("%d: count=%04X status=%04X\n",
 592                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 593         }
 594 }
 595 #else
 596 #define DBGTBUF(info)
 597 #endif
 598
 599 #ifdef DBGRBUF
 600 static void dump_rbufs(struct slgt_info *info)
 601 {
 602         int i;
 603         printk("rbuf_current=%d\n", info->rbuf_current);
 604         for (i=0 ; i < info->rbuf_count ; i++) {
 605                 printk("%d: count=%04X status=%04X\n",
 606                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 607         }
 608 }
 609 #else
 610 #define DBGRBUF(info)
 611 #endif
 612
 613 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 614 {
 615 #ifdef SANITY_CHECK
 616         if (!info) {
 617                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 618                 return 1;
 619         }
 620         if (info->magic != MGSL_MAGIC) {
 621                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 622                 return 1;
 623         }
 624 #else
 625         if (!info)
 626                 return 1;
 627 #endif
 628         return 0;
 629 }
 630
 631 /**
 632  * line discipline callback wrappers
 633  *
 634  * The wrappers maintain line discipline references
 635  * while calling into the line discipline.
 636  *
 637  * ldisc_receive_buf  - pass receive data to line discipline
 638  */
 639 static void ldisc_receive_buf(struct tty_struct *tty,
 640                               const __u8 *data, char *flags, int count)
 641 {
 642         struct tty_ldisc *ld;
 643         if (!tty)
 644                 return;
 645         ld = tty_ldisc_ref(tty);
 646         if (ld) {
 647                 if (ld->receive_buf)
 648                         ld->receive_buf(tty, data, flags, count);
 649                 tty_ldisc_deref(ld);
 650         }
 651 }
 652
 653 /* tty callbacks */
 654
 655 static int open(struct tty_struct *tty, struct file *filp)
 656 {
 657         struct slgt_info *info;
 658         int retval, line;
 659         unsigned long flags;
 660
 661         line = tty->index;
 662         if ((line < 0) || (line >= slgt_device_count)) {
 663                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 664                 return -ENODEV;
 665         }
 666
 667         info = slgt_device_list;
 668         while(info && info->line != line)
 669                 info = info->next_device;
 670         if (sanity_check(info, tty->name, "open"))
 671                 return -ENODEV;
 672         if (info->init_error) {
 673                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 674                 return -ENODEV;
 675         }
 676
 677         tty->driver_data = info;
 678         info->tty = tty;
 679
 680         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 681
 682         /* If port is closing, signal caller to try again */
 683         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 684                 if (info->flags & ASYNC_CLOSING)
 685                         interruptible_sleep_on(&info->close_wait);
 686                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 687                         -EAGAIN : -ERESTARTSYS);
 688                 goto cleanup;
 689         }
 690
 691         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 692
 693         spin_lock_irqsave(&info->netlock, flags);
 694         if (info->netcount) {
 695                 retval = -EBUSY;
 696                 spin_unlock_irqrestore(&info->netlock, flags);
 697                 goto cleanup;
 698         }
 699         info->count++;
 700         spin_unlock_irqrestore(&info->netlock, flags);
 701
 702         if (info->count == 1) {
 703                 /* 1st open on this device, init hardware */
 704                 retval = startup(info);
 705                 if (retval < 0)
 706                         goto cleanup;
 707         }
 708
 709         retval = block_til_ready(tty, filp, info);
 710         if (retval) {
 711                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 712                 goto cleanup;
 713         }
 714
 715         retval = 0;
 716
 717 cleanup:
 718         if (retval) {
 719                 if (tty->count == 1)
 720                         info->tty = NULL; /* tty layer will release tty struct */
 721                 if(info->count)
 722                         info->count--;
 723         }
 724
 725         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 726         return retval;
 727 }
 728
 729 static void close(struct tty_struct *tty, struct file *filp)
 730 {
 731         struct slgt_info *info = tty->driver_data;
 732
 733         if (sanity_check(info, tty->name, "close"))
 734                 return;
 735         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 736
 737         if (!info->count)
 738                 return;
 739
 740         if (tty_hung_up_p(filp))
 741                 goto cleanup;
 742
 743         if ((tty->count == 1) && (info->count != 1)) {
 744                 /*
 745                  * tty->count is 1 and the tty structure will be freed.
 746                  * info->count should be one in this case.
 747                  * if it's not, correct it so that the port is shutdown.
 748                  */
 749                 DBGERR(("%s close: bad refcount; tty->count=1, "
 750                        "info->count=%d\n", info->device_name, info->count));
 751                 info->count = 1;
 752         }
 753
 754         info->count--;
 755
 756         /* if at least one open remaining, leave hardware active */
 757         if (info->count)
 758                 goto cleanup;
 759
 760         info->flags |= ASYNC_CLOSING;
 761
 762         /* set tty->closing to notify line discipline to
 763          * only process XON/XOFF characters. Only the N_TTY
 764          * discipline appears to use this (ppp does not).
 765          */
 766         tty->closing = 1;
 767
 768         /* wait for transmit data to clear all layers */
 769
 770         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 771                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 772                 tty_wait_until_sent(tty, info->closing_wait);
 773         }
 774
 775         if (info->flags & ASYNC_INITIALIZED)
 776                 wait_until_sent(tty, info->timeout);
 777         if (tty->driver->flush_buffer)
 778                 tty->driver->flush_buffer(tty);
 779         tty_ldisc_flush(tty);
 780
 781         shutdown(info);
 782
 783         tty->closing = 0;
 784         info->tty = NULL;
 785
 786         if (info->blocked_open) {
 787                 if (info->close_delay) {
 788                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 789                 }
 790                 wake_up_interruptible(&info->open_wait);
 791         }
 792
 793         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 794
 795         wake_up_interruptible(&info->close_wait);
 796
 797 cleanup:
 798         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 799 }
 800
 801 static void hangup(struct tty_struct *tty)
 802 {
 803         struct slgt_info *info = tty->driver_data;
 804
 805         if (sanity_check(info, tty->name, "hangup"))
 806                 return;
 807         DBGINFO(("%s hangup\n", info->device_name));
 808
 809         flush_buffer(tty);
 810         shutdown(info);
 811
 812         info->count = 0;
 813         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 814         info->tty = NULL;
 815
 816         wake_up_interruptible(&info->open_wait);
 817 }
 818
 819 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 820 {
 821         struct slgt_info *info = tty->driver_data;
 822         unsigned long flags;
 823
 824         DBGINFO(("%s set_termios\n", tty->driver->name));
 825
 826         /* just return if nothing has changed */
 827         if ((tty->termios->c_cflag == old_termios->c_cflag)
 828             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 829                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 830                 return;
 831
 832         change_params(info);
 833
 834         /* Handle transition to B0 status */
 835         if (old_termios->c_cflag & CBAUD &&
 836             !(tty->termios->c_cflag & CBAUD)) {
 837                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 838                 spin_lock_irqsave(&info->lock,flags);
 839                 set_signals(info);
 840                 spin_unlock_irqrestore(&info->lock,flags);
 841         }
 842
 843         /* Handle transition away from B0 status */
 844         if (!(old_termios->c_cflag & CBAUD) &&
 845             tty->termios->c_cflag & CBAUD) {
 846                 info->signals |= SerialSignal_DTR;
 847                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 848                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 849                         info->signals |= SerialSignal_RTS;
 850                 }
 851                 spin_lock_irqsave(&info->lock,flags);
 852                 set_signals(info);
 853                 spin_unlock_irqrestore(&info->lock,flags);
 854         }
 855
 856         /* Handle turning off CRTSCTS */
 857         if (old_termios->c_cflag & CRTSCTS &&
 858             !(tty->termios->c_cflag & CRTSCTS)) {
 859                 tty->hw_stopped = 0;
 860                 tx_release(tty);
 861         }
 862 }
 863
 864 static int write(struct tty_struct *tty,
 865                  const unsigned char *buf, int count)
 866 {
 867         int ret = 0;
 868         struct slgt_info *info = tty->driver_data;
 869         unsigned long flags;
 870
 871         if (sanity_check(info, tty->name, "write"))
 872                 goto cleanup;
 873         DBGINFO(("%s write count=%d\n", info->device_name, count));
 874
 875         if (!info->tx_buf)
 876                 goto cleanup;
 877
 878         if (count > info->max_frame_size) {
 879                 ret = -EIO;
 880                 goto cleanup;
 881         }
 882
 883         if (!count)
 884                 goto cleanup;
 885
 886         if (info->params.mode == MGSL_MODE_RAW ||
 887             info->params.mode == MGSL_MODE_MONOSYNC ||
 888             info->params.mode == MGSL_MODE_BISYNC) {
 889                 unsigned int bufs_needed = (count/DMABUFSIZE);
 890                 unsigned int bufs_free = free_tbuf_count(info);
 891                 if (count % DMABUFSIZE)
 892                         ++bufs_needed;
 893                 if (bufs_needed > bufs_free)
 894                         goto cleanup;
 895         } else {
 896                 if (info->tx_active)
 897                         goto cleanup;
 898                 if (info->tx_count) {
 899                         /* send accumulated data from send_char() calls */
 900                         /* as frame and wait before accepting more data. */
 901                         tx_load(info, info->tx_buf, info->tx_count);
 902                         goto start;
 903                 }
 904         }
 905
 906         ret = info->tx_count = count;
 907         tx_load(info, buf, count);
 908         goto start;
 909
 910 start:
 911         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 912                 spin_lock_irqsave(&info->lock,flags);
 913                 if (!info->tx_active)
 914                         tx_start(info);
 915                 spin_unlock_irqrestore(&info->lock,flags);
 916         }
 917
 918 cleanup:
 919         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 920         return ret;
 921 }
 922
 923 static void put_char(struct tty_struct *tty, unsigned char ch)
 924 {
 925         struct slgt_info *info = tty->driver_data;
 926         unsigned long flags;
 927
 928         if (sanity_check(info, tty->name, "put_char"))
 929                 return;
 930         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 931         if (!info->tx_buf)
 932                 return;
 933         spin_lock_irqsave(&info->lock,flags);
 934         if (!info->tx_active && (info->tx_count < info->max_frame_size))
 935                 info->tx_buf[info->tx_count++] = ch;
 936         spin_unlock_irqrestore(&info->lock,flags);
 937 }
 938
 939 static void send_xchar(struct tty_struct *tty, char ch)
 940 {
 941         struct slgt_info *info = tty->driver_data;
 942         unsigned long flags;
 943
 944         if (sanity_check(info, tty->name, "send_xchar"))
 945                 return;
 946         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 947         info->x_char = ch;
 948         if (ch) {
 949                 spin_lock_irqsave(&info->lock,flags);
 950                 if (!info->tx_enabled)
 951                         tx_start(info);
 952                 spin_unlock_irqrestore(&info->lock,flags);
 953         }
 954 }
 955
 956 static void wait_until_sent(struct tty_struct *tty, int timeout)
 957 {
 958         struct slgt_info *info = tty->driver_data;
 959         unsigned long orig_jiffies, char_time;
 960
 961         if (!info )
 962                 return;
 963         if (sanity_check(info, tty->name, "wait_until_sent"))
 964                 return;
 965         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 966         if (!(info->flags & ASYNC_INITIALIZED))
 967                 goto exit;
 968
 969         orig_jiffies = jiffies;
 970
 971         /* Set check interval to 1/5 of estimated time to
 972          * send a character, and make it at least 1. The check
 973          * interval should also be less than the timeout.
 974          * Note: use tight timings here to satisfy the NIST-PCTS.
 975          */
 976
 977         if (info->params.data_rate) {
 978                 char_time = info->timeout/(32 * 5);
 979                 if (!char_time)
 980                         char_time++;
 981         } else
 982                 char_time = 1;
 983
 984         if (timeout)
 985                 char_time = min_t(unsigned long, char_time, timeout);
 986
 987         while (info->tx_active) {
 988                 msleep_interruptible(jiffies_to_msecs(char_time));
 989                 if (signal_pending(current))
 990                         break;
 991                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 992                         break;
 993         }
 994
 995 exit:
 996         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 997 }
 998
 999 static int write_room(struct tty_struct *tty)
1000 {
1001         struct slgt_info *info = tty->driver_data;
1002         int ret;
1003
1004         if (sanity_check(info, tty->name, "write_room"))
1005                 return 0;
1006         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1007         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1008         return ret;
1009 }
1010
1011 static void flush_chars(struct tty_struct *tty)
1012 {
1013         struct slgt_info *info = tty->driver_data;
1014         unsigned long flags;
1015
1016         if (sanity_check(info, tty->name, "flush_chars"))
1017                 return;
1018         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1019
1020         if (info->tx_count <= 0 || tty->stopped ||
1021             tty->hw_stopped || !info->tx_buf)
1022                 return;
1023
1024         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1025
1026         spin_lock_irqsave(&info->lock,flags);
1027         if (!info->tx_active && info->tx_count) {
1028                 tx_load(info, info->tx_buf,info->tx_count);
1029                 tx_start(info);
1030         }
1031         spin_unlock_irqrestore(&info->lock,flags);
1032 }
1033
1034 static void flush_buffer(struct tty_struct *tty)
1035 {
1036         struct slgt_info *info = tty->driver_data;
1037         unsigned long flags;
1038
1039         if (sanity_check(info, tty->name, "flush_buffer"))
1040                 return;
1041         DBGINFO(("%s flush_buffer\n", info->device_name));
1042
1043         spin_lock_irqsave(&info->lock,flags);
1044         if (!info->tx_active)
1045                 info->tx_count = 0;
1046         spin_unlock_irqrestore(&info->lock,flags);
1047
1048         tty_wakeup(tty);
1049 }
1050
1051 /*
1052  * throttle (stop) transmitter
1053  */
1054 static void tx_hold(struct tty_struct *tty)
1055 {
1056         struct slgt_info *info = tty->driver_data;
1057         unsigned long flags;
1058
1059         if (sanity_check(info, tty->name, "tx_hold"))
1060                 return;
1061         DBGINFO(("%s tx_hold\n", info->device_name));
1062         spin_lock_irqsave(&info->lock,flags);
1063         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1064                 tx_stop(info);
1065         spin_unlock_irqrestore(&info->lock,flags);
1066 }
1067
1068 /*
1069  * release (start) transmitter
1070  */
1071 static void tx_release(struct tty_struct *tty)
1072 {
1073         struct slgt_info *info = tty->driver_data;
1074         unsigned long flags;
1075
1076         if (sanity_check(info, tty->name, "tx_release"))
1077                 return;
1078         DBGINFO(("%s tx_release\n", info->device_name));
1079         spin_lock_irqsave(&info->lock,flags);
1080         if (!info->tx_active && info->tx_count) {
1081                 tx_load(info, info->tx_buf, info->tx_count);
1082                 tx_start(info);
1083         }
1084         spin_unlock_irqrestore(&info->lock,flags);
1085 }
1086
1087 /*
1088  * Service an IOCTL request
1089  *
1090  * Arguments
1091  *
1092  *      tty     pointer to tty instance data
1093  *      file    pointer to associated file object for device
1094  *      cmd     IOCTL command code
1095  *      arg     command argument/context
1096  *
1097  * Return 0 if success, otherwise error code
1098  */
1099 static int ioctl(struct tty_struct *tty, struct file *file,
1100                  unsigned int cmd, unsigned long arg)
1101 {
1102         struct slgt_info *info = tty->driver_data;
1103         struct mgsl_icount cnow;        /* kernel counter temps */
1104         struct serial_icounter_struct __user *p_cuser;  /* user space */
1105         unsigned long flags;
1106         void __user *argp = (void __user *)arg;
1107
1108         if (sanity_check(info, tty->name, "ioctl"))
1109                 return -ENODEV;
1110         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1111
1112         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1113             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1114                 if (tty->flags & (1 << TTY_IO_ERROR))
1115                     return -EIO;
1116         }
1117
1118         switch (cmd) {
1119         case MGSL_IOCGPARAMS:
1120                 return get_params(info, argp);
1121         case MGSL_IOCSPARAMS:
1122                 return set_params(info, argp);
1123         case MGSL_IOCGTXIDLE:
1124                 return get_txidle(info, argp);
1125         case MGSL_IOCSTXIDLE:
1126                 return set_txidle(info, (int)arg);
1127         case MGSL_IOCTXENABLE:
1128                 return tx_enable(info, (int)arg);
1129         case MGSL_IOCRXENABLE:
1130                 return rx_enable(info, (int)arg);
1131         case MGSL_IOCTXABORT:
1132                 return tx_abort(info);
1133         case MGSL_IOCGSTATS:
1134                 return get_stats(info, argp);
1135         case MGSL_IOCWAITEVENT:
1136                 return wait_mgsl_event(info, argp);
1137         case TIOCMIWAIT:
1138                 return modem_input_wait(info,(int)arg);
1139         case MGSL_IOCGIF:
1140                 return get_interface(info, argp);
1141         case MGSL_IOCSIF:
1142                 return set_interface(info,(int)arg);
1143         case MGSL_IOCSGPIO:
1144                 return set_gpio(info, argp);
1145         case MGSL_IOCGGPIO:
1146                 return get_gpio(info, argp);
1147         case MGSL_IOCWAITGPIO:
1148                 return wait_gpio(info, argp);
1149         case TIOCGICOUNT:
1150                 spin_lock_irqsave(&info->lock,flags);
1151                 cnow = info->icount;
1152                 spin_unlock_irqrestore(&info->lock,flags);
1153                 p_cuser = argp;
1154                 if (put_user(cnow.cts, &p_cuser->cts) ||
1155                     put_user(cnow.dsr, &p_cuser->dsr) ||
1156                     put_user(cnow.rng, &p_cuser->rng) ||
1157                     put_user(cnow.dcd, &p_cuser->dcd) ||
1158                     put_user(cnow.rx, &p_cuser->rx) ||
1159                     put_user(cnow.tx, &p_cuser->tx) ||
1160                     put_user(cnow.frame, &p_cuser->frame) ||
1161                     put_user(cnow.overrun, &p_cuser->overrun) ||
1162                     put_user(cnow.parity, &p_cuser->parity) ||
1163                     put_user(cnow.brk, &p_cuser->brk) ||
1164                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1165                         return -EFAULT;
1166                 return 0;
1167         default:
1168                 return -ENOIOCTLCMD;
1169         }
1170         return 0;
1171 }
1172
1173 /*
1174  * proc fs support
1175  */
1176 static inline int line_info(char *buf, struct slgt_info *info)
1177 {
1178         char stat_buf[30];
1179         int ret;
1180         unsigned long flags;
1181
1182         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1183                       info->device_name, info->phys_reg_addr,
1184                       info->irq_level, info->max_frame_size);
1185
1186         /* output current serial signal states */
1187         spin_lock_irqsave(&info->lock,flags);
1188         get_signals(info);
1189         spin_unlock_irqrestore(&info->lock,flags);
1190
1191         stat_buf[0] = 0;
1192         stat_buf[1] = 0;
1193         if (info->signals & SerialSignal_RTS)
1194                 strcat(stat_buf, "|RTS");
1195         if (info->signals & SerialSignal_CTS)
1196                 strcat(stat_buf, "|CTS");
1197         if (info->signals & SerialSignal_DTR)
1198                 strcat(stat_buf, "|DTR");
1199         if (info->signals & SerialSignal_DSR)
1200                 strcat(stat_buf, "|DSR");
1201         if (info->signals & SerialSignal_DCD)
1202                 strcat(stat_buf, "|CD");
1203         if (info->signals & SerialSignal_RI)
1204                 strcat(stat_buf, "|RI");
1205
1206         if (info->params.mode != MGSL_MODE_ASYNC) {
1207                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1208                                info->icount.txok, info->icount.rxok);
1209                 if (info->icount.txunder)
1210                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1211                 if (info->icount.txabort)
1212                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1213                 if (info->icount.rxshort)
1214                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1215                 if (info->icount.rxlong)
1216                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1217                 if (info->icount.rxover)
1218                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1219                 if (info->icount.rxcrc)
1220                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1221         } else {
1222                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1223                                info->icount.tx, info->icount.rx);
1224                 if (info->icount.frame)
1225                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1226                 if (info->icount.parity)
1227                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1228                 if (info->icount.brk)
1229                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1230                 if (info->icount.overrun)
1231                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1232         }
1233
1234         /* Append serial signal status to end */
1235         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1236
1237         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1238                        info->tx_active,info->bh_requested,info->bh_running,
1239                        info->pending_bh);
1240
1241         return ret;
1242 }
1243
1244 /* Called to print information about devices
1245  */
1246 static int read_proc(char *page, char **start, off_t off, int count,
1247                      int *eof, void *data)
1248 {
1249         int len = 0, l;
1250         off_t   begin = 0;
1251         struct slgt_info *info;
1252
1253         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1254
1255         info = slgt_device_list;
1256         while( info ) {
1257                 l = line_info(page + len, info);
1258                 len += l;
1259                 if (len+begin > off+count)
1260                         goto done;
1261                 if (len+begin < off) {
1262                         begin += len;
1263                         len = 0;
1264                 }
1265                 info = info->next_device;
1266         }
1267
1268         *eof = 1;
1269 done:
1270         if (off >= len+begin)
1271                 return 0;
1272         *start = page + (off-begin);
1273         return ((count < begin+len-off) ? count : begin+len-off);
1274 }
1275
1276 /*
1277  * return count of bytes in transmit buffer
1278  */
1279 static int chars_in_buffer(struct tty_struct *tty)
1280 {
1281         struct slgt_info *info = tty->driver_data;
1282         if (sanity_check(info, tty->name, "chars_in_buffer"))
1283                 return 0;
1284         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1285         return info->tx_count;
1286 }
1287
1288 /*
1289  * signal remote device to throttle send data (our receive data)
1290  */
1291 static void throttle(struct tty_struct * tty)
1292 {
1293         struct slgt_info *info = tty->driver_data;
1294         unsigned long flags;
1295
1296         if (sanity_check(info, tty->name, "throttle"))
1297                 return;
1298         DBGINFO(("%s throttle\n", info->device_name));
1299         if (I_IXOFF(tty))
1300                 send_xchar(tty, STOP_CHAR(tty));
1301         if (tty->termios->c_cflag & CRTSCTS) {
1302                 spin_lock_irqsave(&info->lock,flags);
1303                 info->signals &= ~SerialSignal_RTS;
1304                 set_signals(info);
1305                 spin_unlock_irqrestore(&info->lock,flags);
1306         }
1307 }
1308
1309 /*
1310  * signal remote device to stop throttling send data (our receive data)
1311  */
1312 static void unthrottle(struct tty_struct * tty)
1313 {
1314         struct slgt_info *info = tty->driver_data;
1315         unsigned long flags;
1316
1317         if (sanity_check(info, tty->name, "unthrottle"))
1318                 return;
1319         DBGINFO(("%s unthrottle\n", info->device_name));
1320         if (I_IXOFF(tty)) {
1321                 if (info->x_char)
1322                         info->x_char = 0;
1323                 else
1324                         send_xchar(tty, START_CHAR(tty));
1325         }
1326         if (tty->termios->c_cflag & CRTSCTS) {
1327                 spin_lock_irqsave(&info->lock,flags);
1328                 info->signals |= SerialSignal_RTS;
1329                 set_signals(info);
1330                 spin_unlock_irqrestore(&info->lock,flags);
1331         }
1332 }
1333
1334 /*
1335  * set or clear transmit break condition
1336  * break_state  -1=set break condition, 0=clear
1337  */
1338 static void set_break(struct tty_struct *tty, int break_state)
1339 {
1340         struct slgt_info *info = tty->driver_data;
1341         unsigned short value;
1342         unsigned long flags;
1343
1344         if (sanity_check(info, tty->name, "set_break"))
1345                 return;
1346         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1347
1348         spin_lock_irqsave(&info->lock,flags);
1349         value = rd_reg16(info, TCR);
1350         if (break_state == -1)
1351                 value |= BIT6;
1352         else
1353                 value &= ~BIT6;
1354         wr_reg16(info, TCR, value);
1355         spin_unlock_irqrestore(&info->lock,flags);
1356 }
1357
1358 #if SYNCLINK_GENERIC_HDLC
1359
1360 /**
1361  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1362  * set encoding and frame check sequence (FCS) options
1363  *
1364  * dev       pointer to network device structure
1365  * encoding  serial encoding setting
1366  * parity    FCS setting
1367  *
1368  * returns 0 if success, otherwise error code
1369  */
1370 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1371                           unsigned short parity)
1372 {
1373         struct slgt_info *info = dev_to_port(dev);
1374         unsigned char  new_encoding;
1375         unsigned short new_crctype;
1376
1377         /* return error if TTY interface open */
1378         if (info->count)
1379                 return -EBUSY;
1380
1381         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1382
1383         switch (encoding)
1384         {
1385         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1386         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1387         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1388         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1389         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1390         default: return -EINVAL;
1391         }
1392
1393         switch (parity)
1394         {
1395         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1396         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1397         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1398         default: return -EINVAL;
1399         }
1400
1401         info->params.encoding = new_encoding;
1402         info->params.crc_type = new_crctype;
1403
1404         /* if network interface up, reprogram hardware */
1405         if (info->netcount)
1406                 program_hw(info);
1407
1408         return 0;
1409 }
1410
1411 /**
1412  * called by generic HDLC layer to send frame
1413  *
1414  * skb  socket buffer containing HDLC frame
1415  * dev  pointer to network device structure
1416  *
1417  * returns 0 if success, otherwise error code
1418  */
1419 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1420 {
1421         struct slgt_info *info = dev_to_port(dev);
1422         struct net_device_stats *stats = hdlc_stats(dev);
1423         unsigned long flags;
1424
1425         DBGINFO(("%s hdlc_xmit\n", dev->name));
1426
1427         /* stop sending until this frame completes */
1428         netif_stop_queue(dev);
1429
1430         /* copy data to device buffers */
1431         info->tx_count = skb->len;
1432         tx_load(info, skb->data, skb->len);
1433
1434         /* update network statistics */
1435         stats->tx_packets++;
1436         stats->tx_bytes += skb->len;
1437
1438         /* done with socket buffer, so free it */
1439         dev_kfree_skb(skb);
1440
1441         /* save start time for transmit timeout detection */
1442         dev->trans_start = jiffies;
1443
1444         /* start hardware transmitter if necessary */
1445         spin_lock_irqsave(&info->lock,flags);
1446         if (!info->tx_active)
1447                 tx_start(info);
1448         spin_unlock_irqrestore(&info->lock,flags);
1449
1450         return 0;
1451 }
1452
1453 /**
1454  * called by network layer when interface enabled
1455  * claim resources and initialize hardware
1456  *
1457  * dev  pointer to network device structure
1458  *
1459  * returns 0 if success, otherwise error code
1460  */
1461 static int hdlcdev_open(struct net_device *dev)
1462 {
1463         struct slgt_info *info = dev_to_port(dev);
1464         int rc;
1465         unsigned long flags;
1466
1467         DBGINFO(("%s hdlcdev_open\n", dev->name));
1468
1469         /* generic HDLC layer open processing */
1470         if ((rc = hdlc_open(dev)))
1471                 return rc;
1472
1473         /* arbitrate between network and tty opens */
1474         spin_lock_irqsave(&info->netlock, flags);
1475         if (info->count != 0 || info->netcount != 0) {
1476                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1477                 spin_unlock_irqrestore(&info->netlock, flags);
1478                 return -EBUSY;
1479         }
1480         info->netcount=1;
1481         spin_unlock_irqrestore(&info->netlock, flags);
1482
1483         /* claim resources and init adapter */
1484         if ((rc = startup(info)) != 0) {
1485                 spin_lock_irqsave(&info->netlock, flags);
1486                 info->netcount=0;
1487                 spin_unlock_irqrestore(&info->netlock, flags);
1488                 return rc;
1489         }
1490
1491         /* assert DTR and RTS, apply hardware settings */
1492         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1493         program_hw(info);
1494
1495         /* enable network layer transmit */
1496         dev->trans_start = jiffies;
1497         netif_start_queue(dev);
1498
1499         /* inform generic HDLC layer of current DCD status */
1500         spin_lock_irqsave(&info->lock, flags);
1501         get_signals(info);
1502         spin_unlock_irqrestore(&info->lock, flags);
1503         if (info->signals & SerialSignal_DCD)
1504                 netif_carrier_on(dev);
1505         else
1506                 netif_carrier_off(dev);
1507         return 0;
1508 }
1509
1510 /**
1511  * called by network layer when interface is disabled
1512  * shutdown hardware and release resources
1513  *
1514  * dev  pointer to network device structure
1515  *
1516  * returns 0 if success, otherwise error code
1517  */
1518 static int hdlcdev_close(struct net_device *dev)
1519 {
1520         struct slgt_info *info = dev_to_port(dev);
1521         unsigned long flags;
1522
1523         DBGINFO(("%s hdlcdev_close\n", dev->name));
1524
1525         netif_stop_queue(dev);
1526
1527         /* shutdown adapter and release resources */
1528         shutdown(info);
1529
1530         hdlc_close(dev);
1531
1532         spin_lock_irqsave(&info->netlock, flags);
1533         info->netcount=0;
1534         spin_unlock_irqrestore(&info->netlock, flags);
1535
1536         return 0;
1537 }
1538
1539 /**
1540  * called by network layer to process IOCTL call to network device
1541  *
1542  * dev  pointer to network device structure
1543  * ifr  pointer to network interface request structure
1544  * cmd  IOCTL command code
1545  *
1546  * returns 0 if success, otherwise error code
1547  */
1548 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1549 {
1550         const size_t size = sizeof(sync_serial_settings);
1551         sync_serial_settings new_line;
1552         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1553         struct slgt_info *info = dev_to_port(dev);
1554         unsigned int flags;
1555
1556         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1557
1558         /* return error if TTY interface open */
1559         if (info->count)
1560                 return -EBUSY;
1561
1562         if (cmd != SIOCWANDEV)
1563                 return hdlc_ioctl(dev, ifr, cmd);
1564
1565         switch(ifr->ifr_settings.type) {
1566         case IF_GET_IFACE: /* return current sync_serial_settings */
1567
1568                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1569                 if (ifr->ifr_settings.size < size) {
1570                         ifr->ifr_settings.size = size; /* data size wanted */
1571                         return -ENOBUFS;
1572                 }
1573
1574                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1575                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1576                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1577                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1578
1579                 switch (flags){
1580                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1581                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1582                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1583                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1584                 default: new_line.clock_type = CLOCK_DEFAULT;
1585                 }
1586
1587                 new_line.clock_rate = info->params.clock_speed;
1588                 new_line.loopback   = info->params.loopback ? 1:0;
1589
1590                 if (copy_to_user(line, &new_line, size))
1591                         return -EFAULT;
1592                 return 0;
1593
1594         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1595
1596                 if(!capable(CAP_NET_ADMIN))
1597                         return -EPERM;
1598                 if (copy_from_user(&new_line, line, size))
1599                         return -EFAULT;
1600
1601                 switch (new_line.clock_type)
1602                 {
1603                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1604                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1605                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1606                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1607                 case CLOCK_DEFAULT:  flags = info->params.flags &
1608                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1609                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1610                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1611                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1612                 default: return -EINVAL;
1613                 }
1614
1615                 if (new_line.loopback != 0 && new_line.loopback != 1)
1616                         return -EINVAL;
1617
1618                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1619                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1620                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1621                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1622                 info->params.flags |= flags;
1623
1624                 info->params.loopback = new_line.loopback;
1625
1626                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1627                         info->params.clock_speed = new_line.clock_rate;
1628                 else
1629                         info->params.clock_speed = 0;
1630
1631                 /* if network interface up, reprogram hardware */
1632                 if (info->netcount)
1633                         program_hw(info);
1634                 return 0;
1635
1636         default:
1637                 return hdlc_ioctl(dev, ifr, cmd);
1638         }
1639 }
1640
1641 /**
1642  * called by network layer when transmit timeout is detected
1643  *
1644  * dev  pointer to network device structure
1645  */
1646 static void hdlcdev_tx_timeout(struct net_device *dev)
1647 {
1648         struct slgt_info *info = dev_to_port(dev);
1649         struct net_device_stats *stats = hdlc_stats(dev);
1650         unsigned long flags;
1651
1652         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1653
1654         stats->tx_errors++;
1655         stats->tx_aborted_errors++;
1656
1657         spin_lock_irqsave(&info->lock,flags);
1658         tx_stop(info);
1659         spin_unlock_irqrestore(&info->lock,flags);
1660
1661         netif_wake_queue(dev);
1662 }
1663
1664 /**
1665  * called by device driver when transmit completes
1666  * reenable network layer transmit if stopped
1667  *
1668  * info  pointer to device instance information
1669  */
1670 static void hdlcdev_tx_done(struct slgt_info *info)
1671 {
1672         if (netif_queue_stopped(info->netdev))
1673                 netif_wake_queue(info->netdev);
1674 }
1675
1676 /**
1677  * called by device driver when frame received
1678  * pass frame to network layer
1679  *
1680  * info  pointer to device instance information
1681  * buf   pointer to buffer contianing frame data
1682  * size  count of data bytes in buf
1683  */
1684 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1685 {
1686         struct sk_buff *skb = dev_alloc_skb(size);
1687         struct net_device *dev = info->netdev;
1688         struct net_device_stats *stats = hdlc_stats(dev);
1689
1690         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1691
1692         if (skb == NULL) {
1693                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1694                 stats->rx_dropped++;
1695                 return;
1696         }
1697
1698         memcpy(skb_put(skb, size),buf,size);
1699
1700         skb->protocol = hdlc_type_trans(skb, info->netdev);
1701
1702         stats->rx_packets++;
1703         stats->rx_bytes += size;
1704
1705         netif_rx(skb);
1706
1707         info->netdev->last_rx = jiffies;
1708 }
1709
1710 /**
1711  * called by device driver when adding device instance
1712  * do generic HDLC initialization
1713  *
1714  * info  pointer to device instance information
1715  *
1716  * returns 0 if success, otherwise error code
1717  */
1718 static int hdlcdev_init(struct slgt_info *info)
1719 {
1720         int rc;
1721         struct net_device *dev;
1722         hdlc_device *hdlc;
1723
1724         /* allocate and initialize network and HDLC layer objects */
1725
1726         if (!(dev = alloc_hdlcdev(info))) {
1727                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1728                 return -ENOMEM;
1729         }
1730
1731         /* for network layer reporting purposes only */
1732         dev->mem_start = info->phys_reg_addr;
1733         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1734         dev->irq       = info->irq_level;
1735
1736         /* network layer callbacks and settings */
1737         dev->do_ioctl       = hdlcdev_ioctl;
1738         dev->open           = hdlcdev_open;
1739         dev->stop           = hdlcdev_close;
1740         dev->tx_timeout     = hdlcdev_tx_timeout;
1741         dev->watchdog_timeo = 10*HZ;
1742         dev->tx_queue_len   = 50;
1743
1744         /* generic HDLC layer callbacks and settings */
1745         hdlc         = dev_to_hdlc(dev);
1746         hdlc->attach = hdlcdev_attach;
1747         hdlc->xmit   = hdlcdev_xmit;
1748
1749         /* register objects with HDLC layer */
1750         if ((rc = register_hdlc_device(dev))) {
1751                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1752                 free_netdev(dev);
1753                 return rc;
1754         }
1755
1756         info->netdev = dev;
1757         return 0;
1758 }
1759
1760 /**
1761  * called by device driver when removing device instance
1762  * do generic HDLC cleanup
1763  *
1764  * info  pointer to device instance information
1765  */
1766 static void hdlcdev_exit(struct slgt_info *info)
1767 {
1768         unregister_hdlc_device(info->netdev);
1769         free_netdev(info->netdev);
1770         info->netdev = NULL;
1771 }
1772
1773 #endif /* ifdef CONFIG_HDLC */
1774
1775 /*
1776  * get async data from rx DMA buffers
1777  */
1778 static void rx_async(struct slgt_info *info)
1779 {
1780         struct tty_struct *tty = info->tty;
1781         struct mgsl_icount *icount = &info->icount;
1782         unsigned int start, end;
1783         unsigned char *p;
1784         unsigned char status;
1785         struct slgt_desc *bufs = info->rbufs;
1786         int i, count;
1787         int chars = 0;
1788         int stat;
1789         unsigned char ch;
1790
1791         start = end = info->rbuf_current;
1792
1793         while(desc_complete(bufs[end])) {
1794                 count = desc_count(bufs[end]) - info->rbuf_index;
1795                 p     = bufs[end].buf + info->rbuf_index;
1796
1797                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1798                 DBGDATA(info, p, count, "rx");
1799
1800                 for(i=0 ; i < count; i+=2, p+=2) {
1801                         ch = *p;
1802                         icount->rx++;
1803
1804                         stat = 0;
1805
1806                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1807                                 if (status & BIT1)
1808                                         icount->parity++;
1809                                 else if (status & BIT0)
1810                                         icount->frame++;
1811                                 /* discard char if tty control flags say so */
1812                                 if (status & info->ignore_status_mask)
1813                                         continue;
1814                                 if (status & BIT1)
1815                                         stat = TTY_PARITY;
1816                                 else if (status & BIT0)
1817                                         stat = TTY_FRAME;
1818                         }
1819                         if (tty) {
1820                                 tty_insert_flip_char(tty, ch, stat);
1821                                 chars++;
1822                         }
1823                 }
1824
1825                 if (i < count) {
1826                         /* receive buffer not completed */
1827                         info->rbuf_index += i;
1828                         info->rx_timer.expires = jiffies + 1;
1829                         add_timer(&info->rx_timer);
1830                         break;
1831                 }
1832
1833                 info->rbuf_index = 0;
1834                 free_rbufs(info, end, end);
1835
1836                 if (++end == info->rbuf_count)
1837                         end = 0;
1838
1839                 /* if entire list searched then no frame available */
1840                 if (end == start)
1841                         break;
1842         }
1843
1844         if (tty && chars)
1845                 tty_flip_buffer_push(tty);
1846 }
1847
1848 /*
1849  * return next bottom half action to perform
1850  */
1851 static int bh_action(struct slgt_info *info)
1852 {
1853         unsigned long flags;
1854         int rc;
1855
1856         spin_lock_irqsave(&info->lock,flags);
1857
1858         if (info->pending_bh & BH_RECEIVE) {
1859                 info->pending_bh &= ~BH_RECEIVE;
1860                 rc = BH_RECEIVE;
1861         } else if (info->pending_bh & BH_TRANSMIT) {
1862                 info->pending_bh &= ~BH_TRANSMIT;
1863                 rc = BH_TRANSMIT;
1864         } else if (info->pending_bh & BH_STATUS) {
1865                 info->pending_bh &= ~BH_STATUS;
1866                 rc = BH_STATUS;
1867         } else {
1868                 /* Mark BH routine as complete */
1869                 info->bh_running   = 0;
1870                 info->bh_requested = 0;
1871                 rc = 0;
1872         }
1873
1874         spin_unlock_irqrestore(&info->lock,flags);
1875
1876         return rc;
1877 }
1878
1879 /*
1880  * perform bottom half processing
1881  */
1882 static void bh_handler(struct work_struct *work)
1883 {
1884         struct slgt_info *info = container_of(work, struct slgt_info, task);
1885         int action;
1886
1887         if (!info)
1888                 return;
1889         info->bh_running = 1;
1890
1891         while((action = bh_action(info))) {
1892                 switch (action) {
1893                 case BH_RECEIVE:
1894                         DBGBH(("%s bh receive\n", info->device_name));
1895                         switch(info->params.mode) {
1896                         case MGSL_MODE_ASYNC:
1897                                 rx_async(info);
1898                                 break;
1899                         case MGSL_MODE_HDLC:
1900                                 while(rx_get_frame(info));
1901                                 break;
1902                         case MGSL_MODE_RAW:
1903                         case MGSL_MODE_MONOSYNC:
1904                         case MGSL_MODE_BISYNC:
1905                                 while(rx_get_buf(info));
1906                                 break;
1907                         }
1908                         /* restart receiver if rx DMA buffers exhausted */
1909                         if (info->rx_restart)
1910                                 rx_start(info);
1911                         break;
1912                 case BH_TRANSMIT:
1913                         bh_transmit(info);
1914                         break;
1915                 case BH_STATUS:
1916                         DBGBH(("%s bh status\n", info->device_name));
1917                         info->ri_chkcount = 0;
1918                         info->dsr_chkcount = 0;
1919                         info->dcd_chkcount = 0;
1920                         info->cts_chkcount = 0;
1921                         break;
1922                 default:
1923                         DBGBH(("%s unknown action\n", info->device_name));
1924                         break;
1925                 }
1926         }
1927         DBGBH(("%s bh_handler exit\n", info->device_name));
1928 }
1929
1930 static void bh_transmit(struct slgt_info *info)
1931 {
1932         struct tty_struct *tty = info->tty;
1933
1934         DBGBH(("%s bh_transmit\n", info->device_name));
1935         if (tty)
1936                 tty_wakeup(tty);
1937 }
1938
1939 static void dsr_change(struct slgt_info *info)
1940 {
1941         get_signals(info);
1942         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1943         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1944                 slgt_irq_off(info, IRQ_DSR);
1945                 return;
1946         }
1947         info->icount.dsr++;
1948         if (info->signals & SerialSignal_DSR)
1949                 info->input_signal_events.dsr_up++;
1950         else
1951                 info->input_signal_events.dsr_down++;
1952         wake_up_interruptible(&info->status_event_wait_q);
1953         wake_up_interruptible(&info->event_wait_q);
1954         info->pending_bh |= BH_STATUS;
1955 }
1956
1957 static void cts_change(struct slgt_info *info)
1958 {
1959         get_signals(info);
1960         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1961         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1962                 slgt_irq_off(info, IRQ_CTS);
1963                 return;
1964         }
1965         info->icount.cts++;
1966         if (info->signals & SerialSignal_CTS)
1967                 info->input_signal_events.cts_up++;
1968         else
1969                 info->input_signal_events.cts_down++;
1970         wake_up_interruptible(&info->status_event_wait_q);
1971         wake_up_interruptible(&info->event_wait_q);
1972         info->pending_bh |= BH_STATUS;
1973
1974         if (info->flags & ASYNC_CTS_FLOW) {
1975                 if (info->tty) {
1976                         if (info->tty->hw_stopped) {
1977                                 if (info->signals & SerialSignal_CTS) {
1978                                         info->tty->hw_stopped = 0;
1979                                         info->pending_bh |= BH_TRANSMIT;
1980                                         return;
1981                                 }
1982                         } else {
1983                                 if (!(info->signals & SerialSignal_CTS))
1984                                         info->tty->hw_stopped = 1;
1985                         }
1986                 }
1987         }
1988 }
1989
1990 static void dcd_change(struct slgt_info *info)
1991 {
1992         get_signals(info);
1993         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1994         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1995                 slgt_irq_off(info, IRQ_DCD);
1996                 return;
1997         }
1998         info->icount.dcd++;
1999         if (info->signals & SerialSignal_DCD) {
2000                 info->input_signal_events.dcd_up++;
2001         } else {
2002                 info->input_signal_events.dcd_down++;
2003         }
2004 #if SYNCLINK_GENERIC_HDLC
2005         if (info->netcount) {
2006                 if (info->signals & SerialSignal_DCD)
2007                         netif_carrier_on(info->netdev);
2008                 else
2009                         netif_carrier_off(info->netdev);
2010         }
2011 #endif
2012         wake_up_interruptible(&info->status_event_wait_q);
2013         wake_up_interruptible(&info->event_wait_q);
2014         info->pending_bh |= BH_STATUS;
2015
2016         if (info->flags & ASYNC_CHECK_CD) {
2017                 if (info->signals & SerialSignal_DCD)
2018                         wake_up_interruptible(&info->open_wait);
2019                 else {
2020                         if (info->tty)
2021                                 tty_hangup(info->tty);
2022                 }
2023         }
2024 }
2025
2026 static void ri_change(struct slgt_info *info)
2027 {
2028         get_signals(info);
2029         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2030         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2031                 slgt_irq_off(info, IRQ_RI);
2032                 return;
2033         }
2034         info->icount.dcd++;
2035         if (info->signals & SerialSignal_RI) {
2036                 info->input_signal_events.ri_up++;
2037         } else {
2038                 info->input_signal_events.ri_down++;
2039         }
2040         wake_up_interruptible(&info->status_event_wait_q);
2041         wake_up_interruptible(&info->event_wait_q);
2042         info->pending_bh |= BH_STATUS;
2043 }
2044
2045 static void isr_serial(struct slgt_info *info)
2046 {
2047         unsigned short status = rd_reg16(info, SSR);
2048
2049         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2050
2051         wr_reg16(info, SSR, status); /* clear pending */
2052
2053         info->irq_occurred = 1;
2054
2055         if (info->params.mode == MGSL_MODE_ASYNC) {
2056                 if (status & IRQ_TXIDLE) {
2057                         if (info->tx_count)
2058                                 isr_txeom(info, status);
2059                 }
2060                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2061                         info->icount.brk++;
2062                         /* process break detection if tty control allows */
2063                         if (info->tty) {
2064                                 if (!(status & info->ignore_status_mask)) {
2065                                         if (info->read_status_mask & MASK_BREAK) {
2066                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2067                                                 if (info->flags & ASYNC_SAK)
2068                                                         do_SAK(info->tty);
2069                                         }
2070                                 }
2071                         }
2072                 }
2073         } else {
2074                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2075                         isr_txeom(info, status);
2076
2077                 if (status & IRQ_RXIDLE) {
2078                         if (status & RXIDLE)
2079                                 info->icount.rxidle++;
2080                         else
2081                                 info->icount.exithunt++;
2082                         wake_up_interruptible(&info->event_wait_q);
2083                 }
2084
2085                 if (status & IRQ_RXOVER)
2086                         rx_start(info);
2087         }
2088
2089         if (status & IRQ_DSR)
2090                 dsr_change(info);
2091         if (status & IRQ_CTS)
2092                 cts_change(info);
2093         if (status & IRQ_DCD)
2094                 dcd_change(info);
2095         if (status & IRQ_RI)
2096                 ri_change(info);
2097 }
2098
2099 static void isr_rdma(struct slgt_info *info)
2100 {
2101         unsigned int status = rd_reg32(info, RDCSR);
2102
2103         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2104
2105         /* RDCSR (rx DMA control/status)
2106          *
2107          * 31..07  reserved
2108          * 06      save status byte to DMA buffer
2109          * 05      error
2110          * 04      eol (end of list)
2111          * 03      eob (end of buffer)
2112          * 02      IRQ enable
2113          * 01      reset
2114          * 00      enable
2115          */
2116         wr_reg32(info, RDCSR, status);  /* clear pending */
2117
2118         if (status & (BIT5 + BIT4)) {
2119                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2120                 info->rx_restart = 1;
2121         }
2122         info->pending_bh |= BH_RECEIVE;
2123 }
2124
2125 static void isr_tdma(struct slgt_info *info)
2126 {
2127         unsigned int status = rd_reg32(info, TDCSR);
2128
2129         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2130
2131         /* TDCSR (tx DMA control/status)
2132          *
2133          * 31..06  reserved
2134          * 05      error
2135          * 04      eol (end of list)
2136          * 03      eob (end of buffer)
2137          * 02      IRQ enable
2138          * 01      reset
2139          * 00      enable
2140          */
2141         wr_reg32(info, TDCSR, status);  /* clear pending */
2142
2143         if (status & (BIT5 + BIT4 + BIT3)) {
2144                 // another transmit buffer has completed
2145                 // run bottom half to get more send data from user
2146                 info->pending_bh |= BH_TRANSMIT;
2147         }
2148 }
2149
2150 static void isr_txeom(struct slgt_info *info, unsigned short status)
2151 {
2152         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2153
2154         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2155         tdma_reset(info);
2156         reset_tbufs(info);
2157         if (status & IRQ_TXUNDER) {
2158                 unsigned short val = rd_reg16(info, TCR);
2159                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2160                 wr_reg16(info, TCR, val); /* clear reset bit */
2161         }
2162
2163         if (info->tx_active) {
2164                 if (info->params.mode != MGSL_MODE_ASYNC) {
2165                         if (status & IRQ_TXUNDER)
2166                                 info->icount.txunder++;
2167                         else if (status & IRQ_TXIDLE)
2168                                 info->icount.txok++;
2169                 }
2170
2171                 info->tx_active = 0;
2172                 info->tx_count = 0;
2173
2174                 del_timer(&info->tx_timer);
2175
2176                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2177                         info->signals &= ~SerialSignal_RTS;
2178                         info->drop_rts_on_tx_done = 0;
2179                         set_signals(info);
2180                 }
2181
2182 #if SYNCLINK_GENERIC_HDLC
2183                 if (info->netcount)
2184                         hdlcdev_tx_done(info);
2185                 else
2186 #endif
2187                 {
2188                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2189                                 tx_stop(info);
2190                                 return;
2191                         }
2192                         info->pending_bh |= BH_TRANSMIT;
2193                 }
2194         }
2195 }
2196
2197 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2198 {
2199         struct cond_wait *w, *prev;
2200
2201         /* wake processes waiting for specific transitions */
2202         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2203                 if (w->data & changed) {
2204                         w->data = state;
2205                         wake_up_interruptible(&w->q);
2206                         if (prev != NULL)
2207                                 prev->next = w->next;
2208                         else
2209                                 info->gpio_wait_q = w->next;
2210                 } else
2211                         prev = w;
2212         }
2213 }
2214
2215 /* interrupt service routine
2216  *
2217  *      irq     interrupt number
2218  *      dev_id  device ID supplied during interrupt registration
2219  */
2220 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2221 {
2222         struct slgt_info *info;
2223         unsigned int gsr;
2224         unsigned int i;
2225
2226         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2227
2228         info = dev_id;
2229         if (!info)
2230                 return IRQ_NONE;
2231
2232         spin_lock(&info->lock);
2233
2234         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2235                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2236                 info->irq_occurred = 1;
2237                 for(i=0; i < info->port_count ; i++) {
2238                         if (info->port_array[i] == NULL)
2239                                 continue;
2240                         if (gsr & (BIT8 << i))
2241                                 isr_serial(info->port_array[i]);
2242                         if (gsr & (BIT16 << (i*2)))
2243                                 isr_rdma(info->port_array[i]);
2244                         if (gsr & (BIT17 << (i*2)))
2245                                 isr_tdma(info->port_array[i]);
2246                 }
2247         }
2248
2249         if (info->gpio_present) {
2250                 unsigned int state;
2251                 unsigned int changed;
2252                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2253                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2254                         /* read latched state of GPIO signals */
2255                         state = rd_reg32(info, IOVR);
2256                         /* clear pending GPIO interrupt bits */
2257                         wr_reg32(info, IOSR, changed);
2258                         for (i=0 ; i < info->port_count ; i++) {
2259                                 if (info->port_array[i] != NULL)
2260                                         isr_gpio(info->port_array[i], changed, state);
2261                         }
2262                 }
2263         }
2264
2265         for(i=0; i < info->port_count ; i++) {
2266                 struct slgt_info *port = info->port_array[i];
2267
2268                 if (port && (port->count || port->netcount) &&
2269                     port->pending_bh && !port->bh_running &&
2270                     !port->bh_requested) {
2271                         DBGISR(("%s bh queued\n", port->device_name));
2272                         schedule_work(&port->task);
2273                         port->bh_requested = 1;
2274                 }
2275         }
2276
2277         spin_unlock(&info->lock);
2278
2279         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2280         return IRQ_HANDLED;
2281 }
2282
2283 static int startup(struct slgt_info *info)
2284 {
2285         DBGINFO(("%s startup\n", info->device_name));
2286
2287         if (info->flags & ASYNC_INITIALIZED)
2288                 return 0;
2289
2290         if (!info->tx_buf) {
2291                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2292                 if (!info->tx_buf) {
2293                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2294                         return -ENOMEM;
2295                 }
2296         }
2297
2298         info->pending_bh = 0;
2299
2300         memset(&info->icount, 0, sizeof(info->icount));
2301
2302         /* program hardware for current parameters */
2303         change_params(info);
2304
2305         if (info->tty)
2306                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2307
2308         info->flags |= ASYNC_INITIALIZED;
2309
2310         return 0;
2311 }
2312
2313 /*
2314  *  called by close() and hangup() to shutdown hardware
2315  */
2316 static void shutdown(struct slgt_info *info)
2317 {
2318         unsigned long flags;
2319
2320         if (!(info->flags & ASYNC_INITIALIZED))
2321                 return;
2322
2323         DBGINFO(("%s shutdown\n", info->device_name));
2324
2325         /* clear status wait queue because status changes */
2326         /* can't happen after shutting down the hardware */
2327         wake_up_interruptible(&info->status_event_wait_q);
2328         wake_up_interruptible(&info->event_wait_q);
2329
2330         del_timer_sync(&info->tx_timer);
2331         del_timer_sync(&info->rx_timer);
2332
2333         kfree(info->tx_buf);
2334         info->tx_buf = NULL;
2335
2336         spin_lock_irqsave(&info->lock,flags);
2337
2338         tx_stop(info);
2339         rx_stop(info);
2340
2341         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2342
2343         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2344                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2345                 set_signals(info);
2346         }
2347
2348         flush_cond_wait(&info->gpio_wait_q);
2349
2350         spin_unlock_irqrestore(&info->lock,flags);
2351
2352         if (info->tty)
2353                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2354
2355         info->flags &= ~ASYNC_INITIALIZED;
2356 }
2357
2358 static void program_hw(struct slgt_info *info)
2359 {
2360         unsigned long flags;
2361
2362         spin_lock_irqsave(&info->lock,flags);
2363
2364         rx_stop(info);
2365         tx_stop(info);
2366
2367         if (info->params.mode != MGSL_MODE_ASYNC ||
2368             info->netcount)
2369                 sync_mode(info);
2370         else
2371                 async_mode(info);
2372
2373         set_signals(info);
2374
2375         info->dcd_chkcount = 0;
2376         info->cts_chkcount = 0;
2377         info->ri_chkcount = 0;
2378         info->dsr_chkcount = 0;
2379
2380         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2381         get_signals(info);
2382
2383         if (info->netcount ||
2384             (info->tty && info->tty->termios->c_cflag & CREAD))
2385                 rx_start(info);
2386
2387         spin_unlock_irqrestore(&info->lock,flags);
2388 }
2389
2390 /*
2391  * reconfigure adapter based on new parameters
2392  */
2393 static void change_params(struct slgt_info *info)
2394 {
2395         unsigned cflag;
2396         int bits_per_char;
2397
2398         if (!info->tty || !info->tty->termios)
2399                 return;
2400         DBGINFO(("%s change_params\n", info->device_name));
2401
2402         cflag = info->tty->termios->c_cflag;
2403
2404         /* if B0 rate (hangup) specified then negate DTR and RTS */
2405         /* otherwise assert DTR and RTS */
2406         if (cflag & CBAUD)
2407                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2408         else
2409                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2410
2411         /* byte size and parity */
2412
2413         switch (cflag & CSIZE) {
2414         case CS5: info->params.data_bits = 5; break;
2415         case CS6: info->params.data_bits = 6; break;
2416         case CS7: info->params.data_bits = 7; break;
2417         case CS8: info->params.data_bits = 8; break;
2418         default:  info->params.data_bits = 7; break;
2419         }
2420
2421         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2422
2423         if (cflag & PARENB)
2424                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2425         else
2426                 info->params.parity = ASYNC_PARITY_NONE;
2427
2428         /* calculate number of jiffies to transmit a full
2429          * FIFO (32 bytes) at specified data rate
2430          */
2431         bits_per_char = info->params.data_bits +
2432                         info->params.stop_bits + 1;
2433
2434         info->params.data_rate = tty_get_baud_rate(info->tty);
2435
2436         if (info->params.data_rate) {
2437                 info->timeout = (32*HZ*bits_per_char) /
2438                                 info->params.data_rate;
2439         }
2440         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2441
2442         if (cflag & CRTSCTS)
2443                 info->flags |= ASYNC_CTS_FLOW;
2444         else
2445                 info->flags &= ~ASYNC_CTS_FLOW;
2446
2447         if (cflag & CLOCAL)
2448                 info->flags &= ~ASYNC_CHECK_CD;
2449         else
2450                 info->flags |= ASYNC_CHECK_CD;
2451
2452         /* process tty input control flags */
2453
2454         info->read_status_mask = IRQ_RXOVER;
2455         if (I_INPCK(info->tty))
2456                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2457         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2458                 info->read_status_mask |= MASK_BREAK;
2459         if (I_IGNPAR(info->tty))
2460                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2461         if (I_IGNBRK(info->tty)) {
2462                 info->ignore_status_mask |= MASK_BREAK;
2463                 /* If ignoring parity and break indicators, ignore
2464                  * overruns too.  (For real raw support).
2465                  */
2466                 if (I_IGNPAR(info->tty))
2467                         info->ignore_status_mask |= MASK_OVERRUN;
2468         }
2469
2470         program_hw(info);
2471 }
2472
2473 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2474 {
2475         DBGINFO(("%s get_stats\n",  info->device_name));
2476         if (!user_icount) {
2477                 memset(&info->icount, 0, sizeof(info->icount));
2478         } else {
2479                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2480                         return -EFAULT;
2481         }
2482         return 0;
2483 }
2484
2485 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2486 {
2487         DBGINFO(("%s get_params\n", info->device_name));
2488         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2489                 return -EFAULT;
2490         return 0;
2491 }
2492
2493 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2494 {
2495         unsigned long flags;
2496         MGSL_PARAMS tmp_params;
2497
2498         DBGINFO(("%s set_params\n", info->device_name));
2499         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2500                 return -EFAULT;
2501
2502         spin_lock_irqsave(&info->lock, flags);
2503         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2504         spin_unlock_irqrestore(&info->lock, flags);
2505
2506         change_params(info);
2507
2508         return 0;
2509 }
2510
2511 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2512 {
2513         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2514         if (put_user(info->idle_mode, idle_mode))
2515                 return -EFAULT;
2516         return 0;
2517 }
2518
2519 static int set_txidle(struct slgt_info *info, int idle_mode)
2520 {
2521         unsigned long flags;
2522         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2523         spin_lock_irqsave(&info->lock,flags);
2524         info->idle_mode = idle_mode;
2525         if (info->params.mode != MGSL_MODE_ASYNC)
2526                 tx_set_idle(info);
2527         spin_unlock_irqrestore(&info->lock,flags);
2528         return 0;
2529 }
2530
2531 static int tx_enable(struct slgt_info *info, int enable)
2532 {
2533         unsigned long flags;
2534         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2535         spin_lock_irqsave(&info->lock,flags);
2536         if (enable) {
2537                 if (!info->tx_enabled)
2538                         tx_start(info);
2539         } else {
2540                 if (info->tx_enabled)
2541                         tx_stop(info);
2542         }
2543         spin_unlock_irqrestore(&info->lock,flags);
2544         return 0;
2545 }
2546
2547 /*
2548  * abort transmit HDLC frame
2549  */
2550 static int tx_abort(struct slgt_info *info)
2551 {
2552         unsigned long flags;
2553         DBGINFO(("%s tx_abort\n", info->device_name));
2554         spin_lock_irqsave(&info->lock,flags);
2555         tdma_reset(info);
2556         spin_unlock_irqrestore(&info->lock,flags);
2557         return 0;
2558 }
2559
2560 static int rx_enable(struct slgt_info *info, int enable)
2561 {
2562         unsigned long flags;
2563         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2564         spin_lock_irqsave(&info->lock,flags);
2565         if (enable) {
2566                 if (!info->rx_enabled)
2567                         rx_start(info);
2568                 else if (enable == 2) {
2569                         /* force hunt mode (write 1 to RCR[3]) */
2570                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2571                 }
2572         } else {
2573                 if (info->rx_enabled)
2574                         rx_stop(info);
2575         }
2576         spin_unlock_irqrestore(&info->lock,flags);
2577         return 0;
2578 }
2579
2580 /*
2581  *  wait for specified event to occur
2582  */
2583 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2584 {
2585         unsigned long flags;
2586         int s;
2587         int rc=0;
2588         struct mgsl_icount cprev, cnow;
2589         int events;
2590         int mask;
2591         struct  _input_signal_events oldsigs, newsigs;
2592         DECLARE_WAITQUEUE(wait, current);
2593
2594         if (get_user(mask, mask_ptr))
2595                 return -EFAULT;
2596
2597         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2598
2599         spin_lock_irqsave(&info->lock,flags);
2600
2601         /* return immediately if state matches requested events */
2602         get_signals(info);
2603         s = info->signals;
2604
2605         events = mask &
2606                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2607                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2608                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2609                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2610         if (events) {
2611                 spin_unlock_irqrestore(&info->lock,flags);
2612                 goto exit;
2613         }
2614
2615         /* save current irq counts */
2616         cprev = info->icount;
2617         oldsigs = info->input_signal_events;
2618
2619         /* enable hunt and idle irqs if needed */
2620         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2621                 unsigned short val = rd_reg16(info, SCR);
2622                 if (!(val & IRQ_RXIDLE))
2623                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2624         }
2625
2626         set_current_state(TASK_INTERRUPTIBLE);
2627         add_wait_queue(&info->event_wait_q, &wait);
2628
2629         spin_unlock_irqrestore(&info->lock,flags);
2630
2631         for(;;) {
2632                 schedule();
2633                 if (signal_pending(current)) {
2634                         rc = -ERESTARTSYS;
2635                         break;
2636                 }
2637
2638                 /* get current irq counts */
2639                 spin_lock_irqsave(&info->lock,flags);
2640                 cnow = info->icount;
2641                 newsigs = info->input_signal_events;
2642                 set_current_state(TASK_INTERRUPTIBLE);
2643                 spin_unlock_irqrestore(&info->lock,flags);
2644
2645                 /* if no change, wait aborted for some reason */
2646                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2647                     newsigs.dsr_down == oldsigs.dsr_down &&
2648                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2649                     newsigs.dcd_down == oldsigs.dcd_down &&
2650                     newsigs.cts_up   == oldsigs.cts_up   &&
2651                     newsigs.cts_down == oldsigs.cts_down &&
2652                     newsigs.ri_up    == oldsigs.ri_up    &&
2653                     newsigs.ri_down  == oldsigs.ri_down  &&
2654                     cnow.exithunt    == cprev.exithunt   &&
2655                     cnow.rxidle      == cprev.rxidle) {
2656                         rc = -EIO;
2657                         break;
2658                 }
2659
2660                 events = mask &
2661                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2662                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2663                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2664                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2665                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2666                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2667                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2668                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2669                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2670                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2671                 if (events)
2672                         break;
2673
2674                 cprev = cnow;
2675                 oldsigs = newsigs;
2676         }
2677
2678         remove_wait_queue(&info->event_wait_q, &wait);
2679         set_current_state(TASK_RUNNING);
2680
2681
2682         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2683                 spin_lock_irqsave(&info->lock,flags);
2684                 if (!waitqueue_active(&info->event_wait_q)) {
2685                         /* disable enable exit hunt mode/idle rcvd IRQs */
2686                         wr_reg16(info, SCR,
2687                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2688                 }
2689                 spin_unlock_irqrestore(&info->lock,flags);
2690         }
2691 exit:
2692         if (rc == 0)
2693                 rc = put_user(events, mask_ptr);
2694         return rc;
2695 }
2696
2697 static int get_interface(struct slgt_info *info, int __user *if_mode)
2698 {
2699         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2700         if (put_user(info->if_mode, if_mode))
2701                 return -EFAULT;
2702         return 0;
2703 }
2704
2705 static int set_interface(struct slgt_info *info, int if_mode)
2706 {
2707         unsigned long flags;
2708         unsigned short val;
2709
2710         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2711         spin_lock_irqsave(&info->lock,flags);
2712         info->if_mode = if_mode;
2713
2714         msc_set_vcr(info);
2715
2716         /* TCR (tx control) 07  1=RTS driver control */
2717         val = rd_reg16(info, TCR);
2718         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2719                 val |= BIT7;
2720         else
2721                 val &= ~BIT7;
2722         wr_reg16(info, TCR, val);
2723
2724         spin_unlock_irqrestore(&info->lock,flags);
2725         return 0;
2726 }
2727
2728 /*
2729  * set general purpose IO pin state and direction
2730  *
2731  * user_gpio fields:
2732  * state   each bit indicates a pin state
2733  * smask   set bit indicates pin state to set
2734  * dir     each bit indicates a pin direction (0=input, 1=output)
2735  * dmask   set bit indicates pin direction to set
2736  */
2737 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2738 {
2739         unsigned long flags;
2740         struct gpio_desc gpio;
2741         __u32 data;
2742
2743         if (!info->gpio_present)
2744                 return -EINVAL;
2745         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2746                 return -EFAULT;
2747         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2748                  info->device_name, gpio.state, gpio.smask,
2749                  gpio.dir, gpio.dmask));
2750
2751         spin_lock_irqsave(&info->lock,flags);
2752         if (gpio.dmask) {
2753                 data = rd_reg32(info, IODR);
2754                 data |= gpio.dmask & gpio.dir;
2755                 data &= ~(gpio.dmask & ~gpio.dir);
2756                 wr_reg32(info, IODR, data);
2757         }
2758         if (gpio.smask) {
2759                 data = rd_reg32(info, IOVR);
2760                 data |= gpio.smask & gpio.state;
2761                 data &= ~(gpio.smask & ~gpio.state);
2762                 wr_reg32(info, IOVR, data);
2763         }
2764         spin_unlock_irqrestore(&info->lock,flags);
2765
2766         return 0;
2767 }
2768
2769 /*
2770  * get general purpose IO pin state and direction
2771  */
2772 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2773 {
2774         struct gpio_desc gpio;
2775         if (!info->gpio_present)
2776                 return -EINVAL;
2777         gpio.state = rd_reg32(info, IOVR);
2778         gpio.smask = 0xffffffff;
2779         gpio.dir   = rd_reg32(info, IODR);
2780         gpio.dmask = 0xffffffff;
2781         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2782                 return -EFAULT;
2783         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2784                  info->device_name, gpio.state, gpio.dir));
2785         return 0;
2786 }
2787
2788 /*
2789  * conditional wait facility
2790  */
2791 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2792 {
2793         init_waitqueue_head(&w->q);
2794         init_waitqueue_entry(&w->wait, current);
2795         w->data = data;
2796 }
2797
2798 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2799 {
2800         set_current_state(TASK_INTERRUPTIBLE);
2801         add_wait_queue(&w->q, &w->wait);
2802         w->next = *head;
2803         *head = w;
2804 }
2805
2806 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2807 {
2808         struct cond_wait *w, *prev;
2809         remove_wait_queue(&cw->q, &cw->wait);
2810         set_current_state(TASK_RUNNING);
2811         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2812                 if (w == cw) {
2813                         if (prev != NULL)
2814                                 prev->next = w->next;
2815                         else
2816                                 *head = w->next;
2817                         break;
2818                 }
2819         }
2820 }
2821
2822 static void flush_cond_wait(struct cond_wait **head)
2823 {
2824         while (*head != NULL) {
2825                 wake_up_interruptible(&(*head)->q);
2826                 *head = (*head)->next;
2827         }
2828 }
2829
2830 /*
2831  * wait for general purpose I/O pin(s) to enter specified state
2832  *
2833  * user_gpio fields:
2834  * state - bit indicates target pin state
2835  * smask - set bit indicates watched pin
2836  *
2837  * The wait ends when at least one watched pin enters the specified
2838  * state. When 0 (no error) is returned, user_gpio->state is set to the
2839  * state of all GPIO pins when the wait ends.
2840  *
2841  * Note: Each pin may be a dedicated input, dedicated output, or
2842  * configurable input/output. The number and configuration of pins
2843  * varies with the specific adapter model. Only input pins (dedicated
2844  * or configured) can be monitored with this function.
2845  */
2846 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2847 {
2848         unsigned long flags;
2849         int rc = 0;
2850         struct gpio_desc gpio;
2851         struct cond_wait wait;
2852         u32 state;
2853
2854         if (!info->gpio_present)
2855                 return -EINVAL;
2856         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2857                 return -EFAULT;
2858         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2859                  info->device_name, gpio.state, gpio.smask));
2860         /* ignore output pins identified by set IODR bit */
2861         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2862                 return -EINVAL;
2863         init_cond_wait(&wait, gpio.smask);
2864
2865         spin_lock_irqsave(&info->lock, flags);
2866         /* enable interrupts for watched pins */
2867         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2868         /* get current pin states */
2869         state = rd_reg32(info, IOVR);
2870
2871         if (gpio.smask & ~(state ^ gpio.state)) {
2872                 /* already in target state */
2873                 gpio.state = state;
2874         } else {
2875                 /* wait for target state */
2876                 add_cond_wait(&info->gpio_wait_q, &wait);
2877                 spin_unlock_irqrestore(&info->lock, flags);
2878                 schedule();
2879                 if (signal_pending(current))
2880                         rc = -ERESTARTSYS;
2881                 else
2882                         gpio.state = wait.data;
2883                 spin_lock_irqsave(&info->lock, flags);
2884                 remove_cond_wait(&info->gpio_wait_q, &wait);
2885         }
2886
2887         /* disable all GPIO interrupts if no waiting processes */
2888         if (info->gpio_wait_q == NULL)
2889                 wr_reg32(info, IOER, 0);
2890         spin_unlock_irqrestore(&info->lock,flags);
2891
2892         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2893                 rc = -EFAULT;
2894         return rc;
2895 }
2896
2897 static int modem_input_wait(struct slgt_info *info,int arg)
2898 {
2899         unsigned long flags;
2900         int rc;
2901         struct mgsl_icount cprev, cnow;
2902         DECLARE_WAITQUEUE(wait, current);
2903
2904         /* save current irq counts */
2905         spin_lock_irqsave(&info->lock,flags);
2906         cprev = info->icount;
2907         add_wait_queue(&info->status_event_wait_q, &wait);
2908         set_current_state(TASK_INTERRUPTIBLE);
2909         spin_unlock_irqrestore(&info->lock,flags);
2910
2911         for(;;) {
2912                 schedule();
2913                 if (signal_pending(current)) {
2914                         rc = -ERESTARTSYS;
2915                         break;
2916                 }
2917
2918                 /* get new irq counts */
2919                 spin_lock_irqsave(&info->lock,flags);
2920                 cnow = info->icount;
2921                 set_current_state(TASK_INTERRUPTIBLE);
2922                 spin_unlock_irqrestore(&info->lock,flags);
2923
2924                 /* if no change, wait aborted for some reason */
2925                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2926                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2927                         rc = -EIO;
2928                         break;
2929                 }
2930
2931                 /* check for change in caller specified modem input */
2932                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2933                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2934                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2935                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2936                         rc = 0;
2937                         break;
2938                 }
2939
2940                 cprev = cnow;
2941         }
2942         remove_wait_queue(&info->status_event_wait_q, &wait);
2943         set_current_state(TASK_RUNNING);
2944         return rc;
2945 }
2946
2947 /*
2948  *  return state of serial control and status signals
2949  */
2950 static int tiocmget(struct tty_struct *tty, struct file *file)
2951 {
2952         struct slgt_info *info = tty->driver_data;
2953         unsigned int result;
2954         unsigned long flags;
2955
2956         spin_lock_irqsave(&info->lock,flags);
2957         get_signals(info);
2958         spin_unlock_irqrestore(&info->lock,flags);
2959
2960         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2961                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2962                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2963                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2964                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2965                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2966
2967         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2968         return result;
2969 }
2970
2971 /*
2972  * set modem control signals (DTR/RTS)
2973  *
2974  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2975  *              TIOCMSET = set/clear signal values
2976  *      value   bit mask for command
2977  */
2978 static int tiocmset(struct tty_struct *tty, struct file *file,
2979                     unsigned int set, unsigned int clear)
2980 {
2981         struct slgt_info *info = tty->driver_data;
2982         unsigned long flags;
2983
2984         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2985
2986         if (set & TIOCM_RTS)
2987                 info->signals |= SerialSignal_RTS;
2988         if (set & TIOCM_DTR)
2989                 info->signals |= SerialSignal_DTR;
2990         if (clear & TIOCM_RTS)
2991                 info->signals &= ~SerialSignal_RTS;
2992         if (clear & TIOCM_DTR)
2993                 info->signals &= ~SerialSignal_DTR;
2994
2995         spin_lock_irqsave(&info->lock,flags);
2996         set_signals(info);
2997         spin_unlock_irqrestore(&info->lock,flags);
2998         return 0;
2999 }
3000
3001 /*
3002  *  block current process until the device is ready to open
3003  */
3004 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3005                            struct slgt_info *info)
3006 {
3007         DECLARE_WAITQUEUE(wait, current);
3008         int             retval;
3009         int             do_clocal = 0, extra_count = 0;
3010         unsigned long   flags;
3011
3012         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3013
3014         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3015                 /* nonblock mode is set or port is not enabled */
3016                 info->flags |= ASYNC_NORMAL_ACTIVE;
3017                 return 0;
3018         }
3019
3020         if (tty->termios->c_cflag & CLOCAL)
3021                 do_clocal = 1;
3022
3023         /* Wait for carrier detect and the line to become
3024          * free (i.e., not in use by the callout).  While we are in
3025          * this loop, info->count is dropped by one, so that
3026          * close() knows when to free things.  We restore it upon
3027          * exit, either normal or abnormal.
3028          */
3029
3030         retval = 0;
3031         add_wait_queue(&info->open_wait, &wait);
3032
3033         spin_lock_irqsave(&info->lock, flags);
3034         if (!tty_hung_up_p(filp)) {
3035                 extra_count = 1;
3036                 info->count--;
3037         }
3038         spin_unlock_irqrestore(&info->lock, flags);
3039         info->blocked_open++;
3040
3041         while (1) {
3042                 if ((tty->termios->c_cflag & CBAUD)) {
3043                         spin_lock_irqsave(&info->lock,flags);
3044                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3045                         set_signals(info);
3046                         spin_unlock_irqrestore(&info->lock,flags);
3047                 }
3048
3049                 set_current_state(TASK_INTERRUPTIBLE);
3050
3051                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3052                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3053                                         -EAGAIN : -ERESTARTSYS;
3054                         break;
3055                 }
3056
3057                 spin_lock_irqsave(&info->lock,flags);
3058                 get_signals(info);
3059                 spin_unlock_irqrestore(&info->lock,flags);
3060
3061                 if (!(info->flags & ASYNC_CLOSING) &&
3062                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3063                         break;
3064                 }
3065
3066                 if (signal_pending(current)) {
3067                         retval = -ERESTARTSYS;
3068                         break;
3069                 }
3070
3071                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3072                 schedule();
3073         }
3074
3075         set_current_state(TASK_RUNNING);
3076         remove_wait_queue(&info->open_wait, &wait);
3077
3078         if (extra_count)
3079                 info->count++;
3080         info->blocked_open--;
3081
3082         if (!retval)
3083                 info->flags |= ASYNC_NORMAL_ACTIVE;
3084
3085         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3086         return retval;
3087 }
3088
3089 static int alloc_tmp_rbuf(struct slgt_info *info)
3090 {
3091         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3092         if (info->tmp_rbuf == NULL)
3093                 return -ENOMEM;
3094         return 0;
3095 }
3096
3097 static void free_tmp_rbuf(struct slgt_info *info)
3098 {
3099         kfree(info->tmp_rbuf);
3100         info->tmp_rbuf = NULL;
3101 }
3102
3103 /*
3104  * allocate DMA descriptor lists.
3105  */
3106 static int alloc_desc(struct slgt_info *info)
3107 {
3108         unsigned int i;
3109         unsigned int pbufs;
3110
3111         /* allocate memory to hold descriptor lists */
3112         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3113         if (info->bufs == NULL)
3114                 return -ENOMEM;
3115
3116         memset(info->bufs, 0, DESC_LIST_SIZE);
3117
3118         info->rbufs = (struct slgt_desc*)info->bufs;
3119         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3120
3121         pbufs = (unsigned int)info->bufs_dma_addr;
3122
3123         /*
3124          * Build circular lists of descriptors
3125          */
3126
3127         for (i=0; i < info->rbuf_count; i++) {
3128                 /* physical address of this descriptor */
3129                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3130
3131                 /* physical address of next descriptor */
3132                 if (i == info->rbuf_count - 1)
3133                         info->rbufs[i].next = cpu_to_le32(pbufs);
3134                 else
3135                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3136                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3137         }
3138
3139         for (i=0; i < info->tbuf_count; i++) {
3140                 /* physical address of this descriptor */
3141                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3142
3143                 /* physical address of next descriptor */
3144                 if (i == info->tbuf_count - 1)
3145                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3146                 else
3147                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3148         }
3149
3150         return 0;
3151 }
3152
3153 static void free_desc(struct slgt_info *info)
3154 {
3155         if (info->bufs != NULL) {
3156                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3157                 info->bufs  = NULL;
3158                 info->rbufs = NULL;
3159                 info->tbufs = NULL;
3160         }
3161 }
3162
3163 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3164 {
3165         int i;
3166         for (i=0; i < count; i++) {
3167                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3168                         return -ENOMEM;
3169                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3170         }
3171         return 0;
3172 }
3173
3174 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3175 {
3176         int i;
3177         for (i=0; i < count; i++) {
3178                 if (bufs[i].buf == NULL)
3179                         continue;
3180                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3181                 bufs[i].buf = NULL;
3182         }
3183 }
3184
3185 static int alloc_dma_bufs(struct slgt_info *info)
3186 {
3187         info->rbuf_count = 32;
3188         info->tbuf_count = 32;
3189
3190         if (alloc_desc(info) < 0 ||
3191             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3192             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3193             alloc_tmp_rbuf(info) < 0) {
3194                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3195                 return -ENOMEM;
3196         }
3197         reset_rbufs(info);
3198         return 0;
3199 }
3200
3201 static void free_dma_bufs(struct slgt_info *info)
3202 {
3203         if (info->bufs) {
3204                 free_bufs(info, info->rbufs, info->rbuf_count);
3205                 free_bufs(info, info->tbufs, info->tbuf_count);
3206                 free_desc(info);
3207         }
3208         free_tmp_rbuf(info);
3209 }
3210
3211 static int claim_resources(struct slgt_info *info)
3212 {
3213         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3214                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3215                         info->device_name, info->phys_reg_addr));
3216                 info->init_error = DiagStatus_AddressConflict;
3217                 goto errout;
3218         }
3219         else
3220                 info->reg_addr_requested = 1;
3221
3222         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3223         if (!info->reg_addr) {
3224                 DBGERR(("%s cant map device registers, addr=%08X\n",
3225                         info->device_name, info->phys_reg_addr));
3226                 info->init_error = DiagStatus_CantAssignPciResources;
3227                 goto errout;
3228         }
3229         return 0;
3230
3231 errout:
3232         release_resources(info);
3233         return -ENODEV;
3234 }
3235
3236 static void release_resources(struct slgt_info *info)
3237 {
3238         if (info->irq_requested) {
3239                 free_irq(info->irq_level, info);
3240                 info->irq_requested = 0;
3241         }
3242
3243         if (info->reg_addr_requested) {
3244                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3245                 info->reg_addr_requested = 0;
3246         }
3247
3248         if (info->reg_addr) {
3249                 iounmap(info->reg_addr);
3250                 info->reg_addr = NULL;
3251         }
3252 }
3253
3254 /* Add the specified device instance data structure to the
3255  * global linked list of devices and increment the device count.
3256  */
3257 static void add_device(struct slgt_info *info)
3258 {
3259         char *devstr;
3260
3261         info->next_device = NULL;
3262         info->line = slgt_device_count;
3263         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3264
3265         if (info->line < MAX_DEVICES) {
3266                 if (maxframe[info->line])
3267                         info->max_frame_size = maxframe[info->line];
3268                 info->dosyncppp = dosyncppp[info->line];
3269         }
3270
3271         slgt_device_count++;
3272
3273         if (!slgt_device_list)
3274                 slgt_device_list = info;
3275         else {
3276                 struct slgt_info *current_dev = slgt_device_list;
3277                 while(current_dev->next_device)
3278                         current_dev = current_dev->next_device;
3279                 current_dev->next_device = info;
3280         }
3281
3282         if (info->max_frame_size < 4096)
3283                 info->max_frame_size = 4096;
3284         else if (info->max_frame_size > 65535)
3285                 info->max_frame_size = 65535;
3286
3287         switch(info->pdev->device) {
3288         case SYNCLINK_GT_DEVICE_ID:
3289                 devstr = "GT";
3290                 break;
3291         case SYNCLINK_GT2_DEVICE_ID:
3292                 devstr = "GT2";
3293                 break;
3294         case SYNCLINK_GT4_DEVICE_ID:
3295                 devstr = "GT4";
3296                 break;
3297         case SYNCLINK_AC_DEVICE_ID:
3298                 devstr = "AC";
3299                 info->params.mode = MGSL_MODE_ASYNC;
3300                 break;
3301         default:
3302                 devstr = "(unknown model)";
3303         }
3304         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3305                 devstr, info->device_name, info->phys_reg_addr,
3306                 info->irq_level, info->max_frame_size);
3307
3308 #if SYNCLINK_GENERIC_HDLC
3309         hdlcdev_init(info);
3310 #endif
3311 }
3312
3313 /*
3314  *  allocate device instance structure, return NULL on failure
3315  */
3316 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3317 {
3318         struct slgt_info *info;
3319
3320         info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3321
3322         if (!info) {
3323                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3324                         driver_name, adapter_num, port_num));
3325         } else {
3326                 memset(info, 0, sizeof(struct slgt_info));
3327                 info->magic = MGSL_MAGIC;
3328                 INIT_WORK(&info->task, bh_handler);
3329                 info->max_frame_size = 4096;
3330                 info->raw_rx_size = DMABUFSIZE;
3331                 info->close_delay = 5*HZ/10;
3332                 info->closing_wait = 30*HZ;
3333                 init_waitqueue_head(&info->open_wait);
3334                 init_waitqueue_head(&info->close_wait);
3335                 init_waitqueue_head(&info->status_event_wait_q);
3336                 init_waitqueue_head(&info->event_wait_q);
3337                 spin_lock_init(&info->netlock);
3338                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3339                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3340                 info->adapter_num = adapter_num;
3341                 info->port_num = port_num;
3342
3343                 init_timer(&info->tx_timer);
3344                 info->tx_timer.data = (unsigned long)info;
3345                 info->tx_timer.function = tx_timeout;
3346
3347                 init_timer(&info->rx_timer);
3348                 info->rx_timer.data = (unsigned long)info;
3349                 info->rx_timer.function = rx_timeout;
3350
3351                 /* Copy configuration info to device instance data */
3352                 info->pdev = pdev;
3353                 info->irq_level = pdev->irq;
3354                 info->phys_reg_addr = pci_resource_start(pdev,0);
3355
3356                 info->bus_type = MGSL_BUS_TYPE_PCI;
3357                 info->irq_flags = IRQF_SHARED;
3358
3359                 info->init_error = -1; /* assume error, set to 0 on successful init */
3360         }
3361
3362         return info;
3363 }
3364
3365 static void device_init(int adapter_num, struct pci_dev *pdev)
3366 {
3367         struct slgt_info *port_array[SLGT_MAX_PORTS];
3368         int i;
3369         int port_count = 1;
3370
3371         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3372                 port_count = 2;
3373         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3374                 port_count = 4;
3375
3376         /* allocate device instances for all ports */
3377         for (i=0; i < port_count; ++i) {
3378                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3379                 if (port_array[i] == NULL) {
3380                         for (--i; i >= 0; --i)
3381                                 kfree(port_array[i]);
3382                         return;
3383                 }
3384         }
3385
3386         /* give copy of port_array to all ports and add to device list  */
3387         for (i=0; i < port_count; ++i) {
3388                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3389                 add_device(port_array[i]);
3390                 port_array[i]->port_count = port_count;
3391                 spin_lock_init(&port_array[i]->lock);
3392         }
3393
3394         /* Allocate and claim adapter resources */
3395         if (!claim_resources(port_array[0])) {
3396
3397                 alloc_dma_bufs(port_array[0]);
3398
3399                 /* copy resource information from first port to others */
3400                 for (i = 1; i < port_count; ++i) {
3401                         port_array[i]->lock      = port_array[0]->lock;
3402                         port_array[i]->irq_level = port_array[0]->irq_level;
3403                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3404                         alloc_dma_bufs(port_array[i]);
3405                 }
3406
3407                 if (request_irq(port_array[0]->irq_level,
3408                                         slgt_interrupt,
3409                                         port_array[0]->irq_flags,
3410                                         port_array[0]->device_name,
3411                                         port_array[0]) < 0) {
3412                         DBGERR(("%s request_irq failed IRQ=%d\n",
3413                                 port_array[0]->device_name,
3414                                 port_array[0]->irq_level));
3415                 } else {
3416                         port_array[0]->irq_requested = 1;
3417                         adapter_test(port_array[0]);
3418                         for (i=1 ; i < port_count ; i++) {
3419                                 port_array[i]->init_error = port_array[0]->init_error;
3420                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3421                         }
3422                 }
3423         }
3424 }
3425
3426 static int __devinit init_one(struct pci_dev *dev,
3427                               const struct pci_device_id *ent)
3428 {
3429         if (pci_enable_device(dev)) {
3430                 printk("error enabling pci device %p\n", dev);
3431                 return -EIO;
3432         }
3433         pci_set_master(dev);
3434         device_init(slgt_device_count, dev);
3435         return 0;
3436 }
3437
3438 static void __devexit remove_one(struct pci_dev *dev)
3439 {
3440 }
3441
3442 static const struct tty_operations ops = {
3443         .open = open,
3444         .close = close,
3445         .write = write,
3446         .put_char = put_char,
3447         .flush_chars = flush_chars,
3448         .write_room = write_room,
3449         .chars_in_buffer = chars_in_buffer,
3450         .flush_buffer = flush_buffer,
3451         .ioctl = ioctl,
3452         .throttle = throttle,
3453         .unthrottle = unthrottle,
3454         .send_xchar = send_xchar,
3455         .break_ctl = set_break,
3456         .wait_until_sent = wait_until_sent,
3457         .read_proc = read_proc,
3458         .set_termios = set_termios,
3459         .stop = tx_hold,
3460         .start = tx_release,
3461         .hangup = hangup,
3462         .tiocmget = tiocmget,
3463         .tiocmset = tiocmset,
3464 };
3465
3466 static void slgt_cleanup(void)
3467 {
3468         int rc;
3469         struct slgt_info *info;
3470         struct slgt_info *tmp;
3471
3472         printk("unload %s %s\n", driver_name, driver_version);
3473
3474         if (serial_driver) {
3475                 if ((rc = tty_unregister_driver(serial_driver)))
3476                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3477                 put_tty_driver(serial_driver);
3478         }
3479
3480         /* reset devices */
3481         info = slgt_device_list;
3482         while(info) {
3483                 reset_port(info);
3484                 info = info->next_device;
3485         }
3486
3487         /* release devices */
3488         info = slgt_device_list;
3489         while(info) {
3490 #if SYNCLINK_GENERIC_HDLC
3491                 hdlcdev_exit(info);
3492 #endif
3493                 free_dma_bufs(info);
3494                 free_tmp_rbuf(info);
3495                 if (info->port_num == 0)
3496                         release_resources(info);
3497                 tmp = info;
3498                 info = info->next_device;
3499                 kfree(tmp);
3500         }
3501
3502         if (pci_registered)
3503                 pci_unregister_driver(&pci_driver);
3504 }
3505
3506 /*
3507  *  Driver initialization entry point.
3508  */
3509 static int __init slgt_init(void)
3510 {
3511         int rc;
3512
3513         printk("%s %s\n", driver_name, driver_version);
3514
3515         slgt_device_count = 0;
3516         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3517                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3518                 return rc;
3519         }
3520         pci_registered = 1;
3521
3522         if (!slgt_device_list) {
3523                 printk("%s no devices found\n",driver_name);
3524                 pci_unregister_driver(&pci_driver);
3525                 return -ENODEV;
3526         }
3527
3528         serial_driver = alloc_tty_driver(MAX_DEVICES);
3529         if (!serial_driver) {
3530                 rc = -ENOMEM;
3531                 goto error;
3532         }
3533
3534         /* Initialize the tty_driver structure */
3535
3536         serial_driver->owner = THIS_MODULE;
3537         serial_driver->driver_name = tty_driver_name;
3538         serial_driver->name = tty_dev_prefix;
3539         serial_driver->major = ttymajor;
3540         serial_driver->minor_start = 64;
3541         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3542         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3543         serial_driver->init_termios = tty_std_termios;
3544         serial_driver->init_termios.c_cflag =
3545                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3546         serial_driver->init_termios.c_ispeed = 9600;
3547         serial_driver->init_termios.c_ospeed = 9600;
3548         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3549         tty_set_operations(serial_driver, &ops);
3550         if ((rc = tty_register_driver(serial_driver)) < 0) {
3551                 DBGERR(("%s can't register serial driver\n", driver_name));
3552                 put_tty_driver(serial_driver);
3553                 serial_driver = NULL;
3554                 goto error;
3555         }
3556
3557         printk("%s %s, tty major#%d\n",
3558                 driver_name, driver_version,
3559                 serial_driver->major);
3560
3561         return 0;
3562
3563 error:
3564         slgt_cleanup();
3565         return rc;
3566 }
3567
3568 static void __exit slgt_exit(void)
3569 {
3570         slgt_cleanup();
3571 }
3572
3573 module_init(slgt_init);
3574 module_exit(slgt_exit);
3575
3576 /*
3577  * register access routines
3578  */
3579
3580 #define CALC_REGADDR() \
3581         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3582         if (addr >= 0x80) \
3583                 reg_addr += (info->port_num) * 32;
3584
3585 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3586 {
3587         CALC_REGADDR();
3588         return readb((void __iomem *)reg_addr);
3589 }
3590
3591 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3592 {
3593         CALC_REGADDR();
3594         writeb(value, (void __iomem *)reg_addr);
3595 }
3596
3597 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3598 {
3599         CALC_REGADDR();
3600         return readw((void __iomem *)reg_addr);
3601 }
3602
3603 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3604 {
3605         CALC_REGADDR();
3606         writew(value, (void __iomem *)reg_addr);
3607 }
3608
3609 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3610 {
3611         CALC_REGADDR();
3612         return readl((void __iomem *)reg_addr);
3613 }
3614
3615 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3616 {
3617         CALC_REGADDR();
3618         writel(value, (void __iomem *)reg_addr);
3619 }
3620
3621 static void rdma_reset(struct slgt_info *info)
3622 {
3623         unsigned int i;
3624
3625         /* set reset bit */
3626         wr_reg32(info, RDCSR, BIT1);
3627
3628         /* wait for enable bit cleared */
3629         for(i=0 ; i < 1000 ; i++)
3630                 if (!(rd_reg32(info, RDCSR) & BIT0))
3631                         break;
3632 }
3633
3634 static void tdma_reset(struct slgt_info *info)
3635 {
3636         unsigned int i;
3637
3638         /* set reset bit */
3639         wr_reg32(info, TDCSR, BIT1);
3640
3641         /* wait for enable bit cleared */
3642         for(i=0 ; i < 1000 ; i++)
3643                 if (!(rd_reg32(info, TDCSR) & BIT0))
3644                         break;
3645 }
3646
3647 /*
3648  * enable internal loopback
3649  * TxCLK and RxCLK are generated from BRG
3650  * and TxD is looped back to RxD internally.
3651  */
3652 static void enable_loopback(struct slgt_info *info)
3653 {
3654         /* SCR (serial control) BIT2=looopback enable */
3655         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3656
3657         if (info->params.mode != MGSL_MODE_ASYNC) {
3658                 /* CCR (clock control)
3659                  * 07..05  tx clock source (010 = BRG)
3660                  * 04..02  rx clock source (010 = BRG)
3661                  * 01      auxclk enable   (0 = disable)
3662                  * 00      BRG enable      (1 = enable)
3663                  *
3664                  * 0100 1001
3665                  */
3666                 wr_reg8(info, CCR, 0x49);
3667
3668                 /* set speed if available, otherwise use default */
3669                 if (info->params.clock_speed)
3670                         set_rate(info, info->params.clock_speed);
3671                 else
3672                         set_rate(info, 3686400);
3673         }
3674 }
3675
3676 /*
3677  *  set baud rate generator to specified rate
3678  */
3679 static void set_rate(struct slgt_info *info, u32 rate)
3680 {
3681         unsigned int div;
3682         static unsigned int osc = 14745600;
3683
3684         /* div = osc/rate - 1
3685          *
3686          * Round div up if osc/rate is not integer to
3687          * force to next slowest rate.
3688          */
3689
3690         if (rate) {
3691                 div = osc/rate;
3692                 if (!(osc % rate) && div)
3693                         div--;
3694                 wr_reg16(info, BDR, (unsigned short)div);
3695         }
3696 }
3697
3698 static void rx_stop(struct slgt_info *info)
3699 {
3700         unsigned short val;
3701
3702         /* disable and reset receiver */
3703         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3704         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3705         wr_reg16(info, RCR, val);                  /* clear reset bit */
3706
3707         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3708
3709         /* clear pending rx interrupts */
3710         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3711
3712         rdma_reset(info);
3713
3714         info->rx_enabled = 0;
3715         info->rx_restart = 0;
3716 }
3717
3718 static void rx_start(struct slgt_info *info)
3719 {
3720         unsigned short val;
3721
3722         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3723
3724         /* clear pending rx overrun IRQ */
3725         wr_reg16(info, SSR, IRQ_RXOVER);
3726
3727         /* reset and disable receiver */
3728         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3729         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3730         wr_reg16(info, RCR, val);                  /* clear reset bit */
3731
3732         rdma_reset(info);
3733         reset_rbufs(info);
3734
3735         /* set 1st descriptor address */
3736         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3737
3738         if (info->params.mode != MGSL_MODE_ASYNC) {
3739                 /* enable rx DMA and DMA interrupt */
3740                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3741         } else {
3742                 /* enable saving of rx status, rx DMA and DMA interrupt */
3743                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3744         }
3745
3746         slgt_irq_on(info, IRQ_RXOVER);
3747
3748         /* enable receiver */
3749         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3750
3751         info->rx_restart = 0;
3752         info->rx_enabled = 1;
3753 }
3754
3755 static void tx_start(struct slgt_info *info)
3756 {
3757         if (!info->tx_enabled) {
3758                 wr_reg16(info, TCR,
3759                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3760                 info->tx_enabled = TRUE;
3761         }
3762
3763         if (info->tx_count) {
3764                 info->drop_rts_on_tx_done = 0;
3765
3766                 if (info->params.mode != MGSL_MODE_ASYNC) {
3767                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3768                                 get_signals(info);
3769                                 if (!(info->signals & SerialSignal_RTS)) {
3770                                         info->signals |= SerialSignal_RTS;
3771                                         set_signals(info);
3772                                         info->drop_rts_on_tx_done = 1;
3773                                 }
3774                         }
3775
3776                         slgt_irq_off(info, IRQ_TXDATA);
3777                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3778                         /* clear tx idle and underrun status bits */
3779                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3780
3781                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3782                                 /* tx DMA stopped, restart tx DMA */
3783                                 tdma_reset(info);
3784                                 /* set 1st descriptor address */
3785                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3786                                 switch(info->params.mode) {
3787                                 case MGSL_MODE_RAW:
3788                                 case MGSL_MODE_MONOSYNC:
3789                                 case MGSL_MODE_BISYNC:
3790                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3791                                         break;
3792                                 default:
3793                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3794                                 }
3795                         }
3796
3797                         if (info->params.mode == MGSL_MODE_HDLC) {
3798                                 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3799                                 add_timer(&info->tx_timer);
3800                         }
3801                 } else {
3802                         tdma_reset(info);
3803                         /* set 1st descriptor address */
3804                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3805
3806                         slgt_irq_off(info, IRQ_TXDATA);
3807                         slgt_irq_on(info, IRQ_TXIDLE);
3808                         /* clear tx idle status bit */
3809                         wr_reg16(info, SSR, IRQ_TXIDLE);
3810
3811                         /* enable tx DMA */
3812                         wr_reg32(info, TDCSR, BIT0);
3813                 }
3814
3815                 info->tx_active = 1;
3816         }
3817 }
3818
3819 static void tx_stop(struct slgt_info *info)
3820 {
3821         unsigned short val;
3822
3823         del_timer(&info->tx_timer);
3824
3825         tdma_reset(info);
3826
3827         /* reset and disable transmitter */
3828         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3829         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3830
3831         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3832
3833         /* clear tx idle and underrun status bit */
3834         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3835
3836         reset_tbufs(info);
3837
3838         info->tx_enabled = 0;
3839         info->tx_active  = 0;
3840 }
3841
3842 static void reset_port(struct slgt_info *info)
3843 {
3844         if (!info->reg_addr)
3845                 return;
3846
3847         tx_stop(info);
3848         rx_stop(info);
3849
3850         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3851         set_signals(info);
3852
3853         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3854 }
3855
3856 static void reset_adapter(struct slgt_info *info)
3857 {
3858         int i;
3859         for (i=0; i < info->port_count; ++i) {
3860                 if (info->port_array[i])
3861                         reset_port(info->port_array[i]);
3862         }
3863 }
3864
3865 static void async_mode(struct slgt_info *info)
3866 {
3867         unsigned short val;
3868
3869         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3870         tx_stop(info);
3871         rx_stop(info);
3872
3873         /* TCR (tx control)
3874          *
3875          * 15..13  mode, 010=async
3876          * 12..10  encoding, 000=NRZ
3877          * 09      parity enable
3878          * 08      1=odd parity, 0=even parity
3879          * 07      1=RTS driver control
3880          * 06      1=break enable
3881          * 05..04  character length
3882          *         00=5 bits
3883          *         01=6 bits
3884          *         10=7 bits
3885          *         11=8 bits
3886          * 03      0=1 stop bit, 1=2 stop bits
3887          * 02      reset
3888          * 01      enable
3889          * 00      auto-CTS enable
3890          */
3891         val = 0x4000;
3892
3893         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3894                 val |= BIT7;
3895
3896         if (info->params.parity != ASYNC_PARITY_NONE) {
3897                 val |= BIT9;
3898                 if (info->params.parity == ASYNC_PARITY_ODD)
3899                         val |= BIT8;
3900         }
3901
3902         switch (info->params.data_bits)
3903         {
3904         case 6: val |= BIT4; break;
3905         case 7: val |= BIT5; break;
3906         case 8: val |= BIT5 + BIT4; break;
3907         }
3908
3909         if (info->params.stop_bits != 1)
3910                 val |= BIT3;
3911
3912         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3913                 val |= BIT0;
3914
3915         wr_reg16(info, TCR, val);
3916
3917         /* RCR (rx control)
3918          *
3919          * 15..13  mode, 010=async
3920          * 12..10  encoding, 000=NRZ
3921          * 09      parity enable
3922          * 08      1=odd parity, 0=even parity
3923          * 07..06  reserved, must be 0
3924          * 05..04  character length
3925          *         00=5 bits
3926          *         01=6 bits
3927          *         10=7 bits
3928          *         11=8 bits
3929          * 03      reserved, must be zero
3930          * 02      reset
3931          * 01      enable
3932          * 00      auto-DCD enable
3933          */
3934         val = 0x4000;
3935
3936         if (info->params.parity != ASYNC_PARITY_NONE) {
3937                 val |= BIT9;
3938                 if (info->params.parity == ASYNC_PARITY_ODD)
3939                         val |= BIT8;
3940         }
3941
3942         switch (info->params.data_bits)
3943         {
3944         case 6: val |= BIT4; break;
3945         case 7: val |= BIT5; break;
3946         case 8: val |= BIT5 + BIT4; break;
3947         }
3948
3949         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3950                 val |= BIT0;
3951
3952         wr_reg16(info, RCR, val);
3953
3954         /* CCR (clock control)
3955          *
3956          * 07..05  011 = tx clock source is BRG/16
3957          * 04..02  010 = rx clock source is BRG
3958          * 01      0 = auxclk disabled
3959          * 00      1 = BRG enabled
3960          *
3961          * 0110 1001
3962          */
3963         wr_reg8(info, CCR, 0x69);
3964
3965         msc_set_vcr(info);
3966
3967         /* SCR (serial control)
3968          *
3969          * 15  1=tx req on FIFO half empty
3970          * 14  1=rx req on FIFO half full
3971          * 13  tx data  IRQ enable
3972          * 12  tx idle  IRQ enable
3973          * 11  rx break on IRQ enable
3974          * 10  rx data  IRQ enable
3975          * 09  rx break off IRQ enable
3976          * 08  overrun  IRQ enable
3977          * 07  DSR      IRQ enable
3978          * 06  CTS      IRQ enable
3979          * 05  DCD      IRQ enable
3980          * 04  RI       IRQ enable
3981          * 03  reserved, must be zero
3982          * 02  1=txd->rxd internal loopback enable
3983          * 01  reserved, must be zero
3984          * 00  1=master IRQ enable
3985          */
3986         val = BIT15 + BIT14 + BIT0;
3987         wr_reg16(info, SCR, val);
3988
3989         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3990
3991         set_rate(info, info->params.data_rate * 16);
3992
3993         if (info->params.loopback)
3994                 enable_loopback(info);
3995 }
3996
3997 static void sync_mode(struct slgt_info *info)
3998 {
3999         unsigned short val;
4000
4001         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4002         tx_stop(info);
4003         rx_stop(info);
4004
4005         /* TCR (tx control)
4006          *
4007          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4008          * 12..10  encoding
4009          * 09      CRC enable
4010          * 08      CRC32
4011          * 07      1=RTS driver control
4012          * 06      preamble enable
4013          * 05..04  preamble length
4014          * 03      share open/close flag
4015          * 02      reset
4016          * 01      enable
4017          * 00      auto-CTS enable
4018          */
4019         val = 0;
4020
4021         switch(info->params.mode) {
4022         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4023         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4024         case MGSL_MODE_RAW:      val |= BIT13; break;
4025         }
4026         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4027                 val |= BIT7;
4028
4029         switch(info->params.encoding)
4030         {
4031         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4032         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4033         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4034         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4035         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4036         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4037         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4038         }
4039
4040         switch (info->params.crc_type & HDLC_CRC_MASK)
4041         {
4042         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4043         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4044         }
4045
4046         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4047                 val |= BIT6;
4048
4049         switch (info->params.preamble_length)
4050         {
4051         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4052         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4053         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4054         }
4055
4056         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4057                 val |= BIT0;
4058
4059         wr_reg16(info, TCR, val);
4060
4061         /* TPR (transmit preamble) */
4062
4063         switch (info->params.preamble)
4064         {
4065         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4066         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4067         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4068         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4069         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4070         default:                          val = 0x7e; break;
4071         }
4072         wr_reg8(info, TPR, (unsigned char)val);
4073
4074         /* RCR (rx control)
4075          *
4076          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4077          * 12..10  encoding
4078          * 09      CRC enable
4079          * 08      CRC32
4080          * 07..03  reserved, must be 0
4081          * 02      reset
4082          * 01      enable
4083          * 00      auto-DCD enable
4084          */
4085         val = 0;
4086
4087         switch(info->params.mode) {
4088         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4089         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4090         case MGSL_MODE_RAW:      val |= BIT13; break;
4091         }
4092
4093         switch(info->params.encoding)
4094         {
4095         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4096         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4097         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4098         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4099         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4100         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4101         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4102         }
4103
4104         switch (info->params.crc_type & HDLC_CRC_MASK)
4105         {
4106         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4107         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4108         }
4109
4110         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4111                 val |= BIT0;
4112
4113         wr_reg16(info, RCR, val);
4114
4115         /* CCR (clock control)
4116          *
4117          * 07..05  tx clock source
4118          * 04..02  rx clock source
4119          * 01      auxclk enable
4120          * 00      BRG enable
4121          */
4122         val = 0;
4123
4124         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4125         {
4126                 // when RxC source is DPLL, BRG generates 16X DPLL
4127                 // reference clock, so take TxC from BRG/16 to get
4128                 // transmit clock at actual data rate
4129                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4130                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4131                 else
4132                         val |= BIT6;    /* 010, txclk = BRG */
4133         }
4134         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4135                 val |= BIT7;    /* 100, txclk = DPLL Input */
4136         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4137                 val |= BIT5;    /* 001, txclk = RXC Input */
4138
4139         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4140                 val |= BIT3;    /* 010, rxclk = BRG */
4141         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4142                 val |= BIT4;    /* 100, rxclk = DPLL */
4143         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4144                 val |= BIT2;    /* 001, rxclk = TXC Input */
4145
4146         if (info->params.clock_speed)
4147                 val |= BIT1 + BIT0;
4148
4149         wr_reg8(info, CCR, (unsigned char)val);
4150
4151         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4152         {
4153                 // program DPLL mode
4154                 switch(info->params.encoding)
4155                 {
4156                 case HDLC_ENCODING_BIPHASE_MARK:
4157                 case HDLC_ENCODING_BIPHASE_SPACE:
4158                         val = BIT7; break;
4159                 case HDLC_ENCODING_BIPHASE_LEVEL:
4160                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4161                         val = BIT7 + BIT6; break;
4162                 default: val = BIT6;    // NRZ encodings
4163                 }
4164                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4165
4166                 // DPLL requires a 16X reference clock from BRG
4167                 set_rate(info, info->params.clock_speed * 16);
4168         }
4169         else
4170                 set_rate(info, info->params.clock_speed);
4171
4172         tx_set_idle(info);
4173
4174         msc_set_vcr(info);
4175
4176         /* SCR (serial control)
4177          *
4178          * 15  1=tx req on FIFO half empty
4179          * 14  1=rx req on FIFO half full
4180          * 13  tx data  IRQ enable
4181          * 12  tx idle  IRQ enable
4182          * 11  underrun IRQ enable
4183          * 10  rx data  IRQ enable
4184          * 09  rx idle  IRQ enable
4185          * 08  overrun  IRQ enable
4186          * 07  DSR      IRQ enable
4187          * 06  CTS      IRQ enable
4188          * 05  DCD      IRQ enable
4189          * 04  RI       IRQ enable
4190          * 03  reserved, must be zero
4191          * 02  1=txd->rxd internal loopback enable
4192          * 01  reserved, must be zero
4193          * 00  1=master IRQ enable
4194          */
4195         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4196
4197         if (info->params.loopback)
4198                 enable_loopback(info);
4199 }
4200
4201 /*
4202  *  set transmit idle mode
4203  */
4204 static void tx_set_idle(struct slgt_info *info)
4205 {
4206         unsigned char val;
4207         unsigned short tcr;
4208
4209         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4210          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4211          */
4212         tcr = rd_reg16(info, TCR);
4213         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4214                 /* disable preamble, set idle size to 16 bits */
4215                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4216                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4217                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4218         } else if (!(tcr & BIT6)) {
4219                 /* preamble is disabled, set idle size to 8 bits */
4220                 tcr &= ~(BIT5 + BIT4);
4221         }
4222         wr_reg16(info, TCR, tcr);
4223
4224         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4225                 /* LSB of custom tx idle specified in tx idle register */
4226                 val = (unsigned char)(info->idle_mode & 0xff);
4227         } else {
4228                 /* standard 8 bit idle patterns */
4229                 switch(info->idle_mode)
4230                 {
4231                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4232                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4233                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4234                 case HDLC_TXIDLE_ZEROS:
4235                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4236                 default:                         val = 0xff;
4237                 }
4238         }
4239
4240         wr_reg8(info, TIR, val);
4241 }
4242
4243 /*
4244  * get state of V24 status (input) signals
4245  */
4246 static void get_signals(struct slgt_info *info)
4247 {
4248         unsigned short status = rd_reg16(info, SSR);
4249
4250         /* clear all serial signals except DTR and RTS */
4251         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4252
4253         if (status & BIT3)
4254                 info->signals |= SerialSignal_DSR;
4255         if (status & BIT2)
4256                 info->signals |= SerialSignal_CTS;
4257         if (status & BIT1)
4258                 info->signals |= SerialSignal_DCD;
4259         if (status & BIT0)
4260                 info->signals |= SerialSignal_RI;
4261 }
4262
4263 /*
4264  * set V.24 Control Register based on current configuration
4265  */
4266 static void msc_set_vcr(struct slgt_info *info)
4267 {
4268         unsigned char val = 0;
4269
4270         /* VCR (V.24 control)
4271          *
4272          * 07..04  serial IF select
4273          * 03      DTR
4274          * 02      RTS
4275          * 01      LL
4276          * 00      RL
4277          */
4278
4279         switch(info->if_mode & MGSL_INTERFACE_MASK)
4280         {
4281         case MGSL_INTERFACE_RS232:
4282                 val |= BIT5; /* 0010 */
4283                 break;
4284         case MGSL_INTERFACE_V35:
4285                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4286                 break;
4287         case MGSL_INTERFACE_RS422:
4288                 val |= BIT6; /* 0100 */
4289                 break;
4290         }
4291
4292         if (info->signals & SerialSignal_DTR)
4293                 val |= BIT3;
4294         if (info->signals & SerialSignal_RTS)
4295                 val |= BIT2;
4296         if (info->if_mode & MGSL_INTERFACE_LL)
4297                 val |= BIT1;
4298         if (info->if_mode & MGSL_INTERFACE_RL)
4299                 val |= BIT0;
4300         wr_reg8(info, VCR, val);
4301 }
4302
4303 /*
4304  * set state of V24 control (output) signals
4305  */
4306 static void set_signals(struct slgt_info *info)
4307 {
4308         unsigned char val = rd_reg8(info, VCR);
4309         if (info->signals & SerialSignal_DTR)
4310                 val |= BIT3;
4311         else
4312                 val &= ~BIT3;
4313         if (info->signals & SerialSignal_RTS)
4314                 val |= BIT2;
4315         else
4316                 val &= ~BIT2;
4317         wr_reg8(info, VCR, val);
4318 }
4319
4320 /*
4321  * free range of receive DMA buffers (i to last)
4322  */
4323 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4324 {
4325         int done = 0;
4326
4327         while(!done) {
4328                 /* reset current buffer for reuse */
4329                 info->rbufs[i].status = 0;
4330                 switch(info->params.mode) {
4331                 case MGSL_MODE_RAW:
4332                 case MGSL_MODE_MONOSYNC:
4333                 case MGSL_MODE_BISYNC:
4334                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4335                         break;
4336                 default:
4337                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4338                 }
4339
4340                 if (i == last)
4341                         done = 1;
4342                 if (++i == info->rbuf_count)
4343                         i = 0;
4344         }
4345         info->rbuf_current = i;
4346 }
4347
4348 /*
4349  * mark all receive DMA buffers as free
4350  */
4351 static void reset_rbufs(struct slgt_info *info)
4352 {
4353         free_rbufs(info, 0, info->rbuf_count - 1);
4354 }
4355
4356 /*
4357  * pass receive HDLC frame to upper layer
4358  *
4359  * return 1 if frame available, otherwise 0
4360  */
4361 static int rx_get_frame(struct slgt_info *info)
4362 {
4363         unsigned int start, end;
4364         unsigned short status;
4365         unsigned int framesize = 0;
4366         int rc = 0;
4367         unsigned long flags;
4368         struct tty_struct *tty = info->tty;
4369         unsigned char addr_field = 0xff;
4370         unsigned int crc_size = 0;
4371
4372         switch (info->params.crc_type & HDLC_CRC_MASK) {
4373         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4374         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4375         }
4376
4377 check_again:
4378
4379         framesize = 0;
4380         addr_field = 0xff;
4381         start = end = info->rbuf_current;
4382
4383         for (;;) {
4384                 if (!desc_complete(info->rbufs[end]))
4385                         goto cleanup;
4386
4387                 if (framesize == 0 && info->params.addr_filter != 0xff)
4388                         addr_field = info->rbufs[end].buf[0];
4389
4390                 framesize += desc_count(info->rbufs[end]);
4391
4392                 if (desc_eof(info->rbufs[end]))
4393                         break;
4394
4395                 if (++end == info->rbuf_count)
4396                         end = 0;
4397
4398                 if (end == info->rbuf_current) {
4399                         if (info->rx_enabled){
4400                                 spin_lock_irqsave(&info->lock,flags);
4401                                 rx_start(info);
4402                                 spin_unlock_irqrestore(&info->lock,flags);
4403                         }
4404                         goto cleanup;
4405                 }
4406         }
4407
4408         /* status
4409          *
4410          * 15      buffer complete
4411          * 14..06  reserved
4412          * 05..04  residue
4413          * 02      eof (end of frame)
4414          * 01      CRC error
4415          * 00      abort
4416          */
4417         status = desc_status(info->rbufs[end]);
4418
4419         /* ignore CRC bit if not using CRC (bit is undefined) */
4420         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4421                 status &= ~BIT1;
4422
4423         if (framesize == 0 ||
4424                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4425                 free_rbufs(info, start, end);
4426                 goto check_again;
4427         }
4428
4429         if (framesize < (2 + crc_size) || status & BIT0) {
4430                 info->icount.rxshort++;
4431                 framesize = 0;
4432         } else if (status & BIT1) {
4433                 info->icount.rxcrc++;
4434                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4435                         framesize = 0;
4436         }
4437
4438 #if SYNCLINK_GENERIC_HDLC
4439         if (framesize == 0) {
4440                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4441                 stats->rx_errors++;
4442                 stats->rx_frame_errors++;
4443         }
4444 #endif
4445
4446         DBGBH(("%s rx frame status=%04X size=%d\n",
4447                 info->device_name, status, framesize));
4448         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4449
4450         if (framesize) {
4451                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4452                         framesize -= crc_size;
4453                         crc_size = 0;
4454                 }
4455
4456                 if (framesize > info->max_frame_size + crc_size)
4457                         info->icount.rxlong++;
4458                 else {
4459                         /* copy dma buffer(s) to contiguous temp buffer */
4460                         int copy_count = framesize;
4461                         int i = start;
4462                         unsigned char *p = info->tmp_rbuf;
4463                         info->tmp_rbuf_count = framesize;
4464
4465                         info->icount.rxok++;
4466
4467                         while(copy_count) {
4468                                 int partial_count = min(copy_count, DMABUFSIZE);
4469                                 memcpy(p, info->rbufs[i].buf, partial_count);
4470                                 p += partial_count;
4471                                 copy_count -= partial_count;
4472                                 if (++i == info->rbuf_count)
4473                                         i = 0;
4474                         }
4475
4476                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4477                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4478                                 framesize++;
4479                         }
4480
4481 #if SYNCLINK_GENERIC_HDLC
4482                         if (info->netcount)
4483                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4484                         else
4485 #endif
4486                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4487                 }
4488         }
4489         free_rbufs(info, start, end);
4490         rc = 1;
4491
4492 cleanup:
4493         return rc;
4494 }
4495
4496 /*
4497  * pass receive buffer (RAW synchronous mode) to tty layer
4498  * return 1 if buffer available, otherwise 0
4499  */
4500 static int rx_get_buf(struct slgt_info *info)
4501 {
4502         unsigned int i = info->rbuf_current;
4503         unsigned int count;
4504
4505         if (!desc_complete(info->rbufs[i]))
4506                 return 0;
4507         count = desc_count(info->rbufs[i]);
4508         switch(info->params.mode) {
4509         case MGSL_MODE_MONOSYNC:
4510         case MGSL_MODE_BISYNC:
4511                 /* ignore residue in byte synchronous modes */
4512                 if (desc_residue(info->rbufs[i]))
4513                         count--;
4514                 break;
4515         }
4516         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4517         DBGINFO(("rx_get_buf size=%d\n", count));
4518         if (count)
4519                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4520                                   info->flag_buf, count);
4521         free_rbufs(info, i, i);
4522         return 1;
4523 }
4524
4525 static void reset_tbufs(struct slgt_info *info)
4526 {
4527         unsigned int i;
4528         info->tbuf_current = 0;
4529         for (i=0 ; i < info->tbuf_count ; i++) {
4530                 info->tbufs[i].status = 0;
4531                 info->tbufs[i].count  = 0;
4532         }
4533 }
4534
4535 /*
4536  * return number of free transmit DMA buffers
4537  */
4538 static unsigned int free_tbuf_count(struct slgt_info *info)
4539 {
4540         unsigned int count = 0;
4541         unsigned int i = info->tbuf_current;
4542
4543         do
4544         {
4545                 if (desc_count(info->tbufs[i]))
4546                         break; /* buffer in use */
4547                 ++count;
4548                 if (++i == info->tbuf_count)
4549                         i=0;
4550         } while (i != info->tbuf_current);
4551
4552         /* last buffer with zero count may be in use, assume it is */
4553         if (count)
4554                 --count;
4555
4556         return count;
4557 }
4558
4559 /*
4560  * load transmit DMA buffer(s) with data
4561  */
4562 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4563 {
4564         unsigned short count;
4565         unsigned int i;
4566         struct slgt_desc *d;
4567
4568         if (size == 0)
4569                 return;
4570
4571         DBGDATA(info, buf, size, "tx");
4572
4573         info->tbuf_start = i = info->tbuf_current;
4574
4575         while (size) {
4576                 d = &info->tbufs[i];
4577                 if (++i == info->tbuf_count)
4578                         i = 0;
4579
4580                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4581                 memcpy(d->buf, buf, count);
4582
4583                 size -= count;
4584                 buf  += count;
4585
4586                 /*
4587                  * set EOF bit for last buffer of HDLC frame or
4588                  * for every buffer in raw mode
4589                  */
4590                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4591                     info->params.mode == MGSL_MODE_RAW)
4592                         set_desc_eof(*d, 1);
4593                 else
4594                         set_desc_eof(*d, 0);
4595
4596                 set_desc_count(*d, count);
4597         }
4598
4599         info->tbuf_current = i;
4600 }
4601
4602 static int register_test(struct slgt_info *info)
4603 {
4604         static unsigned short patterns[] =
4605                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4606         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4607         unsigned int i;
4608         int rc = 0;
4609
4610         for (i=0 ; i < count ; i++) {
4611                 wr_reg16(info, TIR, patterns[i]);
4612                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4613                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4614                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4615                         rc = -ENODEV;
4616                         break;
4617                 }
4618         }
4619         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4620         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4621         return rc;
4622 }
4623
4624 static int irq_test(struct slgt_info *info)
4625 {
4626         unsigned long timeout;
4627         unsigned long flags;
4628         struct tty_struct *oldtty = info->tty;
4629         u32 speed = info->params.data_rate;
4630
4631         info->params.data_rate = 921600;
4632         info->tty = NULL;
4633
4634         spin_lock_irqsave(&info->lock, flags);
4635         async_mode(info);
4636         slgt_irq_on(info, IRQ_TXIDLE);
4637
4638         /* enable transmitter */
4639         wr_reg16(info, TCR,
4640                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4641
4642         /* write one byte and wait for tx idle */
4643         wr_reg16(info, TDR, 0);
4644
4645         /* assume failure */
4646         info->init_error = DiagStatus_IrqFailure;
4647         info->irq_occurred = FALSE;
4648
4649         spin_unlock_irqrestore(&info->lock, flags);
4650
4651         timeout=100;
4652         while(timeout-- && !info->irq_occurred)
4653                 msleep_interruptible(10);
4654
4655         spin_lock_irqsave(&info->lock,flags);
4656         reset_port(info);
4657         spin_unlock_irqrestore(&info->lock,flags);
4658
4659         info->params.data_rate = speed;
4660         info->tty = oldtty;
4661
4662         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4663         return info->irq_occurred ? 0 : -ENODEV;
4664 }
4665
4666 static int loopback_test_rx(struct slgt_info *info)
4667 {
4668         unsigned char *src, *dest;
4669         int count;
4670
4671         if (desc_complete(info->rbufs[0])) {
4672                 count = desc_count(info->rbufs[0]);
4673                 src   = info->rbufs[0].buf;
4674                 dest  = info->tmp_rbuf;
4675
4676                 for( ; count ; count-=2, src+=2) {
4677                         /* src=data byte (src+1)=status byte */
4678                         if (!(*(src+1) & (BIT9 + BIT8))) {
4679                                 *dest = *src;
4680                                 dest++;
4681                                 info->tmp_rbuf_count++;
4682                         }
4683                 }
4684                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4685                 return 1;
4686         }
4687         return 0;
4688 }
4689
4690 static int loopback_test(struct slgt_info *info)
4691 {
4692 #define TESTFRAMESIZE 20
4693
4694         unsigned long timeout;
4695         u16 count = TESTFRAMESIZE;
4696         unsigned char buf[TESTFRAMESIZE];
4697         int rc = -ENODEV;
4698         unsigned long flags;
4699
4700         struct tty_struct *oldtty = info->tty;
4701         MGSL_PARAMS params;
4702
4703         memcpy(&params, &info->params, sizeof(params));
4704
4705         info->params.mode = MGSL_MODE_ASYNC;
4706         info->params.data_rate = 921600;
4707         info->params.loopback = 1;
4708         info->tty = NULL;
4709
4710         /* build and send transmit frame */
4711         for (count = 0; count < TESTFRAMESIZE; ++count)
4712                 buf[count] = (unsigned char)count;
4713
4714         info->tmp_rbuf_count = 0;
4715         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4716
4717         /* program hardware for HDLC and enabled receiver */
4718         spin_lock_irqsave(&info->lock,flags);
4719         async_mode(info);
4720         rx_start(info);
4721         info->tx_count = count;
4722         tx_load(info, buf, count);
4723         tx_start(info);
4724         spin_unlock_irqrestore(&info->lock, flags);
4725
4726         /* wait for receive complete */
4727         for (timeout = 100; timeout; --timeout) {
4728                 msleep_interruptible(10);
4729                 if (loopback_test_rx(info)) {
4730                         rc = 0;
4731                         break;
4732                 }
4733         }
4734
4735         /* verify received frame length and contents */
4736         if (!rc && (info->tmp_rbuf_count != count ||
4737                   memcmp(buf, info->tmp_rbuf, count))) {
4738                 rc = -ENODEV;
4739         }
4740
4741         spin_lock_irqsave(&info->lock,flags);
4742         reset_adapter(info);
4743         spin_unlock_irqrestore(&info->lock,flags);
4744
4745         memcpy(&info->params, &params, sizeof(info->params));
4746         info->tty = oldtty;
4747
4748         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4749         return rc;
4750 }
4751
4752 static int adapter_test(struct slgt_info *info)
4753 {
4754         DBGINFO(("testing %s\n", info->device_name));
4755         if (register_test(info) < 0) {
4756                 printk("register test failure %s addr=%08X\n",
4757                         info->device_name, info->phys_reg_addr);
4758         } else if (irq_test(info) < 0) {
4759                 printk("IRQ test failure %s IRQ=%d\n",
4760                         info->device_name, info->irq_level);
4761         } else if (loopback_test(info) < 0) {
4762                 printk("loopback test failure %s\n", info->device_name);
4763         }
4764         return info->init_error;
4765 }
4766
4767 /*
4768  * transmit timeout handler
4769  */
4770 static void tx_timeout(unsigned long context)
4771 {
4772         struct slgt_info *info = (struct slgt_info*)context;
4773         unsigned long flags;
4774
4775         DBGINFO(("%s tx_timeout\n", info->device_name));
4776         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4777                 info->icount.txtimeout++;
4778         }
4779         spin_lock_irqsave(&info->lock,flags);
4780         info->tx_active = 0;
4781         info->tx_count = 0;
4782         spin_unlock_irqrestore(&info->lock,flags);
4783
4784 #if SYNCLINK_GENERIC_HDLC
4785         if (info->netcount)
4786                 hdlcdev_tx_done(info);
4787         else
4788 #endif
4789                 bh_transmit(info);
4790 }
4791
4792 /*
4793  * receive buffer polling timer
4794  */
4795 static void rx_timeout(unsigned long context)
4796 {
4797         struct slgt_info *info = (struct slgt_info*)context;
4798         unsigned long flags;
4799
4800         DBGINFO(("%s rx_timeout\n", info->device_name));
4801         spin_lock_irqsave(&info->lock, flags);
4802         info->pending_bh |= BH_RECEIVE;
4803         spin_unlock_irqrestore(&info->lock, flags);
4804         bh_handler(&info->task);
4805 }
4806