drivers/ata/ahci_tegra.c

   1 /*
   2  * drivers/ata/ahci_tegra.c
   3  *
   4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Mikko Perttunen <mperttunen@nvidia.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/ahci_platform.h>
  21 #include <linux/errno.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/reset.h>
  28
  29 #include <soc/tegra/fuse.h>
  30 #include <soc/tegra/pmc.h>
  31
  32 #include "ahci.h"
  33
  34 #define SATA_CONFIGURATION_0                            0x180
  35 #define SATA_CONFIGURATION_EN_FPCI                      BIT(0)
  36
  37 #define SCFG_OFFSET                                     0x1000
  38
  39 #define T_SATA0_CFG_1                                   0x04
  40 #define T_SATA0_CFG_1_IO_SPACE                          BIT(0)
  41 #define T_SATA0_CFG_1_MEMORY_SPACE                      BIT(1)
  42 #define T_SATA0_CFG_1_BUS_MASTER                        BIT(2)
  43 #define T_SATA0_CFG_1_SERR                              BIT(8)
  44
  45 #define T_SATA0_CFG_9                                   0x24
  46 #define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT                13
  47
  48 #define SATA_FPCI_BAR5                                  0x94
  49 #define SATA_FPCI_BAR5_START_SHIFT                      4
  50
  51 #define SATA_INTR_MASK                                  0x188
  52 #define SATA_INTR_MASK_IP_INT_MASK                      BIT(16)
  53
  54 #define T_SATA0_AHCI_HBA_CAP_BKDR                       0x300
  55
  56 #define T_SATA0_BKDOOR_CC                               0x4a4
  57
  58 #define T_SATA0_CFG_SATA                                0x54c
  59 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN            BIT(12)
  60
  61 #define T_SATA0_CFG_MISC                                0x550
  62
  63 #define T_SATA0_INDEX                                   0x680
  64
  65 #define T_SATA0_CHX_PHY_CTRL1_GEN1                      0x690
  66 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK          0xff
  67 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT         0
  68 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK         (0xff << 8)
  69 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT        8
  70
  71 #define T_SATA0_CHX_PHY_CTRL1_GEN2                      0x694
  72 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK          0xff
  73 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT         0
  74 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK         (0xff << 12)
  75 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT        12
  76
  77 #define T_SATA0_CHX_PHY_CTRL2                           0x69c
  78 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1             0x23
  79
  80 #define T_SATA0_CHX_PHY_CTRL11                          0x6d0
  81 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ               (0x2800 << 16)
  82
  83 #define FUSE_SATA_CALIB                                 0x124
  84 #define FUSE_SATA_CALIB_MASK                            0x3
  85
  86 struct sata_pad_calibration {
  87         u8 gen1_tx_amp;
  88         u8 gen1_tx_peak;
  89         u8 gen2_tx_amp;
  90         u8 gen2_tx_peak;
  91 };
  92
  93 static const struct sata_pad_calibration tegra124_pad_calibration[] = {
  94         {0x18, 0x04, 0x18, 0x0a},
  95         {0x0e, 0x04, 0x14, 0x0a},
  96         {0x0e, 0x07, 0x1a, 0x0e},
  97         {0x14, 0x0e, 0x1a, 0x0e},
  98 };
  99
 100 struct tegra_ahci_priv {
 101         struct platform_device     *pdev;
 102         void __iomem               *sata_regs;
 103         struct reset_control       *sata_rst;
 104         struct reset_control       *sata_oob_rst;
 105         struct reset_control       *sata_cold_rst;
 106         /* Needs special handling, cannot use ahci_platform */
 107         struct clk                 *sata_clk;
 108         struct regulator_bulk_data supplies[5];
 109 };
 110
 111 static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 112 {
 113         struct tegra_ahci_priv *tegra = hpriv->plat_data;
 114         int ret;
 115
 116         ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
 117                                     tegra->supplies);
 118         if (ret)
 119                 return ret;
 120
 121         ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
 122                                                 tegra->sata_clk,
 123                                                 tegra->sata_rst);
 124         if (ret)
 125                 goto disable_regulators;
 126
 127         reset_control_assert(tegra->sata_oob_rst);
 128         reset_control_assert(tegra->sata_cold_rst);
 129
 130         ret = ahci_platform_enable_resources(hpriv);
 131         if (ret)
 132                 goto disable_power;
 133
 134         reset_control_deassert(tegra->sata_cold_rst);
 135         reset_control_deassert(tegra->sata_oob_rst);
 136
 137         return 0;
 138
 139 disable_power:
 140         clk_disable_unprepare(tegra->sata_clk);
 141
 142         tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 143
 144 disable_regulators:
 145         regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
 146
 147         return ret;
 148 }
 149
 150 static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
 151 {
 152         struct tegra_ahci_priv *tegra = hpriv->plat_data;
 153
 154         ahci_platform_disable_resources(hpriv);
 155
 156         reset_control_assert(tegra->sata_rst);
 157         reset_control_assert(tegra->sata_oob_rst);
 158         reset_control_assert(tegra->sata_cold_rst);
 159
 160         clk_disable_unprepare(tegra->sata_clk);
 161         tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 162
 163         regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
 164 }
 165
 166 static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
 167 {
 168         struct tegra_ahci_priv *tegra = hpriv->plat_data;
 169         int ret;
 170         unsigned int val;
 171         struct sata_pad_calibration calib;
 172
 173         ret = tegra_ahci_power_on(hpriv);
 174         if (ret) {
 175                 dev_err(&tegra->pdev->dev,
 176                         "failed to power on AHCI controller: %d\n", ret);
 177                 return ret;
 178         }
 179
 180         val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
 181         val |= SATA_CONFIGURATION_EN_FPCI;
 182         writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
 183
 184         /* Pad calibration */
 185
 186         ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
 187         if (ret) {
 188                 dev_err(&tegra->pdev->dev,
 189                         "failed to read calibration fuse: %d\n", ret);
 190                 return ret;
 191         }
 192
 193         calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
 194
 195         writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
 196
 197         val = readl(tegra->sata_regs +
 198                 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
 199         val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
 200         val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
 201         val |= calib.gen1_tx_amp <<
 202                         T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
 203         val |= calib.gen1_tx_peak <<
 204                         T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
 205         writel(val, tegra->sata_regs + SCFG_OFFSET +
 206                 T_SATA0_CHX_PHY_CTRL1_GEN1);
 207
 208         val = readl(tegra->sata_regs +
 209                         SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
 210         val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
 211         val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
 212         val |= calib.gen2_tx_amp <<
 213                         T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
 214         val |= calib.gen2_tx_peak <<
 215                         T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
 216         writel(val, tegra->sata_regs + SCFG_OFFSET +
 217                 T_SATA0_CHX_PHY_CTRL1_GEN2);
 218
 219         writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
 220                 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
 221         writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
 222                 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
 223
 224         writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
 225
 226         /* Program controller device ID */
 227
 228         val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 229         val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 230         writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 231
 232         writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
 233
 234         val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 235         val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
 236         writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
 237
 238         /* Enable IO & memory access, bus master mode */
 239
 240         val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
 241         val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
 242                 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
 243         writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
 244
 245         /* Program SATA MMIO */
 246
 247         writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
 248                tegra->sata_regs + SATA_FPCI_BAR5);
 249
 250         writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
 251                tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
 252
 253         /* Unmask SATA interrupts */
 254
 255         val = readl(tegra->sata_regs + SATA_INTR_MASK);
 256         val |= SATA_INTR_MASK_IP_INT_MASK;
 257         writel(val, tegra->sata_regs + SATA_INTR_MASK);
 258
 259         return 0;
 260 }
 261
 262 static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
 263 {
 264         tegra_ahci_power_off(hpriv);
 265 }
 266
 267 static void tegra_ahci_host_stop(struct ata_host *host)
 268 {
 269         struct ahci_host_priv *hpriv = host->private_data;
 270
 271         tegra_ahci_controller_deinit(hpriv);
 272 }
 273
 274 static struct ata_port_operations ahci_tegra_port_ops = {
 275         .inherits       = &ahci_ops,
 276         .host_stop      = tegra_ahci_host_stop,
 277 };
 278
 279 static const struct ata_port_info ahci_tegra_port_info = {
 280         .flags          = AHCI_FLAG_COMMON,
 281         .pio_mask       = ATA_PIO4,
 282         .udma_mask      = ATA_UDMA6,
 283         .port_ops       = &ahci_tegra_port_ops,
 284 };
 285
 286 static const struct of_device_id tegra_ahci_of_match[] = {
 287         { .compatible = "nvidia,tegra124-ahci" },
 288         {}
 289 };
 290 MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
 291
 292 static int tegra_ahci_probe(struct platform_device *pdev)
 293 {
 294         struct ahci_host_priv *hpriv;
 295         struct tegra_ahci_priv *tegra;
 296         struct resource *res;
 297         int ret;
 298
 299         hpriv = ahci_platform_get_resources(pdev);
 300         if (IS_ERR(hpriv))
 301                 return PTR_ERR(hpriv);
 302
 303         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 304         if (!tegra)
 305                 return -ENOMEM;
 306
 307         hpriv->plat_data = tegra;
 308
 309         tegra->pdev = pdev;
 310
 311         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 312         tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
 313         if (IS_ERR(tegra->sata_regs))
 314                 return PTR_ERR(tegra->sata_regs);
 315
 316         tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
 317         if (IS_ERR(tegra->sata_rst)) {
 318                 dev_err(&pdev->dev, "Failed to get sata reset\n");
 319                 return PTR_ERR(tegra->sata_rst);
 320         }
 321
 322         tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
 323         if (IS_ERR(tegra->sata_oob_rst)) {
 324                 dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
 325                 return PTR_ERR(tegra->sata_oob_rst);
 326         }
 327
 328         tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
 329         if (IS_ERR(tegra->sata_cold_rst)) {
 330                 dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
 331                 return PTR_ERR(tegra->sata_cold_rst);
 332         }
 333
 334         tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
 335         if (IS_ERR(tegra->sata_clk)) {
 336                 dev_err(&pdev->dev, "Failed to get sata clock\n");
 337                 return PTR_ERR(tegra->sata_clk);
 338         }
 339
 340         tegra->supplies[0].supply = "avdd";
 341         tegra->supplies[1].supply = "hvdd";
 342         tegra->supplies[2].supply = "vddio";
 343         tegra->supplies[3].supply = "target-5v";
 344         tegra->supplies[4].supply = "target-12v";
 345
 346         ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
 347                                       tegra->supplies);
 348         if (ret) {
 349                 dev_err(&pdev->dev, "Failed to get regulators\n");
 350                 return ret;
 351         }
 352
 353         ret = tegra_ahci_controller_init(hpriv);
 354         if (ret)
 355                 return ret;
 356
 357         ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info);
 358         if (ret)
 359                 goto deinit_controller;
 360
 361         return 0;
 362
 363 deinit_controller:
 364         tegra_ahci_controller_deinit(hpriv);
 365
 366         return ret;
 367 };
 368
 369 static struct platform_driver tegra_ahci_driver = {
 370         .probe = tegra_ahci_probe,
 371         .remove = ata_platform_remove_one,
 372         .driver = {
 373                 .name = "tegra-ahci",
 374                 .of_match_table = tegra_ahci_of_match,
 375         },
 376         /* LP0 suspend support not implemented */
 377 };
 378 module_platform_driver(tegra_ahci_driver);
 379
 380 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
 381 MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
 382 MODULE_LICENSE("GPL v2");