drivers/ata/ahci_imx.c

   1 /*
   2  * copyright (c) 2013 Freescale Semiconductor, Inc.
   3  * Freescale IMX AHCI SATA platform driver
   4  *
   5  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program. If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/ahci_platform.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  28 #include <linux/libata.h>
  29 #include "ahci.h"
  30
  31 enum {
  32         PORT_PHY_CTL = 0x178,                   /* Port0 PHY Control */
  33         PORT_PHY_CTL_PDDQ_LOC = 0x100000,       /* PORT_PHY_CTL bits */
  34         HOST_TIMER1MS = 0xe0,                   /* Timer 1-ms */
  35 };
  36
  37 struct imx_ahci_priv {
  38         struct platform_device *ahci_pdev;
  39         struct clk *sata_ref_clk;
  40         struct clk *ahb_clk;
  41         struct regmap *gpr;
  42         bool no_device;
  43         bool first_time;
  44 };
  45
  46 static int ahci_imx_hotplug;
  47 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
  48 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
  49
  50 static void ahci_imx_error_handler(struct ata_port *ap)
  51 {
  52         u32 reg_val;
  53         struct ata_device *dev;
  54         struct ata_host *host = dev_get_drvdata(ap->dev);
  55         struct ahci_host_priv *hpriv = host->private_data;
  56         void __iomem *mmio = hpriv->mmio;
  57         struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
  58
  59         ahci_error_handler(ap);
  60
  61         if (!(imxpriv->first_time) || ahci_imx_hotplug)
  62                 return;
  63
  64         imxpriv->first_time = false;
  65
  66         ata_for_each_dev(dev, &ap->link, ENABLED)
  67                 return;
  68         /*
  69          * Disable link to save power.  An imx ahci port can't be recovered
  70          * without full reset once the pddq mode is enabled making it
  71          * impossible to use as part of libata LPM.
  72          */
  73         reg_val = readl(mmio + PORT_PHY_CTL);
  74         writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
  75         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
  76                         IMX6Q_GPR13_SATA_MPLL_CLK_EN,
  77                         !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
  78         clk_disable_unprepare(imxpriv->sata_ref_clk);
  79         imxpriv->no_device = true;
  80 }
  81
  82 static struct ata_port_operations ahci_imx_ops = {
  83         .inherits       = &ahci_platform_ops,
  84         .error_handler  = ahci_imx_error_handler,
  85 };
  86
  87 static const struct ata_port_info ahci_imx_port_info = {
  88         .flags          = AHCI_FLAG_COMMON,
  89         .pio_mask       = ATA_PIO4,
  90         .udma_mask      = ATA_UDMA6,
  91         .port_ops       = &ahci_imx_ops,
  92 };
  93
  94 static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
  95 {
  96         int ret = 0;
  97         unsigned int reg_val;
  98         struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
  99
 100         imxpriv->gpr =
 101                 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 102         if (IS_ERR(imxpriv->gpr)) {
 103                 dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
 104                 return PTR_ERR(imxpriv->gpr);
 105         }
 106
 107         ret = clk_prepare_enable(imxpriv->sata_ref_clk);
 108         if (ret < 0) {
 109                 dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
 110                 return ret;
 111         }
 112
 113         /*
 114          * set PHY Paremeters, two steps to configure the GPR13,
 115          * one write for rest of parameters, mask of first write
 116          * is 0x07fffffd, and the other one write for setting
 117          * the mpll_clk_en.
 118          */
 119         regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
 120                         | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
 121                         | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
 122                         | IMX6Q_GPR13_SATA_SPD_MODE_MASK
 123                         | IMX6Q_GPR13_SATA_MPLL_SS_EN
 124                         | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
 125                         | IMX6Q_GPR13_SATA_TX_BOOST_MASK
 126                         | IMX6Q_GPR13_SATA_TX_LVL_MASK
 127                         | IMX6Q_GPR13_SATA_TX_EDGE_RATE
 128                         , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
 129                         | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
 130                         | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
 131                         | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
 132                         | IMX6Q_GPR13_SATA_MPLL_SS_EN
 133                         | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
 134                         | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
 135                         | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
 136         regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 137                         IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 138         usleep_range(100, 200);
 139
 140         /*
 141          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
 142          * and IP vendor specific register HOST_TIMER1MS.
 143          * Configure CAP_SSS (support stagered spin up).
 144          * Implement the port0.
 145          * Get the ahb clock rate, and configure the TIMER1MS register.
 146          */
 147         reg_val = readl(mmio + HOST_CAP);
 148         if (!(reg_val & HOST_CAP_SSS)) {
 149                 reg_val |= HOST_CAP_SSS;
 150                 writel(reg_val, mmio + HOST_CAP);
 151         }
 152         reg_val = readl(mmio + HOST_PORTS_IMPL);
 153         if (!(reg_val & 0x1)) {
 154                 reg_val |= 0x1;
 155                 writel(reg_val, mmio + HOST_PORTS_IMPL);
 156         }
 157
 158         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
 159         writel(reg_val, mmio + HOST_TIMER1MS);
 160
 161         return 0;
 162 }
 163
 164 static void imx6q_sata_exit(struct device *dev)
 165 {
 166         struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
 167
 168         regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 169                         !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 170         clk_disable_unprepare(imxpriv->sata_ref_clk);
 171 }
 172
 173 static int imx_ahci_suspend(struct device *dev)
 174 {
 175         struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
 176
 177         /*
 178          * If no_device is set, The CLKs had been gated off in the
 179          * initialization so don't do it again here.
 180          */
 181         if (!imxpriv->no_device) {
 182                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 183                                 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 184                                 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 185                 clk_disable_unprepare(imxpriv->sata_ref_clk);
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int imx_ahci_resume(struct device *dev)
 192 {
 193         struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
 194         int ret;
 195
 196         if (!imxpriv->no_device) {
 197                 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
 198                 if (ret < 0) {
 199                         dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
 200                         return ret;
 201                 }
 202
 203                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 204                                 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 205                                 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 206                 usleep_range(1000, 2000);
 207         }
 208
 209         return 0;
 210 }
 211
 212 static struct ahci_platform_data imx6q_sata_pdata = {
 213         .init = imx6q_sata_init,
 214         .exit = imx6q_sata_exit,
 215         .ata_port_info = &ahci_imx_port_info,
 216         .suspend = imx_ahci_suspend,
 217         .resume = imx_ahci_resume,
 218 };
 219
 220 static const struct of_device_id imx_ahci_of_match[] = {
 221         { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
 222         {},
 223 };
 224 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 225
 226 static int imx_ahci_probe(struct platform_device *pdev)
 227 {
 228         struct device *dev = &pdev->dev;
 229         struct resource *mem, *irq, res[2];
 230         const struct of_device_id *of_id;
 231         const struct ahci_platform_data *pdata = NULL;
 232         struct imx_ahci_priv *imxpriv;
 233         struct device *ahci_dev;
 234         struct platform_device *ahci_pdev;
 235         int ret;
 236
 237         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
 238         if (!imxpriv) {
 239                 dev_err(dev, "can't alloc ahci_host_priv\n");
 240                 return -ENOMEM;
 241         }
 242
 243         ahci_pdev = platform_device_alloc("ahci", -1);
 244         if (!ahci_pdev)
 245                 return -ENODEV;
 246
 247         ahci_dev = &ahci_pdev->dev;
 248         ahci_dev->parent = dev;
 249
 250         imxpriv->no_device = false;
 251         imxpriv->first_time = true;
 252         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
 253         if (IS_ERR(imxpriv->ahb_clk)) {
 254                 dev_err(dev, "can't get ahb clock.\n");
 255                 ret = PTR_ERR(imxpriv->ahb_clk);
 256                 goto err_out;
 257         }
 258
 259         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
 260         if (IS_ERR(imxpriv->sata_ref_clk)) {
 261                 dev_err(dev, "can't get sata_ref clock.\n");
 262                 ret = PTR_ERR(imxpriv->sata_ref_clk);
 263                 goto err_out;
 264         }
 265
 266         imxpriv->ahci_pdev = ahci_pdev;
 267         platform_set_drvdata(pdev, imxpriv);
 268
 269         of_id = of_match_device(imx_ahci_of_match, dev);
 270         if (of_id) {
 271                 pdata = of_id->data;
 272         } else {
 273                 ret = -EINVAL;
 274                 goto err_out;
 275         }
 276
 277         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 278         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 279         if (!mem || !irq) {
 280                 dev_err(dev, "no mmio/irq resource\n");
 281                 ret = -ENOMEM;
 282                 goto err_out;
 283         }
 284
 285         res[0] = *mem;
 286         res[1] = *irq;
 287
 288         ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
 289         ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
 290         ahci_dev->of_node = dev->of_node;
 291
 292         ret = platform_device_add_resources(ahci_pdev, res, 2);
 293         if (ret)
 294                 goto err_out;
 295
 296         ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
 297         if (ret)
 298                 goto err_out;
 299
 300         ret = platform_device_add(ahci_pdev);
 301         if (ret) {
 302 err_out:
 303                 platform_device_put(ahci_pdev);
 304                 return ret;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int imx_ahci_remove(struct platform_device *pdev)
 311 {
 312         struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
 313         struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
 314
 315         platform_device_unregister(ahci_pdev);
 316         return 0;
 317 }
 318
 319 static struct platform_driver imx_ahci_driver = {
 320         .probe = imx_ahci_probe,
 321         .remove = imx_ahci_remove,
 322         .driver = {
 323                 .name = "ahci-imx",
 324                 .owner = THIS_MODULE,
 325                 .of_match_table = imx_ahci_of_match,
 326         },
 327 };
 328 module_platform_driver(imx_ahci_driver);
 329
 330 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
 331 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
 332 MODULE_LICENSE("GPL");
 333 MODULE_ALIAS("ahci:imx");