2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
10 #include <asm/processor.h>
14 /* By default disabled */
15 int mce_p5_enabled __read_mostly;
17 /* Machine check handler for Pentium class Intel CPUs: */
18 static void pentium_machine_check(struct pt_regs *regs, long error_code)
20 u32 loaddr, hi, lotype;
22 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
23 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
26 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
27 smp_processor_id(), loaddr, lotype);
29 if (lotype & (1<<5)) {
31 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
35 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
38 /* Set up machine check reporting for processors with Intel style MCE: */
39 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
43 /* Default P5 to off as its often misconnected: */
47 /* Check for MCE support: */
48 if (!cpu_has(c, X86_FEATURE_MCE))
51 machine_check_vector = pentium_machine_check;
52 /* Make sure the vector pointer is visible before we enable MCEs: */
55 /* Read registers before enabling: */
56 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
57 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
59 "Intel old style machine check architecture supported.\n");
62 set_in_cr4(X86_CR4_MCE);
64 "Intel old style machine check reporting enabled on CPU#%d.\n",