arch/sparc64/kernel/pci_sabre.c

   1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
   2  * pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/pbm.h>
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/oplib.h>
  22
  23 #include "pci_impl.h"
  24 #include "iommu_common.h"
  25
  26 /* All SABRE registers are 64-bits.  The following accessor
  27  * routines are how they are accessed.  The REG parameter
  28  * is a physical address.
  29  */
  30 #define sabre_read(__reg) \
  31 ({      u64 __ret; \
  32         __asm__ __volatile__("ldxa [%1] %2, %0" \
  33                              : "=r" (__ret) \
  34                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  35                              : "memory"); \
  36         __ret; \
  37 })
  38 #define sabre_write(__reg, __val) \
  39         __asm__ __volatile__("stxa %0, [%1] %2" \
  40                              : /* no outputs */ \
  41                              : "r" (__val), "r" (__reg), \
  42                                "i" (ASI_PHYS_BYPASS_EC_E) \
  43                              : "memory")
  44
  45 /* SABRE PCI controller register offsets and definitions. */
  46 #define SABRE_UE_AFSR           0x0030UL
  47 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  48 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  49 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  50 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  51 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  52 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  53 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  54 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  55 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  56 #define SABRE_UECE_AFAR         0x0038UL
  57 #define SABRE_CE_AFSR           0x0040UL
  58 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  59 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  60 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  61 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  62 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  63 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  64 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  65 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  66 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  67 #define SABRE_IOMMU_CONTROL     0x0200UL
  68 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  69 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  70 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  71 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  72 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  73 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  74 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  75 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  76 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  77 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  78 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  79 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  80 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  81 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  82 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  83 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  84 #define SABRE_IOMMU_TSBBASE     0x0208UL
  85 #define SABRE_IOMMU_FLUSH       0x0210UL
  86 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  87 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  88 #define SABRE_IMAP_SCSI         0x1000UL
  89 #define SABRE_IMAP_ETH          0x1008UL
  90 #define SABRE_IMAP_BPP          0x1010UL
  91 #define SABRE_IMAP_AU_REC       0x1018UL
  92 #define SABRE_IMAP_AU_PLAY      0x1020UL
  93 #define SABRE_IMAP_PFAIL        0x1028UL
  94 #define SABRE_IMAP_KMS          0x1030UL
  95 #define SABRE_IMAP_FLPY         0x1038UL
  96 #define SABRE_IMAP_SHW          0x1040UL
  97 #define SABRE_IMAP_KBD          0x1048UL
  98 #define SABRE_IMAP_MS           0x1050UL
  99 #define SABRE_IMAP_SER          0x1058UL
 100 #define SABRE_IMAP_UE           0x1070UL
 101 #define SABRE_IMAP_CE           0x1078UL
 102 #define SABRE_IMAP_PCIERR       0x1080UL
 103 #define SABRE_IMAP_GFX          0x1098UL
 104 #define SABRE_IMAP_EUPA         0x10a0UL
 105 #define SABRE_ICLR_A_SLOT0      0x1400UL
 106 #define SABRE_ICLR_B_SLOT0      0x1480UL
 107 #define SABRE_ICLR_SCSI         0x1800UL
 108 #define SABRE_ICLR_ETH          0x1808UL
 109 #define SABRE_ICLR_BPP          0x1810UL
 110 #define SABRE_ICLR_AU_REC       0x1818UL
 111 #define SABRE_ICLR_AU_PLAY      0x1820UL
 112 #define SABRE_ICLR_PFAIL        0x1828UL
 113 #define SABRE_ICLR_KMS          0x1830UL
 114 #define SABRE_ICLR_FLPY         0x1838UL
 115 #define SABRE_ICLR_SHW          0x1840UL
 116 #define SABRE_ICLR_KBD          0x1848UL
 117 #define SABRE_ICLR_MS           0x1850UL
 118 #define SABRE_ICLR_SER          0x1858UL
 119 #define SABRE_ICLR_UE           0x1870UL
 120 #define SABRE_ICLR_CE           0x1878UL
 121 #define SABRE_ICLR_PCIERR       0x1880UL
 122 #define SABRE_WRSYNC            0x1c20UL
 123 #define SABRE_PCICTRL           0x2000UL
 124 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 125 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 126 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 127 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 128 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 129 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 130 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 131 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 132 #define SABRE_PIOAFSR           0x2010UL
 133 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 134 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 135 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 136 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 137 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 138 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 139 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 140 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 141 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 142 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 143 #define SABRE_PIOAFAR           0x2018UL
 144 #define SABRE_PCIDIAG           0x2020UL
 145 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 146 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 147 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 148 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 149 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 150 #define SABRE_PCITASR           0x2028UL
 151 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 152 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 153 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 154 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 155 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 156 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 157 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 158 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 159 #define SABRE_PIOBUF_DIAG       0x5000UL
 160 #define SABRE_DMABUF_DIAGLO     0x5100UL
 161 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 162 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 163 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 164 #define SABRE_IOMMU_VADIAG      0xa400UL
 165 #define SABRE_IOMMU_TCDIAG      0xa408UL
 166 #define SABRE_IOMMU_TAG         0xa580UL
 167 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 168 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 169 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 170 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 171 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 172 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 173 #define SABRE_IOMMU_DATA        0xa600UL
 174 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 175 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 176 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 177 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 178 #define SABRE_PCI_IRQSTATE      0xa800UL
 179 #define SABRE_OBIO_IRQSTATE     0xa808UL
 180 #define SABRE_FFBCFG            0xf000UL
 181 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 182 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 183 #define SABRE_MCCTRL0           0xf010UL
 184 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 185 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 186 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 187 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 188 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 189 #define SABRE_MCCTRL1           0xf018UL
 190 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 191 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 192 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 193 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 194 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 195 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 196 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 197 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 198 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 199 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 200 #define SABRE_RESETCTRL         0xf020UL
 201
 202 #define SABRE_CONFIGSPACE       0x001000000UL
 203 #define SABRE_IOSPACE           0x002000000UL
 204 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 205 #define SABRE_MEMSPACE          0x100000000UL
 206 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 207
 208 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
 209  * configuration space address format:
 210  *
 211  *  32             24 23 16 15    11 10       8 7   2  1 0
 212  * ---------------------------------------------------------
 213  * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
 214  * ---------------------------------------------------------
 215  */
 216 #define SABRE_CONFIG_BASE(PBM)  \
 217         ((PBM)->config_space | (1UL << 24))
 218 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
 219         (((unsigned long)(BUS)   << 16) |       \
 220          ((unsigned long)(DEVFN) << 8)  |       \
 221          ((unsigned long)(REG)))
 222
 223 static int hummingbird_p;
 224 static struct pci_bus *sabre_root_bus;
 225
 226 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
 227                                      unsigned char bus,
 228                                      unsigned int devfn,
 229                                      int where)
 230 {
 231         if (!pbm)
 232                 return NULL;
 233         return (void *)
 234                 (SABRE_CONFIG_BASE(pbm) |
 235                  SABRE_CONFIG_ENCODE(bus, devfn, where));
 236 }
 237
 238 static int sabre_out_of_range(unsigned char devfn)
 239 {
 240         if (hummingbird_p)
 241                 return 0;
 242
 243         return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
 244                 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
 245                 (PCI_SLOT(devfn) > 1));
 246 }
 247
 248 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
 249                                 unsigned char bus,
 250                                 unsigned char devfn)
 251 {
 252         if (hummingbird_p)
 253                 return 0;
 254
 255         return ((pbm->parent == 0) ||
 256                 ((pbm == &pbm->parent->pbm_B) &&
 257                  (bus == pbm->pci_first_busno) &&
 258                  PCI_SLOT(devfn) > 8) ||
 259                 ((pbm == &pbm->parent->pbm_A) &&
 260                  (bus == pbm->pci_first_busno) &&
 261                  PCI_SLOT(devfn) > 8));
 262 }
 263
 264 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 265                                 int where, int size, u32 *value)
 266 {
 267         struct pci_pbm_info *pbm = bus_dev->sysdata;
 268         unsigned char bus = bus_dev->number;
 269         u32 *addr;
 270         u16 tmp16;
 271         u8 tmp8;
 272
 273         switch (size) {
 274         case 1:
 275                 *value = 0xff;
 276                 break;
 277         case 2:
 278                 *value = 0xffff;
 279                 break;
 280         case 4:
 281                 *value = 0xffffffff;
 282                 break;
 283         }
 284
 285         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 286         if (!addr)
 287                 return PCIBIOS_SUCCESSFUL;
 288
 289         if (__sabre_out_of_range(pbm, bus, devfn))
 290                 return PCIBIOS_SUCCESSFUL;
 291
 292         switch (size) {
 293         case 1:
 294                 pci_config_read8((u8 *) addr, &tmp8);
 295                 *value = tmp8;
 296                 break;
 297
 298         case 2:
 299                 if (where & 0x01) {
 300                         printk("pci_read_config_word: misaligned reg [%x]\n",
 301                                where);
 302                         return PCIBIOS_SUCCESSFUL;
 303                 }
 304                 pci_config_read16((u16 *) addr, &tmp16);
 305                 *value = tmp16;
 306                 break;
 307
 308         case 4:
 309                 if (where & 0x03) {
 310                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 311                                where);
 312                         return PCIBIOS_SUCCESSFUL;
 313                 }
 314                 pci_config_read32(addr, value);
 315                 break;
 316         }
 317
 318         return PCIBIOS_SUCCESSFUL;
 319 }
 320
 321 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 322                               int where, int size, u32 *value)
 323 {
 324         if (!bus->number && sabre_out_of_range(devfn)) {
 325                 switch (size) {
 326                 case 1:
 327                         *value = 0xff;
 328                         break;
 329                 case 2:
 330                         *value = 0xffff;
 331                         break;
 332                 case 4:
 333                         *value = 0xffffffff;
 334                         break;
 335                 }
 336                 return PCIBIOS_SUCCESSFUL;
 337         }
 338
 339         if (bus->number || PCI_SLOT(devfn))
 340                 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
 341
 342         /* When accessing PCI config space of the PCI controller itself (bus
 343          * 0, device slot 0, function 0) there are restrictions.  Each
 344          * register must be accessed as it's natural size.  Thus, for example
 345          * the Vendor ID must be accessed as a 16-bit quantity.
 346          */
 347
 348         switch (size) {
 349         case 1:
 350                 if (where < 8) {
 351                         u32 tmp32;
 352                         u16 tmp16;
 353
 354                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 355                         tmp16 = (u16) tmp32;
 356                         if (where & 1)
 357                                 *value = tmp16 >> 8;
 358                         else
 359                                 *value = tmp16 & 0xff;
 360                 } else
 361                         return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
 362                 break;
 363
 364         case 2:
 365                 if (where < 8)
 366                         return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
 367                 else {
 368                         u32 tmp32;
 369                         u8 tmp8;
 370
 371                         __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
 372                         tmp8 = (u8) tmp32;
 373                         *value = tmp8;
 374                         __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
 375                         tmp8 = (u8) tmp32;
 376                         *value |= tmp8 << 8;
 377                 }
 378                 break;
 379
 380         case 4: {
 381                 u32 tmp32;
 382                 u16 tmp16;
 383
 384                 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
 385                 tmp16 = (u16) tmp32;
 386                 *value = tmp16;
 387                 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
 388                 tmp16 = (u16) tmp32;
 389                 *value |= tmp16 << 16;
 390                 break;
 391         }
 392         }
 393         return PCIBIOS_SUCCESSFUL;
 394 }
 395
 396 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 397                                  int where, int size, u32 value)
 398 {
 399         struct pci_pbm_info *pbm = bus_dev->sysdata;
 400         unsigned char bus = bus_dev->number;
 401         u32 *addr;
 402
 403         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 404         if (!addr)
 405                 return PCIBIOS_SUCCESSFUL;
 406
 407         if (__sabre_out_of_range(pbm, bus, devfn))
 408                 return PCIBIOS_SUCCESSFUL;
 409
 410         switch (size) {
 411         case 1:
 412                 pci_config_write8((u8 *) addr, value);
 413                 break;
 414
 415         case 2:
 416                 if (where & 0x01) {
 417                         printk("pci_write_config_word: misaligned reg [%x]\n",
 418                                where);
 419                         return PCIBIOS_SUCCESSFUL;
 420                 }
 421                 pci_config_write16((u16 *) addr, value);
 422                 break;
 423
 424         case 4:
 425                 if (where & 0x03) {
 426                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 427                                where);
 428                         return PCIBIOS_SUCCESSFUL;
 429                 }
 430                 pci_config_write32(addr, value);
 431                 break;
 432         }
 433
 434         return PCIBIOS_SUCCESSFUL;
 435 }
 436
 437 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 438                                int where, int size, u32 value)
 439 {
 440         if (bus->number)
 441                 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 442
 443         if (sabre_out_of_range(devfn))
 444                 return PCIBIOS_SUCCESSFUL;
 445
 446         switch (size) {
 447         case 1:
 448                 if (where < 8) {
 449                         u32 tmp32;
 450                         u16 tmp16;
 451
 452                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 453                         tmp16 = (u16) tmp32;
 454                         if (where & 1) {
 455                                 value &= 0x00ff;
 456                                 value |= tmp16 << 8;
 457                         } else {
 458                                 value &= 0xff00;
 459                                 value |= tmp16;
 460                         }
 461                         tmp32 = (u32) tmp16;
 462                         return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
 463                 } else
 464                         return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
 465                 break;
 466         case 2:
 467                 if (where < 8)
 468                         return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
 469                 else {
 470                         __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
 471                         __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
 472                 }
 473                 break;
 474         case 4:
 475                 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
 476                 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
 477                 break;
 478         }
 479         return PCIBIOS_SUCCESSFUL;
 480 }
 481
 482 static struct pci_ops sabre_ops = {
 483         .read =         sabre_read_pci_cfg,
 484         .write =        sabre_write_pci_cfg,
 485 };
 486
 487 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
 488 {
 489         unsigned int bus =  (ino & 0x10) >> 4;
 490         unsigned int slot = (ino & 0x0c) >> 2;
 491
 492         if (bus == 0)
 493                 return SABRE_IMAP_A_SLOT0 + (slot * 8);
 494         else
 495                 return SABRE_IMAP_B_SLOT0 + (slot * 8);
 496 }
 497
 498 static unsigned long __onboard_imap_off[] = {
 499 /*0x20*/        SABRE_IMAP_SCSI,
 500 /*0x21*/        SABRE_IMAP_ETH,
 501 /*0x22*/        SABRE_IMAP_BPP,
 502 /*0x23*/        SABRE_IMAP_AU_REC,
 503 /*0x24*/        SABRE_IMAP_AU_PLAY,
 504 /*0x25*/        SABRE_IMAP_PFAIL,
 505 /*0x26*/        SABRE_IMAP_KMS,
 506 /*0x27*/        SABRE_IMAP_FLPY,
 507 /*0x28*/        SABRE_IMAP_SHW,
 508 /*0x29*/        SABRE_IMAP_KBD,
 509 /*0x2a*/        SABRE_IMAP_MS,
 510 /*0x2b*/        SABRE_IMAP_SER,
 511 /*0x2c*/        0 /* reserved */,
 512 /*0x2d*/        0 /* reserved */,
 513 /*0x2e*/        SABRE_IMAP_UE,
 514 /*0x2f*/        SABRE_IMAP_CE,
 515 /*0x30*/        SABRE_IMAP_PCIERR,
 516 };
 517 #define SABRE_ONBOARD_IRQ_BASE          0x20
 518 #define SABRE_ONBOARD_IRQ_LAST          0x30
 519 #define sabre_onboard_imap_offset(__ino) \
 520         __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
 521
 522 #define sabre_iclr_offset(ino)                                        \
 523         ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) :  \
 524                         (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
 525
 526 /* When a device lives behind a bridge deeper in the PCI bus topology
 527  * than APB, a special sequence must run to make sure all pending DMA
 528  * transfers at the time of IRQ delivery are visible in the coherency
 529  * domain by the cpu.  This sequence is to perform a read on the far
 530  * side of the non-APB bridge, then perform a read of Sabre's DMA
 531  * write-sync register.
 532  */
 533 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
 534 {
 535         struct pci_dev *pdev = _arg1;
 536         unsigned long sync_reg = (unsigned long) _arg2;
 537         u16 _unused;
 538
 539         pci_read_config_word(pdev, PCI_VENDOR_ID, &_unused);
 540         sabre_read(sync_reg);
 541 }
 542
 543 static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
 544                                     struct pci_dev *pdev,
 545                                     unsigned int ino)
 546 {
 547         unsigned long imap, iclr;
 548         unsigned long imap_off, iclr_off;
 549         int inofixup = 0;
 550         int virt_irq;
 551
 552         ino &= PCI_IRQ_INO;
 553         if (ino < SABRE_ONBOARD_IRQ_BASE) {
 554                 /* PCI slot */
 555                 imap_off = sabre_pcislot_imap_offset(ino);
 556         } else {
 557                 /* onboard device */
 558                 if (ino > SABRE_ONBOARD_IRQ_LAST) {
 559                         prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
 560                         prom_halt();
 561                 }
 562                 imap_off = sabre_onboard_imap_offset(ino);
 563         }
 564
 565         /* Now build the IRQ bucket. */
 566         imap = pbm->controller_regs + imap_off;
 567         imap += 4;
 568
 569         iclr_off = sabre_iclr_offset(ino);
 570         iclr = pbm->controller_regs + iclr_off;
 571         iclr += 4;
 572
 573         if ((ino & 0x20) == 0)
 574                 inofixup = ino & 0x03;
 575
 576         virt_irq = build_irq(inofixup, iclr, imap);
 577
 578         if (pdev) {
 579                 struct pcidev_cookie *pcp = pdev->sysdata;
 580
 581                 if (pdev->bus->number != pcp->pbm->pci_first_busno) {
 582                         struct pci_controller_info *p = pcp->pbm->parent;
 583
 584                         irq_install_pre_handler(virt_irq,
 585                                                 sabre_wsync_handler,
 586                                                 pdev,
 587                                                 (void *)
 588                                                 p->pbm_A.controller_regs +
 589                                                 SABRE_WRSYNC);
 590                 }
 591         }
 592         return virt_irq;
 593 }
 594
 595 /* SABRE error handling support. */
 596 static void sabre_check_iommu_error(struct pci_controller_info *p,
 597                                     unsigned long afsr,
 598                                     unsigned long afar)
 599 {
 600         struct pci_iommu *iommu = p->pbm_A.iommu;
 601         unsigned long iommu_tag[16];
 602         unsigned long iommu_data[16];
 603         unsigned long flags;
 604         u64 control;
 605         int i;
 606
 607         spin_lock_irqsave(&iommu->lock, flags);
 608         control = sabre_read(iommu->iommu_control);
 609         if (control & SABRE_IOMMUCTRL_ERR) {
 610                 char *type_string;
 611
 612                 /* Clear the error encountered bit.
 613                  * NOTE: On Sabre this is write 1 to clear,
 614                  *       which is different from Psycho.
 615                  */
 616                 sabre_write(iommu->iommu_control, control);
 617                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 618                 case 1:
 619                         type_string = "Invalid Error";
 620                         break;
 621                 case 3:
 622                         type_string = "ECC Error";
 623                         break;
 624                 default:
 625                         type_string = "Unknown";
 626                         break;
 627                 };
 628                 printk("SABRE%d: IOMMU Error, type[%s]\n",
 629                        p->index, type_string);
 630
 631                 /* Enter diagnostic mode and probe for error'd
 632                  * entries in the IOTLB.
 633                  */
 634                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 635                 sabre_write(iommu->iommu_control,
 636                             (control | SABRE_IOMMUCTRL_DENAB));
 637                 for (i = 0; i < 16; i++) {
 638                         unsigned long base = p->pbm_A.controller_regs;
 639
 640                         iommu_tag[i] =
 641                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 642                         iommu_data[i] =
 643                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 644                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 645                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 646                 }
 647                 sabre_write(iommu->iommu_control, control);
 648
 649                 for (i = 0; i < 16; i++) {
 650                         unsigned long tag, data;
 651
 652                         tag = iommu_tag[i];
 653                         if (!(tag & SABRE_IOMMUTAG_ERR))
 654                                 continue;
 655
 656                         data = iommu_data[i];
 657                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 658                         case 1:
 659                                 type_string = "Invalid Error";
 660                                 break;
 661                         case 3:
 662                                 type_string = "ECC Error";
 663                                 break;
 664                         default:
 665                                 type_string = "Unknown";
 666                                 break;
 667                         };
 668                         printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 669                                p->index, i, tag, type_string,
 670                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 671                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 672                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 673                         printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 674                                p->index, i, data,
 675                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 676                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 677                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 678                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 679                 }
 680         }
 681         spin_unlock_irqrestore(&iommu->lock, flags);
 682 }
 683
 684 static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
 685 {
 686         struct pci_controller_info *p = dev_id;
 687         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
 688         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 689         unsigned long afsr, afar, error_bits;
 690         int reported;
 691
 692         /* Latch uncorrectable error status. */
 693         afar = sabre_read(afar_reg);
 694         afsr = sabre_read(afsr_reg);
 695
 696         /* Clear the primary/secondary error status bits. */
 697         error_bits = afsr &
 698                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 699                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 700                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 701         if (!error_bits)
 702                 return IRQ_NONE;
 703         sabre_write(afsr_reg, error_bits);
 704
 705         /* Log the error. */
 706         printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
 707                p->index,
 708                ((error_bits & SABRE_UEAFSR_PDRD) ?
 709                 "DMA Read" :
 710                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 711                  "DMA Write" : "???")),
 712                ((error_bits & SABRE_UEAFSR_PDTE) ?
 713                 ":Translation Error" : ""));
 714         printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 715                p->index,
 716                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 717                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 718                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 719         printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
 720         printk("SABRE%d: UE Secondary errors [", p->index);
 721         reported = 0;
 722         if (afsr & SABRE_UEAFSR_SDRD) {
 723                 reported++;
 724                 printk("(DMA Read)");
 725         }
 726         if (afsr & SABRE_UEAFSR_SDWR) {
 727                 reported++;
 728                 printk("(DMA Write)");
 729         }
 730         if (afsr & SABRE_UEAFSR_SDTE) {
 731                 reported++;
 732                 printk("(Translation Error)");
 733         }
 734         if (!reported)
 735                 printk("(none)");
 736         printk("]\n");
 737
 738         /* Interrogate IOMMU for error status. */
 739         sabre_check_iommu_error(p, afsr, afar);
 740
 741         return IRQ_HANDLED;
 742 }
 743
 744 static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
 745 {
 746         struct pci_controller_info *p = dev_id;
 747         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
 748         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 749         unsigned long afsr, afar, error_bits;
 750         int reported;
 751
 752         /* Latch error status. */
 753         afar = sabre_read(afar_reg);
 754         afsr = sabre_read(afsr_reg);
 755
 756         /* Clear primary/secondary error status bits. */
 757         error_bits = afsr &
 758                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 759                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 760         if (!error_bits)
 761                 return IRQ_NONE;
 762         sabre_write(afsr_reg, error_bits);
 763
 764         /* Log the error. */
 765         printk("SABRE%d: Correctable Error, primary error type[%s]\n",
 766                p->index,
 767                ((error_bits & SABRE_CEAFSR_PDRD) ?
 768                 "DMA Read" :
 769                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 770                  "DMA Write" : "???")));
 771
 772         /* XXX Use syndrome and afar to print out module string just like
 773          * XXX UDB CE trap handler does... -DaveM
 774          */
 775         printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 776                "was_block(%d)\n",
 777                p->index,
 778                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 779                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 780                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 781                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 782         printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
 783         printk("SABRE%d: CE Secondary errors [", p->index);
 784         reported = 0;
 785         if (afsr & SABRE_CEAFSR_SDRD) {
 786                 reported++;
 787                 printk("(DMA Read)");
 788         }
 789         if (afsr & SABRE_CEAFSR_SDWR) {
 790                 reported++;
 791                 printk("(DMA Write)");
 792         }
 793         if (!reported)
 794                 printk("(none)");
 795         printk("]\n");
 796
 797         return IRQ_HANDLED;
 798 }
 799
 800 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
 801 {
 802         unsigned long csr_reg, csr, csr_error_bits;
 803         irqreturn_t ret = IRQ_NONE;
 804         u16 stat;
 805
 806         csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
 807         csr = sabre_read(csr_reg);
 808         csr_error_bits =
 809                 csr & SABRE_PCICTRL_SERR;
 810         if (csr_error_bits) {
 811                 /* Clear the errors.  */
 812                 sabre_write(csr_reg, csr);
 813
 814                 /* Log 'em.  */
 815                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 816                         printk("SABRE%d: PCI SERR signal asserted.\n",
 817                                p->index);
 818                 ret = IRQ_HANDLED;
 819         }
 820         pci_read_config_word(sabre_root_bus->self,
 821                              PCI_STATUS, &stat);
 822         if (stat & (PCI_STATUS_PARITY |
 823                     PCI_STATUS_SIG_TARGET_ABORT |
 824                     PCI_STATUS_REC_TARGET_ABORT |
 825                     PCI_STATUS_REC_MASTER_ABORT |
 826                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 827                 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
 828                        p->index, stat);
 829                 pci_write_config_word(sabre_root_bus->self,
 830                                       PCI_STATUS, 0xffff);
 831                 ret = IRQ_HANDLED;
 832         }
 833         return ret;
 834 }
 835
 836 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
 837 {
 838         struct pci_controller_info *p = dev_id;
 839         unsigned long afsr_reg, afar_reg;
 840         unsigned long afsr, afar, error_bits;
 841         int reported;
 842
 843         afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
 844         afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
 845
 846         /* Latch error status. */
 847         afar = sabre_read(afar_reg);
 848         afsr = sabre_read(afsr_reg);
 849
 850         /* Clear primary/secondary error status bits. */
 851         error_bits = afsr &
 852                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 853                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 854                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 855                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 856         if (!error_bits)
 857                 return sabre_pcierr_intr_other(p);
 858         sabre_write(afsr_reg, error_bits);
 859
 860         /* Log the error. */
 861         printk("SABRE%d: PCI Error, primary error type[%s]\n",
 862                p->index,
 863                (((error_bits & SABRE_PIOAFSR_PMA) ?
 864                  "Master Abort" :
 865                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 866                   "Target Abort" :
 867                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 868                    "Excessive Retries" :
 869                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 870                     "Parity Error" : "???"))))));
 871         printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
 872                p->index,
 873                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 874                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 875         printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
 876         printk("SABRE%d: PCI Secondary errors [", p->index);
 877         reported = 0;
 878         if (afsr & SABRE_PIOAFSR_SMA) {
 879                 reported++;
 880                 printk("(Master Abort)");
 881         }
 882         if (afsr & SABRE_PIOAFSR_STA) {
 883                 reported++;
 884                 printk("(Target Abort)");
 885         }
 886         if (afsr & SABRE_PIOAFSR_SRTRY) {
 887                 reported++;
 888                 printk("(Excessive Retries)");
 889         }
 890         if (afsr & SABRE_PIOAFSR_SPERR) {
 891                 reported++;
 892                 printk("(Parity Error)");
 893         }
 894         if (!reported)
 895                 printk("(none)");
 896         printk("]\n");
 897
 898         /* For the error types shown, scan both PCI buses for devices
 899          * which have logged that error type.
 900          */
 901
 902         /* If we see a Target Abort, this could be the result of an
 903          * IOMMU translation error of some sort.  It is extremely
 904          * useful to log this information as usually it indicates
 905          * a bug in the IOMMU support code or a PCI device driver.
 906          */
 907         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 908                 sabre_check_iommu_error(p, afsr, afar);
 909                 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 910                 pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 911         }
 912         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
 913                 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 914                 pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 915         }
 916         /* For excessive retries, SABRE/PBM will abort the device
 917          * and there is no way to specifically check for excessive
 918          * retries in the config space status registers.  So what
 919          * we hope is that we'll catch it via the master/target
 920          * abort events.
 921          */
 922
 923         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
 924                 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
 925                 pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
 926         }
 927
 928         return IRQ_HANDLED;
 929 }
 930
 931 /* XXX What about PowerFail/PowerManagement??? -DaveM */
 932 #define SABRE_UE_INO            0x2e
 933 #define SABRE_CE_INO            0x2f
 934 #define SABRE_PCIERR_INO        0x30
 935 static void sabre_register_error_handlers(struct pci_controller_info *p)
 936 {
 937         struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
 938         unsigned long base = pbm->controller_regs;
 939         unsigned long irq, portid = pbm->portid;
 940         u64 tmp;
 941
 942         /* We clear the error bits in the appropriate AFSR before
 943          * registering the handler so that we don't get spurious
 944          * interrupts.
 945          */
 946         sabre_write(base + SABRE_UE_AFSR,
 947                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 948                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 949                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 950         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO);
 951         if (request_irq(irq, sabre_ue_intr,
 952                         SA_SHIRQ, "SABRE UE", p) < 0) {
 953                 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
 954                             p->index);
 955                 prom_halt();
 956         }
 957
 958         sabre_write(base + SABRE_CE_AFSR,
 959                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 960                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 961         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);
 962         if (request_irq(irq, sabre_ce_intr,
 963                         SA_SHIRQ, "SABRE CE", p) < 0) {
 964                 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
 965                             p->index);
 966                 prom_halt();
 967         }
 968
 969         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO);
 970         if (request_irq(irq, sabre_pcierr_intr,
 971                         SA_SHIRQ, "SABRE PCIERR", p) < 0) {
 972                 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
 973                             p->index);
 974                 prom_halt();
 975         }
 976
 977         tmp = sabre_read(base + SABRE_PCICTRL);
 978         tmp |= SABRE_PCICTRL_ERREN;
 979         sabre_write(base + SABRE_PCICTRL, tmp);
 980 }
 981
 982 static void sabre_resource_adjust(struct pci_dev *pdev,
 983                                   struct resource *res,
 984                                   struct resource *root)
 985 {
 986         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 987         unsigned long base;
 988
 989         if (res->flags & IORESOURCE_IO)
 990                 base = pbm->controller_regs + SABRE_IOSPACE;
 991         else
 992                 base = pbm->controller_regs + SABRE_MEMSPACE;
 993
 994         res->start += base;
 995         res->end += base;
 996 }
 997
 998 static void sabre_base_address_update(struct pci_dev *pdev, int resource)
 999 {
1000         struct pcidev_cookie *pcp = pdev->sysdata;
1001         struct pci_pbm_info *pbm = pcp->pbm;
1002         struct resource *res;
1003         unsigned long base;
1004         u32 reg;
1005         int where, size, is_64bit;
1006
1007         res = &pdev->resource[resource];
1008         if (resource < 6) {
1009                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1010         } else if (resource == PCI_ROM_RESOURCE) {
1011                 where = pdev->rom_base_reg;
1012         } else {
1013                 /* Somebody might have asked allocation of a non-standard resource */
1014                 return;
1015         }
1016
1017         is_64bit = 0;
1018         if (res->flags & IORESOURCE_IO)
1019                 base = pbm->controller_regs + SABRE_IOSPACE;
1020         else {
1021                 base = pbm->controller_regs + SABRE_MEMSPACE;
1022                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1023                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
1024                         is_64bit = 1;
1025         }
1026
1027         size = res->end - res->start;
1028         pci_read_config_dword(pdev, where, &reg);
1029         reg = ((reg & size) |
1030                (((u32)(res->start - base)) & ~size));
1031         if (resource == PCI_ROM_RESOURCE) {
1032                 reg |= PCI_ROM_ADDRESS_ENABLE;
1033                 res->flags |= IORESOURCE_ROM_ENABLE;
1034         }
1035         pci_write_config_dword(pdev, where, reg);
1036
1037         /* This knows that the upper 32-bits of the address
1038          * must be zero.  Our PCI common layer enforces this.
1039          */
1040         if (is_64bit)
1041                 pci_write_config_dword(pdev, where + 4, 0);
1042 }
1043
1044 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
1045 {
1046         struct pci_dev *pdev;
1047
1048         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
1049
1050                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1051                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
1052                         u32 word32;
1053                         u16 word16;
1054
1055                         sabre_read_pci_cfg(pdev->bus, pdev->devfn,
1056                                            PCI_COMMAND, 2, &word32);
1057                         word16 = (u16) word32;
1058                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
1059                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
1060                                 PCI_COMMAND_IO;
1061                         word32 = (u32) word16;
1062                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1063                                             PCI_COMMAND, 2, word32);
1064
1065                         /* Status register bits are "write 1 to clear". */
1066                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1067                                             PCI_STATUS, 2, 0xffff);
1068                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1069                                             PCI_SEC_STATUS, 2, 0xffff);
1070
1071                         /* Use a primary/seconday latency timer value
1072                          * of 64.
1073                          */
1074                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1075                                             PCI_LATENCY_TIMER, 1, 64);
1076                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1077                                             PCI_SEC_LATENCY_TIMER, 1, 64);
1078
1079                         /* Enable reporting/forwarding of master aborts,
1080                          * parity, and SERR.
1081                          */
1082                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1083                                             PCI_BRIDGE_CONTROL, 1,
1084                                             (PCI_BRIDGE_CTL_PARITY |
1085                                              PCI_BRIDGE_CTL_SERR |
1086                                              PCI_BRIDGE_CTL_MASTER_ABORT));
1087                 }
1088         }
1089 }
1090
1091 static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
1092 {
1093         struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1094
1095         if (!cookie) {
1096                 prom_printf("SABRE: Critical allocation failure.\n");
1097                 prom_halt();
1098         }
1099
1100         /* All we care about is the PBM. */
1101         cookie->pbm = pbm;
1102
1103         return cookie;
1104 }
1105
1106 static void sabre_scan_bus(struct pci_controller_info *p)
1107 {
1108         static int once;
1109         struct pci_bus *sabre_bus, *pbus;
1110         struct pci_pbm_info *pbm;
1111         struct pcidev_cookie *cookie;
1112         int sabres_scanned;
1113
1114         /* The APB bridge speaks to the Sabre host PCI bridge
1115          * at 66Mhz, but the front side of APB runs at 33Mhz
1116          * for both segments.
1117          */
1118         p->pbm_A.is_66mhz_capable = 0;
1119         p->pbm_B.is_66mhz_capable = 0;
1120
1121         /* This driver has not been verified to handle
1122          * multiple SABREs yet, so trap this.
1123          *
1124          * Also note that the SABRE host bridge is hardwired
1125          * to live at bus 0.
1126          */
1127         if (once != 0) {
1128                 prom_printf("SABRE: Multiple controllers unsupported.\n");
1129                 prom_halt();
1130         }
1131         once++;
1132
1133         cookie = alloc_bridge_cookie(&p->pbm_A);
1134
1135         sabre_bus = pci_scan_bus(p->pci_first_busno,
1136                                  p->pci_ops,
1137                                  &p->pbm_A);
1138         pci_fixup_host_bridge_self(sabre_bus);
1139         sabre_bus->self->sysdata = cookie;
1140
1141         sabre_root_bus = sabre_bus;
1142
1143         apb_init(p, sabre_bus);
1144
1145         sabres_scanned = 0;
1146
1147         list_for_each_entry(pbus, &sabre_bus->children, node) {
1148
1149                 if (pbus->number == p->pbm_A.pci_first_busno) {
1150                         pbm = &p->pbm_A;
1151                 } else if (pbus->number == p->pbm_B.pci_first_busno) {
1152                         pbm = &p->pbm_B;
1153                 } else
1154                         continue;
1155
1156                 cookie = alloc_bridge_cookie(pbm);
1157                 pbus->self->sysdata = cookie;
1158
1159                 sabres_scanned++;
1160
1161                 pbus->sysdata = pbm;
1162                 pbm->pci_bus = pbus;
1163                 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1164                 pci_record_assignments(pbm, pbus);
1165                 pci_assign_unassigned(pbm, pbus);
1166                 pci_fixup_irq(pbm, pbus);
1167                 pci_determine_66mhz_disposition(pbm, pbus);
1168                 pci_setup_busmastering(pbm, pbus);
1169         }
1170
1171         if (!sabres_scanned) {
1172                 /* Hummingbird, no APBs. */
1173                 pbm = &p->pbm_A;
1174                 sabre_bus->sysdata = pbm;
1175                 pbm->pci_bus = sabre_bus;
1176                 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1177                 pci_record_assignments(pbm, sabre_bus);
1178                 pci_assign_unassigned(pbm, sabre_bus);
1179                 pci_fixup_irq(pbm, sabre_bus);
1180                 pci_determine_66mhz_disposition(pbm, sabre_bus);
1181                 pci_setup_busmastering(pbm, sabre_bus);
1182         }
1183
1184         sabre_register_error_handlers(p);
1185 }
1186
1187 static void sabre_iommu_init(struct pci_controller_info *p,
1188                              int tsbsize, unsigned long dvma_offset,
1189                              u32 dma_mask)
1190 {
1191         struct pci_iommu *iommu = p->pbm_A.iommu;
1192         unsigned long i;
1193         u64 control;
1194
1195         /* Register addresses. */
1196         iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
1197         iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
1198         iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
1199         iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
1200         /* Sabre's IOMMU lacks ctx flushing. */
1201         iommu->iommu_ctxflush = 0;
1202
1203         /* Invalidate TLB Entries. */
1204         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1205         control |= SABRE_IOMMUCTRL_DENAB;
1206         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1207
1208         for(i = 0; i < 16; i++) {
1209                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1210                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1211         }
1212
1213         /* Leave diag mode enabled for full-flushing done
1214          * in pci_iommu.c
1215          */
1216         pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
1217
1218         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
1219                     __pa(iommu->page_table));
1220
1221         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1222         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1223         control |= SABRE_IOMMUCTRL_ENAB;
1224         switch(tsbsize) {
1225         case 64:
1226                 control |= SABRE_IOMMU_TSBSZ_64K;
1227                 break;
1228         case 128:
1229                 control |= SABRE_IOMMU_TSBSZ_128K;
1230                 break;
1231         default:
1232                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1233                 prom_halt();
1234                 break;
1235         }
1236         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1237 }
1238
1239 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1240                                             struct pci_pbm_info *pbm)
1241 {
1242         char *name = pbm->name;
1243         unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
1244         unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1245         unsigned int devfn;
1246         unsigned long first, last, i;
1247         u8 *addr, map;
1248
1249         sprintf(name, "SABRE%d PBM%c",
1250                 p->index,
1251                 (pbm == &p->pbm_A ? 'A' : 'B'));
1252         pbm->io_space.name = pbm->mem_space.name = name;
1253
1254         devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
1255         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
1256         map = 0;
1257         pci_config_read8(addr, &map);
1258
1259         first = 8;
1260         last = 0;
1261         for (i = 0; i < 8; i++) {
1262                 if ((map & (1 << i)) != 0) {
1263                         if (first > i)
1264                                 first = i;
1265                         if (last < i)
1266                                 last = i;
1267                 }
1268         }
1269         pbm->io_space.start = ibase + (first << 21UL);
1270         pbm->io_space.end   = ibase + (last << 21UL) + ((1 << 21UL) - 1);
1271         pbm->io_space.flags = IORESOURCE_IO;
1272
1273         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
1274         map = 0;
1275         pci_config_read8(addr, &map);
1276
1277         first = 8;
1278         last = 0;
1279         for (i = 0; i < 8; i++) {
1280                 if ((map & (1 << i)) != 0) {
1281                         if (first > i)
1282                                 first = i;
1283                         if (last < i)
1284                                 last = i;
1285                 }
1286         }
1287         pbm->mem_space.start = mbase + (first << 29UL);
1288         pbm->mem_space.end   = mbase + (last << 29UL) + ((1 << 29UL) - 1);
1289         pbm->mem_space.flags = IORESOURCE_MEM;
1290
1291         if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1292                 prom_printf("Cannot register PBM-%c's IO space.\n",
1293                             (pbm == &p->pbm_A ? 'A' : 'B'));
1294                 prom_halt();
1295         }
1296         if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1297                 prom_printf("Cannot register PBM-%c's MEM space.\n",
1298                             (pbm == &p->pbm_A ? 'A' : 'B'));
1299                 prom_halt();
1300         }
1301
1302         /* Register legacy regions if this PBM covers that area. */
1303         if (pbm->io_space.start == ibase &&
1304             pbm->mem_space.start == mbase)
1305                 pci_register_legacy_regions(&pbm->io_space,
1306                                             &pbm->mem_space);
1307 }
1308
1309 static void sabre_pbm_init(struct pci_controller_info *p, int sabre_node, u32 dma_begin)
1310 {
1311         struct pci_pbm_info *pbm;
1312         char namebuf[128];
1313         u32 busrange[2];
1314         int node, simbas_found;
1315
1316         simbas_found = 0;
1317         node = prom_getchild(sabre_node);
1318         while ((node = prom_searchsiblings(node, "pci")) != 0) {
1319                 int err;
1320
1321                 err = prom_getproperty(node, "model", namebuf, sizeof(namebuf));
1322                 if ((err <= 0) || strncmp(namebuf, "SUNW,simba", err))
1323                         goto next_pci;
1324
1325                 err = prom_getproperty(node, "bus-range",
1326                                        (char *)&busrange[0], sizeof(busrange));
1327                 if (err == 0 || err == -1) {
1328                         prom_printf("APB: Error, cannot get PCI bus-range.\n");
1329                         prom_halt();
1330                 }
1331
1332                 simbas_found++;
1333                 if (busrange[0] == 1)
1334                         pbm = &p->pbm_B;
1335                 else
1336                         pbm = &p->pbm_A;
1337                 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1338                 pbm->parent = p;
1339                 pbm->prom_node = node;
1340                 pbm->pci_first_slot = 1;
1341                 pbm->pci_first_busno = busrange[0];
1342                 pbm->pci_last_busno = busrange[1];
1343
1344                 prom_getstring(node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1345                 err = prom_getproperty(node, "ranges",
1346                                        (char *)pbm->pbm_ranges,
1347                                        sizeof(pbm->pbm_ranges));
1348                 if (err != -1)
1349                         pbm->num_pbm_ranges =
1350                                 (err / sizeof(struct linux_prom_pci_ranges));
1351                 else
1352                         pbm->num_pbm_ranges = 0;
1353
1354                 err = prom_getproperty(node, "interrupt-map",
1355                                        (char *)pbm->pbm_intmap,
1356                                        sizeof(pbm->pbm_intmap));
1357                 if (err != -1) {
1358                         pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1359                         err = prom_getproperty(node, "interrupt-map-mask",
1360                                                (char *)&pbm->pbm_intmask,
1361                                                sizeof(pbm->pbm_intmask));
1362                         if (err == -1) {
1363                                 prom_printf("APB: Fatal error, no interrupt-map-mask.\n");
1364                                 prom_halt();
1365                         }
1366                 } else {
1367                         pbm->num_pbm_intmap = 0;
1368                         memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1369                 }
1370
1371                 pbm_register_toplevel_resources(p, pbm);
1372
1373         next_pci:
1374                 node = prom_getsibling(node);
1375                 if (!node)
1376                         break;
1377         }
1378         if (simbas_found == 0) {
1379                 int err;
1380
1381                 /* No APBs underneath, probably this is a hummingbird
1382                  * system.
1383                  */
1384                 pbm = &p->pbm_A;
1385                 pbm->parent = p;
1386                 pbm->prom_node = sabre_node;
1387                 pbm->pci_first_busno = p->pci_first_busno;
1388                 pbm->pci_last_busno = p->pci_last_busno;
1389
1390                 prom_getstring(sabre_node, "name", pbm->prom_name, sizeof(pbm->prom_name));
1391                 err = prom_getproperty(sabre_node, "ranges",
1392                                        (char *) pbm->pbm_ranges,
1393                                        sizeof(pbm->pbm_ranges));
1394                 if (err != -1)
1395                         pbm->num_pbm_ranges =
1396                                 (err / sizeof(struct linux_prom_pci_ranges));
1397                 else
1398                         pbm->num_pbm_ranges = 0;
1399
1400                 err = prom_getproperty(sabre_node, "interrupt-map",
1401                                        (char *) pbm->pbm_intmap,
1402                                        sizeof(pbm->pbm_intmap));
1403
1404                 if (err != -1) {
1405                         pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1406                         err = prom_getproperty(sabre_node, "interrupt-map-mask",
1407                                                (char *)&pbm->pbm_intmask,
1408                                                sizeof(pbm->pbm_intmask));
1409                         if (err == -1) {
1410                                 prom_printf("Hummingbird: Fatal error, no interrupt-map-mask.\n");
1411                                 prom_halt();
1412                         }
1413                 } else {
1414                         pbm->num_pbm_intmap = 0;
1415                         memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1416                 }
1417
1418
1419                 sprintf(pbm->name, "SABRE%d PBM%c", p->index,
1420                         (pbm == &p->pbm_A ? 'A' : 'B'));
1421                 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1422
1423                 /* Hack up top-level resources. */
1424                 pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
1425                 pbm->io_space.end   = pbm->io_space.start + (1UL << 24) - 1UL;
1426                 pbm->io_space.flags = IORESOURCE_IO;
1427
1428                 pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1429                 pbm->mem_space.end   = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
1430                 pbm->mem_space.flags = IORESOURCE_MEM;
1431
1432                 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1433                         prom_printf("Cannot register Hummingbird's IO space.\n");
1434                         prom_halt();
1435                 }
1436                 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1437                         prom_printf("Cannot register Hummingbird's MEM space.\n");
1438                         prom_halt();
1439                 }
1440
1441                 pci_register_legacy_regions(&pbm->io_space,
1442                                             &pbm->mem_space);
1443         }
1444 }
1445
1446 void sabre_init(int pnode, char *model_name)
1447 {
1448         struct linux_prom64_registers pr_regs[2];
1449         struct pci_controller_info *p;
1450         struct pci_iommu *iommu;
1451         int tsbsize, err;
1452         u32 busrange[2];
1453         u32 vdma[2];
1454         u32 upa_portid, dma_mask;
1455         u64 clear_irq;
1456
1457         hummingbird_p = 0;
1458         if (!strcmp(model_name, "pci108e,a001"))
1459                 hummingbird_p = 1;
1460         else if (!strcmp(model_name, "SUNW,sabre")) {
1461                 char compat[64];
1462
1463                 if (prom_getproperty(pnode, "compatible",
1464                                      compat, sizeof(compat)) > 0 &&
1465                     !strcmp(compat, "pci108e,a001")) {
1466                         hummingbird_p = 1;
1467                 } else {
1468                         int cpu_node;
1469
1470                         /* Of course, Sun has to encode things a thousand
1471                          * different ways, inconsistently.
1472                          */
1473                         cpu_find_by_instance(0, &cpu_node, NULL);
1474                         if (prom_getproperty(cpu_node, "name",
1475                                              compat, sizeof(compat)) > 0 &&
1476                             !strcmp(compat, "SUNW,UltraSPARC-IIe"))
1477                                 hummingbird_p = 1;
1478                 }
1479         }
1480
1481         p = kzalloc(sizeof(*p), GFP_ATOMIC);
1482         if (!p) {
1483                 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1484                 prom_halt();
1485         }
1486
1487         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1488         if (!iommu) {
1489                 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1490                 prom_halt();
1491         }
1492         p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1493
1494         upa_portid = prom_getintdefault(pnode, "upa-portid", 0xff);
1495
1496         p->next = pci_controller_root;
1497         pci_controller_root = p;
1498
1499         p->pbm_A.portid = upa_portid;
1500         p->pbm_B.portid = upa_portid;
1501         p->index = pci_num_controllers++;
1502         p->pbms_same_domain = 1;
1503         p->scan_bus = sabre_scan_bus;
1504         p->irq_build = sabre_irq_build;
1505         p->base_address_update = sabre_base_address_update;
1506         p->resource_adjust = sabre_resource_adjust;
1507         p->pci_ops = &sabre_ops;
1508
1509         /*
1510          * Map in SABRE register set and report the presence of this SABRE.
1511          */
1512         err = prom_getproperty(pnode, "reg",
1513                                (char *)&pr_regs[0], sizeof(pr_regs));
1514         if(err == 0 || err == -1) {
1515                 prom_printf("SABRE: Error, cannot get U2P registers "
1516                             "from PROM.\n");
1517                 prom_halt();
1518         }
1519
1520         /*
1521          * First REG in property is base of entire SABRE register space.
1522          */
1523         p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1524         p->pbm_B.controller_regs = pr_regs[0].phys_addr;
1525
1526         printk("PCI: Found SABRE, main regs at %016lx\n",
1527                p->pbm_A.controller_regs);
1528
1529         /* Clear interrupts */
1530
1531         /* PCI first */
1532         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1533                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1534
1535         /* Then OBIO */
1536         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1537                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1538
1539         /* Error interrupts are enabled later after the bus scan. */
1540         sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1541                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
1542                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1543
1544         /* Now map in PCI config space for entire SABRE. */
1545         p->pbm_A.config_space = p->pbm_B.config_space =
1546                 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1547         printk("SABRE: Shared PCI config space at %016lx\n",
1548                p->pbm_A.config_space);
1549
1550         err = prom_getproperty(pnode, "virtual-dma",
1551                                (char *)&vdma[0], sizeof(vdma));
1552         if(err == 0 || err == -1) {
1553                 prom_printf("SABRE: Error, cannot get virtual-dma property "
1554                             "from PROM.\n");
1555                 prom_halt();
1556         }
1557
1558         dma_mask = vdma[0];
1559         switch(vdma[1]) {
1560                 case 0x20000000:
1561                         dma_mask |= 0x1fffffff;
1562                         tsbsize = 64;
1563                         break;
1564                 case 0x40000000:
1565                         dma_mask |= 0x3fffffff;
1566                         tsbsize = 128;
1567                         break;
1568
1569                 case 0x80000000:
1570                         dma_mask |= 0x7fffffff;
1571                         tsbsize = 128;
1572                         break;
1573                 default:
1574                         prom_printf("SABRE: strange virtual-dma size.\n");
1575                         prom_halt();
1576         }
1577
1578         sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1579
1580         printk("SABRE: DVMA at %08x [%08x]\n", vdma[0], vdma[1]);
1581
1582         err = prom_getproperty(pnode, "bus-range",
1583                                        (char *)&busrange[0], sizeof(busrange));
1584         if(err == 0 || err == -1) {
1585                 prom_printf("SABRE: Error, cannot get PCI bus-range "
1586                             " from PROM.\n");
1587                 prom_halt();
1588         }
1589
1590         p->pci_first_busno = busrange[0];
1591         p->pci_last_busno = busrange[1];
1592
1593         /*
1594          * Look for APB underneath.
1595          */
1596         sabre_pbm_init(p, pnode, vdma[0]);
1597 }