2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/bitops.h>
25 #include <linux/config.h>
26 #include <linux/errno.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/types.h>
34 #undef PARISC_IRQ_CR16_COUNTS
36 extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
37 extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);
39 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
41 /* Bits in EIEM correlate with cpu_irq_action[].
42 ** Numbered *Big Endian*! (ie bit 0 is MSB)
44 static volatile unsigned long cpu_eiem = 0;
46 static void cpu_disable_irq(unsigned int irq)
48 unsigned long eirr_bit = EIEM_MASK(irq);
50 cpu_eiem &= ~eirr_bit;
51 /* Do nothing on the other CPUs. If they get this interrupt,
52 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
53 * handle it, and the set_eiem() at the bottom will ensure it
54 * then gets disabled */
57 static void cpu_enable_irq(unsigned int irq)
59 unsigned long eirr_bit = EIEM_MASK(irq);
63 /* FIXME: while our interrupts aren't nested, we cannot reset
64 * the eiem mask if we're already in an interrupt. Once we
65 * implement nested interrupts, this can go away
70 /* This is just a simple NOP IPI. But what it does is cause
71 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
72 * of the interrupt handler */
76 static unsigned int cpu_startup_irq(unsigned int irq)
82 void no_ack_irq(unsigned int irq) { }
83 void no_end_irq(unsigned int irq) { }
85 static struct hw_interrupt_type cpu_interrupt_type = {
87 .startup = cpu_startup_irq,
88 .shutdown = cpu_disable_irq,
89 .enable = cpu_enable_irq,
90 .disable = cpu_disable_irq,
93 // .set_affinity = cpu_set_affinity_irq,
96 int show_interrupts(struct seq_file *p, void *v)
98 int i = *(loff_t *) v, j;
103 for_each_online_cpu(j)
104 seq_printf(p, " CPU%d", j);
106 #ifdef PARISC_IRQ_CR16_COUNTS
107 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
113 struct irqaction *action;
115 spin_lock_irqsave(&irq_desc[i].lock, flags);
116 action = irq_desc[i].action;
119 seq_printf(p, "%3d: ", i);
121 for_each_online_cpu(j)
122 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
124 seq_printf(p, "%10u ", kstat_irqs(i));
127 seq_printf(p, " %14s", irq_desc[i].handler->typename);
128 #ifndef PARISC_IRQ_CR16_COUNTS
129 seq_printf(p, " %s", action->name);
131 while ((action = action->next))
132 seq_printf(p, ", %s", action->name);
134 for ( ;action; action = action->next) {
135 unsigned int k, avg, min, max;
137 min = max = action->cr16_hist[0];
139 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
140 int hist = action->cr16_hist[k];
147 if (hist > max) max = hist;
148 if (hist < min) min = hist;
152 seq_printf(p, " %s[%d/%d/%d]", action->name,
159 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
168 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
169 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
171 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
172 ** Then use that to get the Transaction address and data.
175 int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
177 if (irq_desc[irq].action)
179 if (irq_desc[irq].handler != &cpu_interrupt_type)
183 irq_desc[irq].handler = type;
184 irq_desc[irq].handler_data = data;
185 cpu_interrupt_type.enable(irq);
190 int txn_claim_irq(int irq)
192 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
196 * The bits_wide parameter accommodates the limitations of the HW/SW which
198 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
199 * V-class (EPIC): 6 bits
200 * N/L/A-class (iosapic): 8 bits
201 * PCI 2.2 MSI: 16 bits
202 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
204 * On the service provider side:
205 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
206 * o PA 2.0 wide mode 6-bits (per processor)
207 * o IA64 8-bits (0-256 total)
209 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
210 * by the processor...and the N/L-class I/O subsystem supports more bits than
211 * PA2.0 has. The first case is the problem.
213 int txn_alloc_irq(unsigned int bits_wide)
217 /* never return irq 0 cause that's the interval timer */
218 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
219 if (cpu_claim_irq(irq, NULL, NULL) < 0)
221 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
226 /* unlikely, but be prepared */
230 unsigned long txn_alloc_addr(unsigned int virt_irq)
232 static int next_cpu = -1;
234 next_cpu++; /* assign to "next" CPU we want this bugger on */
237 while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
238 !cpu_online(next_cpu)))
241 if (next_cpu >= NR_CPUS)
242 next_cpu = 0; /* nothing else, assign monarch */
244 return cpu_data[next_cpu].txn_addr;
248 unsigned int txn_alloc_data(unsigned int virt_irq)
250 return virt_irq - CPU_IRQ_BASE;
253 /* ONLY called from entry.S:intr_extint() */
254 void do_cpu_irq_mask(struct pt_regs *regs)
256 unsigned long eirr_val;
261 * Don't allow TIMER or IPI nested interrupts.
262 * Allowing any single interrupt to nest can lead to that CPU
263 * handling interrupts with all enabled interrupts unmasked.
267 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
268 * 2) We loop here on EIRR contents in order to avoid
269 * nested interrupts or having to take another interrupt
270 * when we could have just handled it right away.
273 unsigned long bit = (1UL << (BITS_PER_LONG - 1));
275 eirr_val = mfctl(23) & cpu_eiem;
279 mtctl(eirr_val, 23); /* reset bits we are going to process */
281 /* Work our way from MSb to LSb...same order we alloc EIRs */
282 for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
283 if (!(bit & eirr_val))
286 /* clear bit in mask - can exit loop sooner */
293 set_eiem(cpu_eiem); /* restore original mask */
298 static struct irqaction timer_action = {
299 .handler = timer_interrupt,
301 .flags = SA_INTERRUPT,
305 static struct irqaction ipi_action = {
306 .handler = ipi_interrupt,
308 .flags = SA_INTERRUPT,
312 static void claim_cpu_irqs(void)
315 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
316 irq_desc[i].handler = &cpu_interrupt_type;
319 irq_desc[TIMER_IRQ].action = &timer_action;
320 irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
322 irq_desc[IPI_IRQ].action = &ipi_action;
323 irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
327 void __init init_IRQ(void)
329 local_irq_disable(); /* PARANOID - should already be disabled */
330 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
334 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
336 cpu_eiem = EIEM_MASK(TIMER_IRQ);
338 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
342 void hw_resend_irq(struct hw_interrupt_type *type, unsigned int irq)
344 /* XXX: Needs to be written. We managed without it so far, but
345 * we really ought to write it.
349 void ack_bad_irq(unsigned int irq)
351 printk("unexpected IRQ %d\n", irq);