arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_BADVADDR $8
  54 #define CP0_COUNT $9
  55 #define CP0_ENTRYHI $10
  56 #define CP0_COMPARE $11
  57 #define CP0_STATUS $12
  58 #define CP0_CAUSE $13
  59 #define CP0_EPC $14
  60 #define CP0_PRID $15
  61 #define CP0_CONFIG $16
  62 #define CP0_LLADDR $17
  63 #define CP0_WATCHLO $18
  64 #define CP0_WATCHHI $19
  65 #define CP0_XCONTEXT $20
  66 #define CP0_FRAMEMASK $21
  67 #define CP0_DIAGNOSTIC $22
  68 #define CP0_DEBUG $23
  69 #define CP0_DEPC $24
  70 #define CP0_PERFORMANCE $25
  71 #define CP0_ECC $26
  72 #define CP0_CACHEERR $27
  73 #define CP0_TAGLO $28
  74 #define CP0_TAGHI $29
  75 #define CP0_ERROREPC $30
  76 #define CP0_DESAVE $31
  77
  78 /*
  79  * R4640/R4650 cp0 register names.  These registers are listed
  80  * here only for completeness; without MMU these CPUs are not useable
  81  * by Linux.  A future ELKS port might take make Linux run on them
  82  * though ...
  83  */
  84 #define CP0_IBASE $0
  85 #define CP0_IBOUND $1
  86 #define CP0_DBASE $2
  87 #define CP0_DBOUND $3
  88 #define CP0_CALG $17
  89 #define CP0_IWATCH $18
  90 #define CP0_DWATCH $19
  91
  92 /*
  93  * Coprocessor 0 Set 1 register names
  94  */
  95 #define CP0_S1_DERRADDR0  $26
  96 #define CP0_S1_DERRADDR1  $27
  97 #define CP0_S1_INTCONTROL $20
  98
  99 /*
 100  * Coprocessor 0 Set 2 register names
 101  */
 102 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 103
 104 /*
 105  * Coprocessor 0 Set 3 register names
 106  */
 107 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 108
 109 /*
 110  *  TX39 Series
 111  */
 112 #define CP0_TX39_CACHE  $7
 113
 114 /*
 115  * Coprocessor 1 (FPU) register names
 116  */
 117 #define CP1_REVISION   $0
 118 #define CP1_STATUS     $31
 119
 120 /*
 121  * FPU Status Register Values
 122  */
 123 /*
 124  * Status Register Values
 125  */
 126
 127 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 128 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 129 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 130 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 131 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 132 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 133 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 134 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 135 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 136 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 137
 138 /*
 139  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 140  * and should be written as zero.
 141  */
 142 #define FPU_CSR_RSVD    0x001c0000
 143
 144 /*
 145  * X the exception cause indicator
 146  * E the exception enable
 147  * S the sticky/flag bit
 148 */
 149 #define FPU_CSR_ALL_X   0x0003f000
 150 #define FPU_CSR_UNI_X   0x00020000
 151 #define FPU_CSR_INV_X   0x00010000
 152 #define FPU_CSR_DIV_X   0x00008000
 153 #define FPU_CSR_OVF_X   0x00004000
 154 #define FPU_CSR_UDF_X   0x00002000
 155 #define FPU_CSR_INE_X   0x00001000
 156
 157 #define FPU_CSR_ALL_E   0x00000f80
 158 #define FPU_CSR_INV_E   0x00000800
 159 #define FPU_CSR_DIV_E   0x00000400
 160 #define FPU_CSR_OVF_E   0x00000200
 161 #define FPU_CSR_UDF_E   0x00000100
 162 #define FPU_CSR_INE_E   0x00000080
 163
 164 #define FPU_CSR_ALL_S   0x0000007c
 165 #define FPU_CSR_INV_S   0x00000040
 166 #define FPU_CSR_DIV_S   0x00000020
 167 #define FPU_CSR_OVF_S   0x00000010
 168 #define FPU_CSR_UDF_S   0x00000008
 169 #define FPU_CSR_INE_S   0x00000004
 170
 171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 172 #define FPU_CSR_RM      0x00000003
 173 #define FPU_CSR_RN      0x0     /* nearest */
 174 #define FPU_CSR_RZ      0x1     /* towards zero */
 175 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 176 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 177
 178
 179 /*
 180  * Values for PageMask register
 181  */
 182 #ifdef CONFIG_CPU_VR41XX
 183
 184 /* Why doesn't stupidity hurt ... */
 185
 186 #define PM_1K           0x00000000
 187 #define PM_4K           0x00001800
 188 #define PM_16K          0x00007800
 189 #define PM_64K          0x0001f800
 190 #define PM_256K         0x0007f800
 191
 192 #else
 193
 194 #define PM_4K           0x00000000
 195 #define PM_8K           0x00002000
 196 #define PM_16K          0x00006000
 197 #define PM_32K          0x0000e000
 198 #define PM_64K          0x0001e000
 199 #define PM_128K         0x0003e000
 200 #define PM_256K         0x0007e000
 201 #define PM_512K         0x000fe000
 202 #define PM_1M           0x001fe000
 203 #define PM_2M           0x003fe000
 204 #define PM_4M           0x007fe000
 205 #define PM_8M           0x00ffe000
 206 #define PM_16M          0x01ffe000
 207 #define PM_32M          0x03ffe000
 208 #define PM_64M          0x07ffe000
 209 #define PM_256M         0x1fffe000
 210 #define PM_1G           0x7fffe000
 211
 212 #endif
 213
 214 /*
 215  * Default page size for a given kernel configuration
 216  */
 217 #ifdef CONFIG_PAGE_SIZE_4KB
 218 #define PM_DEFAULT_MASK PM_4K
 219 #elif defined(CONFIG_PAGE_SIZE_8KB)
 220 #define PM_DEFAULT_MASK PM_8K
 221 #elif defined(CONFIG_PAGE_SIZE_16KB)
 222 #define PM_DEFAULT_MASK PM_16K
 223 #elif defined(CONFIG_PAGE_SIZE_32KB)
 224 #define PM_DEFAULT_MASK PM_32K
 225 #elif defined(CONFIG_PAGE_SIZE_64KB)
 226 #define PM_DEFAULT_MASK PM_64K
 227 #else
 228 #error Bad page size configuration!
 229 #endif
 230
 231 /*
 232  * Default huge tlb size for a given kernel configuration
 233  */
 234 #ifdef CONFIG_PAGE_SIZE_4KB
 235 #define PM_HUGE_MASK    PM_1M
 236 #elif defined(CONFIG_PAGE_SIZE_8KB)
 237 #define PM_HUGE_MASK    PM_4M
 238 #elif defined(CONFIG_PAGE_SIZE_16KB)
 239 #define PM_HUGE_MASK    PM_16M
 240 #elif defined(CONFIG_PAGE_SIZE_32KB)
 241 #define PM_HUGE_MASK    PM_64M
 242 #elif defined(CONFIG_PAGE_SIZE_64KB)
 243 #define PM_HUGE_MASK    PM_256M
 244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 245 #error Bad page size configuration for hugetlbfs!
 246 #endif
 247
 248 /*
 249  * Values used for computation of new tlb entries
 250  */
 251 #define PL_4K           12
 252 #define PL_16K          14
 253 #define PL_64K          16
 254 #define PL_256K         18
 255 #define PL_1M           20
 256 #define PL_4M           22
 257 #define PL_16M          24
 258 #define PL_64M          26
 259 #define PL_256M         28
 260
 261 /*
 262  * PageGrain bits
 263  */
 264 #define PG_RIE          (_ULCAST_(1) <<  31)
 265 #define PG_XIE          (_ULCAST_(1) <<  30)
 266 #define PG_ELPA         (_ULCAST_(1) <<  29)
 267 #define PG_ESP          (_ULCAST_(1) <<  28)
 268 #define PG_IEC          (_ULCAST_(1) <<  27)
 269
 270 /*
 271  * R4x00 interrupt enable / cause bits
 272  */
 273 #define IE_SW0          (_ULCAST_(1) <<  8)
 274 #define IE_SW1          (_ULCAST_(1) <<  9)
 275 #define IE_IRQ0         (_ULCAST_(1) << 10)
 276 #define IE_IRQ1         (_ULCAST_(1) << 11)
 277 #define IE_IRQ2         (_ULCAST_(1) << 12)
 278 #define IE_IRQ3         (_ULCAST_(1) << 13)
 279 #define IE_IRQ4         (_ULCAST_(1) << 14)
 280 #define IE_IRQ5         (_ULCAST_(1) << 15)
 281
 282 /*
 283  * R4x00 interrupt cause bits
 284  */
 285 #define C_SW0           (_ULCAST_(1) <<  8)
 286 #define C_SW1           (_ULCAST_(1) <<  9)
 287 #define C_IRQ0          (_ULCAST_(1) << 10)
 288 #define C_IRQ1          (_ULCAST_(1) << 11)
 289 #define C_IRQ2          (_ULCAST_(1) << 12)
 290 #define C_IRQ3          (_ULCAST_(1) << 13)
 291 #define C_IRQ4          (_ULCAST_(1) << 14)
 292 #define C_IRQ5          (_ULCAST_(1) << 15)
 293
 294 /*
 295  * Bitfields in the R4xx0 cp0 status register
 296  */
 297 #define ST0_IE                  0x00000001
 298 #define ST0_EXL                 0x00000002
 299 #define ST0_ERL                 0x00000004
 300 #define ST0_KSU                 0x00000018
 301 #  define KSU_USER              0x00000010
 302 #  define KSU_SUPERVISOR        0x00000008
 303 #  define KSU_KERNEL            0x00000000
 304 #define ST0_UX                  0x00000020
 305 #define ST0_SX                  0x00000040
 306 #define ST0_KX                  0x00000080
 307 #define ST0_DE                  0x00010000
 308 #define ST0_CE                  0x00020000
 309
 310 /*
 311  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 312  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 313  * processors.
 314  */
 315 #define ST0_CO                  0x08000000
 316
 317 /*
 318  * Bitfields in the R[23]000 cp0 status register.
 319  */
 320 #define ST0_IEC                 0x00000001
 321 #define ST0_KUC                 0x00000002
 322 #define ST0_IEP                 0x00000004
 323 #define ST0_KUP                 0x00000008
 324 #define ST0_IEO                 0x00000010
 325 #define ST0_KUO                 0x00000020
 326 /* bits 6 & 7 are reserved on R[23]000 */
 327 #define ST0_ISC                 0x00010000
 328 #define ST0_SWC                 0x00020000
 329 #define ST0_CM                  0x00080000
 330
 331 /*
 332  * Bits specific to the R4640/R4650
 333  */
 334 #define ST0_UM                  (_ULCAST_(1) <<  4)
 335 #define ST0_IL                  (_ULCAST_(1) << 23)
 336 #define ST0_DL                  (_ULCAST_(1) << 24)
 337
 338 /*
 339  * Enable the MIPS MDMX and DSP ASEs
 340  */
 341 #define ST0_MX                  0x01000000
 342
 343 /*
 344  * Bitfields in the TX39 family CP0 Configuration Register 3
 345  */
 346 #define TX39_CONF_ICS_SHIFT     19
 347 #define TX39_CONF_ICS_MASK      0x00380000
 348 #define TX39_CONF_ICS_1KB       0x00000000
 349 #define TX39_CONF_ICS_2KB       0x00080000
 350 #define TX39_CONF_ICS_4KB       0x00100000
 351 #define TX39_CONF_ICS_8KB       0x00180000
 352 #define TX39_CONF_ICS_16KB      0x00200000
 353
 354 #define TX39_CONF_DCS_SHIFT     16
 355 #define TX39_CONF_DCS_MASK      0x00070000
 356 #define TX39_CONF_DCS_1KB       0x00000000
 357 #define TX39_CONF_DCS_2KB       0x00010000
 358 #define TX39_CONF_DCS_4KB       0x00020000
 359 #define TX39_CONF_DCS_8KB       0x00030000
 360 #define TX39_CONF_DCS_16KB      0x00040000
 361
 362 #define TX39_CONF_CWFON         0x00004000
 363 #define TX39_CONF_WBON          0x00002000
 364 #define TX39_CONF_RF_SHIFT      10
 365 #define TX39_CONF_RF_MASK       0x00000c00
 366 #define TX39_CONF_DOZE          0x00000200
 367 #define TX39_CONF_HALT          0x00000100
 368 #define TX39_CONF_LOCK          0x00000080
 369 #define TX39_CONF_ICE           0x00000020
 370 #define TX39_CONF_DCE           0x00000010
 371 #define TX39_CONF_IRSIZE_SHIFT  2
 372 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 373 #define TX39_CONF_DRSIZE_SHIFT  0
 374 #define TX39_CONF_DRSIZE_MASK   0x00000003
 375
 376 /*
 377  * Status register bits available in all MIPS CPUs.
 378  */
 379 #define ST0_IM                  0x0000ff00
 380 #define  STATUSB_IP0            8
 381 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 382 #define  STATUSB_IP1            9
 383 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 384 #define  STATUSB_IP2            10
 385 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 386 #define  STATUSB_IP3            11
 387 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 388 #define  STATUSB_IP4            12
 389 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 390 #define  STATUSB_IP5            13
 391 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 392 #define  STATUSB_IP6            14
 393 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 394 #define  STATUSB_IP7            15
 395 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 396 #define  STATUSB_IP8            0
 397 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 398 #define  STATUSB_IP9            1
 399 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 400 #define  STATUSB_IP10           2
 401 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 402 #define  STATUSB_IP11           3
 403 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 404 #define  STATUSB_IP12           4
 405 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 406 #define  STATUSB_IP13           5
 407 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 408 #define  STATUSB_IP14           6
 409 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 410 #define  STATUSB_IP15           7
 411 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 412 #define ST0_CH                  0x00040000
 413 #define ST0_NMI                 0x00080000
 414 #define ST0_SR                  0x00100000
 415 #define ST0_TS                  0x00200000
 416 #define ST0_BEV                 0x00400000
 417 #define ST0_RE                  0x02000000
 418 #define ST0_FR                  0x04000000
 419 #define ST0_CU                  0xf0000000
 420 #define ST0_CU0                 0x10000000
 421 #define ST0_CU1                 0x20000000
 422 #define ST0_CU2                 0x40000000
 423 #define ST0_CU3                 0x80000000
 424 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 425
 426 /*
 427  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 428  *
 429  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 430  */
 431 #define INTCTLB_IPPCI           26
 432 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 433 #define INTCTLB_IPTI            29
 434 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 435
 436 /*
 437  * Bitfields and bit numbers in the coprocessor 0 cause register.
 438  *
 439  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 440  */
 441 #define  CAUSEB_EXCCODE         2
 442 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 443 #define  CAUSEB_IP              8
 444 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 445 #define  CAUSEB_IP0             8
 446 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 447 #define  CAUSEB_IP1             9
 448 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 449 #define  CAUSEB_IP2             10
 450 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 451 #define  CAUSEB_IP3             11
 452 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 453 #define  CAUSEB_IP4             12
 454 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 455 #define  CAUSEB_IP5             13
 456 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 457 #define  CAUSEB_IP6             14
 458 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 459 #define  CAUSEB_IP7             15
 460 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 461 #define  CAUSEB_IV              23
 462 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 463 #define  CAUSEB_PCI             26
 464 #define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 465 #define  CAUSEB_CE              28
 466 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 467 #define  CAUSEB_TI              30
 468 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
 469 #define  CAUSEB_BD              31
 470 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 471
 472 /*
 473  * Bits in the coprocessor 0 config register.
 474  */
 475 /* Generic bits.  */
 476 #define CONF_CM_CACHABLE_NO_WA          0
 477 #define CONF_CM_CACHABLE_WA             1
 478 #define CONF_CM_UNCACHED                2
 479 #define CONF_CM_CACHABLE_NONCOHERENT    3
 480 #define CONF_CM_CACHABLE_CE             4
 481 #define CONF_CM_CACHABLE_COW            5
 482 #define CONF_CM_CACHABLE_CUW            6
 483 #define CONF_CM_CACHABLE_ACCELERATED    7
 484 #define CONF_CM_CMASK                   7
 485 #define CONF_BE                 (_ULCAST_(1) << 15)
 486
 487 /* Bits common to various processors.  */
 488 #define CONF_CU                 (_ULCAST_(1) <<  3)
 489 #define CONF_DB                 (_ULCAST_(1) <<  4)
 490 #define CONF_IB                 (_ULCAST_(1) <<  5)
 491 #define CONF_DC                 (_ULCAST_(7) <<  6)
 492 #define CONF_IC                 (_ULCAST_(7) <<  9)
 493 #define CONF_EB                 (_ULCAST_(1) << 13)
 494 #define CONF_EM                 (_ULCAST_(1) << 14)
 495 #define CONF_SM                 (_ULCAST_(1) << 16)
 496 #define CONF_SC                 (_ULCAST_(1) << 17)
 497 #define CONF_EW                 (_ULCAST_(3) << 18)
 498 #define CONF_EP                 (_ULCAST_(15)<< 24)
 499 #define CONF_EC                 (_ULCAST_(7) << 28)
 500 #define CONF_CM                 (_ULCAST_(1) << 31)
 501
 502 /* Bits specific to the R4xx0.  */
 503 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 504 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 505 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 506
 507 /* Bits specific to the R5000.  */
 508 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 509 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 510
 511 /* Bits specific to the RM7000.  */
 512 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 513 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 514 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 515 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 516 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 517 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 518
 519 /* Bits specific to the R10000.  */
 520 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 521 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 522 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 523 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 524 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 525 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 526 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 527 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 528 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 529 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 530 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 531
 532 /* Bits specific to the VR41xx.  */
 533 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 534 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 535 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 536 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 537 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 538
 539 /* Bits specific to the R30xx.  */
 540 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 541 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 542 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 543 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 544 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 545 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 546 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 547 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 548 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 549
 550 /* Bits specific to the TX49.  */
 551 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 552 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 553 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 554 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 555
 556 /* Bits specific to the MIPS32/64 PRA.  */
 557 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 558 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 559 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 560 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 561
 562 /*
 563  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 564  */
 565 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 566 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 567 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 568 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 569 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 570 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 571 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 572 #define MIPS_CONF1_DA_SHF       7
 573 #define MIPS_CONF1_DA_SZ        3
 574 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 575 #define MIPS_CONF1_DL_SHF       10
 576 #define MIPS_CONF1_DL_SZ        3
 577 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 578 #define MIPS_CONF1_DS_SHF       13
 579 #define MIPS_CONF1_DS_SZ        3
 580 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 581 #define MIPS_CONF1_IA_SHF       16
 582 #define MIPS_CONF1_IA_SZ        3
 583 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 584 #define MIPS_CONF1_IL_SHF       19
 585 #define MIPS_CONF1_IL_SZ        3
 586 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 587 #define MIPS_CONF1_IS_SHF       22
 588 #define MIPS_CONF1_IS_SZ        3
 589 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 590 #define MIPS_CONF1_TLBS_SHIFT   (25)
 591 #define MIPS_CONF1_TLBS_SIZE    (6)
 592 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 593
 594 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 595 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 596 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 597 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 598 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 599 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 600 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 601 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 602
 603 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 604 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 605 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 606 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 607 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 608 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 609 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 610 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 611 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 612 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 613 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 614 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 615 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 616 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 617 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 618 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 619 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 620 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 621 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 622 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 623 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 624 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 625 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 626 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 627 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 628 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 629 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 630
 631 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 632 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 633 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 634 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 635 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 636 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 637 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 638 /* bits 10:8 in FTLB-only configurations */
 639 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 640 /* bits 12:8 in VTLB-FTLB only configurations */
 641 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 642 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 643 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 644 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 645 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 646 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 647 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 648 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 649 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 650 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 651 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 652
 653 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 654 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 655 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 656 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 657 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 658 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 659 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 660 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 661 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 662 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 663 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 664
 665 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 666 /* proAptiv FTLB on/off bit */
 667 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 668 /* FTLB probability bits */
 669 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 670
 671 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 672
 673 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 674
 675 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 676 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 677
 678 /* MAAR bit definitions */
 679 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 680 #define MIPS_MAAR_ADDR_SHIFT    12
 681 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 682 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 683
 684 /*  EntryHI bit definition */
 685 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 686
 687 /* CMGCRBase bit definitions */
 688 #define MIPS_CMGCRB_BASE        11
 689 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 690
 691 /*
 692  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 693  */
 694 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 695 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 696 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 697 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 698 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 699 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 700 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 701 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 702
 703 /*
 704  * Bits in the MIPS32 Memory Segmentation registers.
 705  */
 706 #define MIPS_SEGCFG_PA_SHIFT    9
 707 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 708 #define MIPS_SEGCFG_AM_SHIFT    4
 709 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 710 #define MIPS_SEGCFG_EU_SHIFT    3
 711 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 712 #define MIPS_SEGCFG_C_SHIFT     0
 713 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 714
 715 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 716 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 717 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 718 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 719 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 720 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 721 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 722
 723 #define MIPS_PWFIELD_GDI_SHIFT  24
 724 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 725 #define MIPS_PWFIELD_UDI_SHIFT  18
 726 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 727 #define MIPS_PWFIELD_MDI_SHIFT  12
 728 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 729 #define MIPS_PWFIELD_PTI_SHIFT  6
 730 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 731 #define MIPS_PWFIELD_PTEI_SHIFT 0
 732 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 733
 734 #define MIPS_PWSIZE_GDW_SHIFT   24
 735 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 736 #define MIPS_PWSIZE_UDW_SHIFT   18
 737 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 738 #define MIPS_PWSIZE_MDW_SHIFT   12
 739 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 740 #define MIPS_PWSIZE_PTW_SHIFT   6
 741 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 742 #define MIPS_PWSIZE_PTEW_SHIFT  0
 743 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 744
 745 #define MIPS_PWCTL_PWEN_SHIFT   31
 746 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 747 #define MIPS_PWCTL_DPH_SHIFT    7
 748 #define MIPS_PWCTL_DPH_MASK     0x00000080
 749 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 750 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 751 #define MIPS_PWCTL_PSN_SHIFT    0
 752 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 753
 754 #ifndef __ASSEMBLY__
 755
 756 /*
 757  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 758  */
 759 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 760     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 761 #define get_isa16_mode(x)               ((x) & 0x1)
 762 #define msk_isa16_mode(x)               ((x) & ~0x1)
 763 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 764 #else
 765 #define get_isa16_mode(x)               0
 766 #define msk_isa16_mode(x)               (x)
 767 #define set_isa16_mode(x)               do { } while(0)
 768 #endif
 769
 770 /*
 771  * microMIPS instructions can be 16-bit or 32-bit in length. This
 772  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 773  */
 774 static inline int mm_insn_16bit(u16 insn)
 775 {
 776         u16 opcode = (insn >> 10) & 0x7;
 777
 778         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 779 }
 780
 781 /*
 782  * TLB Invalidate Flush
 783  */
 784 static inline void tlbinvf(void)
 785 {
 786         __asm__ __volatile__(
 787                 ".set push\n\t"
 788                 ".set noreorder\n\t"
 789                 ".word 0x42000004\n\t" /* tlbinvf */
 790                 ".set pop");
 791 }
 792
 793
 794 /*
 795  * Functions to access the R10000 performance counters.  These are basically
 796  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 797  * performance counter number encoded into bits 1 ... 5 of the instruction.
 798  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 799  * disassembler these will look like an access to sel 0 or 1.
 800  */
 801 #define read_r10k_perf_cntr(counter)                            \
 802 ({                                                              \
 803         unsigned int __res;                                     \
 804         __asm__ __volatile__(                                   \
 805         "mfpc\t%0, %1"                                          \
 806         : "=r" (__res)                                          \
 807         : "i" (counter));                                       \
 808                                                                 \
 809         __res;                                                  \
 810 })
 811
 812 #define write_r10k_perf_cntr(counter,val)                       \
 813 do {                                                            \
 814         __asm__ __volatile__(                                   \
 815         "mtpc\t%0, %1"                                          \
 816         :                                                       \
 817         : "r" (val), "i" (counter));                            \
 818 } while (0)
 819
 820 #define read_r10k_perf_event(counter)                           \
 821 ({                                                              \
 822         unsigned int __res;                                     \
 823         __asm__ __volatile__(                                   \
 824         "mfps\t%0, %1"                                          \
 825         : "=r" (__res)                                          \
 826         : "i" (counter));                                       \
 827                                                                 \
 828         __res;                                                  \
 829 })
 830
 831 #define write_r10k_perf_cntl(counter,val)                       \
 832 do {                                                            \
 833         __asm__ __volatile__(                                   \
 834         "mtps\t%0, %1"                                          \
 835         :                                                       \
 836         : "r" (val), "i" (counter));                            \
 837 } while (0)
 838
 839
 840 /*
 841  * Macros to access the system control coprocessor
 842  */
 843
 844 #define __read_32bit_c0_register(source, sel)                           \
 845 ({ int __res;                                                           \
 846         if (sel == 0)                                                   \
 847                 __asm__ __volatile__(                                   \
 848                         "mfc0\t%0, " #source "\n\t"                     \
 849                         : "=r" (__res));                                \
 850         else                                                            \
 851                 __asm__ __volatile__(                                   \
 852                         ".set\tmips32\n\t"                              \
 853                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 854                         ".set\tmips0\n\t"                               \
 855                         : "=r" (__res));                                \
 856         __res;                                                          \
 857 })
 858
 859 #define __read_64bit_c0_register(source, sel)                           \
 860 ({ unsigned long long __res;                                            \
 861         if (sizeof(unsigned long) == 4)                                 \
 862                 __res = __read_64bit_c0_split(source, sel);             \
 863         else if (sel == 0)                                              \
 864                 __asm__ __volatile__(                                   \
 865                         ".set\tmips3\n\t"                               \
 866                         "dmfc0\t%0, " #source "\n\t"                    \
 867                         ".set\tmips0"                                   \
 868                         : "=r" (__res));                                \
 869         else                                                            \
 870                 __asm__ __volatile__(                                   \
 871                         ".set\tmips64\n\t"                              \
 872                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 873                         ".set\tmips0"                                   \
 874                         : "=r" (__res));                                \
 875         __res;                                                          \
 876 })
 877
 878 #define __write_32bit_c0_register(register, sel, value)                 \
 879 do {                                                                    \
 880         if (sel == 0)                                                   \
 881                 __asm__ __volatile__(                                   \
 882                         "mtc0\t%z0, " #register "\n\t"                  \
 883                         : : "Jr" ((unsigned int)(value)));              \
 884         else                                                            \
 885                 __asm__ __volatile__(                                   \
 886                         ".set\tmips32\n\t"                              \
 887                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 888                         ".set\tmips0"                                   \
 889                         : : "Jr" ((unsigned int)(value)));              \
 890 } while (0)
 891
 892 #define __write_64bit_c0_register(register, sel, value)                 \
 893 do {                                                                    \
 894         if (sizeof(unsigned long) == 4)                                 \
 895                 __write_64bit_c0_split(register, sel, value);           \
 896         else if (sel == 0)                                              \
 897                 __asm__ __volatile__(                                   \
 898                         ".set\tmips3\n\t"                               \
 899                         "dmtc0\t%z0, " #register "\n\t"                 \
 900                         ".set\tmips0"                                   \
 901                         : : "Jr" (value));                              \
 902         else                                                            \
 903                 __asm__ __volatile__(                                   \
 904                         ".set\tmips64\n\t"                              \
 905                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 906                         ".set\tmips0"                                   \
 907                         : : "Jr" (value));                              \
 908 } while (0)
 909
 910 #define __read_ulong_c0_register(reg, sel)                              \
 911         ((sizeof(unsigned long) == 4) ?                                 \
 912         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 913         (unsigned long) __read_64bit_c0_register(reg, sel))
 914
 915 #define __write_ulong_c0_register(reg, sel, val)                        \
 916 do {                                                                    \
 917         if (sizeof(unsigned long) == 4)                                 \
 918                 __write_32bit_c0_register(reg, sel, val);               \
 919         else                                                            \
 920                 __write_64bit_c0_register(reg, sel, val);               \
 921 } while (0)
 922
 923 /*
 924  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 925  */
 926 #define __read_32bit_c0_ctrl_register(source)                           \
 927 ({ int __res;                                                           \
 928         __asm__ __volatile__(                                           \
 929                 "cfc0\t%0, " #source "\n\t"                             \
 930                 : "=r" (__res));                                        \
 931         __res;                                                          \
 932 })
 933
 934 #define __write_32bit_c0_ctrl_register(register, value)                 \
 935 do {                                                                    \
 936         __asm__ __volatile__(                                           \
 937                 "ctc0\t%z0, " #register "\n\t"                          \
 938                 : : "Jr" ((unsigned int)(value)));                      \
 939 } while (0)
 940
 941 /*
 942  * These versions are only needed for systems with more than 38 bits of
 943  * physical address space running the 32-bit kernel.  That's none atm :-)
 944  */
 945 #define __read_64bit_c0_split(source, sel)                              \
 946 ({                                                                      \
 947         unsigned long long __val;                                       \
 948         unsigned long __flags;                                          \
 949                                                                         \
 950         local_irq_save(__flags);                                        \
 951         if (sel == 0)                                                   \
 952                 __asm__ __volatile__(                                   \
 953                         ".set\tmips64\n\t"                              \
 954                         "dmfc0\t%M0, " #source "\n\t"                   \
 955                         "dsll\t%L0, %M0, 32\n\t"                        \
 956                         "dsra\t%M0, %M0, 32\n\t"                        \
 957                         "dsra\t%L0, %L0, 32\n\t"                        \
 958                         ".set\tmips0"                                   \
 959                         : "=r" (__val));                                \
 960         else                                                            \
 961                 __asm__ __volatile__(                                   \
 962                         ".set\tmips64\n\t"                              \
 963                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 964                         "dsll\t%L0, %M0, 32\n\t"                        \
 965                         "dsra\t%M0, %M0, 32\n\t"                        \
 966                         "dsra\t%L0, %L0, 32\n\t"                        \
 967                         ".set\tmips0"                                   \
 968                         : "=r" (__val));                                \
 969         local_irq_restore(__flags);                                     \
 970                                                                         \
 971         __val;                                                          \
 972 })
 973
 974 #define __write_64bit_c0_split(source, sel, val)                        \
 975 do {                                                                    \
 976         unsigned long __flags;                                          \
 977                                                                         \
 978         local_irq_save(__flags);                                        \
 979         if (sel == 0)                                                   \
 980                 __asm__ __volatile__(                                   \
 981                         ".set\tmips64\n\t"                              \
 982                         "dsll\t%L0, %L0, 32\n\t"                        \
 983                         "dsrl\t%L0, %L0, 32\n\t"                        \
 984                         "dsll\t%M0, %M0, 32\n\t"                        \
 985                         "or\t%L0, %L0, %M0\n\t"                         \
 986                         "dmtc0\t%L0, " #source "\n\t"                   \
 987                         ".set\tmips0"                                   \
 988                         : : "r" (val));                                 \
 989         else                                                            \
 990                 __asm__ __volatile__(                                   \
 991                         ".set\tmips64\n\t"                              \
 992                         "dsll\t%L0, %L0, 32\n\t"                        \
 993                         "dsrl\t%L0, %L0, 32\n\t"                        \
 994                         "dsll\t%M0, %M0, 32\n\t"                        \
 995                         "or\t%L0, %L0, %M0\n\t"                         \
 996                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 997                         ".set\tmips0"                                   \
 998                         : : "r" (val));                                 \
 999         local_irq_restore(__flags);                                     \
1000 } while (0)
1001
1002 #define __readx_32bit_c0_register(source)                               \
1003 ({                                                                      \
1004         unsigned int __res;                                             \
1005                                                                         \
1006         __asm__ __volatile__(                                           \
1007         "       .set    push                                    \n"     \
1008         "       .set    noat                                    \n"     \
1009         "       .set    mips32r2                                \n"     \
1010         "       .insn                                           \n"     \
1011         "       # mfhc0 $1, %1                                  \n"     \
1012         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1013         "       move    %0, $1                                  \n"     \
1014         "       .set    pop                                     \n"     \
1015         : "=r" (__res)                                                  \
1016         : "i" (source));                                                \
1017         __res;                                                          \
1018 })
1019
1020 #define __writex_32bit_c0_register(register, value)                     \
1021 do {                                                                    \
1022         __asm__ __volatile__(                                           \
1023         "       .set    push                                    \n"     \
1024         "       .set    noat                                    \n"     \
1025         "       .set    mips32r2                                \n"     \
1026         "       move    $1, %0                                  \n"     \
1027         "       # mthc0 $1, %1                                  \n"     \
1028         "       .insn                                           \n"     \
1029         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1030         "       .set    pop                                     \n"     \
1031         :                                                               \
1032         : "r" (value), "i" (register));                                 \
1033 } while (0)
1034
1035 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1036 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1037
1038 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1039 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1040
1041 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1042 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1043
1044 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1045 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1046
1047 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1048 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1049
1050 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1051 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1052
1053 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1054 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1055
1056 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1057 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1058
1059 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1060 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1061
1062 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1063 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1064
1065 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1066 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1067
1068 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1069 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1070
1071 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1072
1073 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1074 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1075
1076 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1077 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1078
1079 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1080 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1081
1082 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1083 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1084
1085 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1086 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1087
1088 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1089 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1090
1091 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1092 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1093
1094 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1095 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1096
1097 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1098 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1099
1100 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1101
1102 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1103
1104 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1105 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1106
1107 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1108 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1109
1110 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1111
1112 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1113
1114 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1115 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1116 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1117 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1118 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1119 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1120 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1121 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1122 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1123 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1124 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1125 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1126 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1127 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1128 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1129 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1130
1131 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1132 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1133 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1134 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1135
1136 /*
1137  * The WatchLo register.  There may be up to 8 of them.
1138  */
1139 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1140 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1141 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1142 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1143 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1144 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1145 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1146 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1147 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1148 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1149 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1150 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1151 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1152 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1153 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1154 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1155
1156 /*
1157  * The WatchHi register.  There may be up to 8 of them.
1158  */
1159 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1160 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1161 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1162 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1163 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1164 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1165 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1166 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1167
1168 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1169 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1170 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1171 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1172 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1173 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1174 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1175 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1176
1177 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1178 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1179
1180 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1181 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1182
1183 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1184 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1185
1186 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1187 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1188
1189 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1190 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1191
1192 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1193 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1194
1195 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1196 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1197
1198 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1199 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1200
1201 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1202 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1203
1204 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1205 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1206
1207 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1208 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1209
1210 /*
1211  * MIPS32 / MIPS64 performance counters
1212  */
1213 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1214 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1215 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1216 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1217 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1218 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1219 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1220 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1221 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1222 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1223 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1224 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1225 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1226 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1227 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1228 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1229 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1230 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1231 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1232 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1233 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1234 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1235 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1236 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1237
1238 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1239 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1240
1241 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1242 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1243
1244 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1245
1246 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1247 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1248
1249 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1250 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1251
1252 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1253 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1254
1255 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1256 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1257
1258 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1259 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1260
1261 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1262 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1263
1264 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1265 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1266
1267 /* MIPSR2 */
1268 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1269 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1270
1271 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1272 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1273
1274 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1275 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1276
1277 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1278 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1279
1280 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1281 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1282
1283 /* MIPSR3 */
1284 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1285 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1286
1287 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1288 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1289
1290 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1291 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1292
1293 /* Hardware Page Table Walker */
1294 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1295 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1296
1297 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1298 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1299
1300 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1301 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1302
1303 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1304 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1305
1306 /* Cavium OCTEON (cnMIPS) */
1307 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1308 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1309
1310 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1311 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1312
1313 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1314 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1315 /*
1316  * The cacheerr registers are not standardized.  On OCTEON, they are
1317  * 64 bits wide.
1318  */
1319 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1320 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1321
1322 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1323 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1324
1325 /* BMIPS3300 */
1326 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1327 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1328
1329 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1330 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1331
1332 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1333 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1334
1335 /* BMIPS43xx */
1336 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1337 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1338
1339 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1340 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1341
1342 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1343 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1344
1345 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1346 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1347
1348 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1349 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1350
1351 /* BMIPS5000 */
1352 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1353 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1354
1355 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1356 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1357
1358 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1359 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1360
1361 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1362 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1363
1364 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1365 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1366
1367 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1368 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1369
1370 /*
1371  * Macros to access the floating point coprocessor control registers
1372  */
1373 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1374 ({                                                                      \
1375         int __res;                                                      \
1376                                                                         \
1377         __asm__ __volatile__(                                           \
1378         "       .set    push                                    \n"     \
1379         "       .set    reorder                                 \n"     \
1380         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1381         "       # like Octeon.                                  \n"     \
1382         "       .set    mips1                                   \n"     \
1383         "       "STR(gas_hardfloat)"                            \n"     \
1384         "       cfc1    %0,"STR(source)"                        \n"     \
1385         "       .set    pop                                     \n"     \
1386         : "=r" (__res));                                                \
1387         __res;                                                          \
1388 })
1389
1390 #ifdef GAS_HAS_SET_HARDFLOAT
1391 #define read_32bit_cp1_register(source)                                 \
1392         _read_32bit_cp1_register(source, .set hardfloat)
1393 #else
1394 #define read_32bit_cp1_register(source)                                 \
1395         _read_32bit_cp1_register(source, )
1396 #endif
1397
1398 #ifdef HAVE_AS_DSP
1399 #define rddsp(mask)                                                     \
1400 ({                                                                      \
1401         unsigned int __dspctl;                                          \
1402                                                                         \
1403         __asm__ __volatile__(                                           \
1404         "       .set push                                       \n"     \
1405         "       .set dsp                                        \n"     \
1406         "       rddsp   %0, %x1                                 \n"     \
1407         "       .set pop                                        \n"     \
1408         : "=r" (__dspctl)                                               \
1409         : "i" (mask));                                                  \
1410         __dspctl;                                                       \
1411 })
1412
1413 #define wrdsp(val, mask)                                                \
1414 do {                                                                    \
1415         __asm__ __volatile__(                                           \
1416         "       .set push                                       \n"     \
1417         "       .set dsp                                        \n"     \
1418         "       wrdsp   %0, %x1                                 \n"     \
1419         "       .set pop                                        \n"     \
1420         :                                                               \
1421         : "r" (val), "i" (mask));                                       \
1422 } while (0)
1423
1424 #define mflo0()                                                         \
1425 ({                                                                      \
1426         long mflo0;                                                     \
1427         __asm__(                                                        \
1428         "       .set push                                       \n"     \
1429         "       .set dsp                                        \n"     \
1430         "       mflo %0, $ac0                                   \n"     \
1431         "       .set pop                                        \n"     \
1432         : "=r" (mflo0));                                                \
1433         mflo0;                                                          \
1434 })
1435
1436 #define mflo1()                                                         \
1437 ({                                                                      \
1438         long mflo1;                                                     \
1439         __asm__(                                                        \
1440         "       .set push                                       \n"     \
1441         "       .set dsp                                        \n"     \
1442         "       mflo %0, $ac1                                   \n"     \
1443         "       .set pop                                        \n"     \
1444         : "=r" (mflo1));                                                \
1445         mflo1;                                                          \
1446 })
1447
1448 #define mflo2()                                                         \
1449 ({                                                                      \
1450         long mflo2;                                                     \
1451         __asm__(                                                        \
1452         "       .set push                                       \n"     \
1453         "       .set dsp                                        \n"     \
1454         "       mflo %0, $ac2                                   \n"     \
1455         "       .set pop                                        \n"     \
1456         : "=r" (mflo2));                                                \
1457         mflo2;                                                          \
1458 })
1459
1460 #define mflo3()                                                         \
1461 ({                                                                      \
1462         long mflo3;                                                     \
1463         __asm__(                                                        \
1464         "       .set push                                       \n"     \
1465         "       .set dsp                                        \n"     \
1466         "       mflo %0, $ac3                                   \n"     \
1467         "       .set pop                                        \n"     \
1468         : "=r" (mflo3));                                                \
1469         mflo3;                                                          \
1470 })
1471
1472 #define mfhi0()                                                         \
1473 ({                                                                      \
1474         long mfhi0;                                                     \
1475         __asm__(                                                        \
1476         "       .set push                                       \n"     \
1477         "       .set dsp                                        \n"     \
1478         "       mfhi %0, $ac0                                   \n"     \
1479         "       .set pop                                        \n"     \
1480         : "=r" (mfhi0));                                                \
1481         mfhi0;                                                          \
1482 })
1483
1484 #define mfhi1()                                                         \
1485 ({                                                                      \
1486         long mfhi1;                                                     \
1487         __asm__(                                                        \
1488         "       .set push                                       \n"     \
1489         "       .set dsp                                        \n"     \
1490         "       mfhi %0, $ac1                                   \n"     \
1491         "       .set pop                                        \n"     \
1492         : "=r" (mfhi1));                                                \
1493         mfhi1;                                                          \
1494 })
1495
1496 #define mfhi2()                                                         \
1497 ({                                                                      \
1498         long mfhi2;                                                     \
1499         __asm__(                                                        \
1500         "       .set push                                       \n"     \
1501         "       .set dsp                                        \n"     \
1502         "       mfhi %0, $ac2                                   \n"     \
1503         "       .set pop                                        \n"     \
1504         : "=r" (mfhi2));                                                \
1505         mfhi2;                                                          \
1506 })
1507
1508 #define mfhi3()                                                         \
1509 ({                                                                      \
1510         long mfhi3;                                                     \
1511         __asm__(                                                        \
1512         "       .set push                                       \n"     \
1513         "       .set dsp                                        \n"     \
1514         "       mfhi %0, $ac3                                   \n"     \
1515         "       .set pop                                        \n"     \
1516         : "=r" (mfhi3));                                                \
1517         mfhi3;                                                          \
1518 })
1519
1520
1521 #define mtlo0(x)                                                        \
1522 ({                                                                      \
1523         __asm__(                                                        \
1524         "       .set push                                       \n"     \
1525         "       .set dsp                                        \n"     \
1526         "       mtlo %0, $ac0                                   \n"     \
1527         "       .set pop                                        \n"     \
1528         :                                                               \
1529         : "r" (x));                                                     \
1530 })
1531
1532 #define mtlo1(x)                                                        \
1533 ({                                                                      \
1534         __asm__(                                                        \
1535         "       .set push                                       \n"     \
1536         "       .set dsp                                        \n"     \
1537         "       mtlo %0, $ac1                                   \n"     \
1538         "       .set pop                                        \n"     \
1539         :                                                               \
1540         : "r" (x));                                                     \
1541 })
1542
1543 #define mtlo2(x)                                                        \
1544 ({                                                                      \
1545         __asm__(                                                        \
1546         "       .set push                                       \n"     \
1547         "       .set dsp                                        \n"     \
1548         "       mtlo %0, $ac2                                   \n"     \
1549         "       .set pop                                        \n"     \
1550         :                                                               \
1551         : "r" (x));                                                     \
1552 })
1553
1554 #define mtlo3(x)                                                        \
1555 ({                                                                      \
1556         __asm__(                                                        \
1557         "       .set push                                       \n"     \
1558         "       .set dsp                                        \n"     \
1559         "       mtlo %0, $ac3                                   \n"     \
1560         "       .set pop                                        \n"     \
1561         :                                                               \
1562         : "r" (x));                                                     \
1563 })
1564
1565 #define mthi0(x)                                                        \
1566 ({                                                                      \
1567         __asm__(                                                        \
1568         "       .set push                                       \n"     \
1569         "       .set dsp                                        \n"     \
1570         "       mthi %0, $ac0                                   \n"     \
1571         "       .set pop                                        \n"     \
1572         :                                                               \
1573         : "r" (x));                                                     \
1574 })
1575
1576 #define mthi1(x)                                                        \
1577 ({                                                                      \
1578         __asm__(                                                        \
1579         "       .set push                                       \n"     \
1580         "       .set dsp                                        \n"     \
1581         "       mthi %0, $ac1                                   \n"     \
1582         "       .set pop                                        \n"     \
1583         :                                                               \
1584         : "r" (x));                                                     \
1585 })
1586
1587 #define mthi2(x)                                                        \
1588 ({                                                                      \
1589         __asm__(                                                        \
1590         "       .set push                                       \n"     \
1591         "       .set dsp                                        \n"     \
1592         "       mthi %0, $ac2                                   \n"     \
1593         "       .set pop                                        \n"     \
1594         :                                                               \
1595         : "r" (x));                                                     \
1596 })
1597
1598 #define mthi3(x)                                                        \
1599 ({                                                                      \
1600         __asm__(                                                        \
1601         "       .set push                                       \n"     \
1602         "       .set dsp                                        \n"     \
1603         "       mthi %0, $ac3                                   \n"     \
1604         "       .set pop                                        \n"     \
1605         :                                                               \
1606         : "r" (x));                                                     \
1607 })
1608
1609 #else
1610
1611 #ifdef CONFIG_CPU_MICROMIPS
1612 #define rddsp(mask)                                                     \
1613 ({                                                                      \
1614         unsigned int __res;                                             \
1615                                                                         \
1616         __asm__ __volatile__(                                           \
1617         "       .set    push                                    \n"     \
1618         "       .set    noat                                    \n"     \
1619         "       # rddsp $1, %x1                                 \n"     \
1620         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1621         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1622         "       move    %0, $1                                  \n"     \
1623         "       .set    pop                                     \n"     \
1624         : "=r" (__res)                                                  \
1625         : "i" (mask));                                                  \
1626         __res;                                                          \
1627 })
1628
1629 #define wrdsp(val, mask)                                                \
1630 do {                                                                    \
1631         __asm__ __volatile__(                                           \
1632         "       .set    push                                    \n"     \
1633         "       .set    noat                                    \n"     \
1634         "       move    $1, %0                                  \n"     \
1635         "       # wrdsp $1, %x1                                 \n"     \
1636         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1637         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1638         "       .set    pop                                     \n"     \
1639         :                                                               \
1640         : "r" (val), "i" (mask));                                       \
1641 } while (0)
1642
1643 #define _umips_dsp_mfxxx(ins)                                           \
1644 ({                                                                      \
1645         unsigned long __treg;                                           \
1646                                                                         \
1647         __asm__ __volatile__(                                           \
1648         "       .set    push                                    \n"     \
1649         "       .set    noat                                    \n"     \
1650         "       .hword  0x0001                                  \n"     \
1651         "       .hword  %x1                                     \n"     \
1652         "       move    %0, $1                                  \n"     \
1653         "       .set    pop                                     \n"     \
1654         : "=r" (__treg)                                                 \
1655         : "i" (ins));                                                   \
1656         __treg;                                                         \
1657 })
1658
1659 #define _umips_dsp_mtxxx(val, ins)                                      \
1660 do {                                                                    \
1661         __asm__ __volatile__(                                           \
1662         "       .set    push                                    \n"     \
1663         "       .set    noat                                    \n"     \
1664         "       move    $1, %0                                  \n"     \
1665         "       .hword  0x0001                                  \n"     \
1666         "       .hword  %x1                                     \n"     \
1667         "       .set    pop                                     \n"     \
1668         :                                                               \
1669         : "r" (val), "i" (ins));                                        \
1670 } while (0)
1671
1672 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1673 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1674
1675 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1676 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1677
1678 #define mflo0() _umips_dsp_mflo(0)
1679 #define mflo1() _umips_dsp_mflo(1)
1680 #define mflo2() _umips_dsp_mflo(2)
1681 #define mflo3() _umips_dsp_mflo(3)
1682
1683 #define mfhi0() _umips_dsp_mfhi(0)
1684 #define mfhi1() _umips_dsp_mfhi(1)
1685 #define mfhi2() _umips_dsp_mfhi(2)
1686 #define mfhi3() _umips_dsp_mfhi(3)
1687
1688 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1689 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1690 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1691 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1692
1693 #define mthi0(x) _umips_dsp_mthi(x, 0)
1694 #define mthi1(x) _umips_dsp_mthi(x, 1)
1695 #define mthi2(x) _umips_dsp_mthi(x, 2)
1696 #define mthi3(x) _umips_dsp_mthi(x, 3)
1697
1698 #else  /* !CONFIG_CPU_MICROMIPS */
1699 #define rddsp(mask)                                                     \
1700 ({                                                                      \
1701         unsigned int __res;                                             \
1702                                                                         \
1703         __asm__ __volatile__(                                           \
1704         "       .set    push                            \n"             \
1705         "       .set    noat                            \n"             \
1706         "       # rddsp $1, %x1                         \n"             \
1707         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1708         "       move    %0, $1                          \n"             \
1709         "       .set    pop                             \n"             \
1710         : "=r" (__res)                                                  \
1711         : "i" (mask));                                                  \
1712         __res;                                                          \
1713 })
1714
1715 #define wrdsp(val, mask)                                                \
1716 do {                                                                    \
1717         __asm__ __volatile__(                                           \
1718         "       .set    push                                    \n"     \
1719         "       .set    noat                                    \n"     \
1720         "       move    $1, %0                                  \n"     \
1721         "       # wrdsp $1, %x1                                 \n"     \
1722         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1723         "       .set    pop                                     \n"     \
1724         :                                                               \
1725         : "r" (val), "i" (mask));                                       \
1726 } while (0)
1727
1728 #define _dsp_mfxxx(ins)                                                 \
1729 ({                                                                      \
1730         unsigned long __treg;                                           \
1731                                                                         \
1732         __asm__ __volatile__(                                           \
1733         "       .set    push                                    \n"     \
1734         "       .set    noat                                    \n"     \
1735         "       .word   (0x00000810 | %1)                       \n"     \
1736         "       move    %0, $1                                  \n"     \
1737         "       .set    pop                                     \n"     \
1738         : "=r" (__treg)                                                 \
1739         : "i" (ins));                                                   \
1740         __treg;                                                         \
1741 })
1742
1743 #define _dsp_mtxxx(val, ins)                                            \
1744 do {                                                                    \
1745         __asm__ __volatile__(                                           \
1746         "       .set    push                                    \n"     \
1747         "       .set    noat                                    \n"     \
1748         "       move    $1, %0                                  \n"     \
1749         "       .word   (0x00200011 | %1)                       \n"     \
1750         "       .set    pop                                     \n"     \
1751         :                                                               \
1752         : "r" (val), "i" (ins));                                        \
1753 } while (0)
1754
1755 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1756 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1757
1758 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1759 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1760
1761 #define mflo0() _dsp_mflo(0)
1762 #define mflo1() _dsp_mflo(1)
1763 #define mflo2() _dsp_mflo(2)
1764 #define mflo3() _dsp_mflo(3)
1765
1766 #define mfhi0() _dsp_mfhi(0)
1767 #define mfhi1() _dsp_mfhi(1)
1768 #define mfhi2() _dsp_mfhi(2)
1769 #define mfhi3() _dsp_mfhi(3)
1770
1771 #define mtlo0(x) _dsp_mtlo(x, 0)
1772 #define mtlo1(x) _dsp_mtlo(x, 1)
1773 #define mtlo2(x) _dsp_mtlo(x, 2)
1774 #define mtlo3(x) _dsp_mtlo(x, 3)
1775
1776 #define mthi0(x) _dsp_mthi(x, 0)
1777 #define mthi1(x) _dsp_mthi(x, 1)
1778 #define mthi2(x) _dsp_mthi(x, 2)
1779 #define mthi3(x) _dsp_mthi(x, 3)
1780
1781 #endif /* CONFIG_CPU_MICROMIPS */
1782 #endif
1783
1784 /*
1785  * TLB operations.
1786  *
1787  * It is responsibility of the caller to take care of any TLB hazards.
1788  */
1789 static inline void tlb_probe(void)
1790 {
1791         __asm__ __volatile__(
1792                 ".set noreorder\n\t"
1793                 "tlbp\n\t"
1794                 ".set reorder");
1795 }
1796
1797 static inline void tlb_read(void)
1798 {
1799 #if MIPS34K_MISSED_ITLB_WAR
1800         int res = 0;
1801
1802         __asm__ __volatile__(
1803         "       .set    push                                    \n"
1804         "       .set    noreorder                               \n"
1805         "       .set    noat                                    \n"
1806         "       .set    mips32r2                                \n"
1807         "       .word   0x41610001              # dvpe $1       \n"
1808         "       move    %0, $1                                  \n"
1809         "       ehb                                             \n"
1810         "       .set    pop                                     \n"
1811         : "=r" (res));
1812
1813         instruction_hazard();
1814 #endif
1815
1816         __asm__ __volatile__(
1817                 ".set noreorder\n\t"
1818                 "tlbr\n\t"
1819                 ".set reorder");
1820
1821 #if MIPS34K_MISSED_ITLB_WAR
1822         if ((res & _ULCAST_(1)))
1823                 __asm__ __volatile__(
1824                 "       .set    push                            \n"
1825                 "       .set    noreorder                       \n"
1826                 "       .set    noat                            \n"
1827                 "       .set    mips32r2                        \n"
1828                 "       .word   0x41600021      # evpe          \n"
1829                 "       ehb                                     \n"
1830                 "       .set    pop                             \n");
1831 #endif
1832 }
1833
1834 static inline void tlb_write_indexed(void)
1835 {
1836         __asm__ __volatile__(
1837                 ".set noreorder\n\t"
1838                 "tlbwi\n\t"
1839                 ".set reorder");
1840 }
1841
1842 static inline void tlb_write_random(void)
1843 {
1844         __asm__ __volatile__(
1845                 ".set noreorder\n\t"
1846                 "tlbwr\n\t"
1847                 ".set reorder");
1848 }
1849
1850 /*
1851  * Manipulate bits in a c0 register.
1852  */
1853 #define __BUILD_SET_C0(name)                                    \
1854 static inline unsigned int                                      \
1855 set_c0_##name(unsigned int set)                                 \
1856 {                                                               \
1857         unsigned int res, new;                                  \
1858                                                                 \
1859         res = read_c0_##name();                                 \
1860         new = res | set;                                        \
1861         write_c0_##name(new);                                   \
1862                                                                 \
1863         return res;                                             \
1864 }                                                               \
1865                                                                 \
1866 static inline unsigned int                                      \
1867 clear_c0_##name(unsigned int clear)                             \
1868 {                                                               \
1869         unsigned int res, new;                                  \
1870                                                                 \
1871         res = read_c0_##name();                                 \
1872         new = res & ~clear;                                     \
1873         write_c0_##name(new);                                   \
1874                                                                 \
1875         return res;                                             \
1876 }                                                               \
1877                                                                 \
1878 static inline unsigned int                                      \
1879 change_c0_##name(unsigned int change, unsigned int val)         \
1880 {                                                               \
1881         unsigned int res, new;                                  \
1882                                                                 \
1883         res = read_c0_##name();                                 \
1884         new = res & ~change;                                    \
1885         new |= (val & change);                                  \
1886         write_c0_##name(new);                                   \
1887                                                                 \
1888         return res;                                             \
1889 }
1890
1891 __BUILD_SET_C0(status)
1892 __BUILD_SET_C0(cause)
1893 __BUILD_SET_C0(config)
1894 __BUILD_SET_C0(config5)
1895 __BUILD_SET_C0(intcontrol)
1896 __BUILD_SET_C0(intctl)
1897 __BUILD_SET_C0(srsmap)
1898 __BUILD_SET_C0(brcm_config_0)
1899 __BUILD_SET_C0(brcm_bus_pll)
1900 __BUILD_SET_C0(brcm_reset)
1901 __BUILD_SET_C0(brcm_cmt_intr)
1902 __BUILD_SET_C0(brcm_cmt_ctrl)
1903 __BUILD_SET_C0(brcm_config)
1904 __BUILD_SET_C0(brcm_mode)
1905
1906 /*
1907  * Return low 10 bits of ebase.
1908  * Note that under KVM (MIPSVZ) this returns vcpu id.
1909  */
1910 static inline unsigned int get_ebase_cpunum(void)
1911 {
1912         return read_c0_ebase() & 0x3ff;
1913 }
1914
1915 #endif /* !__ASSEMBLY__ */
1916
1917 #endif /* _ASM_MIPSREGS_H */