arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22 /* MIPS KVM register ids */
  23 #define MIPS_CP0_32(_R, _S)                                     \
  24         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  25
  26 #define MIPS_CP0_64(_R, _S)                                     \
  27         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  28
  29 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  30 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  31 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  32 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  33 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  34 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  35 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  36 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  37 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  38 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  39 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  40 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  41 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  42 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  43 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  44 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  45 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  46 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  47 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  48 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  49 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  50 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  51 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  52 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  53 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  54 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  55 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  56
  57
  58 #define KVM_MAX_VCPUS           1
  59 #define KVM_USER_MEM_SLOTS      8
  60 /* memory slots that does not exposed to userspace */
  61 #define KVM_PRIVATE_MEM_SLOTS   0
  62
  63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  64 #define KVM_HALT_POLL_NS_DEFAULT 500000
  65
  66
  67
  68 /* Special address that contains the comm page, used for reducing # of traps */
  69 #define KVM_GUEST_COMMPAGE_ADDR         0x0
  70
  71 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  72                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  73
  74 #define KVM_GUEST_KUSEG                 0x00000000UL
  75 #define KVM_GUEST_KSEG0                 0x40000000UL
  76 #define KVM_GUEST_KSEG23                0x60000000UL
  77 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0x60000000)
  78 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
  79
  80 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  81 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  82 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  83
  84 /*
  85  * Map an address to a certain kernel segment
  86  */
  87 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  88 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  89 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  90
  91 #define KVM_INVALID_PAGE                0xdeadbeef
  92 #define KVM_INVALID_INST                0xdeadbeef
  93 #define KVM_INVALID_ADDR                0xdeadbeef
  94
  95 extern atomic_t kvm_mips_instance;
  96 extern kvm_pfn_t (*kvm_mips_gfn_to_pfn)(struct kvm *kvm, gfn_t gfn);
  97 extern void (*kvm_mips_release_pfn_clean)(kvm_pfn_t pfn);
  98 extern bool (*kvm_mips_is_error_pfn)(kvm_pfn_t pfn);
  99
 100 struct kvm_vm_stat {
 101         u32 remote_tlb_flush;
 102 };
 103
 104 struct kvm_vcpu_stat {
 105         u32 wait_exits;
 106         u32 cache_exits;
 107         u32 signal_exits;
 108         u32 int_exits;
 109         u32 cop_unusable_exits;
 110         u32 tlbmod_exits;
 111         u32 tlbmiss_ld_exits;
 112         u32 tlbmiss_st_exits;
 113         u32 addrerr_st_exits;
 114         u32 addrerr_ld_exits;
 115         u32 syscall_exits;
 116         u32 resvd_inst_exits;
 117         u32 break_inst_exits;
 118         u32 trap_inst_exits;
 119         u32 msa_fpe_exits;
 120         u32 fpe_exits;
 121         u32 msa_disabled_exits;
 122         u32 flush_dcache_exits;
 123         u32 halt_successful_poll;
 124         u32 halt_attempted_poll;
 125         u32 halt_wakeup;
 126 };
 127
 128 enum kvm_mips_exit_types {
 129         WAIT_EXITS,
 130         CACHE_EXITS,
 131         SIGNAL_EXITS,
 132         INT_EXITS,
 133         COP_UNUSABLE_EXITS,
 134         TLBMOD_EXITS,
 135         TLBMISS_LD_EXITS,
 136         TLBMISS_ST_EXITS,
 137         ADDRERR_ST_EXITS,
 138         ADDRERR_LD_EXITS,
 139         SYSCALL_EXITS,
 140         RESVD_INST_EXITS,
 141         BREAK_INST_EXITS,
 142         TRAP_INST_EXITS,
 143         MSA_FPE_EXITS,
 144         FPE_EXITS,
 145         MSA_DISABLED_EXITS,
 146         FLUSH_DCACHE_EXITS,
 147         MAX_KVM_MIPS_EXIT_TYPES
 148 };
 149
 150 struct kvm_arch_memory_slot {
 151 };
 152
 153 struct kvm_arch {
 154         /* Guest GVA->HPA page table */
 155         unsigned long *guest_pmap;
 156         unsigned long guest_pmap_npages;
 157
 158         /* Wired host TLB used for the commpage */
 159         int commpage_tlb;
 160 };
 161
 162 #define N_MIPS_COPROC_REGS      32
 163 #define N_MIPS_COPROC_SEL       8
 164
 165 struct mips_coproc {
 166         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 167 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 168         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 169 #endif
 170 };
 171
 172 /*
 173  * Coprocessor 0 register names
 174  */
 175 #define MIPS_CP0_TLB_INDEX      0
 176 #define MIPS_CP0_TLB_RANDOM     1
 177 #define MIPS_CP0_TLB_LOW        2
 178 #define MIPS_CP0_TLB_LO0        2
 179 #define MIPS_CP0_TLB_LO1        3
 180 #define MIPS_CP0_TLB_CONTEXT    4
 181 #define MIPS_CP0_TLB_PG_MASK    5
 182 #define MIPS_CP0_TLB_WIRED      6
 183 #define MIPS_CP0_HWRENA         7
 184 #define MIPS_CP0_BAD_VADDR      8
 185 #define MIPS_CP0_COUNT          9
 186 #define MIPS_CP0_TLB_HI         10
 187 #define MIPS_CP0_COMPARE        11
 188 #define MIPS_CP0_STATUS         12
 189 #define MIPS_CP0_CAUSE          13
 190 #define MIPS_CP0_EXC_PC         14
 191 #define MIPS_CP0_PRID           15
 192 #define MIPS_CP0_CONFIG         16
 193 #define MIPS_CP0_LLADDR         17
 194 #define MIPS_CP0_WATCH_LO       18
 195 #define MIPS_CP0_WATCH_HI       19
 196 #define MIPS_CP0_TLB_XCONTEXT   20
 197 #define MIPS_CP0_ECC            26
 198 #define MIPS_CP0_CACHE_ERR      27
 199 #define MIPS_CP0_TAG_LO         28
 200 #define MIPS_CP0_TAG_HI         29
 201 #define MIPS_CP0_ERROR_PC       30
 202 #define MIPS_CP0_DEBUG          23
 203 #define MIPS_CP0_DEPC           24
 204 #define MIPS_CP0_PERFCNT        25
 205 #define MIPS_CP0_ERRCTL         26
 206 #define MIPS_CP0_DATA_LO        28
 207 #define MIPS_CP0_DATA_HI        29
 208 #define MIPS_CP0_DESAVE         31
 209
 210 #define MIPS_CP0_CONFIG_SEL     0
 211 #define MIPS_CP0_CONFIG1_SEL    1
 212 #define MIPS_CP0_CONFIG2_SEL    2
 213 #define MIPS_CP0_CONFIG3_SEL    3
 214 #define MIPS_CP0_CONFIG4_SEL    4
 215 #define MIPS_CP0_CONFIG5_SEL    5
 216
 217 /* Config0 register bits */
 218 #define CP0C0_M                 31
 219 #define CP0C0_K23               28
 220 #define CP0C0_KU                25
 221 #define CP0C0_MDU               20
 222 #define CP0C0_MM                17
 223 #define CP0C0_BM                16
 224 #define CP0C0_BE                15
 225 #define CP0C0_AT                13
 226 #define CP0C0_AR                10
 227 #define CP0C0_MT                7
 228 #define CP0C0_VI                3
 229 #define CP0C0_K0                0
 230
 231 /* Config1 register bits */
 232 #define CP0C1_M                 31
 233 #define CP0C1_MMU               25
 234 #define CP0C1_IS                22
 235 #define CP0C1_IL                19
 236 #define CP0C1_IA                16
 237 #define CP0C1_DS                13
 238 #define CP0C1_DL                10
 239 #define CP0C1_DA                7
 240 #define CP0C1_C2                6
 241 #define CP0C1_MD                5
 242 #define CP0C1_PC                4
 243 #define CP0C1_WR                3
 244 #define CP0C1_CA                2
 245 #define CP0C1_EP                1
 246 #define CP0C1_FP                0
 247
 248 /* Config2 Register bits */
 249 #define CP0C2_M                 31
 250 #define CP0C2_TU                28
 251 #define CP0C2_TS                24
 252 #define CP0C2_TL                20
 253 #define CP0C2_TA                16
 254 #define CP0C2_SU                12
 255 #define CP0C2_SS                8
 256 #define CP0C2_SL                4
 257 #define CP0C2_SA                0
 258
 259 /* Config3 Register bits */
 260 #define CP0C3_M                 31
 261 #define CP0C3_ISA_ON_EXC        16
 262 #define CP0C3_ULRI              13
 263 #define CP0C3_DSPP              10
 264 #define CP0C3_LPA               7
 265 #define CP0C3_VEIC              6
 266 #define CP0C3_VInt              5
 267 #define CP0C3_SP                4
 268 #define CP0C3_MT                2
 269 #define CP0C3_SM                1
 270 #define CP0C3_TL                0
 271
 272 /* MMU types, the first four entries have the same layout as the
 273    CP0C0_MT field.  */
 274 enum mips_mmu_types {
 275         MMU_TYPE_NONE,
 276         MMU_TYPE_R4000,
 277         MMU_TYPE_RESERVED,
 278         MMU_TYPE_FMT,
 279         MMU_TYPE_R3000,
 280         MMU_TYPE_R6000,
 281         MMU_TYPE_R8000
 282 };
 283
 284 /* Resume Flags */
 285 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 286 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 287
 288 #define RESUME_GUEST            0
 289 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 290 #define RESUME_HOST             RESUME_FLAG_HOST
 291
 292 enum emulation_result {
 293         EMULATE_DONE,           /* no further processing */
 294         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 295         EMULATE_FAIL,           /* can't emulate this instruction */
 296         EMULATE_WAIT,           /* WAIT instruction */
 297         EMULATE_PRIV_FAIL,
 298 };
 299
 300 #define MIPS3_PG_G      0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
 301 #define MIPS3_PG_V      0x00000002 /* Valid */
 302 #define MIPS3_PG_NV     0x00000000
 303 #define MIPS3_PG_D      0x00000004 /* Dirty */
 304
 305 #define mips3_paddr_to_tlbpfn(x) \
 306         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 307 #define mips3_tlbpfn_to_paddr(x) \
 308         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 309
 310 #define MIPS3_PG_SHIFT          6
 311 #define MIPS3_PG_FRAME          0x3fffffc0
 312
 313 #define VPN2_MASK               0xffffe000
 314 #define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&          \
 315                                  ((x).tlb_lo1 & MIPS3_PG_G))
 316 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 317 #define TLB_ASID(x)             ((x).tlb_hi & ASID_MASK)
 318 #define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))             \
 319                                  ? ((x).tlb_lo1 & MIPS3_PG_V)           \
 320                                  : ((x).tlb_lo0 & MIPS3_PG_V))
 321 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 322                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 323 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 324                                  TLB_ASID(x) == ((y) & ASID_MASK))
 325
 326 struct kvm_mips_tlb {
 327         long tlb_mask;
 328         long tlb_hi;
 329         long tlb_lo0;
 330         long tlb_lo1;
 331 };
 332
 333 #define KVM_MIPS_FPU_FPU        0x1
 334 #define KVM_MIPS_FPU_MSA        0x2
 335
 336 #define KVM_MIPS_GUEST_TLB_SIZE 64
 337 struct kvm_vcpu_arch {
 338         void *host_ebase, *guest_ebase;
 339         unsigned long host_stack;
 340         unsigned long host_gp;
 341
 342         /* Host CP0 registers used when handling exits from guest */
 343         unsigned long host_cp0_badvaddr;
 344         unsigned long host_cp0_cause;
 345         unsigned long host_cp0_epc;
 346         unsigned long host_cp0_entryhi;
 347         uint32_t guest_inst;
 348
 349         /* GPRS */
 350         unsigned long gprs[32];
 351         unsigned long hi;
 352         unsigned long lo;
 353         unsigned long pc;
 354
 355         /* FPU State */
 356         struct mips_fpu_struct fpu;
 357         /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
 358         unsigned int fpu_inuse;
 359
 360         /* COP0 State */
 361         struct mips_coproc *cop0;
 362
 363         /* Host KSEG0 address of the EI/DI offset */
 364         void *kseg0_commpage;
 365
 366         u32 io_gpr;             /* GPR used as IO source/target */
 367
 368         struct hrtimer comparecount_timer;
 369         /* Count timer control KVM register */
 370         uint32_t count_ctl;
 371         /* Count bias from the raw time */
 372         uint32_t count_bias;
 373         /* Frequency of timer in Hz */
 374         uint32_t count_hz;
 375         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 376         s64 count_dyn_bias;
 377         /* Resume time */
 378         ktime_t count_resume;
 379         /* Period of timer tick in ns */
 380         u64 count_period;
 381
 382         /* Bitmask of exceptions that are pending */
 383         unsigned long pending_exceptions;
 384
 385         /* Bitmask of pending exceptions to be cleared */
 386         unsigned long pending_exceptions_clr;
 387
 388         unsigned long pending_load_cause;
 389
 390         /* Save/Restore the entryhi register when are are preempted/scheduled back in */
 391         unsigned long preempt_entryhi;
 392
 393         /* S/W Based TLB for guest */
 394         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 395
 396         /* Cached guest kernel/user ASIDs */
 397         uint32_t guest_user_asid[NR_CPUS];
 398         uint32_t guest_kernel_asid[NR_CPUS];
 399         struct mm_struct guest_kernel_mm, guest_user_mm;
 400
 401         int last_sched_cpu;
 402
 403         /* WAIT executed */
 404         int wait;
 405
 406         u8 fpu_enabled;
 407         u8 msa_enabled;
 408 };
 409
 410
 411 #define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 412 #define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 413 #define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
 414 #define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
 415 #define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 416 #define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 417 #define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 418 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
 419 #define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 420 #define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 421 #define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 422 #define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 423 #define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
 424 #define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
 425 #define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 426 #define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 427 #define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
 428 #define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 429 #define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
 430 #define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 431 #define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
 432 #define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 433 #define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
 434 #define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 435 #define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
 436 #define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 437 #define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
 438 #define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 439 #define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
 440 #define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 441 #define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
 442 #define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
 443 #define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
 444 #define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
 445 #define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
 446 #define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
 447 #define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
 448 #define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
 449 #define kvm_read_c0_guest_config4(cop0)         (cop0->reg[MIPS_CP0_CONFIG][4])
 450 #define kvm_read_c0_guest_config5(cop0)         (cop0->reg[MIPS_CP0_CONFIG][5])
 451 #define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
 452 #define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 453 #define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 454 #define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 455 #define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 456 #define kvm_write_c0_guest_config4(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
 457 #define kvm_write_c0_guest_config5(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
 458 #define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 459 #define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
 460 #define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 461
 462 /*
 463  * Some of the guest registers may be modified asynchronously (e.g. from a
 464  * hrtimer callback in hard irq context) and therefore need stronger atomicity
 465  * guarantees than other registers.
 466  */
 467
 468 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 469                                                 unsigned long val)
 470 {
 471         unsigned long temp;
 472         do {
 473                 __asm__ __volatile__(
 474                 "       .set    mips3                           \n"
 475                 "       " __LL "%0, %1                          \n"
 476                 "       or      %0, %2                          \n"
 477                 "       " __SC  "%0, %1                         \n"
 478                 "       .set    mips0                           \n"
 479                 : "=&r" (temp), "+m" (*reg)
 480                 : "r" (val));
 481         } while (unlikely(!temp));
 482 }
 483
 484 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 485                                                   unsigned long val)
 486 {
 487         unsigned long temp;
 488         do {
 489                 __asm__ __volatile__(
 490                 "       .set    mips3                           \n"
 491                 "       " __LL "%0, %1                          \n"
 492                 "       and     %0, %2                          \n"
 493                 "       " __SC  "%0, %1                         \n"
 494                 "       .set    mips0                           \n"
 495                 : "=&r" (temp), "+m" (*reg)
 496                 : "r" (~val));
 497         } while (unlikely(!temp));
 498 }
 499
 500 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 501                                                    unsigned long change,
 502                                                    unsigned long val)
 503 {
 504         unsigned long temp;
 505         do {
 506                 __asm__ __volatile__(
 507                 "       .set    mips3                           \n"
 508                 "       " __LL "%0, %1                          \n"
 509                 "       and     %0, %2                          \n"
 510                 "       or      %0, %3                          \n"
 511                 "       " __SC  "%0, %1                         \n"
 512                 "       .set    mips0                           \n"
 513                 : "=&r" (temp), "+m" (*reg)
 514                 : "r" (~change), "r" (val & change));
 515         } while (unlikely(!temp));
 516 }
 517
 518 #define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 519 #define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 520
 521 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 522 #define kvm_set_c0_guest_cause(cop0, val)                               \
 523         _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 524 #define kvm_clear_c0_guest_cause(cop0, val)                             \
 525         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 526 #define kvm_change_c0_guest_cause(cop0, change, val)                    \
 527         _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0],  \
 528                                         change, val)
 529
 530 #define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 531 #define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 532 #define kvm_change_c0_guest_ebase(cop0, change, val)                    \
 533 {                                                                       \
 534         kvm_clear_c0_guest_ebase(cop0, change);                         \
 535         kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 536 }
 537
 538 /* Helpers */
 539
 540 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 541 {
 542         return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
 543                 vcpu->fpu_enabled;
 544 }
 545
 546 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 547 {
 548         return kvm_mips_guest_can_have_fpu(vcpu) &&
 549                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 550 }
 551
 552 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 553 {
 554         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 555                 vcpu->msa_enabled;
 556 }
 557
 558 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 559 {
 560         return kvm_mips_guest_can_have_msa(vcpu) &&
 561                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 562 }
 563
 564 struct kvm_mips_callbacks {
 565         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 566         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 567         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 568         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 569         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 570         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 571         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 572         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 573         int (*handle_break)(struct kvm_vcpu *vcpu);
 574         int (*handle_trap)(struct kvm_vcpu *vcpu);
 575         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 576         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 577         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 578         int (*vm_init)(struct kvm *kvm);
 579         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 580         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 581         gpa_t (*gva_to_gpa)(gva_t gva);
 582         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 583         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 584         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 585                              struct kvm_mips_interrupt *irq);
 586         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 587                                struct kvm_mips_interrupt *irq);
 588         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 589                            uint32_t cause);
 590         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 591                          uint32_t cause);
 592         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 593                            const struct kvm_one_reg *reg, s64 *v);
 594         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 595                            const struct kvm_one_reg *reg, s64 v);
 596         int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
 597         int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
 598 };
 599 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 600 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 601
 602 /* Debug: dump vcpu state */
 603 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 604
 605 /* Trampoline ASM routine to start running in "Guest" context */
 606 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
 607
 608 /* FPU/MSA context management */
 609 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 610 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 611 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 612 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 613 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 614 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 615 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 616 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 617 void kvm_own_msa(struct kvm_vcpu *vcpu);
 618 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 619 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 620
 621 /* TLB handling */
 622 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 623
 624 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
 625
 626 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 627
 628 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 629                                            struct kvm_vcpu *vcpu);
 630
 631 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 632                                               struct kvm_vcpu *vcpu);
 633
 634 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 635                                                 struct kvm_mips_tlb *tlb,
 636                                                 unsigned long *hpa0,
 637                                                 unsigned long *hpa1);
 638
 639 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 640                                                      uint32_t *opc,
 641                                                      struct kvm_run *run,
 642                                                      struct kvm_vcpu *vcpu);
 643
 644 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 645                                                     uint32_t *opc,
 646                                                     struct kvm_run *run,
 647                                                     struct kvm_vcpu *vcpu);
 648
 649 extern void kvm_mips_dump_host_tlbs(void);
 650 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 651 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 652 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 653
 654 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 655                                      unsigned long entryhi);
 656 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
 657 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
 658                                                    unsigned long gva);
 659 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
 660                                     struct kvm_vcpu *vcpu);
 661 extern void kvm_local_flush_tlb_all(void);
 662 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 663 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 664 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
 665
 666 /* Emulation */
 667 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
 668 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
 669
 670 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
 671                                                    uint32_t *opc,
 672                                                    struct kvm_run *run,
 673                                                    struct kvm_vcpu *vcpu);
 674
 675 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 676                                                       uint32_t *opc,
 677                                                       struct kvm_run *run,
 678                                                       struct kvm_vcpu *vcpu);
 679
 680 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 681                                                          uint32_t *opc,
 682                                                          struct kvm_run *run,
 683                                                          struct kvm_vcpu *vcpu);
 684
 685 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 686                                                         uint32_t *opc,
 687                                                         struct kvm_run *run,
 688                                                         struct kvm_vcpu *vcpu);
 689
 690 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 691                                                          uint32_t *opc,
 692                                                          struct kvm_run *run,
 693                                                          struct kvm_vcpu *vcpu);
 694
 695 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 696                                                         uint32_t *opc,
 697                                                         struct kvm_run *run,
 698                                                         struct kvm_vcpu *vcpu);
 699
 700 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 701                                                      uint32_t *opc,
 702                                                      struct kvm_run *run,
 703                                                      struct kvm_vcpu *vcpu);
 704
 705 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 706                                                       uint32_t *opc,
 707                                                       struct kvm_run *run,
 708                                                       struct kvm_vcpu *vcpu);
 709
 710 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
 711                                                 uint32_t *opc,
 712                                                 struct kvm_run *run,
 713                                                 struct kvm_vcpu *vcpu);
 714
 715 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 716                                                      uint32_t *opc,
 717                                                      struct kvm_run *run,
 718                                                      struct kvm_vcpu *vcpu);
 719
 720 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 721                                                      uint32_t *opc,
 722                                                      struct kvm_run *run,
 723                                                      struct kvm_vcpu *vcpu);
 724
 725 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
 726                                                        uint32_t *opc,
 727                                                        struct kvm_run *run,
 728                                                        struct kvm_vcpu *vcpu);
 729
 730 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
 731                                                          uint32_t *opc,
 732                                                          struct kvm_run *run,
 733                                                          struct kvm_vcpu *vcpu);
 734
 735 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
 736                                                       uint32_t *opc,
 737                                                       struct kvm_run *run,
 738                                                       struct kvm_vcpu *vcpu);
 739
 740 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
 741                                                          uint32_t *opc,
 742                                                          struct kvm_run *run,
 743                                                          struct kvm_vcpu *vcpu);
 744
 745 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 746                                                          struct kvm_run *run);
 747
 748 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
 749 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
 750 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
 751 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
 752 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
 753 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
 754 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
 755 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
 756 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
 757 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
 758
 759 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 760                                                uint32_t *opc,
 761                                                struct kvm_run *run,
 762                                                struct kvm_vcpu *vcpu);
 763
 764 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
 765                                              uint32_t *opc,
 766                                              uint32_t cause,
 767                                              struct kvm_run *run,
 768                                              struct kvm_vcpu *vcpu);
 769 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
 770                                            uint32_t *opc,
 771                                            uint32_t cause,
 772                                            struct kvm_run *run,
 773                                            struct kvm_vcpu *vcpu);
 774 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
 775                                              uint32_t cause,
 776                                              struct kvm_run *run,
 777                                              struct kvm_vcpu *vcpu);
 778 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
 779                                             uint32_t cause,
 780                                             struct kvm_run *run,
 781                                             struct kvm_vcpu *vcpu);
 782
 783 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
 784 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
 785 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
 786 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
 787
 788 /* Dynamic binary translation */
 789 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
 790                                       struct kvm_vcpu *vcpu);
 791 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
 792                                    struct kvm_vcpu *vcpu);
 793 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
 794                                struct kvm_vcpu *vcpu);
 795 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 796                                struct kvm_vcpu *vcpu);
 797
 798 /* Misc */
 799 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 800 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 801
 802 static inline void kvm_arch_hardware_disable(void) {}
 803 static inline void kvm_arch_hardware_unsetup(void) {}
 804 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
 805 static inline void kvm_arch_free_memslot(struct kvm *kvm,
 806                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
 807 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
 808 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
 809 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 810                 struct kvm_memory_slot *slot) {}
 811 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
 812 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 813 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
 814 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
 815
 816 #endif /* __MIPS_KVM_HOST_H__ */