arch/mips/ath79/irq.c

   1 /*
   2  *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License version 2 as published
  12  *  by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irqchip.h>
  19 #include <linux/of_irq.h>
  20
  21 #include <asm/irq_cpu.h>
  22 #include <asm/mipsregs.h>
  23
  24 #include <asm/mach-ath79/ath79.h>
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26 #include "common.h"
  27 #include "machtypes.h"
  28
  29 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
  30 {
  31         void __iomem *base = ath79_reset_base;
  32         u32 pending;
  33
  34         pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
  35                   __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  36
  37         if (!pending) {
  38                 spurious_interrupt();
  39                 return;
  40         }
  41
  42         while (pending) {
  43                 int bit = __ffs(pending);
  44
  45                 generic_handle_irq(ATH79_MISC_IRQ(bit));
  46                 pending &= ~BIT(bit);
  47         }
  48 }
  49
  50 static void ar71xx_misc_irq_unmask(struct irq_data *d)
  51 {
  52         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  53         void __iomem *base = ath79_reset_base;
  54         u32 t;
  55
  56         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  57         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  58
  59         /* flush write */
  60         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  61 }
  62
  63 static void ar71xx_misc_irq_mask(struct irq_data *d)
  64 {
  65         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  66         void __iomem *base = ath79_reset_base;
  67         u32 t;
  68
  69         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  70         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  71
  72         /* flush write */
  73         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  74 }
  75
  76 static void ar724x_misc_irq_ack(struct irq_data *d)
  77 {
  78         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  79         void __iomem *base = ath79_reset_base;
  80         u32 t;
  81
  82         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
  83         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
  84
  85         /* flush write */
  86         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
  87 }
  88
  89 static struct irq_chip ath79_misc_irq_chip = {
  90         .name           = "MISC",
  91         .irq_unmask     = ar71xx_misc_irq_unmask,
  92         .irq_mask       = ar71xx_misc_irq_mask,
  93 };
  94
  95 static void __init ath79_misc_irq_init(void)
  96 {
  97         void __iomem *base = ath79_reset_base;
  98         int i;
  99
 100         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 101         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 102
 103         if (soc_is_ar71xx() || soc_is_ar913x())
 104                 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
 105         else if (soc_is_ar724x() ||
 106                  soc_is_ar933x() ||
 107                  soc_is_ar934x() ||
 108                  soc_is_qca955x())
 109                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 110         else
 111                 BUG();
 112
 113         for (i = ATH79_MISC_IRQ_BASE;
 114              i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
 115                 irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
 116                                          handle_level_irq);
 117         }
 118
 119         irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
 120 }
 121
 122 static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 123 {
 124         u32 status;
 125
 126         disable_irq_nosync(irq);
 127
 128         status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
 129
 130         if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
 131                 ath79_ddr_wb_flush(3);
 132                 generic_handle_irq(ATH79_IP2_IRQ(0));
 133         } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
 134                 ath79_ddr_wb_flush(4);
 135                 generic_handle_irq(ATH79_IP2_IRQ(1));
 136         } else {
 137                 spurious_interrupt();
 138         }
 139
 140         enable_irq(irq);
 141 }
 142
 143 static void ar934x_ip2_irq_init(void)
 144 {
 145         int i;
 146
 147         for (i = ATH79_IP2_IRQ_BASE;
 148              i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 149                 irq_set_chip_and_handler(i, &dummy_irq_chip,
 150                                          handle_level_irq);
 151
 152         irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
 153 }
 154
 155 static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 156 {
 157         u32 status;
 158
 159         disable_irq_nosync(irq);
 160
 161         status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 162         status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
 163
 164         if (status == 0) {
 165                 spurious_interrupt();
 166                 goto enable;
 167         }
 168
 169         if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
 170                 /* TODO: flush DDR? */
 171                 generic_handle_irq(ATH79_IP2_IRQ(0));
 172         }
 173
 174         if (status & QCA955X_EXT_INT_WMAC_ALL) {
 175                 /* TODO: flush DDR? */
 176                 generic_handle_irq(ATH79_IP2_IRQ(1));
 177         }
 178
 179 enable:
 180         enable_irq(irq);
 181 }
 182
 183 static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 184 {
 185         u32 status;
 186
 187         disable_irq_nosync(irq);
 188
 189         status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
 190         status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
 191                   QCA955X_EXT_INT_USB1 |
 192                   QCA955X_EXT_INT_USB2;
 193
 194         if (status == 0) {
 195                 spurious_interrupt();
 196                 goto enable;
 197         }
 198
 199         if (status & QCA955X_EXT_INT_USB1) {
 200                 /* TODO: flush DDR? */
 201                 generic_handle_irq(ATH79_IP3_IRQ(0));
 202         }
 203
 204         if (status & QCA955X_EXT_INT_USB2) {
 205                 /* TODO: flush DDR? */
 206                 generic_handle_irq(ATH79_IP3_IRQ(1));
 207         }
 208
 209         if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
 210                 /* TODO: flush DDR? */
 211                 generic_handle_irq(ATH79_IP3_IRQ(2));
 212         }
 213
 214 enable:
 215         enable_irq(irq);
 216 }
 217
 218 static void qca955x_irq_init(void)
 219 {
 220         int i;
 221
 222         for (i = ATH79_IP2_IRQ_BASE;
 223              i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 224                 irq_set_chip_and_handler(i, &dummy_irq_chip,
 225                                          handle_level_irq);
 226
 227         irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
 228
 229         for (i = ATH79_IP3_IRQ_BASE;
 230              i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 231                 irq_set_chip_and_handler(i, &dummy_irq_chip,
 232                                          handle_level_irq);
 233
 234         irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 235 }
 236
 237 /*
 238  * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
 239  * these devices typically allocate coherent DMA memory, however the
 240  * DMA controller may still have some unsynchronized data in the FIFO.
 241  * Issue a flush in the handlers to ensure that the driver sees
 242  * the update.
 243  *
 244  * This array map the interrupt lines to the DDR write buffer channels.
 245  */
 246
 247 static unsigned irq_wb_chan[8] = {
 248         -1, -1, -1, -1, -1, -1, -1, -1,
 249 };
 250
 251 asmlinkage void plat_irq_dispatch(void)
 252 {
 253         unsigned long pending;
 254         int irq;
 255
 256         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 257
 258         if (!pending) {
 259                 spurious_interrupt();
 260                 return;
 261         }
 262
 263         pending >>= CAUSEB_IP;
 264         while (pending) {
 265                 irq = fls(pending) - 1;
 266                 if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
 267                         ath79_ddr_wb_flush(irq_wb_chan[irq]);
 268                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 269                 pending &= ~BIT(irq);
 270         }
 271 }
 272
 273 #ifdef CONFIG_IRQCHIP
 274 static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 275 {
 276         irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
 277         return 0;
 278 }
 279
 280 static const struct irq_domain_ops misc_irq_domain_ops = {
 281         .xlate = irq_domain_xlate_onecell,
 282         .map = misc_map,
 283 };
 284
 285 static int __init ath79_misc_intc_of_init(
 286         struct device_node *node, struct device_node *parent)
 287 {
 288         void __iomem *base = ath79_reset_base;
 289         struct irq_domain *domain;
 290         int irq;
 291
 292         irq = irq_of_parse_and_map(node, 0);
 293         if (!irq)
 294                 panic("Failed to get MISC IRQ");
 295
 296         domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
 297                         ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL);
 298         if (!domain)
 299                 panic("Failed to add MISC irqdomain");
 300
 301         /* Disable and clear all interrupts */
 302         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 303         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 304
 305
 306         irq_set_chained_handler(irq, ath79_misc_irq_handler);
 307
 308         return 0;
 309 }
 310 IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
 311                 ath79_misc_intc_of_init);
 312
 313 static int __init ar79_cpu_intc_of_init(
 314         struct device_node *node, struct device_node *parent)
 315 {
 316         int err, i, count;
 317
 318         /* Fill the irq_wb_chan table */
 319         count = of_count_phandle_with_args(
 320                 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
 321
 322         for (i = 0; i < count; i++) {
 323                 struct of_phandle_args args;
 324                 u32 irq = i;
 325
 326                 of_property_read_u32_index(
 327                         node, "qca,ddr-wb-channel-interrupts", i, &irq);
 328                 if (irq >= ARRAY_SIZE(irq_wb_chan))
 329                         continue;
 330
 331                 err = of_parse_phandle_with_args(
 332                         node, "qca,ddr-wb-channels",
 333                         "#qca,ddr-wb-channel-cells",
 334                         i, &args);
 335                 if (err)
 336                         return err;
 337
 338                 irq_wb_chan[irq] = args.args[0];
 339                 pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
 340                         irq, args.args[0]);
 341         }
 342
 343         return mips_cpu_irq_of_init(node, parent);
 344 }
 345 IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
 346                 ar79_cpu_intc_of_init);
 347
 348 #endif
 349
 350 void __init arch_init_irq(void)
 351 {
 352         if (mips_machtype == ATH79_MACH_GENERIC_OF) {
 353                 irqchip_init();
 354                 return;
 355         }
 356
 357         if (soc_is_ar71xx() || soc_is_ar724x() ||
 358             soc_is_ar913x() || soc_is_ar933x()) {
 359                 irq_wb_chan[2] = 3;
 360                 irq_wb_chan[3] = 2;
 361         } else if (soc_is_ar934x()) {
 362                 irq_wb_chan[3] = 2;
 363         }
 364
 365         mips_cpu_irq_init();
 366         ath79_misc_irq_init();
 367
 368         if (soc_is_ar934x())
 369                 ar934x_ip2_irq_init();
 370         else if (soc_is_qca955x())
 371                 qca955x_irq_init();
 372 }