2 * Alchemy Db1550/Pb1550 board support
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
7 #include <linux/dma-mapping.h>
8 #include <linux/gpio.h>
10 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/flash.h>
20 #include <asm/bootinfo.h>
21 #include <asm/mach-au1x00/au1000.h>
22 #include <asm/mach-au1x00/au1xxx_eth.h>
23 #include <asm/mach-au1x00/au1xxx_dbdma.h>
24 #include <asm/mach-au1x00/au1xxx_psc.h>
25 #include <asm/mach-au1x00/au1550_spi.h>
26 #include <asm/mach-au1x00/au1550nd.h>
27 #include <asm/mach-db1x00/bcsr.h>
31 static void __init db1550_hw_setup(void)
35 /* complete SPI setup: link psc0_intclk to a 48MHz source,
36 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC
39 base = (void __iomem *)SYS_CLKSRC;
40 __raw_writel(__raw_readl(base) | 0x000001e0, base);
41 base = (void __iomem *)SYS_PINFUNC;
42 __raw_writel(__raw_readl(base) | 1 | SYS_PF_PSC1_S1, base);
45 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
46 * is apparently too short although it's ridiculous as it is.
48 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
49 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
50 base + PSC_SEL_OFFSET);
51 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
53 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
57 int __init db1550_board_setup(void)
59 unsigned short whoami;
61 bcsr_init(DB1550_BCSR_PHYS_ADDR,
62 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
64 whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
65 if ((BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_SDR) ||
66 (BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_DDR))
67 bcsr_init(PB1550_BCSR_PHYS_ADDR,
68 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
70 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
71 "Daughtercard ID %d\n", get_system_type(),
72 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
78 /*****************************************************************************/
80 static struct mtd_partition db1550_spiflash_parts[] = {
84 .size = MTDPART_SIZ_FULL,
88 static struct flash_platform_data db1550_spiflash_data = {
90 .parts = db1550_spiflash_parts,
91 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
95 static struct spi_board_info db1550_spi_devs[] __initdata = {
97 /* TI TMP121AIDBVR temp sensor */
99 .max_speed_hz = 2400000,
105 /* Spansion S25FL001D0FMA SPI flash */
106 .modalias = "m25p80",
107 .max_speed_hz = 2400000,
111 .platform_data = &db1550_spiflash_data,
115 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
116 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
117 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
118 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
121 /**********************************************************************/
123 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
126 struct nand_chip *this = mtd->priv;
127 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
129 ioaddr &= 0xffffff00;
131 if (ctrl & NAND_CLE) {
132 ioaddr += MEM_STNAND_CMD;
133 } else if (ctrl & NAND_ALE) {
134 ioaddr += MEM_STNAND_ADDR;
136 /* assume we want to r/w real data by default */
137 ioaddr += MEM_STNAND_DATA;
139 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
140 if (cmd != NAND_CMD_NONE) {
141 __raw_writeb(cmd, this->IO_ADDR_W);
146 static int au1550_nand_device_ready(struct mtd_info *mtd)
148 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
151 static struct mtd_partition db1550_nand_parts[] = {
155 .size = 8 * 1024 * 1024,
159 .offset = MTDPART_OFS_APPEND,
160 .size = MTDPART_SIZ_FULL
164 struct platform_nand_data db1550_nand_platdata = {
168 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
169 .partitions = db1550_nand_parts,
173 .dev_ready = au1550_nand_device_ready,
174 .cmd_ctrl = au1550_nand_cmd_ctrl,
178 static struct resource db1550_nand_res[] = {
182 .flags = IORESOURCE_MEM,
186 static struct platform_device db1550_nand_dev = {
188 .num_resources = ARRAY_SIZE(db1550_nand_res),
189 .resource = db1550_nand_res,
192 .platform_data = &db1550_nand_platdata,
196 static struct au1550nd_platdata pb1550_nand_pd = {
197 .parts = db1550_nand_parts,
198 .num_parts = ARRAY_SIZE(db1550_nand_parts),
199 .devwidth = 0, /* x8 NAND default, needs fixing up */
202 static struct platform_device pb1550_nand_dev = {
203 .name = "au1550-nand",
205 .resource = db1550_nand_res,
206 .num_resources = ARRAY_SIZE(db1550_nand_res),
208 .platform_data = &pb1550_nand_pd,
212 static void __init pb1550_nand_setup(void)
214 int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
215 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
217 gpio_direction_input(206); /* de-assert NAND CS# */
218 switch (boot_swapboot) {
219 case 0: case 2: case 8: case 0xC: case 0xD:
221 pb1550_nand_pd.devwidth = 1;
223 case 1: case 3: case 9: case 0xE: case 0xF:
224 /* x8 NAND, already set up */
225 platform_device_register(&pb1550_nand_dev);
229 /**********************************************************************/
231 static struct resource au1550_psc0_res[] = {
233 .start = AU1550_PSC0_PHYS_ADDR,
234 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
235 .flags = IORESOURCE_MEM,
238 .start = AU1550_PSC0_INT,
239 .end = AU1550_PSC0_INT,
240 .flags = IORESOURCE_IRQ,
243 .start = AU1550_DSCR_CMD0_PSC0_TX,
244 .end = AU1550_DSCR_CMD0_PSC0_TX,
245 .flags = IORESOURCE_DMA,
248 .start = AU1550_DSCR_CMD0_PSC0_RX,
249 .end = AU1550_DSCR_CMD0_PSC0_RX,
250 .flags = IORESOURCE_DMA,
254 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
257 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
259 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
262 static struct au1550_spi_info db1550_spi_platdata = {
263 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
265 .activate_cs = db1550_spi_cs_en,
268 static u64 spi_dmamask = DMA_BIT_MASK(32);
270 static struct platform_device db1550_spi_dev = {
272 .dma_mask = &spi_dmamask,
273 .coherent_dma_mask = DMA_BIT_MASK(32),
274 .platform_data = &db1550_spi_platdata,
276 .name = "au1550-spi",
277 .id = 0, /* bus number */
278 .num_resources = ARRAY_SIZE(au1550_psc0_res),
279 .resource = au1550_psc0_res,
282 /**********************************************************************/
284 static struct resource au1550_psc1_res[] = {
286 .start = AU1550_PSC1_PHYS_ADDR,
287 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
288 .flags = IORESOURCE_MEM,
291 .start = AU1550_PSC1_INT,
292 .end = AU1550_PSC1_INT,
293 .flags = IORESOURCE_IRQ,
296 .start = AU1550_DSCR_CMD0_PSC1_TX,
297 .end = AU1550_DSCR_CMD0_PSC1_TX,
298 .flags = IORESOURCE_DMA,
301 .start = AU1550_DSCR_CMD0_PSC1_RX,
302 .end = AU1550_DSCR_CMD0_PSC1_RX,
303 .flags = IORESOURCE_DMA,
307 static struct platform_device db1550_ac97_dev = {
308 .name = "au1xpsc_ac97",
309 .id = 1, /* PSC ID */
310 .num_resources = ARRAY_SIZE(au1550_psc1_res),
311 .resource = au1550_psc1_res,
315 static struct resource au1550_psc2_res[] = {
317 .start = AU1550_PSC2_PHYS_ADDR,
318 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
319 .flags = IORESOURCE_MEM,
322 .start = AU1550_PSC2_INT,
323 .end = AU1550_PSC2_INT,
324 .flags = IORESOURCE_IRQ,
327 .start = AU1550_DSCR_CMD0_PSC2_TX,
328 .end = AU1550_DSCR_CMD0_PSC2_TX,
329 .flags = IORESOURCE_DMA,
332 .start = AU1550_DSCR_CMD0_PSC2_RX,
333 .end = AU1550_DSCR_CMD0_PSC2_RX,
334 .flags = IORESOURCE_DMA,
338 static struct platform_device db1550_i2c_dev = {
339 .name = "au1xpsc_smbus",
340 .id = 0, /* bus number */
341 .num_resources = ARRAY_SIZE(au1550_psc2_res),
342 .resource = au1550_psc2_res,
345 /**********************************************************************/
347 static struct resource au1550_psc3_res[] = {
349 .start = AU1550_PSC3_PHYS_ADDR,
350 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
351 .flags = IORESOURCE_MEM,
354 .start = AU1550_PSC3_INT,
355 .end = AU1550_PSC3_INT,
356 .flags = IORESOURCE_IRQ,
359 .start = AU1550_DSCR_CMD0_PSC3_TX,
360 .end = AU1550_DSCR_CMD0_PSC3_TX,
361 .flags = IORESOURCE_DMA,
364 .start = AU1550_DSCR_CMD0_PSC3_RX,
365 .end = AU1550_DSCR_CMD0_PSC3_RX,
366 .flags = IORESOURCE_DMA,
370 static struct platform_device db1550_i2s_dev = {
371 .name = "au1xpsc_i2s",
372 .id = 3, /* PSC ID */
373 .num_resources = ARRAY_SIZE(au1550_psc3_res),
374 .resource = au1550_psc3_res,
377 /**********************************************************************/
379 static struct platform_device db1550_stac_dev = {
380 .name = "ac97-codec",
381 .id = 1, /* on PSC1 */
384 static struct platform_device db1550_ac97dma_dev = {
385 .name = "au1xpsc-pcm",
386 .id = 1, /* on PSC3 */
389 static struct platform_device db1550_i2sdma_dev = {
390 .name = "au1xpsc-pcm",
391 .id = 3, /* on PSC3 */
394 static struct platform_device db1550_sndac97_dev = {
395 .name = "db1550-ac97",
398 static struct platform_device db1550_sndi2s_dev = {
399 .name = "db1550-i2s",
402 /**********************************************************************/
404 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
406 if ((slot < 11) || (slot > 13) || pin == 0)
409 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
412 case 1: return AU1550_PCI_INTB;
413 case 2: return AU1550_PCI_INTC;
414 case 3: return AU1550_PCI_INTD;
415 case 4: return AU1550_PCI_INTA;
420 case 1: return AU1550_PCI_INTA;
421 case 2: return AU1550_PCI_INTB;
422 case 3: return AU1550_PCI_INTC;
423 case 4: return AU1550_PCI_INTD;
429 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
431 if ((slot < 12) || (slot > 13) || pin == 0)
435 case 1: return AU1500_PCI_INTB;
436 case 2: return AU1500_PCI_INTC;
437 case 3: return AU1500_PCI_INTD;
438 case 4: return AU1500_PCI_INTA;
443 case 1: return AU1500_PCI_INTA;
444 case 2: return AU1500_PCI_INTB;
445 case 3: return AU1500_PCI_INTC;
446 case 4: return AU1500_PCI_INTD;
452 static struct resource alchemy_pci_host_res[] = {
454 .start = AU1500_PCI_PHYS_ADDR,
455 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
456 .flags = IORESOURCE_MEM,
460 static struct alchemy_pci_platdata db1550_pci_pd = {
461 .board_map_irq = db1550_map_pci_irq,
464 static struct platform_device db1550_pci_host_dev = {
465 .dev.platform_data = &db1550_pci_pd,
466 .name = "alchemy-pci",
468 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
469 .resource = alchemy_pci_host_res,
472 /**********************************************************************/
474 static struct platform_device *db1550_devs[] __initdata = {
486 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
487 int __init db1550_pci_setup(int id)
490 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
491 return platform_device_register(&db1550_pci_host_dev);
494 static void __init db1550_devices(void)
496 alchemy_gpio_direction_output(203, 0); /* red led on */
498 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
499 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
500 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
501 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
502 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
503 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
505 db1x_register_pcmcia_socket(
506 AU1000_PCMCIA_ATTR_PHYS_ADDR,
507 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
508 AU1000_PCMCIA_MEM_PHYS_ADDR,
509 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
510 AU1000_PCMCIA_IO_PHYS_ADDR,
511 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
512 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
513 /*AU1550_GPIO21_INT*/0, 0, 0);
515 db1x_register_pcmcia_socket(
516 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
517 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
518 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
519 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
520 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
521 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
522 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
523 /*AU1550_GPIO22_INT*/0, 0, 1);
525 platform_device_register(&db1550_nand_dev);
527 alchemy_gpio_direction_output(202, 0); /* green led on */
530 static void __init pb1550_devices(void)
532 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
533 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
534 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
536 /* enable both PCMCIA card irqs in the shared line */
537 alchemy_gpio2_enable_int(201); /* socket 0 card irq */
538 alchemy_gpio2_enable_int(202); /* socket 1 card irq */
540 /* Pb1550, like all others, also has statuschange irqs; however they're
541 * wired up on one of the Au1550's shared GPIO201_205 line, which also
542 * services the PCMCIA card interrupts. So we ignore statuschange and
543 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
544 * drivers are used to shared irqs and b) statuschange isn't really use-
547 db1x_register_pcmcia_socket(
548 AU1000_PCMCIA_ATTR_PHYS_ADDR,
549 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
550 AU1000_PCMCIA_MEM_PHYS_ADDR,
551 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
552 AU1000_PCMCIA_IO_PHYS_ADDR,
553 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
554 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
556 db1x_register_pcmcia_socket(
557 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
558 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
559 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
560 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
561 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
562 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
563 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
568 int __init db1550_dev_setup(void)
572 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
574 i2c_register_board_info(0, db1550_i2c_devs,
575 ARRAY_SIZE(db1550_i2c_devs));
576 spi_register_board_info(db1550_spi_devs,
577 ARRAY_SIZE(db1550_i2c_devs));
579 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
580 __raw_writel(PSC_SEL_CLK_SERCLK,
581 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
583 __raw_writel(PSC_SEL_CLK_SERCLK,
584 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
586 /* SPI/I2C use internally supplied 50MHz source */
587 __raw_writel(PSC_SEL_CLK_INTCLK,
588 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
590 __raw_writel(PSC_SEL_CLK_INTCLK,
591 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
594 id ? pb1550_devices() : db1550_devices();
596 swapped = bcsr_read(BCSR_STATUS) &
597 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
598 db1x_register_norflash(128 << 20, 4, swapped);
600 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));