arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/nmi.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/percpu.h>
  23 #include <linux/dmi.h>
  24 #include <linux/kprobes.h>
  25 #include <linux/cpumask.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/smp.h>
  29 #include <asm/nmi.h>
  30 #include <asm/kdebug.h>
  31 #include <asm/intel_arch_perfmon.h>
  32
  33 #include "mach_traps.h"
  34
  35 int unknown_nmi_panic;
  36 int nmi_watchdog_enabled;
  37
  38 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  39  * evtsel_nmi_owner tracks the ownership of the event selection
  40  * - different performance counters/ event selection may be reserved for
  41  *   different subsystems this reservation system just tries to coordinate
  42  *   things a little
  43  */
  44 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner);
  45 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner[3]);
  46
  47 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  48
  49 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  50  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  51  */
  52 #define NMI_MAX_COUNTER_BITS 66
  53
  54 /* nmi_active:
  55  * >0: the lapic NMI watchdog is active, but can be disabled
  56  * <0: the lapic NMI watchdog has not been set up, and cannot
  57  *     be enabled
  58  *  0: the lapic NMI watchdog is disabled, but can be enabled
  59  */
  60 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  61
  62 unsigned int nmi_watchdog = NMI_DEFAULT;
  63 static unsigned int nmi_hz = HZ;
  64
  65 struct nmi_watchdog_ctlblk {
  66         int enabled;
  67         u64 check_bit;
  68         unsigned int cccr_msr;
  69         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  70         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  71 };
  72 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  73
  74 /* local prototypes */
  75 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  76
  77 extern void show_registers(struct pt_regs *regs);
  78 extern int unknown_nmi_panic;
  79
  80 /* converts an msr to an appropriate reservation bit */
  81 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  82 {
  83         /* returns the bit offset of the performance counter register */
  84         switch (boot_cpu_data.x86_vendor) {
  85         case X86_VENDOR_AMD:
  86                 return (msr - MSR_K7_PERFCTR0);
  87         case X86_VENDOR_INTEL:
  88                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  89                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  90
  91                 switch (boot_cpu_data.x86) {
  92                 case 6:
  93                         return (msr - MSR_P6_PERFCTR0);
  94                 case 15:
  95                         return (msr - MSR_P4_BPU_PERFCTR0);
  96                 }
  97         }
  98         return 0;
  99 }
 100
 101 /* converts an msr to an appropriate reservation bit */
 102 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 103 {
 104         /* returns the bit offset of the event selection register */
 105         switch (boot_cpu_data.x86_vendor) {
 106         case X86_VENDOR_AMD:
 107                 return (msr - MSR_K7_EVNTSEL0);
 108         case X86_VENDOR_INTEL:
 109                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 110                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 111
 112                 switch (boot_cpu_data.x86) {
 113                 case 6:
 114                         return (msr - MSR_P6_EVNTSEL0);
 115                 case 15:
 116                         return (msr - MSR_P4_BSU_ESCR0);
 117                 }
 118         }
 119         return 0;
 120 }
 121
 122 /* checks for a bit availability (hack for oprofile) */
 123 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 124 {
 125         int cpu;
 126         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 127         for_each_possible_cpu (cpu) {
 128                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 129                         return 0;
 130         }
 131         return 1;
 132 }
 133
 134 /* checks the an msr for availability */
 135 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 136 {
 137         unsigned int counter;
 138         int cpu;
 139
 140         counter = nmi_perfctr_msr_to_bit(msr);
 141         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 142
 143         for_each_possible_cpu (cpu) {
 144                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 145                         return 0;
 146         }
 147         return 1;
 148 }
 149
 150 static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
 151 {
 152         unsigned int counter;
 153         if (cpu < 0)
 154                 cpu = smp_processor_id();
 155
 156         counter = nmi_perfctr_msr_to_bit(msr);
 157         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 158
 159         if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 160                 return 1;
 161         return 0;
 162 }
 163
 164 static void __release_perfctr_nmi(int cpu, unsigned int msr)
 165 {
 166         unsigned int counter;
 167         if (cpu < 0)
 168                 cpu = smp_processor_id();
 169
 170         counter = nmi_perfctr_msr_to_bit(msr);
 171         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 172
 173         clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
 174 }
 175
 176 int reserve_perfctr_nmi(unsigned int msr)
 177 {
 178         int cpu, i;
 179         for_each_possible_cpu (cpu) {
 180                 if (!__reserve_perfctr_nmi(cpu, msr)) {
 181                         for_each_possible_cpu (i) {
 182                                 if (i >= cpu)
 183                                         break;
 184                                 __release_perfctr_nmi(i, msr);
 185                         }
 186                         return 0;
 187                 }
 188         }
 189         return 1;
 190 }
 191
 192 void release_perfctr_nmi(unsigned int msr)
 193 {
 194         int cpu;
 195         for_each_possible_cpu (cpu) {
 196                 __release_perfctr_nmi(cpu, msr);
 197         }
 198 }
 199
 200 int __reserve_evntsel_nmi(int cpu, unsigned int msr)
 201 {
 202         unsigned int counter;
 203         if (cpu < 0)
 204                 cpu = smp_processor_id();
 205
 206         counter = nmi_evntsel_msr_to_bit(msr);
 207         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 208
 209         if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
 210                 return 1;
 211         return 0;
 212 }
 213
 214 static void __release_evntsel_nmi(int cpu, unsigned int msr)
 215 {
 216         unsigned int counter;
 217         if (cpu < 0)
 218                 cpu = smp_processor_id();
 219
 220         counter = nmi_evntsel_msr_to_bit(msr);
 221         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 222
 223         clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
 224 }
 225
 226 int reserve_evntsel_nmi(unsigned int msr)
 227 {
 228         int cpu, i;
 229         for_each_possible_cpu (cpu) {
 230                 if (!__reserve_evntsel_nmi(cpu, msr)) {
 231                         for_each_possible_cpu (i) {
 232                                 if (i >= cpu)
 233                                         break;
 234                                 __release_evntsel_nmi(i, msr);
 235                         }
 236                         return 0;
 237                 }
 238         }
 239         return 1;
 240 }
 241
 242 void release_evntsel_nmi(unsigned int msr)
 243 {
 244         int cpu;
 245         for_each_possible_cpu (cpu) {
 246                 __release_evntsel_nmi(cpu, msr);
 247         }
 248 }
 249
 250 static __cpuinit inline int nmi_known_cpu(void)
 251 {
 252         switch (boot_cpu_data.x86_vendor) {
 253         case X86_VENDOR_AMD:
 254                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6)
 255                         || (boot_cpu_data.x86 == 16));
 256         case X86_VENDOR_INTEL:
 257                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 258                         return 1;
 259                 else
 260                         return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 261         }
 262         return 0;
 263 }
 264
 265 static int endflag __initdata = 0;
 266
 267 #ifdef CONFIG_SMP
 268 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 269  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 270  * CPUs during the test make them busy.
 271  */
 272 static __init void nmi_cpu_busy(void *data)
 273 {
 274         local_irq_enable_in_hardirq();
 275         /* Intentionally don't use cpu_relax here. This is
 276            to make sure that the performance counter really ticks,
 277            even if there is a simulator or similar that catches the
 278            pause instruction. On a real HT machine this is fine because
 279            all other CPUs are busy with "useless" delay loops and don't
 280            care if they get somewhat less cycles. */
 281         while (endflag == 0)
 282                 mb();
 283 }
 284 #endif
 285
 286 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 287 {
 288         u64 counter_val;
 289         unsigned int retval = hz;
 290
 291         /*
 292          * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
 293          * are writable, with higher bits sign extending from bit 31.
 294          * So, we can only program the counter with 31 bit values and
 295          * 32nd bit should be 1, for 33.. to be 1.
 296          * Find the appropriate nmi_hz
 297          */
 298         counter_val = (u64)cpu_khz * 1000;
 299         do_div(counter_val, retval);
 300         if (counter_val > 0x7fffffffULL) {
 301                 u64 count = (u64)cpu_khz * 1000;
 302                 do_div(count, 0x7fffffffUL);
 303                 retval = count + 1;
 304         }
 305         return retval;
 306 }
 307
 308 static int __init check_nmi_watchdog(void)
 309 {
 310         unsigned int *prev_nmi_count;
 311         int cpu;
 312
 313         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 314                 return 0;
 315
 316         if (!atomic_read(&nmi_active))
 317                 return 0;
 318
 319         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 320         if (!prev_nmi_count)
 321                 return -1;
 322
 323         printk(KERN_INFO "Testing NMI watchdog ... ");
 324
 325         if (nmi_watchdog == NMI_LOCAL_APIC)
 326                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 327
 328         for_each_possible_cpu(cpu)
 329                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 330         local_irq_enable();
 331         mdelay((20*1000)/nmi_hz); // wait 20 ticks
 332
 333         for_each_possible_cpu(cpu) {
 334 #ifdef CONFIG_SMP
 335                 /* Check cpu_callin_map here because that is set
 336                    after the timer is started. */
 337                 if (!cpu_isset(cpu, cpu_callin_map))
 338                         continue;
 339 #endif
 340                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 341                         continue;
 342                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 343                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 344                                 cpu,
 345                                 prev_nmi_count[cpu],
 346                                 nmi_count(cpu));
 347                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 348                         atomic_dec(&nmi_active);
 349                 }
 350         }
 351         if (!atomic_read(&nmi_active)) {
 352                 kfree(prev_nmi_count);
 353                 atomic_set(&nmi_active, -1);
 354                 return -1;
 355         }
 356         endflag = 1;
 357         printk("OK.\n");
 358
 359         /* now that we know it works we can reduce NMI frequency to
 360            something more reasonable; makes a difference in some configs */
 361         if (nmi_watchdog == NMI_LOCAL_APIC) {
 362                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 363
 364                 nmi_hz = 1;
 365
 366                 if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
 367                     wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 368                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 369                 }
 370         }
 371
 372         kfree(prev_nmi_count);
 373         return 0;
 374 }
 375 /* This needs to happen later in boot so counters are working */
 376 late_initcall(check_nmi_watchdog);
 377
 378 static int __init setup_nmi_watchdog(char *str)
 379 {
 380         int nmi;
 381
 382         get_option(&str, &nmi);
 383
 384         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 385                 return 0;
 386
 387         nmi_watchdog = nmi;
 388         return 1;
 389 }
 390
 391 __setup("nmi_watchdog=", setup_nmi_watchdog);
 392
 393 static void disable_lapic_nmi_watchdog(void)
 394 {
 395         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 396
 397         if (atomic_read(&nmi_active) <= 0)
 398                 return;
 399
 400         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 401
 402         BUG_ON(atomic_read(&nmi_active) != 0);
 403 }
 404
 405 static void enable_lapic_nmi_watchdog(void)
 406 {
 407         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 408
 409         /* are we already enabled */
 410         if (atomic_read(&nmi_active) != 0)
 411                 return;
 412
 413         /* are we lapic aware */
 414         if (nmi_known_cpu() <= 0)
 415                 return;
 416
 417         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 418         touch_nmi_watchdog();
 419 }
 420
 421 void disable_timer_nmi_watchdog(void)
 422 {
 423         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 424
 425         if (atomic_read(&nmi_active) <= 0)
 426                 return;
 427
 428         disable_irq(0);
 429         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 430
 431         BUG_ON(atomic_read(&nmi_active) != 0);
 432 }
 433
 434 void enable_timer_nmi_watchdog(void)
 435 {
 436         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 437
 438         if (atomic_read(&nmi_active) == 0) {
 439                 touch_nmi_watchdog();
 440                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 441                 enable_irq(0);
 442         }
 443 }
 444
 445 static void __acpi_nmi_disable(void *__unused)
 446 {
 447         apic_write_around(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 448 }
 449
 450 /*
 451  * Disable timer based NMIs on all CPUs:
 452  */
 453 void acpi_nmi_disable(void)
 454 {
 455         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 456                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 457 }
 458
 459 static void __acpi_nmi_enable(void *__unused)
 460 {
 461         apic_write_around(APIC_LVT0, APIC_DM_NMI);
 462 }
 463
 464 /*
 465  * Enable timer based NMIs on all CPUs:
 466  */
 467 void acpi_nmi_enable(void)
 468 {
 469         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 470                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 471 }
 472
 473 #ifdef CONFIG_PM
 474
 475 static int nmi_pm_active; /* nmi_active before suspend */
 476
 477 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 478 {
 479         /* only CPU0 goes here, other CPUs should be offline */
 480         nmi_pm_active = atomic_read(&nmi_active);
 481         stop_apic_nmi_watchdog(NULL);
 482         BUG_ON(atomic_read(&nmi_active) != 0);
 483         return 0;
 484 }
 485
 486 static int lapic_nmi_resume(struct sys_device *dev)
 487 {
 488         /* only CPU0 goes here, other CPUs should be offline */
 489         if (nmi_pm_active > 0) {
 490                 setup_apic_nmi_watchdog(NULL);
 491                 touch_nmi_watchdog();
 492         }
 493         return 0;
 494 }
 495
 496
 497 static struct sysdev_class nmi_sysclass = {
 498         set_kset_name("lapic_nmi"),
 499         .resume         = lapic_nmi_resume,
 500         .suspend        = lapic_nmi_suspend,
 501 };
 502
 503 static struct sys_device device_lapic_nmi = {
 504         .id     = 0,
 505         .cls    = &nmi_sysclass,
 506 };
 507
 508 static int __init init_lapic_nmi_sysfs(void)
 509 {
 510         int error;
 511
 512         /* should really be a BUG_ON but b/c this is an
 513          * init call, it just doesn't work.  -dcz
 514          */
 515         if (nmi_watchdog != NMI_LOCAL_APIC)
 516                 return 0;
 517
 518         if ( atomic_read(&nmi_active) < 0 )
 519                 return 0;
 520
 521         error = sysdev_class_register(&nmi_sysclass);
 522         if (!error)
 523                 error = sysdev_register(&device_lapic_nmi);
 524         return error;
 525 }
 526 /* must come after the local APIC's device_initcall() */
 527 late_initcall(init_lapic_nmi_sysfs);
 528
 529 #endif  /* CONFIG_PM */
 530
 531 /*
 532  * Activate the NMI watchdog via the local APIC.
 533  * Original code written by Keith Owens.
 534  */
 535
 536 static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
 537 {
 538         u64 count = (u64)cpu_khz * 1000;
 539
 540         do_div(count, nmi_hz);
 541         if(descr)
 542                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 543         wrmsrl(perfctr_msr, 0 - count);
 544 }
 545
 546 static void write_watchdog_counter32(unsigned int perfctr_msr,
 547                 const char *descr)
 548 {
 549         u64 count = (u64)cpu_khz * 1000;
 550
 551         do_div(count, nmi_hz);
 552         if(descr)
 553                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 554         wrmsr(perfctr_msr, (u32)(-count), 0);
 555 }
 556
 557 /* Note that these events don't tick when the CPU idles. This means
 558    the frequency varies with CPU load. */
 559
 560 #define K7_EVNTSEL_ENABLE       (1 << 22)
 561 #define K7_EVNTSEL_INT          (1 << 20)
 562 #define K7_EVNTSEL_OS           (1 << 17)
 563 #define K7_EVNTSEL_USR          (1 << 16)
 564 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 565 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 566
 567 static int setup_k7_watchdog(void)
 568 {
 569         unsigned int perfctr_msr, evntsel_msr;
 570         unsigned int evntsel;
 571         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 572
 573         perfctr_msr = MSR_K7_PERFCTR0;
 574         evntsel_msr = MSR_K7_EVNTSEL0;
 575         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 576                 goto fail;
 577
 578         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 579                 goto fail1;
 580
 581         wrmsrl(perfctr_msr, 0UL);
 582
 583         evntsel = K7_EVNTSEL_INT
 584                 | K7_EVNTSEL_OS
 585                 | K7_EVNTSEL_USR
 586                 | K7_NMI_EVENT;
 587
 588         /* setup the timer */
 589         wrmsr(evntsel_msr, evntsel, 0);
 590         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0");
 591         apic_write(APIC_LVTPC, APIC_DM_NMI);
 592         evntsel |= K7_EVNTSEL_ENABLE;
 593         wrmsr(evntsel_msr, evntsel, 0);
 594
 595         wd->perfctr_msr = perfctr_msr;
 596         wd->evntsel_msr = evntsel_msr;
 597         wd->cccr_msr = 0;  //unused
 598         wd->check_bit = 1ULL<<63;
 599         return 1;
 600 fail1:
 601         __release_perfctr_nmi(-1, perfctr_msr);
 602 fail:
 603         return 0;
 604 }
 605
 606 static void stop_k7_watchdog(void)
 607 {
 608         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 609
 610         wrmsr(wd->evntsel_msr, 0, 0);
 611
 612         __release_evntsel_nmi(-1, wd->evntsel_msr);
 613         __release_perfctr_nmi(-1, wd->perfctr_msr);
 614 }
 615
 616 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 617 #define P6_EVNTSEL_INT          (1 << 20)
 618 #define P6_EVNTSEL_OS           (1 << 17)
 619 #define P6_EVNTSEL_USR          (1 << 16)
 620 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 621 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 622
 623 static int setup_p6_watchdog(void)
 624 {
 625         unsigned int perfctr_msr, evntsel_msr;
 626         unsigned int evntsel;
 627         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 628
 629         perfctr_msr = MSR_P6_PERFCTR0;
 630         evntsel_msr = MSR_P6_EVNTSEL0;
 631         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 632                 goto fail;
 633
 634         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 635                 goto fail1;
 636
 637         wrmsrl(perfctr_msr, 0UL);
 638
 639         evntsel = P6_EVNTSEL_INT
 640                 | P6_EVNTSEL_OS
 641                 | P6_EVNTSEL_USR
 642                 | P6_NMI_EVENT;
 643
 644         /* setup the timer */
 645         wrmsr(evntsel_msr, evntsel, 0);
 646         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 647         write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0");
 648         apic_write(APIC_LVTPC, APIC_DM_NMI);
 649         evntsel |= P6_EVNTSEL0_ENABLE;
 650         wrmsr(evntsel_msr, evntsel, 0);
 651
 652         wd->perfctr_msr = perfctr_msr;
 653         wd->evntsel_msr = evntsel_msr;
 654         wd->cccr_msr = 0;  //unused
 655         wd->check_bit = 1ULL<<39;
 656         return 1;
 657 fail1:
 658         __release_perfctr_nmi(-1, perfctr_msr);
 659 fail:
 660         return 0;
 661 }
 662
 663 static void stop_p6_watchdog(void)
 664 {
 665         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 666
 667         wrmsr(wd->evntsel_msr, 0, 0);
 668
 669         __release_evntsel_nmi(-1, wd->evntsel_msr);
 670         __release_perfctr_nmi(-1, wd->perfctr_msr);
 671 }
 672
 673 /* Note that these events don't tick when the CPU idles. This means
 674    the frequency varies with CPU load. */
 675
 676 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 677 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 678 #define P4_ESCR_OS              (1<<3)
 679 #define P4_ESCR_USR             (1<<2)
 680 #define P4_CCCR_OVF_PMI0        (1<<26)
 681 #define P4_CCCR_OVF_PMI1        (1<<27)
 682 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 683 #define P4_CCCR_COMPLEMENT      (1<<19)
 684 #define P4_CCCR_COMPARE         (1<<18)
 685 #define P4_CCCR_REQUIRED        (3<<16)
 686 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 687 #define P4_CCCR_ENABLE          (1<<12)
 688 #define P4_CCCR_OVF             (1<<31)
 689 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 690    CRU_ESCR0 (with any non-null event selector) through a complemented
 691    max threshold. [IA32-Vol3, Section 14.9.9] */
 692
 693 static int setup_p4_watchdog(void)
 694 {
 695         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 696         unsigned int evntsel, cccr_val;
 697         unsigned int misc_enable, dummy;
 698         unsigned int ht_num;
 699         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 700
 701         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 702         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 703                 return 0;
 704
 705 #ifdef CONFIG_SMP
 706         /* detect which hyperthread we are on */
 707         if (smp_num_siblings == 2) {
 708                 unsigned int ebx, apicid;
 709
 710                 ebx = cpuid_ebx(1);
 711                 apicid = (ebx >> 24) & 0xff;
 712                 ht_num = apicid & 1;
 713         } else
 714 #endif
 715                 ht_num = 0;
 716
 717         /* performance counters are shared resources
 718          * assign each hyperthread its own set
 719          * (re-use the ESCR0 register, seems safe
 720          * and keeps the cccr_val the same)
 721          */
 722         if (!ht_num) {
 723                 /* logical cpu 0 */
 724                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 725                 evntsel_msr = MSR_P4_CRU_ESCR0;
 726                 cccr_msr = MSR_P4_IQ_CCCR0;
 727                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 728         } else {
 729                 /* logical cpu 1 */
 730                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 731                 evntsel_msr = MSR_P4_CRU_ESCR0;
 732                 cccr_msr = MSR_P4_IQ_CCCR1;
 733                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 734         }
 735
 736         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 737                 goto fail;
 738
 739         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 740                 goto fail1;
 741
 742         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 743                 | P4_ESCR_OS
 744                 | P4_ESCR_USR;
 745
 746         cccr_val |= P4_CCCR_THRESHOLD(15)
 747                  | P4_CCCR_COMPLEMENT
 748                  | P4_CCCR_COMPARE
 749                  | P4_CCCR_REQUIRED;
 750
 751         wrmsr(evntsel_msr, evntsel, 0);
 752         wrmsr(cccr_msr, cccr_val, 0);
 753         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0");
 754         apic_write(APIC_LVTPC, APIC_DM_NMI);
 755         cccr_val |= P4_CCCR_ENABLE;
 756         wrmsr(cccr_msr, cccr_val, 0);
 757         wd->perfctr_msr = perfctr_msr;
 758         wd->evntsel_msr = evntsel_msr;
 759         wd->cccr_msr = cccr_msr;
 760         wd->check_bit = 1ULL<<39;
 761         return 1;
 762 fail1:
 763         __release_perfctr_nmi(-1, perfctr_msr);
 764 fail:
 765         return 0;
 766 }
 767
 768 static void stop_p4_watchdog(void)
 769 {
 770         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 771
 772         wrmsr(wd->cccr_msr, 0, 0);
 773         wrmsr(wd->evntsel_msr, 0, 0);
 774
 775         __release_evntsel_nmi(-1, wd->evntsel_msr);
 776         __release_perfctr_nmi(-1, wd->perfctr_msr);
 777 }
 778
 779 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 780 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 781
 782 static int setup_intel_arch_watchdog(void)
 783 {
 784         unsigned int ebx;
 785         union cpuid10_eax eax;
 786         unsigned int unused;
 787         unsigned int perfctr_msr, evntsel_msr;
 788         unsigned int evntsel;
 789         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 790
 791         /*
 792          * Check whether the Architectural PerfMon supports
 793          * Unhalted Core Cycles Event or not.
 794          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 795          */
 796         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 797         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 798             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 799                 goto fail;
 800
 801         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 802         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 803
 804         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 805                 goto fail;
 806
 807         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 808                 goto fail1;
 809
 810         wrmsrl(perfctr_msr, 0UL);
 811
 812         evntsel = ARCH_PERFMON_EVENTSEL_INT
 813                 | ARCH_PERFMON_EVENTSEL_OS
 814                 | ARCH_PERFMON_EVENTSEL_USR
 815                 | ARCH_PERFMON_NMI_EVENT_SEL
 816                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 817
 818         /* setup the timer */
 819         wrmsr(evntsel_msr, evntsel, 0);
 820         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 821         write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0");
 822         apic_write(APIC_LVTPC, APIC_DM_NMI);
 823         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 824         wrmsr(evntsel_msr, evntsel, 0);
 825
 826         wd->perfctr_msr = perfctr_msr;
 827         wd->evntsel_msr = evntsel_msr;
 828         wd->cccr_msr = 0;  //unused
 829         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 830         return 1;
 831 fail1:
 832         __release_perfctr_nmi(-1, perfctr_msr);
 833 fail:
 834         return 0;
 835 }
 836
 837 static void stop_intel_arch_watchdog(void)
 838 {
 839         unsigned int ebx;
 840         union cpuid10_eax eax;
 841         unsigned int unused;
 842         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 843
 844         /*
 845          * Check whether the Architectural PerfMon supports
 846          * Unhalted Core Cycles Event or not.
 847          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 848          */
 849         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 850         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 851             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 852                 return;
 853
 854         wrmsr(wd->evntsel_msr, 0, 0);
 855         __release_evntsel_nmi(-1, wd->evntsel_msr);
 856         __release_perfctr_nmi(-1, wd->perfctr_msr);
 857 }
 858
 859 void setup_apic_nmi_watchdog (void *unused)
 860 {
 861         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 862
 863         /* only support LOCAL and IO APICs for now */
 864         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 865             (nmi_watchdog != NMI_IO_APIC))
 866                 return;
 867
 868         if (wd->enabled == 1)
 869                 return;
 870
 871         /* cheap hack to support suspend/resume */
 872         /* if cpu0 is not active neither should the other cpus */
 873         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 874                 return;
 875
 876         if (nmi_watchdog == NMI_LOCAL_APIC) {
 877                 switch (boot_cpu_data.x86_vendor) {
 878                 case X86_VENDOR_AMD:
 879                         if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15 &&
 880                                 boot_cpu_data.x86 != 16)
 881                                 return;
 882                         if (!setup_k7_watchdog())
 883                                 return;
 884                         break;
 885                 case X86_VENDOR_INTEL:
 886                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 887                                 if (!setup_intel_arch_watchdog())
 888                                         return;
 889                                 break;
 890                         }
 891                         switch (boot_cpu_data.x86) {
 892                         case 6:
 893                                 if (boot_cpu_data.x86_model > 0xd)
 894                                         return;
 895
 896                                 if (!setup_p6_watchdog())
 897                                         return;
 898                                 break;
 899                         case 15:
 900                                 if (boot_cpu_data.x86_model > 0x4)
 901                                         return;
 902
 903                                 if (!setup_p4_watchdog())
 904                                         return;
 905                                 break;
 906                         default:
 907                                 return;
 908                         }
 909                         break;
 910                 default:
 911                         return;
 912                 }
 913         }
 914         wd->enabled = 1;
 915         atomic_inc(&nmi_active);
 916 }
 917
 918 void stop_apic_nmi_watchdog(void *unused)
 919 {
 920         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 921
 922         /* only support LOCAL and IO APICs for now */
 923         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 924             (nmi_watchdog != NMI_IO_APIC))
 925                 return;
 926
 927         if (wd->enabled == 0)
 928                 return;
 929
 930         if (nmi_watchdog == NMI_LOCAL_APIC) {
 931                 switch (boot_cpu_data.x86_vendor) {
 932                 case X86_VENDOR_AMD:
 933                         stop_k7_watchdog();
 934                         break;
 935                 case X86_VENDOR_INTEL:
 936                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 937                                 stop_intel_arch_watchdog();
 938                                 break;
 939                         }
 940                         switch (boot_cpu_data.x86) {
 941                         case 6:
 942                                 if (boot_cpu_data.x86_model > 0xd)
 943                                         break;
 944                                 stop_p6_watchdog();
 945                                 break;
 946                         case 15:
 947                                 if (boot_cpu_data.x86_model > 0x4)
 948                                         break;
 949                                 stop_p4_watchdog();
 950                                 break;
 951                         }
 952                         break;
 953                 default:
 954                         return;
 955                 }
 956         }
 957         wd->enabled = 0;
 958         atomic_dec(&nmi_active);
 959 }
 960
 961 /*
 962  * the best way to detect whether a CPU has a 'hard lockup' problem
 963  * is to check it's local APIC timer IRQ counts. If they are not
 964  * changing then that CPU has some problem.
 965  *
 966  * as these watchdog NMI IRQs are generated on every CPU, we only
 967  * have to check the current processor.
 968  *
 969  * since NMIs don't listen to _any_ locks, we have to be extremely
 970  * careful not to rely on unsafe variables. The printk might lock
 971  * up though, so we have to break up any console locks first ...
 972  * [when there will be more tty-related locks, break them up
 973  *  here too!]
 974  */
 975
 976 static unsigned int
 977         last_irq_sums [NR_CPUS],
 978         alert_counter [NR_CPUS];
 979
 980 void touch_nmi_watchdog (void)
 981 {
 982         if (nmi_watchdog > 0) {
 983                 unsigned cpu;
 984
 985                 /*
 986                  * Just reset the alert counters, (other CPUs might be
 987                  * spinning on locks we hold):
 988                  */
 989                 for_each_present_cpu (cpu)
 990                         alert_counter[cpu] = 0;
 991         }
 992
 993         /*
 994          * Tickle the softlockup detector too:
 995          */
 996         touch_softlockup_watchdog();
 997 }
 998 EXPORT_SYMBOL(touch_nmi_watchdog);
 999
1000 extern void die_nmi(struct pt_regs *, const char *msg);
1001
1002 __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
1003 {
1004
1005         /*
1006          * Since current_thread_info()-> is always on the stack, and we
1007          * always switch the stack NMI-atomically, it's safe to use
1008          * smp_processor_id().
1009          */
1010         unsigned int sum;
1011         int touched = 0;
1012         int cpu = smp_processor_id();
1013         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
1014         u64 dummy;
1015         int rc=0;
1016
1017         /* check for other users first */
1018         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
1019                         == NOTIFY_STOP) {
1020                 rc = 1;
1021                 touched = 1;
1022         }
1023
1024         if (cpu_isset(cpu, backtrace_mask)) {
1025                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
1026
1027                 spin_lock(&lock);
1028                 printk("NMI backtrace for cpu %d\n", cpu);
1029                 dump_stack();
1030                 spin_unlock(&lock);
1031                 cpu_clear(cpu, backtrace_mask);
1032         }
1033
1034         /*
1035          * Take the local apic timer and PIT/HPET into account. We don't
1036          * know which one is active, when we have highres/dyntick on
1037          */
1038         sum = per_cpu(irq_stat, cpu).apic_timer_irqs + kstat_irqs(0);
1039
1040         /* if the none of the timers isn't firing, this cpu isn't doing much */
1041         if (!touched && last_irq_sums[cpu] == sum) {
1042                 /*
1043                  * Ayiee, looks like this CPU is stuck ...
1044                  * wait a few IRQs (5 seconds) before doing the oops ...
1045                  */
1046                 alert_counter[cpu]++;
1047                 if (alert_counter[cpu] == 5*nmi_hz)
1048                         /*
1049                          * die_nmi will return ONLY if NOTIFY_STOP happens..
1050                          */
1051                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
1052         } else {
1053                 last_irq_sums[cpu] = sum;
1054                 alert_counter[cpu] = 0;
1055         }
1056         /* see if the nmi watchdog went off */
1057         if (wd->enabled) {
1058                 if (nmi_watchdog == NMI_LOCAL_APIC) {
1059                         rdmsrl(wd->perfctr_msr, dummy);
1060                         if (dummy & wd->check_bit){
1061                                 /* this wasn't a watchdog timer interrupt */
1062                                 goto done;
1063                         }
1064
1065                         /* only Intel P4 uses the cccr msr */
1066                         if (wd->cccr_msr != 0) {
1067                                 /*
1068                                  * P4 quirks:
1069                                  * - An overflown perfctr will assert its interrupt
1070                                  *   until the OVF flag in its CCCR is cleared.
1071                                  * - LVTPC is masked on interrupt and must be
1072                                  *   unmasked by the LVTPC handler.
1073                                  */
1074                                 rdmsrl(wd->cccr_msr, dummy);
1075                                 dummy &= ~P4_CCCR_OVF;
1076                                 wrmsrl(wd->cccr_msr, dummy);
1077                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1078                                 /* start the cycle over again */
1079                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1080                         }
1081                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
1082                                  wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
1083                                 /* P6 based Pentium M need to re-unmask
1084                                  * the apic vector but it doesn't hurt
1085                                  * other P6 variant.
1086                                  * ArchPerfom/Core Duo also needs this */
1087                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1088                                 /* P6/ARCH_PERFMON has 32 bit counter write */
1089                                 write_watchdog_counter32(wd->perfctr_msr, NULL);
1090                         } else {
1091                                 /* start the cycle over again */
1092                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1093                         }
1094                         rc = 1;
1095                 } else if (nmi_watchdog == NMI_IO_APIC) {
1096                         /* don't know how to accurately check for this.
1097                          * just assume it was a watchdog timer interrupt
1098                          * This matches the old behaviour.
1099                          */
1100                         rc = 1;
1101                 }
1102         }
1103 done:
1104         return rc;
1105 }
1106
1107 int do_nmi_callback(struct pt_regs * regs, int cpu)
1108 {
1109 #ifdef CONFIG_SYSCTL
1110         if (unknown_nmi_panic)
1111                 return unknown_nmi_panic_callback(regs, cpu);
1112 #endif
1113         return 0;
1114 }
1115
1116 #ifdef CONFIG_SYSCTL
1117
1118 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
1119 {
1120         unsigned char reason = get_nmi_reason();
1121         char buf[64];
1122
1123         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
1124         die_nmi(regs, buf);
1125         return 0;
1126 }
1127
1128 /*
1129  * proc handler for /proc/sys/kernel/nmi
1130  */
1131 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
1132                         void __user *buffer, size_t *length, loff_t *ppos)
1133 {
1134         int old_state;
1135
1136         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
1137         old_state = nmi_watchdog_enabled;
1138         proc_dointvec(table, write, file, buffer, length, ppos);
1139         if (!!old_state == !!nmi_watchdog_enabled)
1140                 return 0;
1141
1142         if (atomic_read(&nmi_active) < 0) {
1143                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
1144                 return -EIO;
1145         }
1146
1147         if (nmi_watchdog == NMI_DEFAULT) {
1148                 if (nmi_known_cpu() > 0)
1149                         nmi_watchdog = NMI_LOCAL_APIC;
1150                 else
1151                         nmi_watchdog = NMI_IO_APIC;
1152         }
1153
1154         if (nmi_watchdog == NMI_LOCAL_APIC) {
1155                 if (nmi_watchdog_enabled)
1156                         enable_lapic_nmi_watchdog();
1157                 else
1158                         disable_lapic_nmi_watchdog();
1159         } else {
1160                 printk( KERN_WARNING
1161                         "NMI watchdog doesn't know what hardware to touch\n");
1162                 return -EIO;
1163         }
1164         return 0;
1165 }
1166
1167 #endif
1168
1169 void __trigger_all_cpu_backtrace(void)
1170 {
1171         int i;
1172
1173         backtrace_mask = cpu_online_map;
1174         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
1175         for (i = 0; i < 10 * 1000; i++) {
1176                 if (cpus_empty(backtrace_mask))
1177                         break;
1178                 mdelay(1);
1179         }
1180 }
1181
1182 EXPORT_SYMBOL(nmi_active);
1183 EXPORT_SYMBOL(nmi_watchdog);
1184 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1185 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1186 EXPORT_SYMBOL(reserve_perfctr_nmi);
1187 EXPORT_SYMBOL(release_perfctr_nmi);
1188 EXPORT_SYMBOL(reserve_evntsel_nmi);
1189 EXPORT_SYMBOL(release_evntsel_nmi);
1190 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1191 EXPORT_SYMBOL(enable_timer_nmi_watchdog);