3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_JUMP_LABEL
44 select HAVE_ARCH_SECCOMP_FILTER
45 select HAVE_ARCH_TRACEHOOK
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_CC_STACKPROTECTOR
49 select HAVE_CMPXCHG_DOUBLE
50 select HAVE_DEBUG_BUGVERBOSE
51 select HAVE_DEBUG_KMEMLEAK
52 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_CONTIGUOUS
55 select HAVE_DYNAMIC_FTRACE
56 select HAVE_EFFICIENT_UNALIGNED_ACCESS
57 select HAVE_FTRACE_MCOUNT_RECORD
58 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if PERF_EVENTS
63 select HAVE_PATA_PLATFORM
64 select HAVE_PERF_EVENTS
66 select HAVE_PERF_USER_STACK_DUMP
67 select HAVE_RCU_TABLE_FREE
68 select HAVE_SYSCALL_TRACEPOINTS
70 select MODULES_USE_ELF_RELA
73 select OF_EARLY_FLATTREE
74 select OF_RESERVED_MEM
75 select PERF_USE_VMALLOC
80 select SYSCTL_EXCEPTION_TRACE
81 select HAVE_CONTEXT_TRACKING
83 ARM 64-bit (AArch64) Linux support.
88 config ARCH_PHYS_ADDR_T_64BIT
97 config STACKTRACE_SUPPORT
100 config LOCKDEP_SUPPORT
103 config TRACE_IRQFLAGS_SUPPORT
106 config RWSEM_XCHGADD_ALGORITHM
109 config GENERIC_HWEIGHT
115 config GENERIC_CALIBRATE_DELAY
121 config HAVE_GENERIC_RCU_GUP
124 config ARCH_DMA_ADDR_T_64BIT
127 config NEED_DMA_MAP_STATE
130 config NEED_SG_DMA_LENGTH
139 config KERNEL_MODE_NEON
142 config FIX_EARLYCON_MEM
145 source "init/Kconfig"
147 source "kernel/Kconfig.freezer"
149 menu "Platform selection"
152 bool "AMD Seattle SoC Family"
154 This enables support for AMD Seattle SOC Family
157 bool "NVIDIA Tegra SoC Family"
158 select ARCH_HAS_RESET_CONTROLLER
159 select ARCH_REQUIRE_GPIOLIB
163 select GENERIC_CLOCKEVENTS
167 select RESET_CONTROLLER
169 This enables support for the NVIDIA Tegra SoC family.
171 config ARCH_TEGRA_132_SOC
172 bool "NVIDIA Tegra132 SoC"
173 depends on ARCH_TEGRA
174 select PINCTRL_TEGRA124
175 select USB_ARCH_HAS_EHCI if USB_SUPPORT
176 select USB_ULPI if USB_PHY
177 select USB_ULPI_VIEWPORT if USB_PHY
179 Enable support for NVIDIA Tegra132 SoC, based on the Denver
180 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
181 but contains an NVIDIA Denver CPU complex in place of
182 Tegra124's "4+1" Cortex-A15 CPU complex.
185 bool "Cavium Inc. Thunder SoC Family"
187 This enables support for Cavium's Thunder Family of SoCs.
190 bool "ARMv8 software model (Versatile Express)"
191 select ARCH_REQUIRE_GPIOLIB
192 select COMMON_CLK_VERSATILE
193 select POWER_RESET_VEXPRESS
194 select VEXPRESS_CONFIG
196 This enables support for the ARMv8 software model (Versatile
200 bool "AppliedMicro X-Gene SOC Family"
202 This enables support for AppliedMicro X-Gene SOC Family
211 This feature enables support for PCI bus system. If you say Y
212 here, the kernel will include drivers and infrastructure code
213 to support PCI bus devices.
218 config PCI_DOMAINS_GENERIC
224 source "drivers/pci/Kconfig"
225 source "drivers/pci/pcie/Kconfig"
226 source "drivers/pci/hotplug/Kconfig"
230 menu "Kernel Features"
232 menu "ARM errata workarounds via the alternatives framework"
234 config ARM64_ERRATUM_826319
235 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
238 This option adds an alternative code sequence to work around ARM
239 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
240 AXI master interface and an L2 cache.
242 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
243 and is unable to accept a certain write via this interface, it will
244 not progress on read data presented on the read data channel and the
247 The workaround promotes data cache clean instructions to
248 data cache clean-and-invalidate.
249 Please note that this does not necessarily enable the workaround,
250 as it depends on the alternative framework, which will only patch
251 the kernel if an affected CPU is detected.
255 config ARM64_ERRATUM_827319
256 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
259 This option adds an alternative code sequence to work around ARM
260 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
261 master interface and an L2 cache.
263 Under certain conditions this erratum can cause a clean line eviction
264 to occur at the same time as another transaction to the same address
265 on the AMBA 5 CHI interface, which can cause data corruption if the
266 interconnect reorders the two transactions.
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this does not necessarily enable the workaround,
271 as it depends on the alternative framework, which will only patch
272 the kernel if an affected CPU is detected.
276 config ARM64_ERRATUM_824069
277 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
280 This option adds an alternative code sequence to work around ARM
281 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
282 to a coherent interconnect.
284 If a Cortex-A53 processor is executing a store or prefetch for
285 write instruction at the same time as a processor in another
286 cluster is executing a cache maintenance operation to the same
287 address, then this erratum might cause a clean cache line to be
288 incorrectly marked as dirty.
290 The workaround promotes data cache clean instructions to
291 data cache clean-and-invalidate.
292 Please note that this option does not necessarily enable the
293 workaround, as it depends on the alternative framework, which will
294 only patch the kernel if an affected CPU is detected.
298 config ARM64_ERRATUM_819472
299 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
302 This option adds an alternative code sequence to work around ARM
303 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
304 present when it is connected to a coherent interconnect.
306 If the processor is executing a load and store exclusive sequence at
307 the same time as a processor in another cluster is executing a cache
308 maintenance operation to the same address, then this erratum might
309 cause data corruption.
311 The workaround promotes data cache clean instructions to
312 data cache clean-and-invalidate.
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
319 config ARM64_ERRATUM_832075
320 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
323 This option adds an alternative code sequence to work around ARM
324 erratum 832075 on Cortex-A57 parts up to r1p2.
326 Affected Cortex-A57 parts might deadlock when exclusive load/store
327 instructions to Write-Back memory are mixed with Device loads.
329 The workaround is to promote device loads to use Load-Acquire
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
342 default ARM64_4K_PAGES
344 Page size (translation granule) configuration.
346 config ARM64_4K_PAGES
349 This feature enables 4KB pages support.
351 config ARM64_64K_PAGES
354 This feature enables 64KB pages support (4KB by default)
355 allowing only two levels of page tables and faster TLB
356 look-up. AArch32 emulation is not available when this feature
362 prompt "Virtual address space size"
363 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
364 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
366 Allows choosing one of multiple possible virtual address
367 space sizes. The level of translation table is determined by
368 a combination of page size and virtual address space size.
370 config ARM64_VA_BITS_39
372 depends on ARM64_4K_PAGES
374 config ARM64_VA_BITS_42
376 depends on ARM64_64K_PAGES
378 config ARM64_VA_BITS_48
386 default 39 if ARM64_VA_BITS_39
387 default 42 if ARM64_VA_BITS_42
388 default 48 if ARM64_VA_BITS_48
390 config ARM64_PGTABLE_LEVELS
392 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
393 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
394 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
395 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
397 config CPU_BIG_ENDIAN
398 bool "Build big-endian kernel"
400 Say Y if you plan on running a kernel in big-endian mode.
403 bool "Symmetric Multi-Processing"
405 This enables support for systems with more than one CPU. If
406 you say N here, the kernel will run on single and
407 multiprocessor machines, but will use only one CPU of a
408 multiprocessor machine. If you say Y here, the kernel will run
409 on many, but not all, single processor machines. On a single
410 processor machine, the kernel will run faster if you say N
413 If you don't know what to do here, say N.
416 bool "Multi-core scheduler support"
419 Multi-core scheduler support improves the CPU scheduler's decision
420 making when dealing with multi-core CPU chips at a cost of slightly
421 increased overhead in some places. If unsure say N here.
424 bool "SMT scheduler support"
427 Improves the CPU scheduler's decision making when dealing with
428 MultiThreading at a cost of slightly increased overhead in some
429 places. If unsure say N here.
432 int "Maximum number of CPUs (2-64)"
435 # These have to remain sorted largest to smallest
439 bool "Support for hot-pluggable CPUs"
442 Say Y here to experiment with turning CPUs off and on. CPUs
443 can be controlled through /sys/devices/system/cpu.
445 source kernel/Kconfig.preempt
451 config ARCH_HAS_HOLES_MEMORYMODEL
452 def_bool y if SPARSEMEM
454 config ARCH_SPARSEMEM_ENABLE
456 select SPARSEMEM_VMEMMAP_ENABLE
458 config ARCH_SPARSEMEM_DEFAULT
459 def_bool ARCH_SPARSEMEM_ENABLE
461 config ARCH_SELECT_MEMORY_MODEL
462 def_bool ARCH_SPARSEMEM_ENABLE
464 config HAVE_ARCH_PFN_VALID
465 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
467 config HW_PERF_EVENTS
468 bool "Enable hardware performance counter support for perf events"
469 depends on PERF_EVENTS
472 Enable hardware performance counter support for perf events. If
473 disabled, perf events will use software events only.
475 config SYS_SUPPORTS_HUGETLBFS
478 config ARCH_WANT_GENERAL_HUGETLB
481 config ARCH_WANT_HUGE_PMD_SHARE
482 def_bool y if !ARM64_64K_PAGES
484 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
487 config ARCH_HAS_CACHE_LINE_SIZE
493 bool "Enable seccomp to safely compute untrusted bytecode"
495 This kernel feature is useful for number crunching applications
496 that may need to compute untrusted bytecode during their
497 execution. By using pipes or other transports made available to
498 the process as file descriptors supporting the read/write
499 syscalls, it's possible to isolate those applications in
500 their own address space using seccomp. Once seccomp is
501 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
502 and the task is only allowed to execute a few safe syscalls
503 defined by each seccomp mode.
510 bool "Xen guest support on ARM64"
511 depends on ARM64 && OF
514 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
516 config FORCE_MAX_ZONEORDER
518 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
521 menuconfig ARMV8_DEPRECATED
522 bool "Emulate deprecated/obsolete ARMv8 instructions"
525 Legacy software support may require certain instructions
526 that have been deprecated or obsoleted in the architecture.
528 Enable this config to enable selective emulation of these
536 bool "Emulate SWP/SWPB instructions"
538 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
539 they are always undefined. Say Y here to enable software
540 emulation of these instructions for userspace using LDXR/STXR.
542 In some older versions of glibc [<=2.8] SWP is used during futex
543 trylock() operations with the assumption that the code will not
544 be preempted. This invalid assumption may be more likely to fail
545 with SWP emulation enabled, leading to deadlock of the user
548 NOTE: when accessing uncached shared regions, LDXR/STXR rely
549 on an external transaction monitoring block called a global
550 monitor to maintain update atomicity. If your system does not
551 implement a global monitor, this option can cause programs that
552 perform SWP operations to uncached memory to deadlock.
556 config CP15_BARRIER_EMULATION
557 bool "Emulate CP15 Barrier instructions"
559 The CP15 barrier instructions - CP15ISB, CP15DSB, and
560 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
561 strongly recommended to use the ISB, DSB, and DMB
562 instructions instead.
564 Say Y here to enable software emulation of these
565 instructions for AArch32 userspace code. When this option is
566 enabled, CP15 barrier usage is traced which can help
567 identify software that needs updating.
578 string "Default kernel command string"
581 Provide a set of default command-line options at build time by
582 entering them here. As a minimum, you should specify the the
583 root device (e.g. root=/dev/nfs).
586 bool "Always use the default kernel command string"
588 Always use the default kernel command string, even if the boot
589 loader passes other arguments to the kernel.
590 This is useful if you cannot or don't want to change the
591 command-line options your boot loader passes to the kernel.
597 bool "UEFI runtime support"
598 depends on OF && !CPU_BIG_ENDIAN
601 select EFI_PARAMS_FROM_FDT
602 select EFI_RUNTIME_WRAPPERS
607 This option provides support for runtime services provided
608 by UEFI firmware (such as non-volatile variables, realtime
609 clock, and platform reset). A UEFI stub is also provided to
610 allow the kernel to be booted as an EFI application. This
611 is only useful on systems that have UEFI firmware.
614 bool "Enable support for SMBIOS (DMI) tables"
618 This enables SMBIOS/DMI feature for systems.
620 This option is only useful on systems that have UEFI firmware.
621 However, even with this option, the resultant kernel should
622 continue to boot on existing non-UEFI platforms.
626 menu "Userspace binary formats"
628 source "fs/Kconfig.binfmt"
631 bool "Kernel support for 32-bit EL0"
632 depends on !ARM64_64K_PAGES
633 select COMPAT_BINFMT_ELF
635 select OLD_SIGSUSPEND3
636 select COMPAT_OLD_SIGACTION
638 This option enables support for a 32-bit EL0 running under a 64-bit
639 kernel at EL1. AArch32-specific components such as system calls,
640 the user helper functions, VFP support and the ptrace interface are
641 handled appropriately by the kernel.
643 If you want to execute 32-bit userspace applications, say Y.
645 config SYSVIPC_COMPAT
647 depends on COMPAT && SYSVIPC
651 menu "Power management options"
653 source "kernel/power/Kconfig"
655 config ARCH_SUSPEND_POSSIBLE
658 config ARM64_CPU_SUSPEND
663 menu "CPU Power Management"
665 source "drivers/cpuidle/Kconfig"
667 source "drivers/cpufreq/Kconfig"
673 source "drivers/Kconfig"
675 source "drivers/firmware/Kconfig"
679 source "arch/arm64/kvm/Kconfig"
681 source "arch/arm64/Kconfig.debug"
683 source "security/Kconfig"
685 source "crypto/Kconfig"
687 source "arch/arm64/crypto/Kconfig"