3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_JUMP_LABEL
44 select HAVE_ARCH_SECCOMP_FILTER
45 select HAVE_ARCH_TRACEHOOK
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_CC_STACKPROTECTOR
49 select HAVE_CMPXCHG_DOUBLE
50 select HAVE_DEBUG_BUGVERBOSE
51 select HAVE_DEBUG_KMEMLEAK
52 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_CONTIGUOUS
55 select HAVE_DYNAMIC_FTRACE
56 select HAVE_EFFICIENT_UNALIGNED_ACCESS
57 select HAVE_FTRACE_MCOUNT_RECORD
58 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if PERF_EVENTS
63 select HAVE_PATA_PLATFORM
64 select HAVE_PERF_EVENTS
66 select HAVE_PERF_USER_STACK_DUMP
67 select HAVE_RCU_TABLE_FREE
68 select HAVE_SYSCALL_TRACEPOINTS
70 select MODULES_USE_ELF_RELA
73 select OF_EARLY_FLATTREE
74 select OF_RESERVED_MEM
75 select PERF_USE_VMALLOC
80 select SYSCTL_EXCEPTION_TRACE
81 select HAVE_CONTEXT_TRACKING
83 ARM 64-bit (AArch64) Linux support.
88 config ARCH_PHYS_ADDR_T_64BIT
97 config STACKTRACE_SUPPORT
100 config LOCKDEP_SUPPORT
103 config TRACE_IRQFLAGS_SUPPORT
106 config RWSEM_XCHGADD_ALGORITHM
109 config GENERIC_HWEIGHT
115 config GENERIC_CALIBRATE_DELAY
121 config HAVE_GENERIC_RCU_GUP
124 config ARCH_DMA_ADDR_T_64BIT
127 config NEED_DMA_MAP_STATE
130 config NEED_SG_DMA_LENGTH
139 config KERNEL_MODE_NEON
142 config FIX_EARLYCON_MEM
145 source "init/Kconfig"
147 source "kernel/Kconfig.freezer"
149 menu "Platform selection"
154 This enables support for Samsung Exynos SoC family
157 bool "ARMv8 based Samsung Exynos7"
159 select COMMON_CLK_SAMSUNG
160 select HAVE_S3C2410_WATCHDOG if WATCHDOG
161 select HAVE_S3C_RTC if RTC_CLASS
163 select PINCTRL_EXYNOS
166 This enables support for Samsung Exynos7 SoC family
168 config ARCH_FSL_LS2085A
169 bool "Freescale LS2085A SOC"
171 This enables support for Freescale LS2085A SOC.
174 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
177 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
180 bool "AMD Seattle SoC Family"
182 This enables support for AMD Seattle SOC Family
185 bool "NVIDIA Tegra SoC Family"
186 select ARCH_HAS_RESET_CONTROLLER
187 select ARCH_REQUIRE_GPIOLIB
191 select GENERIC_CLOCKEVENTS
194 select RESET_CONTROLLER
196 This enables support for the NVIDIA Tegra SoC family.
198 config ARCH_TEGRA_132_SOC
199 bool "NVIDIA Tegra132 SoC"
200 depends on ARCH_TEGRA
201 select PINCTRL_TEGRA124
202 select USB_ULPI if USB_PHY
203 select USB_ULPI_VIEWPORT if USB_PHY
205 Enable support for NVIDIA Tegra132 SoC, based on the Denver
206 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
207 but contains an NVIDIA Denver CPU complex in place of
208 Tegra124's "4+1" Cortex-A15 CPU complex.
211 bool "Cavium Inc. Thunder SoC Family"
213 This enables support for Cavium's Thunder Family of SoCs.
216 bool "ARMv8 software model (Versatile Express)"
217 select ARCH_REQUIRE_GPIOLIB
218 select COMMON_CLK_VERSATILE
219 select POWER_RESET_VEXPRESS
220 select VEXPRESS_CONFIG
222 This enables support for the ARMv8 software model (Versatile
226 bool "AppliedMicro X-Gene SOC Family"
228 This enables support for AppliedMicro X-Gene SOC Family
237 This feature enables support for PCI bus system. If you say Y
238 here, the kernel will include drivers and infrastructure code
239 to support PCI bus devices.
244 config PCI_DOMAINS_GENERIC
250 source "drivers/pci/Kconfig"
251 source "drivers/pci/pcie/Kconfig"
252 source "drivers/pci/hotplug/Kconfig"
256 menu "Kernel Features"
258 menu "ARM errata workarounds via the alternatives framework"
260 config ARM64_ERRATUM_826319
261 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
264 This option adds an alternative code sequence to work around ARM
265 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
266 AXI master interface and an L2 cache.
268 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
269 and is unable to accept a certain write via this interface, it will
270 not progress on read data presented on the read data channel and the
273 The workaround promotes data cache clean instructions to
274 data cache clean-and-invalidate.
275 Please note that this does not necessarily enable the workaround,
276 as it depends on the alternative framework, which will only patch
277 the kernel if an affected CPU is detected.
281 config ARM64_ERRATUM_827319
282 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
285 This option adds an alternative code sequence to work around ARM
286 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
287 master interface and an L2 cache.
289 Under certain conditions this erratum can cause a clean line eviction
290 to occur at the same time as another transaction to the same address
291 on the AMBA 5 CHI interface, which can cause data corruption if the
292 interconnect reorders the two transactions.
294 The workaround promotes data cache clean instructions to
295 data cache clean-and-invalidate.
296 Please note that this does not necessarily enable the workaround,
297 as it depends on the alternative framework, which will only patch
298 the kernel if an affected CPU is detected.
302 config ARM64_ERRATUM_824069
303 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
306 This option adds an alternative code sequence to work around ARM
307 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
308 to a coherent interconnect.
310 If a Cortex-A53 processor is executing a store or prefetch for
311 write instruction at the same time as a processor in another
312 cluster is executing a cache maintenance operation to the same
313 address, then this erratum might cause a clean cache line to be
314 incorrectly marked as dirty.
316 The workaround promotes data cache clean instructions to
317 data cache clean-and-invalidate.
318 Please note that this option does not necessarily enable the
319 workaround, as it depends on the alternative framework, which will
320 only patch the kernel if an affected CPU is detected.
324 config ARM64_ERRATUM_819472
325 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
328 This option adds an alternative code sequence to work around ARM
329 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
330 present when it is connected to a coherent interconnect.
332 If the processor is executing a load and store exclusive sequence at
333 the same time as a processor in another cluster is executing a cache
334 maintenance operation to the same address, then this erratum might
335 cause data corruption.
337 The workaround promotes data cache clean instructions to
338 data cache clean-and-invalidate.
339 Please note that this does not necessarily enable the workaround,
340 as it depends on the alternative framework, which will only patch
341 the kernel if an affected CPU is detected.
345 config ARM64_ERRATUM_832075
346 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
349 This option adds an alternative code sequence to work around ARM
350 erratum 832075 on Cortex-A57 parts up to r1p2.
352 Affected Cortex-A57 parts might deadlock when exclusive load/store
353 instructions to Write-Back memory are mixed with Device loads.
355 The workaround is to promote device loads to use Load-Acquire
357 Please note that this does not necessarily enable the workaround,
358 as it depends on the alternative framework, which will only patch
359 the kernel if an affected CPU is detected.
368 default ARM64_4K_PAGES
370 Page size (translation granule) configuration.
372 config ARM64_4K_PAGES
375 This feature enables 4KB pages support.
377 config ARM64_64K_PAGES
380 This feature enables 64KB pages support (4KB by default)
381 allowing only two levels of page tables and faster TLB
382 look-up. AArch32 emulation is not available when this feature
388 prompt "Virtual address space size"
389 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
390 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
392 Allows choosing one of multiple possible virtual address
393 space sizes. The level of translation table is determined by
394 a combination of page size and virtual address space size.
396 config ARM64_VA_BITS_39
398 depends on ARM64_4K_PAGES
400 config ARM64_VA_BITS_42
402 depends on ARM64_64K_PAGES
404 config ARM64_VA_BITS_48
412 default 39 if ARM64_VA_BITS_39
413 default 42 if ARM64_VA_BITS_42
414 default 48 if ARM64_VA_BITS_48
416 config ARM64_PGTABLE_LEVELS
418 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
419 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
420 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
421 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
423 config CPU_BIG_ENDIAN
424 bool "Build big-endian kernel"
426 Say Y if you plan on running a kernel in big-endian mode.
429 bool "Symmetric Multi-Processing"
431 This enables support for systems with more than one CPU. If
432 you say N here, the kernel will run on single and
433 multiprocessor machines, but will use only one CPU of a
434 multiprocessor machine. If you say Y here, the kernel will run
435 on many, but not all, single processor machines. On a single
436 processor machine, the kernel will run faster if you say N
439 If you don't know what to do here, say N.
442 bool "Multi-core scheduler support"
445 Multi-core scheduler support improves the CPU scheduler's decision
446 making when dealing with multi-core CPU chips at a cost of slightly
447 increased overhead in some places. If unsure say N here.
450 bool "SMT scheduler support"
453 Improves the CPU scheduler's decision making when dealing with
454 MultiThreading at a cost of slightly increased overhead in some
455 places. If unsure say N here.
458 int "Maximum number of CPUs (2-64)"
461 # These have to remain sorted largest to smallest
465 bool "Support for hot-pluggable CPUs"
468 Say Y here to experiment with turning CPUs off and on. CPUs
469 can be controlled through /sys/devices/system/cpu.
471 source kernel/Kconfig.preempt
477 config ARCH_HAS_HOLES_MEMORYMODEL
478 def_bool y if SPARSEMEM
480 config ARCH_SPARSEMEM_ENABLE
482 select SPARSEMEM_VMEMMAP_ENABLE
484 config ARCH_SPARSEMEM_DEFAULT
485 def_bool ARCH_SPARSEMEM_ENABLE
487 config ARCH_SELECT_MEMORY_MODEL
488 def_bool ARCH_SPARSEMEM_ENABLE
490 config HAVE_ARCH_PFN_VALID
491 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
493 config HW_PERF_EVENTS
494 bool "Enable hardware performance counter support for perf events"
495 depends on PERF_EVENTS
498 Enable hardware performance counter support for perf events. If
499 disabled, perf events will use software events only.
501 config SYS_SUPPORTS_HUGETLBFS
504 config ARCH_WANT_GENERAL_HUGETLB
507 config ARCH_WANT_HUGE_PMD_SHARE
508 def_bool y if !ARM64_64K_PAGES
510 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
513 config ARCH_HAS_CACHE_LINE_SIZE
519 bool "Enable seccomp to safely compute untrusted bytecode"
521 This kernel feature is useful for number crunching applications
522 that may need to compute untrusted bytecode during their
523 execution. By using pipes or other transports made available to
524 the process as file descriptors supporting the read/write
525 syscalls, it's possible to isolate those applications in
526 their own address space using seccomp. Once seccomp is
527 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
528 and the task is only allowed to execute a few safe syscalls
529 defined by each seccomp mode.
536 bool "Xen guest support on ARM64"
537 depends on ARM64 && OF
540 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
542 config FORCE_MAX_ZONEORDER
544 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
547 menuconfig ARMV8_DEPRECATED
548 bool "Emulate deprecated/obsolete ARMv8 instructions"
551 Legacy software support may require certain instructions
552 that have been deprecated or obsoleted in the architecture.
554 Enable this config to enable selective emulation of these
562 bool "Emulate SWP/SWPB instructions"
564 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
565 they are always undefined. Say Y here to enable software
566 emulation of these instructions for userspace using LDXR/STXR.
568 In some older versions of glibc [<=2.8] SWP is used during futex
569 trylock() operations with the assumption that the code will not
570 be preempted. This invalid assumption may be more likely to fail
571 with SWP emulation enabled, leading to deadlock of the user
574 NOTE: when accessing uncached shared regions, LDXR/STXR rely
575 on an external transaction monitoring block called a global
576 monitor to maintain update atomicity. If your system does not
577 implement a global monitor, this option can cause programs that
578 perform SWP operations to uncached memory to deadlock.
582 config CP15_BARRIER_EMULATION
583 bool "Emulate CP15 Barrier instructions"
585 The CP15 barrier instructions - CP15ISB, CP15DSB, and
586 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
587 strongly recommended to use the ISB, DSB, and DMB
588 instructions instead.
590 Say Y here to enable software emulation of these
591 instructions for AArch32 userspace code. When this option is
592 enabled, CP15 barrier usage is traced which can help
593 identify software that needs updating.
604 string "Default kernel command string"
607 Provide a set of default command-line options at build time by
608 entering them here. As a minimum, you should specify the the
609 root device (e.g. root=/dev/nfs).
612 bool "Always use the default kernel command string"
614 Always use the default kernel command string, even if the boot
615 loader passes other arguments to the kernel.
616 This is useful if you cannot or don't want to change the
617 command-line options your boot loader passes to the kernel.
623 bool "UEFI runtime support"
624 depends on OF && !CPU_BIG_ENDIAN
627 select EFI_PARAMS_FROM_FDT
628 select EFI_RUNTIME_WRAPPERS
633 This option provides support for runtime services provided
634 by UEFI firmware (such as non-volatile variables, realtime
635 clock, and platform reset). A UEFI stub is also provided to
636 allow the kernel to be booted as an EFI application. This
637 is only useful on systems that have UEFI firmware.
640 bool "Enable support for SMBIOS (DMI) tables"
644 This enables SMBIOS/DMI feature for systems.
646 This option is only useful on systems that have UEFI firmware.
647 However, even with this option, the resultant kernel should
648 continue to boot on existing non-UEFI platforms.
652 menu "Userspace binary formats"
654 source "fs/Kconfig.binfmt"
657 bool "Kernel support for 32-bit EL0"
658 depends on !ARM64_64K_PAGES
659 select COMPAT_BINFMT_ELF
661 select OLD_SIGSUSPEND3
662 select COMPAT_OLD_SIGACTION
664 This option enables support for a 32-bit EL0 running under a 64-bit
665 kernel at EL1. AArch32-specific components such as system calls,
666 the user helper functions, VFP support and the ptrace interface are
667 handled appropriately by the kernel.
669 If you want to execute 32-bit userspace applications, say Y.
671 config SYSVIPC_COMPAT
673 depends on COMPAT && SYSVIPC
677 menu "Power management options"
679 source "kernel/power/Kconfig"
681 config ARCH_SUSPEND_POSSIBLE
684 config ARM64_CPU_SUSPEND
689 menu "CPU Power Management"
691 source "drivers/cpuidle/Kconfig"
693 source "drivers/cpufreq/Kconfig"
699 source "drivers/Kconfig"
701 source "drivers/firmware/Kconfig"
705 source "arch/arm64/kvm/Kconfig"
707 source "arch/arm64/Kconfig.debug"
709 source "security/Kconfig"
711 source "crypto/Kconfig"
713 source "arch/arm64/crypto/Kconfig"