arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78 };
  79
  80 #ifdef CONFIG_ARCH_OMAP1
  81
  82 #define omap_dm_clk_enable(x)
  83 #define omap_dm_clk_disable(x)
  84
  85 static struct omap_dm_timer dm_timers[] = {
  86         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  87         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  88         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  89         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  90         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  91         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  92         { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
  93         { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
  94 };
  95
  96 #elif defined(CONFIG_ARCH_OMAP2)
  97
  98 #define omap_dm_clk_enable(x) clk_enable(x)
  99 #define omap_dm_clk_disable(x) clk_disable(x)
 100
 101 static struct omap_dm_timer dm_timers[] = {
 102         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
 103         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
 104         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
 105         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 106         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 107         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 108         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 109         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 110         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 111         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 112         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 113         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 114 };
 115
 116 static const char *dm_source_names[] = {
 117         "sys_ck",
 118         "func_32k_ck",
 119         "alt_ck"
 120 };
 121
 122 static struct clk *dm_source_clocks[3];
 123
 124 #else
 125
 126 #error OMAP architecture not supported!
 127
 128 #endif
 129
 130 static const int dm_timer_count = ARRAY_SIZE(dm_timers);
 131 static spinlock_t dm_timer_lock;
 132
 133 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 134 {
 135         return readl(timer->io_base + reg);
 136 }
 137
 138 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 139 {
 140         writel(value, timer->io_base + reg);
 141         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 142                 ;
 143 }
 144
 145 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 146 {
 147         int c;
 148
 149         c = 0;
 150         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 151                 c++;
 152                 if (c > 100000) {
 153                         printk(KERN_ERR "Timer failed to reset\n");
 154                         return;
 155                 }
 156         }
 157 }
 158
 159 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 160 {
 161         u32 l;
 162
 163         if (timer != &dm_timers[0]) {
 164                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 165                 omap_dm_timer_wait_for_reset(timer);
 166         }
 167         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
 168
 169         /* Set to smart-idle mode */
 170         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 171         l |= 0x02 << 3;
 172         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 173 }
 174
 175 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 176 {
 177         omap_dm_clk_enable(timer->fclk);
 178         omap_dm_clk_enable(timer->iclk);
 179
 180         omap_dm_timer_reset(timer);
 181
 182         /* Leave iclk enabled for GPT1 as it is needed for the
 183          * system timer to work properly. */
 184         if (timer != &dm_timers[0])
 185                 omap_dm_clk_disable(timer->iclk);
 186 }
 187
 188 struct omap_dm_timer *omap_dm_timer_request(void)
 189 {
 190         struct omap_dm_timer *timer = NULL;
 191         unsigned long flags;
 192         int i;
 193
 194         spin_lock_irqsave(&dm_timer_lock, flags);
 195         for (i = 0; i < dm_timer_count; i++) {
 196                 if (dm_timers[i].reserved)
 197                         continue;
 198
 199                 timer = &dm_timers[i];
 200                 timer->reserved = 1;
 201                 break;
 202         }
 203         spin_unlock_irqrestore(&dm_timer_lock, flags);
 204
 205         if (timer != NULL)
 206                 omap_dm_timer_prepare(timer);
 207
 208         return timer;
 209 }
 210
 211 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 212 {
 213         struct omap_dm_timer *timer;
 214         unsigned long flags;
 215
 216         spin_lock_irqsave(&dm_timer_lock, flags);
 217         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 218                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 219                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 220                        __FILE__, __LINE__, __FUNCTION__, id);
 221                 dump_stack();
 222                 return NULL;
 223         }
 224
 225         timer = &dm_timers[id-1];
 226         timer->reserved = 1;
 227         spin_unlock_irqrestore(&dm_timer_lock, flags);
 228
 229         omap_dm_timer_prepare(timer);
 230
 231         return timer;
 232 }
 233
 234 void omap_dm_timer_free(struct omap_dm_timer *timer)
 235 {
 236         omap_dm_clk_enable(timer->iclk);
 237         omap_dm_timer_reset(timer);
 238         omap_dm_clk_disable(timer->iclk);
 239
 240         if (timer == &dm_timers[0])
 241                 omap_dm_clk_disable(timer->iclk);
 242         omap_dm_clk_disable(timer->fclk);
 243
 244         WARN_ON(!timer->reserved);
 245         timer->reserved = 0;
 246 }
 247
 248 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 249 {
 250         return timer->irq;
 251 }
 252
 253 #if defined(CONFIG_ARCH_OMAP1)
 254
 255 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 256 {
 257         BUG();
 258 }
 259
 260 /**
 261  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 262  * @inputmask: current value of idlect mask
 263  */
 264 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 265 {
 266         int i;
 267
 268         /* If ARMXOR cannot be idled this function call is unnecessary */
 269         if (!(inputmask & (1 << 1)))
 270                 return inputmask;
 271
 272         /* If any active timer is using ARMXOR return modified mask */
 273         for (i = 0; i < dm_timer_count; i++) {
 274                 u32 l;
 275
 276                 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
 277                 if (l & OMAP_TIMER_CTRL_ST) {
 278                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 279                                 inputmask &= ~(1 << 1);
 280                         else
 281                                 inputmask &= ~(1 << 2);
 282                 }
 283         }
 284
 285         return inputmask;
 286 }
 287
 288 #elif defined(CONFIG_ARCH_OMAP2)
 289
 290 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 291 {
 292         return timer->fclk;
 293 }
 294
 295 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 296 {
 297         BUG();
 298 }
 299
 300 #endif
 301
 302 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 303 {
 304         omap_dm_clk_enable(timer->iclk);
 305         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 306         omap_dm_clk_disable(timer->iclk);
 307 }
 308
 309 void omap_dm_timer_start(struct omap_dm_timer *timer)
 310 {
 311         u32 l;
 312
 313         omap_dm_clk_enable(timer->iclk);
 314         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 315         if (!(l & OMAP_TIMER_CTRL_ST)) {
 316                 l |= OMAP_TIMER_CTRL_ST;
 317                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 318         }
 319         omap_dm_clk_disable(timer->iclk);
 320 }
 321
 322 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 323 {
 324         u32 l;
 325
 326         omap_dm_clk_enable(timer->iclk);
 327         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 328         if (l & OMAP_TIMER_CTRL_ST) {
 329                 l &= ~0x1;
 330                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 331         }
 332         omap_dm_clk_disable(timer->iclk);
 333 }
 334
 335 #ifdef CONFIG_ARCH_OMAP1
 336
 337 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 338 {
 339         int n = (timer - dm_timers) << 1;
 340         u32 l;
 341
 342         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 343         l |= source << n;
 344         omap_writel(l, MOD_CONF_CTRL_1);
 345 }
 346
 347 #else
 348
 349 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 350 {
 351         if (source < 0 || source >= 3)
 352                 return;
 353
 354         clk_disable(timer->fclk);
 355         clk_set_parent(timer->fclk, dm_source_clocks[source]);
 356         clk_enable(timer->fclk);
 357
 358         /* When the functional clock disappears, too quick writes seem to
 359          * cause an abort. */
 360         __delay(15000);
 361 }
 362
 363 #endif
 364
 365 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 366                             unsigned int load)
 367 {
 368         u32 l;
 369
 370         omap_dm_clk_enable(timer->iclk);
 371         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 372         if (autoreload)
 373                 l |= OMAP_TIMER_CTRL_AR;
 374         else
 375                 l &= ~OMAP_TIMER_CTRL_AR;
 376         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 377         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 378         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 379         omap_dm_clk_disable(timer->iclk);
 380 }
 381
 382 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 383                              unsigned int match)
 384 {
 385         u32 l;
 386
 387         omap_dm_clk_enable(timer->iclk);
 388         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 389         if (enable)
 390                 l |= OMAP_TIMER_CTRL_CE;
 391         else
 392                 l &= ~OMAP_TIMER_CTRL_CE;
 393         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 394         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 395         omap_dm_clk_disable(timer->iclk);
 396 }
 397
 398
 399 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 400                            int toggle, int trigger)
 401 {
 402         u32 l;
 403
 404         omap_dm_clk_enable(timer->iclk);
 405         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 406         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 407                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 408         if (def_on)
 409                 l |= OMAP_TIMER_CTRL_SCPWM;
 410         if (toggle)
 411                 l |= OMAP_TIMER_CTRL_PT;
 412         l |= trigger << 10;
 413         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 414         omap_dm_clk_disable(timer->iclk);
 415 }
 416
 417 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 418 {
 419         u32 l;
 420
 421         omap_dm_clk_enable(timer->iclk);
 422         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 423         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 424         if (prescaler >= 0x00 && prescaler <= 0x07) {
 425                 l |= OMAP_TIMER_CTRL_PRE;
 426                 l |= prescaler << 2;
 427         }
 428         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 429         omap_dm_clk_disable(timer->iclk);
 430 }
 431
 432 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 433                                   unsigned int value)
 434 {
 435         omap_dm_clk_enable(timer->iclk);
 436         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 437         omap_dm_clk_disable(timer->iclk);
 438 }
 439
 440 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 441 {
 442         unsigned int l;
 443
 444         omap_dm_clk_enable(timer->iclk);
 445         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 446         omap_dm_clk_disable(timer->iclk);
 447
 448         return l;
 449 }
 450
 451 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 452 {
 453         omap_dm_clk_enable(timer->iclk);
 454         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 455         omap_dm_clk_disable(timer->iclk);
 456 }
 457
 458 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 459 {
 460         unsigned int l;
 461
 462         omap_dm_clk_enable(timer->iclk);
 463         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 464         omap_dm_clk_disable(timer->iclk);
 465
 466         return l;
 467 }
 468
 469 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 470 {
 471         omap_dm_clk_enable(timer->iclk);
 472         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 473         omap_dm_clk_disable(timer->iclk);
 474 }
 475
 476 int omap_dm_timers_active(void)
 477 {
 478         int i;
 479
 480         for (i = 0; i < dm_timer_count; i++) {
 481                 struct omap_dm_timer *timer;
 482
 483                 timer = &dm_timers[i];
 484                 omap_dm_clk_enable(timer->iclk);
 485                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 486                     OMAP_TIMER_CTRL_ST) {
 487                         omap_dm_clk_disable(timer->iclk);
 488                         return 1;
 489                 }
 490                 omap_dm_clk_disable(timer->iclk);
 491         }
 492         return 0;
 493 }
 494
 495 int omap_dm_timer_init(void)
 496 {
 497         struct omap_dm_timer *timer;
 498         int i;
 499
 500         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 501                 return -ENODEV;
 502
 503         spin_lock_init(&dm_timer_lock);
 504 #ifdef CONFIG_ARCH_OMAP2
 505         for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
 506                 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
 507                 BUG_ON(dm_source_clocks[i] == NULL);
 508         }
 509 #endif
 510
 511         for (i = 0; i < dm_timer_count; i++) {
 512 #ifdef CONFIG_ARCH_OMAP2
 513                 char clk_name[16];
 514 #endif
 515
 516                 timer = &dm_timers[i];
 517                 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
 518 #ifdef CONFIG_ARCH_OMAP2
 519                 sprintf(clk_name, "gpt%d_ick", i + 1);
 520                 timer->iclk = clk_get(NULL, clk_name);
 521                 sprintf(clk_name, "gpt%d_fck", i + 1);
 522                 timer->fclk = clk_get(NULL, clk_name);
 523 #endif
 524         }
 525
 526         return 0;
 527 }