arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #ifdef CONFIG_SOC_BUS
  24 #include <linux/sys_soc.h>
  25 #endif
  26
  27 #include <asm/cputype.h>
  28
  29 #include "common.h"
  30
  31 #include "id.h"
  32
  33 #include "soc.h"
  34 #include "control.h"
  35
  36 #define OMAP4_SILICON_TYPE_STANDARD             0x01
  37 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
  38
  39 #define OMAP_SOC_MAX_NAME_LENGTH                16
  40
  41 static unsigned int omap_revision;
  42 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  43 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  44 u32 omap_features;
  45
  46 unsigned int omap_rev(void)
  47 {
  48         return omap_revision;
  49 }
  50 EXPORT_SYMBOL(omap_rev);
  51
  52 int omap_type(void)
  53 {
  54         u32 val = 0;
  55
  56         if (cpu_is_omap24xx()) {
  57                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  58         } else if (soc_is_am33xx() || soc_is_am43xx()) {
  59                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  60         } else if (cpu_is_omap34xx()) {
  61                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  62         } else if (cpu_is_omap44xx()) {
  63                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  64         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
  65                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  66                 val &= OMAP5_DEVICETYPE_MASK;
  67                 val >>= 6;
  68                 goto out;
  69         } else {
  70                 pr_err("Cannot detect omap type!\n");
  71                 goto out;
  72         }
  73
  74         val &= OMAP2_DEVICETYPE_MASK;
  75         val >>= 8;
  76
  77 out:
  78         return val;
  79 }
  80 EXPORT_SYMBOL(omap_type);
  81
  82
  83 /*----------------------------------------------------------------------------*/
  84
  85 #define OMAP_TAP_IDCODE         0x0204
  86 #define OMAP_TAP_DIE_ID_0       0x0218
  87 #define OMAP_TAP_DIE_ID_1       0x021C
  88 #define OMAP_TAP_DIE_ID_2       0x0220
  89 #define OMAP_TAP_DIE_ID_3       0x0224
  90
  91 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  92 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  93 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  94 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  95
  96 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  97
  98 struct omap_id {
  99         u16     hawkeye;        /* Silicon type (Hawkeye id) */
 100         u8      dev;            /* Device type from production_id reg */
 101         u32     type;           /* Combined type id copied to omap_revision */
 102 };
 103
 104 /* Register values to detect the OMAP version */
 105 static struct omap_id omap_ids[] __initdata = {
 106         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
 107         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
 108         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
 109         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
 110         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 111         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 112 };
 113
 114 static void __iomem *tap_base;
 115 static u16 tap_prod_id;
 116
 117 void omap_get_die_id(struct omap_die_id *odi)
 118 {
 119         if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
 120                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 121                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 122                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 123                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 124
 125                 return;
 126         }
 127         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 128         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 129         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 130         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 131 }
 132
 133 void __init omap2xxx_check_revision(void)
 134 {
 135         int i, j;
 136         u32 idcode, prod_id;
 137         u16 hawkeye;
 138         u8  dev_type, rev;
 139         struct omap_die_id odi;
 140
 141         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 142         prod_id = read_tap_reg(tap_prod_id);
 143         hawkeye = (idcode >> 12) & 0xffff;
 144         rev = (idcode >> 28) & 0x0f;
 145         dev_type = (prod_id >> 16) & 0x0f;
 146         omap_get_die_id(&odi);
 147
 148         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 149                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 150         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 151         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 152                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 153         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 154         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 155         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 156                  prod_id, dev_type);
 157
 158         /* Check hawkeye ids */
 159         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 160                 if (hawkeye == omap_ids[i].hawkeye)
 161                         break;
 162         }
 163
 164         if (i == ARRAY_SIZE(omap_ids)) {
 165                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 166                 return;
 167         }
 168
 169         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 170                 if (dev_type == omap_ids[j].dev)
 171                         break;
 172         }
 173
 174         if (j == ARRAY_SIZE(omap_ids)) {
 175                 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
 176                        omap_ids[i].type >> 16);
 177                 j = i;
 178         }
 179
 180         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 181         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 182
 183         pr_info("%s", soc_name);
 184         if ((omap_rev() >> 8) & 0x0f)
 185                 pr_info("%s", soc_rev);
 186         pr_info("\n");
 187 }
 188
 189 #define OMAP3_SHOW_FEATURE(feat)                \
 190         if (omap3_has_ ##feat())                \
 191                 printk(#feat" ");
 192
 193 static void __init omap3_cpuinfo(void)
 194 {
 195         const char *cpu_name;
 196
 197         /*
 198          * OMAP3430 and OMAP3530 are assumed to be same.
 199          *
 200          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 201          * on available features. Upon detection, update the CPU id
 202          * and CPU class bits.
 203          */
 204         if (cpu_is_omap3630()) {
 205                 cpu_name = "OMAP3630";
 206         } else if (soc_is_am35xx()) {
 207                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 208         } else if (cpu_is_ti816x()) {
 209                 cpu_name = "TI816X";
 210         } else if (soc_is_am335x()) {
 211                 cpu_name =  "AM335X";
 212         } else if (soc_is_am437x()) {
 213                 cpu_name =  "AM437x";
 214         } else if (cpu_is_ti814x()) {
 215                 cpu_name = "TI814X";
 216         } else if (omap3_has_iva() && omap3_has_sgx()) {
 217                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 218                 cpu_name = "OMAP3430/3530";
 219         } else if (omap3_has_iva()) {
 220                 cpu_name = "OMAP3525";
 221         } else if (omap3_has_sgx()) {
 222                 cpu_name = "OMAP3515";
 223         } else {
 224                 cpu_name = "OMAP3503";
 225         }
 226
 227         sprintf(soc_name, "%s", cpu_name);
 228
 229         /* Print verbose information */
 230         pr_info("%s %s (", soc_name, soc_rev);
 231
 232         OMAP3_SHOW_FEATURE(l2cache);
 233         OMAP3_SHOW_FEATURE(iva);
 234         OMAP3_SHOW_FEATURE(sgx);
 235         OMAP3_SHOW_FEATURE(neon);
 236         OMAP3_SHOW_FEATURE(isp);
 237         OMAP3_SHOW_FEATURE(192mhz_clk);
 238
 239         printk(")\n");
 240 }
 241
 242 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 243         if (((status & OMAP3_ ##feat## _MASK)                           \
 244                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 245                 omap_features |= OMAP3_HAS_ ##feat;                     \
 246         }
 247
 248 void __init omap3xxx_check_features(void)
 249 {
 250         u32 status;
 251
 252         omap_features = 0;
 253
 254         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 255
 256         OMAP3_CHECK_FEATURE(status, L2CACHE);
 257         OMAP3_CHECK_FEATURE(status, IVA);
 258         OMAP3_CHECK_FEATURE(status, SGX);
 259         OMAP3_CHECK_FEATURE(status, NEON);
 260         OMAP3_CHECK_FEATURE(status, ISP);
 261         if (cpu_is_omap3630())
 262                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 263         if (cpu_is_omap3430() || cpu_is_omap3630())
 264                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 265         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 266             omap_rev() == OMAP3430_REV_ES3_1_2)
 267                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 268
 269         omap_features |= OMAP3_HAS_SDRC;
 270
 271         /*
 272          * am35x fixups:
 273          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
 274          *   reserved and therefore return 0 when read.  Unfortunately,
 275          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
 276          *   mean that a feature is present even though it isn't so clear
 277          *   the incorrectly set feature bits.
 278          */
 279         if (soc_is_am35xx())
 280                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
 281
 282         /*
 283          * TODO: Get additional info (where applicable)
 284          *       e.g. Size of L2 cache.
 285          */
 286
 287         omap3_cpuinfo();
 288 }
 289
 290 void __init omap4xxx_check_features(void)
 291 {
 292         u32 si_type;
 293
 294         si_type =
 295         (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
 296
 297         if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
 298                 omap_features = OMAP4_HAS_PERF_SILICON;
 299 }
 300
 301 void __init ti81xx_check_features(void)
 302 {
 303         omap_features = OMAP3_HAS_NEON;
 304         omap3_cpuinfo();
 305 }
 306
 307 void __init am33xx_check_features(void)
 308 {
 309         u32 status;
 310
 311         omap_features = OMAP3_HAS_NEON;
 312
 313         status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
 314         if (status & AM33XX_SGX_MASK)
 315                 omap_features |= OMAP3_HAS_SGX;
 316
 317         omap3_cpuinfo();
 318 }
 319
 320 void __init omap3xxx_check_revision(void)
 321 {
 322         const char *cpu_rev;
 323         u32 cpuid, idcode;
 324         u16 hawkeye;
 325         u8 rev;
 326
 327         /*
 328          * We cannot access revision registers on ES1.0.
 329          * If the processor type is Cortex-A8 and the revision is 0x0
 330          * it means its Cortex r0p0 which is 3430 ES1.0.
 331          */
 332         cpuid = read_cpuid_id();
 333         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 334                 omap_revision = OMAP3430_REV_ES1_0;
 335                 cpu_rev = "1.0";
 336                 return;
 337         }
 338
 339         /*
 340          * Detection for 34xx ES2.0 and above can be done with just
 341          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 342          * Note that rev does not map directly to our defined processor
 343          * revision numbers as ES1.0 uses value 0.
 344          */
 345         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 346         hawkeye = (idcode >> 12) & 0xffff;
 347         rev = (idcode >> 28) & 0xff;
 348
 349         switch (hawkeye) {
 350         case 0xb7ae:
 351                 /* Handle 34xx/35xx devices */
 352                 switch (rev) {
 353                 case 0: /* Take care of early samples */
 354                 case 1:
 355                         omap_revision = OMAP3430_REV_ES2_0;
 356                         cpu_rev = "2.0";
 357                         break;
 358                 case 2:
 359                         omap_revision = OMAP3430_REV_ES2_1;
 360                         cpu_rev = "2.1";
 361                         break;
 362                 case 3:
 363                         omap_revision = OMAP3430_REV_ES3_0;
 364                         cpu_rev = "3.0";
 365                         break;
 366                 case 4:
 367                         omap_revision = OMAP3430_REV_ES3_1;
 368                         cpu_rev = "3.1";
 369                         break;
 370                 case 7:
 371                 /* FALLTHROUGH */
 372                 default:
 373                         /* Use the latest known revision as default */
 374                         omap_revision = OMAP3430_REV_ES3_1_2;
 375                         cpu_rev = "3.1.2";
 376                 }
 377                 break;
 378         case 0xb868:
 379                 /*
 380                  * Handle OMAP/AM 3505/3517 devices
 381                  *
 382                  * Set the device to be OMAP3517 here. Actual device
 383                  * is identified later based on the features.
 384                  */
 385                 switch (rev) {
 386                 case 0:
 387                         omap_revision = AM35XX_REV_ES1_0;
 388                         cpu_rev = "1.0";
 389                         break;
 390                 case 1:
 391                 /* FALLTHROUGH */
 392                 default:
 393                         omap_revision = AM35XX_REV_ES1_1;
 394                         cpu_rev = "1.1";
 395                 }
 396                 break;
 397         case 0xb891:
 398                 /* Handle 36xx devices */
 399
 400                 switch(rev) {
 401                 case 0: /* Take care of early samples */
 402                         omap_revision = OMAP3630_REV_ES1_0;
 403                         cpu_rev = "1.0";
 404                         break;
 405                 case 1:
 406                         omap_revision = OMAP3630_REV_ES1_1;
 407                         cpu_rev = "1.1";
 408                         break;
 409                 case 2:
 410                 /* FALLTHROUGH */
 411                 default:
 412                         omap_revision = OMAP3630_REV_ES1_2;
 413                         cpu_rev = "1.2";
 414                 }
 415                 break;
 416         case 0xb81e:
 417                 switch (rev) {
 418                 case 0:
 419                         omap_revision = TI8168_REV_ES1_0;
 420                         cpu_rev = "1.0";
 421                         break;
 422                 case 1:
 423                         omap_revision = TI8168_REV_ES1_1;
 424                         cpu_rev = "1.1";
 425                         break;
 426                 case 2:
 427                         omap_revision = TI8168_REV_ES2_0;
 428                         cpu_rev = "2.0";
 429                         break;
 430                 case 3:
 431                         /* FALLTHROUGH */
 432                 default:
 433                         omap_revision = TI8168_REV_ES2_1;
 434                         cpu_rev = "2.1";
 435                 }
 436                 break;
 437         case 0xb944:
 438                 switch (rev) {
 439                 case 0:
 440                         omap_revision = AM335X_REV_ES1_0;
 441                         cpu_rev = "1.0";
 442                         break;
 443                 case 1:
 444                         omap_revision = AM335X_REV_ES2_0;
 445                         cpu_rev = "2.0";
 446                         break;
 447                 case 2:
 448                 /* FALLTHROUGH */
 449                 default:
 450                         omap_revision = AM335X_REV_ES2_1;
 451                         cpu_rev = "2.1";
 452                         break;
 453                 }
 454                 break;
 455         case 0xb98c:
 456                 omap_revision = AM437X_REV_ES1_0;
 457                 cpu_rev = "1.0";
 458                 break;
 459         case 0xb8f2:
 460                 switch (rev) {
 461                 case 0:
 462                 /* FALLTHROUGH */
 463                 case 1:
 464                         omap_revision = TI8148_REV_ES1_0;
 465                         cpu_rev = "1.0";
 466                         break;
 467                 case 2:
 468                         omap_revision = TI8148_REV_ES2_0;
 469                         cpu_rev = "2.0";
 470                         break;
 471                 case 3:
 472                 /* FALLTHROUGH */
 473                 default:
 474                         omap_revision = TI8148_REV_ES2_1;
 475                         cpu_rev = "2.1";
 476                         break;
 477                 }
 478                 break;
 479         default:
 480                 /* Unknown default to latest silicon rev as default */
 481                 omap_revision = OMAP3630_REV_ES1_2;
 482                 cpu_rev = "1.2";
 483                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 484         }
 485         sprintf(soc_rev, "ES%s", cpu_rev);
 486 }
 487
 488 void __init omap4xxx_check_revision(void)
 489 {
 490         u32 idcode;
 491         u16 hawkeye;
 492         u8 rev;
 493
 494         /*
 495          * The IC rev detection is done with hawkeye and rev.
 496          * Note that rev does not map directly to defined processor
 497          * revision numbers as ES1.0 uses value 0.
 498          */
 499         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 500         hawkeye = (idcode >> 12) & 0xffff;
 501         rev = (idcode >> 28) & 0xf;
 502
 503         /*
 504          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 505          * Use ARM register to detect the correct ES version
 506          */
 507         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 508                 idcode = read_cpuid_id();
 509                 rev = (idcode & 0xf) - 1;
 510         }
 511
 512         switch (hawkeye) {
 513         case 0xb852:
 514                 switch (rev) {
 515                 case 0:
 516                         omap_revision = OMAP4430_REV_ES1_0;
 517                         break;
 518                 case 1:
 519                 default:
 520                         omap_revision = OMAP4430_REV_ES2_0;
 521                 }
 522                 break;
 523         case 0xb95c:
 524                 switch (rev) {
 525                 case 3:
 526                         omap_revision = OMAP4430_REV_ES2_1;
 527                         break;
 528                 case 4:
 529                         omap_revision = OMAP4430_REV_ES2_2;
 530                         break;
 531                 case 6:
 532                 default:
 533                         omap_revision = OMAP4430_REV_ES2_3;
 534                 }
 535                 break;
 536         case 0xb94e:
 537                 switch (rev) {
 538                 case 0:
 539                         omap_revision = OMAP4460_REV_ES1_0;
 540                         break;
 541                 case 2:
 542                 default:
 543                         omap_revision = OMAP4460_REV_ES1_1;
 544                         break;
 545                 }
 546                 break;
 547         case 0xb975:
 548                 switch (rev) {
 549                 case 0:
 550                 default:
 551                         omap_revision = OMAP4470_REV_ES1_0;
 552                         break;
 553                 }
 554                 break;
 555         default:
 556                 /* Unknown default to latest silicon rev as default */
 557                 omap_revision = OMAP4430_REV_ES2_3;
 558         }
 559
 560         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 561         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 562                                                 (omap_rev() >> 8) & 0xf);
 563         pr_info("%s %s\n", soc_name, soc_rev);
 564 }
 565
 566 void __init omap5xxx_check_revision(void)
 567 {
 568         u32 idcode;
 569         u16 hawkeye;
 570         u8 rev;
 571
 572         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 573         hawkeye = (idcode >> 12) & 0xffff;
 574         rev = (idcode >> 28) & 0xff;
 575         switch (hawkeye) {
 576         case 0xb942:
 577                 switch (rev) {
 578                 case 0:
 579                         omap_revision = OMAP5430_REV_ES1_0;
 580                         break;
 581                 case 1:
 582                 default:
 583                         omap_revision = OMAP5430_REV_ES2_0;
 584                 }
 585                 break;
 586
 587         case 0xb998:
 588                 switch (rev) {
 589                 case 0:
 590                         omap_revision = OMAP5432_REV_ES1_0;
 591                         break;
 592                 case 1:
 593                 default:
 594                         omap_revision = OMAP5432_REV_ES2_0;
 595                 }
 596                 break;
 597
 598         default:
 599                 /* Unknown default to latest silicon rev as default*/
 600                 omap_revision = OMAP5430_REV_ES2_0;
 601         }
 602
 603         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 604         sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
 605
 606         pr_info("%s %s\n", soc_name, soc_rev);
 607 }
 608
 609 /*
 610  * Set up things for map_io and processor detection later on. Gets called
 611  * pretty much first thing from board init. For multi-omap, this gets
 612  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 613  * detect the exact revision later on in omap2_detect_revision() once map_io
 614  * is done.
 615  */
 616 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 617 {
 618         omap_revision = class;
 619         tap_base = tap;
 620
 621         /* XXX What is this intended to do? */
 622         if (cpu_is_omap34xx())
 623                 tap_prod_id = 0x0210;
 624         else
 625                 tap_prod_id = 0x0208;
 626 }
 627
 628 #ifdef CONFIG_SOC_BUS
 629
 630 static const char * const omap_types[] = {
 631         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
 632         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
 633         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
 634         [OMAP2_DEVICE_TYPE_GP]          = "GP",
 635         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
 636 };
 637
 638 static const char * __init omap_get_family(void)
 639 {
 640         if (cpu_is_omap24xx())
 641                 return kasprintf(GFP_KERNEL, "OMAP2");
 642         else if (cpu_is_omap34xx())
 643                 return kasprintf(GFP_KERNEL, "OMAP3");
 644         else if (cpu_is_omap44xx())
 645                 return kasprintf(GFP_KERNEL, "OMAP4");
 646         else if (soc_is_omap54xx())
 647                 return kasprintf(GFP_KERNEL, "OMAP5");
 648         else
 649                 return kasprintf(GFP_KERNEL, "Unknown");
 650 }
 651
 652 static ssize_t omap_get_type(struct device *dev,
 653                                         struct device_attribute *attr,
 654                                         char *buf)
 655 {
 656         return sprintf(buf, "%s\n", omap_types[omap_type()]);
 657 }
 658
 659 static struct device_attribute omap_soc_attr =
 660         __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
 661
 662 void __init omap_soc_device_init(void)
 663 {
 664         struct device *parent;
 665         struct soc_device *soc_dev;
 666         struct soc_device_attribute *soc_dev_attr;
 667
 668         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 669         if (!soc_dev_attr)
 670                 return;
 671
 672         soc_dev_attr->machine  = soc_name;
 673         soc_dev_attr->family   = omap_get_family();
 674         soc_dev_attr->revision = soc_rev;
 675
 676         soc_dev = soc_device_register(soc_dev_attr);
 677         if (IS_ERR(soc_dev)) {
 678                 kfree(soc_dev_attr);
 679                 return;
 680         }
 681
 682         parent = soc_device_to_device(soc_dev);
 683         device_create_file(parent, &omap_soc_attr);
 684 }
 685 #endif /* CONFIG_SOC_BUS */