arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         model = "Qualcomm APQ8064";
  12         compatible = "qcom,apq8064";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,krait";
  21                         enable-method = "qcom,kpss-acc-v1";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                         cpu-idle-states = <&CPU_SPC>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu@2 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <2>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc2>;
  48                         qcom,saw = <&saw2>;
  49                         cpu-idle-states = <&CPU_SPC>;
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "qcom,krait";
  54                         enable-method = "qcom,kpss-acc-v1";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                         next-level-cache = <&L2>;
  58                         qcom,acc = <&acc3>;
  59                         qcom,saw = <&saw3>;
  60                         cpu-idle-states = <&CPU_SPC>;
  61                 };
  62
  63                 L2: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <2>;
  66                 };
  67
  68                 idle-states {
  69                         CPU_SPC: spc {
  70                                 compatible = "qcom,idle-state-spc",
  71                                                 "arm,idle-state";
  72                                 entry-latency-us = <400>;
  73                                 exit-latency-us = <900>;
  74                                 min-residency-us = <3000>;
  75                         };
  76                 };
  77         };
  78
  79         cpu-pmu {
  80                 compatible = "qcom,krait-pmu";
  81                 interrupts = <1 10 0x304>;
  82         };
  83
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 compatible = "simple-bus";
  89
  90                 tlmm_pinmux: pinctrl@800000 {
  91                         compatible = "qcom,apq8064-pinctrl";
  92                         reg = <0x800000 0x4000>;
  93
  94                         gpio-controller;
  95                         #gpio-cells = <2>;
  96                         interrupt-controller;
  97                         #interrupt-cells = <2>;
  98                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  99
 100                         pinctrl-names = "default";
 101                         pinctrl-0 = <&ps_hold>;
 102
 103                         sdc4_gpios: sdc4-gpios {
 104                                 pios {
 105                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 106                                         function = "sdc4";
 107                                 };
 108                         };
 109
 110                         ps_hold: ps_hold {
 111                                 mux {
 112                                         pins = "gpio78";
 113                                         function = "ps_hold";
 114                                 };
 115                         };
 116
 117                         i2c1_pins: i2c1 {
 118                                 mux {
 119                                         pins = "gpio20", "gpio21";
 120                                         function = "gsbi1";
 121                                 };
 122                         };
 123
 124                         i2c3_pins: i2c3 {
 125                                 mux {
 126                                         pins = "gpio8", "gpio9";
 127                                         function = "gsbi3";
 128                                 };
 129                         };
 130                 };
 131
 132                 intc: interrupt-controller@2000000 {
 133                         compatible = "qcom,msm-qgic2";
 134                         interrupt-controller;
 135                         #interrupt-cells = <3>;
 136                         reg = <0x02000000 0x1000>,
 137                               <0x02002000 0x1000>;
 138                 };
 139
 140                 timer@200a000 {
 141                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 142                         interrupts = <1 1 0x301>,
 143                                      <1 2 0x301>,
 144                                      <1 3 0x301>;
 145                         reg = <0x0200a000 0x100>;
 146                         clock-frequency = <27000000>,
 147                                           <32768>;
 148                         cpu-offset = <0x80000>;
 149                 };
 150
 151                 acc0: clock-controller@2088000 {
 152                         compatible = "qcom,kpss-acc-v1";
 153                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 154                 };
 155
 156                 acc1: clock-controller@2098000 {
 157                         compatible = "qcom,kpss-acc-v1";
 158                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 159                 };
 160
 161                 acc2: clock-controller@20a8000 {
 162                         compatible = "qcom,kpss-acc-v1";
 163                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 164                 };
 165
 166                 acc3: clock-controller@20b8000 {
 167                         compatible = "qcom,kpss-acc-v1";
 168                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 169                 };
 170
 171                 saw0: power-controller@2089000 {
 172                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 173                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 174                         regulator;
 175                 };
 176
 177                 saw1: power-controller@2099000 {
 178                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 179                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 180                         regulator;
 181                 };
 182
 183                 saw2: power-controller@20a9000 {
 184                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 185                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 186                         regulator;
 187                 };
 188
 189                 saw3: power-controller@20b9000 {
 190                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 191                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 192                         regulator;
 193                 };
 194
 195                 gsbi1: gsbi@12440000 {
 196                         status = "disabled";
 197                         compatible = "qcom,gsbi-v1.0.0";
 198                         cell-index = <1>;
 199                         reg = <0x12440000 0x100>;
 200                         clocks = <&gcc GSBI1_H_CLK>;
 201                         clock-names = "iface";
 202                         #address-cells = <1>;
 203                         #size-cells = <1>;
 204                         ranges;
 205
 206                         syscon-tcsr = <&tcsr>;
 207
 208                         i2c1: i2c@12460000 {
 209                                 compatible = "qcom,i2c-qup-v1.1.1";
 210                                 reg = <0x12460000 0x1000>;
 211                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 212                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 213                                 clock-names = "core", "iface";
 214                                 #address-cells = <1>;
 215                                 #size-cells = <0>;
 216                         };
 217                 };
 218
 219                 gsbi2: gsbi@12480000 {
 220                         status = "disabled";
 221                         compatible = "qcom,gsbi-v1.0.0";
 222                         cell-index = <2>;
 223                         reg = <0x12480000 0x100>;
 224                         clocks = <&gcc GSBI2_H_CLK>;
 225                         clock-names = "iface";
 226                         #address-cells = <1>;
 227                         #size-cells = <1>;
 228                         ranges;
 229
 230                         syscon-tcsr = <&tcsr>;
 231
 232                         i2c2: i2c@124a0000 {
 233                                 compatible = "qcom,i2c-qup-v1.1.1";
 234                                 reg = <0x124a0000 0x1000>;
 235                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 236                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 237                                 clock-names = "core", "iface";
 238                                 #address-cells = <1>;
 239                                 #size-cells = <0>;
 240                         };
 241                 };
 242
 243                 gsbi3: gsbi@16200000 {
 244                         status = "disabled";
 245                         compatible = "qcom,gsbi-v1.0.0";
 246                         reg = <0x16200000 0x100>;
 247                         clocks = <&gcc GSBI3_H_CLK>;
 248                         clock-names = "iface";
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         ranges;
 252
 253                         i2c3: i2c@16280000 {
 254                                 compatible = "qcom,i2c-qup-v1.1.1";
 255                                 reg = <0x16280000 0x1000>;
 256                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 257                                 clocks = <&gcc GSBI3_QUP_CLK>,
 258                                          <&gcc GSBI3_H_CLK>;
 259                                 clock-names = "core", "iface";
 260                         };
 261                 };
 262
 263                 gsbi7: gsbi@16600000 {
 264                         status = "disabled";
 265                         compatible = "qcom,gsbi-v1.0.0";
 266                         cell-index = <7>;
 267                         reg = <0x16600000 0x100>;
 268                         clocks = <&gcc GSBI7_H_CLK>;
 269                         clock-names = "iface";
 270                         #address-cells = <1>;
 271                         #size-cells = <1>;
 272                         ranges;
 273                         syscon-tcsr = <&tcsr>;
 274
 275                         gsbi7_serial: serial@16640000 {
 276                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 277                                 reg = <0x16640000 0x1000>,
 278                                       <0x16600000 0x1000>;
 279                                 interrupts = <0 158 0x0>;
 280                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 281                                 clock-names = "core", "iface";
 282                                 status = "disabled";
 283                         };
 284                 };
 285
 286                 qcom,ssbi@500000 {
 287                         compatible = "qcom,ssbi";
 288                         reg = <0x00500000 0x1000>;
 289                         qcom,controller-type = "pmic-arbiter";
 290                 };
 291
 292                 gcc: clock-controller@900000 {
 293                         compatible = "qcom,gcc-apq8064";
 294                         reg = <0x00900000 0x4000>;
 295                         #clock-cells = <1>;
 296                         #reset-cells = <1>;
 297                 };
 298
 299                 lcc: clock-controller@28000000 {
 300                         compatible = "qcom,lcc-apq8064";
 301                         reg = <0x28000000 0x1000>;
 302                         #clock-cells = <1>;
 303                         #reset-cells = <1>;
 304                 };
 305
 306                 mmcc: clock-controller@4000000 {
 307                         compatible = "qcom,mmcc-apq8064";
 308                         reg = <0x4000000 0x1000>;
 309                         #clock-cells = <1>;
 310                         #reset-cells = <1>;
 311                 };
 312
 313                 l2cc: clock-controller@2011000 {
 314                         compatible      = "syscon";
 315                         reg             = <0x2011000 0x1000>;
 316                 };
 317
 318                 rpm@108000 {
 319                         compatible      = "qcom,rpm-apq8064";
 320                         reg             = <0x108000 0x1000>;
 321                         qcom,ipc        = <&l2cc 0x8 2>;
 322
 323                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 324                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 325                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 326                         interrupt-names = "ack", "err", "wakeup";
 327
 328                         regulators {
 329                                 compatible = "qcom,rpm-pm8921-regulators";
 330
 331                                 pm8921_hdmi_switch: hdmi-switch {
 332                                         bias-pull-down;
 333                                 };
 334                         };
 335                 };
 336
 337                 usb1_phy: phy@12500000 {
 338                         compatible      = "qcom,usb-otg-ci";
 339                         reg             = <0x12500000 0x400>;
 340                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 341                         status          = "disabled";
 342                         dr_mode         = "host";
 343
 344                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 345                                           <&gcc USB_HS1_H_CLK>;
 346                         clock-names     = "core", "iface";
 347
 348                         resets          = <&gcc USB_HS1_RESET>;
 349                         reset-names     = "link";
 350                 };
 351
 352                 usb3_phy: phy@12520000 {
 353                         compatible      = "qcom,usb-otg-ci";
 354                         reg             = <0x12520000 0x400>;
 355                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 356                         status          = "disabled";
 357                         dr_mode         = "host";
 358
 359                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 360                                           <&gcc USB_HS3_H_CLK>;
 361                         clock-names     = "core", "iface";
 362
 363                         resets          = <&gcc USB_HS3_RESET>;
 364                         reset-names     = "link";
 365                 };
 366
 367                 usb4_phy: phy@12530000 {
 368                         compatible      = "qcom,usb-otg-ci";
 369                         reg             = <0x12530000 0x400>;
 370                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 371                         status          = "disabled";
 372                         dr_mode         = "host";
 373
 374                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 375                                           <&gcc USB_HS4_H_CLK>;
 376                         clock-names     = "core", "iface";
 377
 378                         resets          = <&gcc USB_HS4_RESET>;
 379                         reset-names     = "link";
 380                 };
 381
 382                 gadget1: gadget@12500000 {
 383                         compatible      = "qcom,ci-hdrc";
 384                         reg             = <0x12500000 0x400>;
 385                         status          = "disabled";
 386                         dr_mode         = "peripheral";
 387                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 388                         usb-phy         = <&usb1_phy>;
 389                 };
 390
 391                 usb1: usb@12500000 {
 392                         compatible      = "qcom,ehci-host";
 393                         reg             = <0x12500000 0x400>;
 394                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 395                         status          = "disabled";
 396                         usb-phy         = <&usb1_phy>;
 397                 };
 398
 399                 usb3: usb@12520000 {
 400                         compatible      = "qcom,ehci-host";
 401                         reg             = <0x12520000 0x400>;
 402                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 403                         status          = "disabled";
 404                         usb-phy         = <&usb3_phy>;
 405                 };
 406
 407                 usb4: usb@12530000 {
 408                         compatible      = "qcom,ehci-host";
 409                         reg             = <0x12530000 0x400>;
 410                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 411                         status          = "disabled";
 412                         usb-phy         = <&usb4_phy>;
 413                 };
 414
 415                 sata_phy0: phy@1b400000 {
 416                         compatible      = "qcom,apq8064-sata-phy";
 417                         status          = "disabled";
 418                         reg             = <0x1b400000 0x200>;
 419                         reg-names       = "phy_mem";
 420                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 421                         clock-names     = "cfg";
 422                         #phy-cells      = <0>;
 423                 };
 424
 425                 sata0: sata@29000000 {
 426                         compatible              = "generic-ahci";
 427                         status                  = "disabled";
 428                         reg                     = <0x29000000 0x180>;
 429                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 430
 431                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 432                                                 <&gcc SATA_H_CLK>,
 433                                                 <&gcc SATA_A_CLK>,
 434                                                 <&gcc SATA_RXOOB_CLK>,
 435                                                 <&gcc SATA_PMALIVE_CLK>;
 436                         clock-names             = "slave_iface",
 437                                                 "iface",
 438                                                 "bus",
 439                                                 "rxoob",
 440                                                 "core_pmalive";
 441
 442                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 443                                                 <&gcc SATA_PMALIVE_CLK>;
 444                         assigned-clock-rates    = <100000000>, <100000000>;
 445
 446                         phys                    = <&sata_phy0>;
 447                         phy-names               = "sata-phy";
 448                 };
 449
 450                 /* Temporary fixed regulator */
 451                 vsdcc_fixed: vsdcc-regulator {
 452                         compatible = "regulator-fixed";
 453                         regulator-name = "SDCC Power";
 454                         regulator-min-microvolt = <2700000>;
 455                         regulator-max-microvolt = <2700000>;
 456                         regulator-always-on;
 457                 };
 458
 459                 sdcc1bam:dma@12402000{
 460                         compatible = "qcom,bam-v1.3.0";
 461                         reg = <0x12402000 0x8000>;
 462                         interrupts = <0 98 0>;
 463                         clocks = <&gcc SDC1_H_CLK>;
 464                         clock-names = "bam_clk";
 465                         #dma-cells = <1>;
 466                         qcom,ee = <0>;
 467                 };
 468
 469                 sdcc3bam:dma@12182000{
 470                         compatible = "qcom,bam-v1.3.0";
 471                         reg = <0x12182000 0x8000>;
 472                         interrupts = <0 96 0>;
 473                         clocks = <&gcc SDC3_H_CLK>;
 474                         clock-names = "bam_clk";
 475                         #dma-cells = <1>;
 476                         qcom,ee = <0>;
 477                 };
 478
 479                 sdcc4bam:dma@121c2000{
 480                         compatible = "qcom,bam-v1.3.0";
 481                         reg = <0x121c2000 0x8000>;
 482                         interrupts = <0 95 0>;
 483                         clocks = <&gcc SDC4_H_CLK>;
 484                         clock-names = "bam_clk";
 485                         #dma-cells = <1>;
 486                         qcom,ee = <0>;
 487                 };
 488
 489                 amba {
 490                         compatible = "arm,amba-bus";
 491                         #address-cells = <1>;
 492                         #size-cells = <1>;
 493                         ranges;
 494                         sdcc1: sdcc@12400000 {
 495                                 status          = "disabled";
 496                                 compatible      = "arm,pl18x", "arm,primecell";
 497                                 arm,primecell-periphid = <0x00051180>;
 498                                 reg             = <0x12400000 0x2000>;
 499                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 500                                 interrupt-names = "cmd_irq";
 501                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 502                                 clock-names     = "mclk", "apb_pclk";
 503                                 bus-width       = <8>;
 504                                 max-frequency   = <96000000>;
 505                                 non-removable;
 506                                 cap-sd-highspeed;
 507                                 cap-mmc-highspeed;
 508                                 vmmc-supply = <&vsdcc_fixed>;
 509                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 510                                 dma-names = "tx", "rx";
 511                         };
 512
 513                         sdcc3: sdcc@12180000 {
 514                                 compatible      = "arm,pl18x", "arm,primecell";
 515                                 arm,primecell-periphid = <0x00051180>;
 516                                 status          = "disabled";
 517                                 reg             = <0x12180000 0x2000>;
 518                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 519                                 interrupt-names = "cmd_irq";
 520                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 521                                 clock-names     = "mclk", "apb_pclk";
 522                                 bus-width       = <4>;
 523                                 cap-sd-highspeed;
 524                                 cap-mmc-highspeed;
 525                                 max-frequency   = <192000000>;
 526                                 no-1-8-v;
 527                                 vmmc-supply = <&vsdcc_fixed>;
 528                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 529                                 dma-names = "tx", "rx";
 530                         };
 531
 532                         sdcc4: sdcc@121c0000 {
 533                                 compatible      = "arm,pl18x", "arm,primecell";
 534                                 arm,primecell-periphid = <0x00051180>;
 535                                 status          = "disabled";
 536                                 reg             = <0x121c0000 0x2000>;
 537                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 538                                 interrupt-names = "cmd_irq";
 539                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 540                                 clock-names     = "mclk", "apb_pclk";
 541                                 bus-width       = <4>;
 542                                 cap-sd-highspeed;
 543                                 cap-mmc-highspeed;
 544                                 max-frequency   = <48000000>;
 545                                 vmmc-supply = <&vsdcc_fixed>;
 546                                 vqmmc-supply = <&vsdcc_fixed>;
 547                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 548                                 dma-names = "tx", "rx";
 549                                 pinctrl-names = "default";
 550                                 pinctrl-0 = <&sdc4_gpios>;
 551                         };
 552                 };
 553
 554                 tcsr: syscon@1a400000 {
 555                         compatible = "qcom,tcsr-apq8064", "syscon";
 556                         reg = <0x1a400000 0x100>;
 557                 };
 558         };
 559 };