arch/arm/boot/dts/mt8135.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Joe.C <yingjoe.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include "skeleton64.dtsi"
  18 #include "mt8135-pinfunc.h"
  19
  20 / {
  21         compatible = "mediatek,mt8135";
  22         interrupt-parent = <&sysirq>;
  23
  24         cpu-map {
  25                 cluster0 {
  26                         core0 {
  27                                 cpu = <&cpu0>;
  28                         };
  29                         core1 {
  30                                 cpu = <&cpu1>;
  31                         };
  32                 };
  33
  34                 cluster1 {
  35                         core0 {
  36                                 cpu = <&cpu2>;
  37                         };
  38                         core1 {
  39                                 cpu = <&cpu3>;
  40                         };
  41                 };
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0x000>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0x001>;
  58                 };
  59
  60                 cpu2: cpu@100 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0x100>;
  64                 };
  65
  66                 cpu3: cpu@101 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x101>;
  70                 };
  71         };
  72
  73         clocks {
  74                 #address-cells = <2>;
  75                 #size-cells = <2>;
  76                 compatible = "simple-bus";
  77                 ranges;
  78
  79                 system_clk: dummy13m {
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <13000000>;
  82                         #clock-cells = <0>;
  83                 };
  84
  85                 rtc_clk: dummy32k {
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <32000>;
  88                         #clock-cells = <0>;
  89                 };
  90
  91                 uart_clk: dummy26m {
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <26000000>;
  94                         #clock-cells = <0>;
  95                 };
  96
  97         };
  98
  99         soc {
 100                 #address-cells = <2>;
 101                 #size-cells = <2>;
 102                 compatible = "simple-bus";
 103                 ranges;
 104
 105                 /*
 106                  * Pinctrl access register at 0x10005000 and 0x1020c000 through
 107                  * regmap. Register 0x1000b000 is used by EINT.
 108                  */
 109                 pio: pinctrl@10005000 {
 110                         compatible = "mediatek,mt8135-pinctrl";
 111                         reg = <0 0x1000b000 0 0x1000>;
 112                         mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
 113                         pins-are-numbered;
 114                         gpio-controller;
 115                         #gpio-cells = <2>;
 116                         interrupt-controller;
 117                         #interrupt-cells = <2>;
 118                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 121                 };
 122
 123                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 124                         compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 125                         reg = <0 0x10005000 0 0x1000>;
 126                 };
 127
 128                 timer: timer@10008000 {
 129                         compatible = "mediatek,mt8135-timer",
 130                                         "mediatek,mt6577-timer";
 131                         reg = <0 0x10008000 0 0x80>;
 132                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
 133                         clocks = <&system_clk>, <&rtc_clk>;
 134                         clock-names = "system-clk", "rtc-clk";
 135                 };
 136
 137                 sysirq: interrupt-controller@10200030 {
 138                         compatible = "mediatek,mt8135-sysirq",
 139                                      "mediatek,mt6577-sysirq";
 140                         interrupt-controller;
 141                         #interrupt-cells = <3>;
 142                         interrupt-parent = <&gic>;
 143                         reg = <0 0x10200030 0 0x1c>;
 144                 };
 145
 146                 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
 147                         compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 148                         reg = <0 0x1020c000 0 0x1000>;
 149                 };
 150
 151                 gic: interrupt-controller@10211000 {
 152                         compatible = "arm,cortex-a15-gic";
 153                         interrupt-controller;
 154                         #interrupt-cells = <3>;
 155                         interrupt-parent = <&gic>;
 156                         reg = <0 0x10211000 0 0x1000>,
 157                               <0 0x10212000 0 0x1000>,
 158                               <0 0x10214000 0 0x2000>,
 159                               <0 0x10216000 0 0x2000>;
 160                 };
 161
 162                 uart0: serial@11006000 {
 163                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 164                         reg = <0 0x11006000 0 0x400>;
 165                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 166                         clocks = <&uart_clk>;
 167                         status = "disabled";
 168                 };
 169
 170                 uart1: serial@11007000 {
 171                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 172                         reg = <0 0x11007000 0 0x400>;
 173                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 174                         clocks = <&uart_clk>;
 175                         status = "disabled";
 176                 };
 177
 178                 uart2: serial@11008000 {
 179                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 180                         reg = <0 0x11008000 0 0x400>;
 181                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 182                         clocks = <&uart_clk>;
 183                         status = "disabled";
 184                 };
 185
 186                 uart3: serial@11009000 {
 187                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 188                         reg = <0 0x11009000 0 0x400>;
 189                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 190                         clocks = <&uart_clk>;
 191                         status = "disabled";
 192                 };
 193
 194         };
 195 };