Documentation/devicetree/bindings/pci/designware-pcie.txt

   1 * Synopsys Designware PCIe interface
   2
   3 Required properties:
   4 - compatible: should contain "snps,dw-pcie" to identify the
   5         core, plus an identifier for the specific instance, such
   6         as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
   7 - reg: base addresses and lengths of the pcie controller,
   8         the phy controller, additional register for the phy controller.
   9 - interrupts: interrupt values for level interrupt,
  10         pulse interrupt, special interrupt.
  11 - clocks: from common clock binding: handle to pci clock.
  12 - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
  13 - #address-cells: set to <3>
  14 - #size-cells: set to <2>
  15 - device_type: set to "pci"
  16 - ranges: ranges for the PCI memory and I/O regions
  17 - #interrupt-cells: set to <1>
  18 - interrupt-map-mask and interrupt-map: standard PCI properties
  19         to define the mapping of the PCIe interface to interrupt
  20         numbers.
  21 - num-lanes: number of lanes to use
  22 - reset-gpio: gpio pin number of power good signal
  23
  24 Optional properties for fsl,imx6q-pcie
  25 - power-on-gpio: gpio pin number of power-enable signal
  26 - wake-up-gpio: gpio pin number of incoming wakeup signal
  27 - disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
  28
  29 Example:
  30
  31 SoC specific DT Entry:
  32
  33         pcie@290000 {
  34                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  35                 reg = <0x290000 0x1000
  36                         0x270000 0x1000
  37                         0x271000 0x40>;
  38                 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
  39                 clocks = <&clock 28>, <&clock 27>;
  40                 clock-names = "pcie", "pcie_bus";
  41                 #address-cells = <3>;
  42                 #size-cells = <2>;
  43                 device_type = "pci";
  44                 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
  45                           0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
  46                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
  47                 #interrupt-cells = <1>;
  48                 interrupt-map-mask = <0 0 0 0>;
  49                 interrupt-map = <0x0 0 &gic 53>;
  50                 num-lanes = <4>;
  51         };
  52
  53         pcie@2a0000 {
  54                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  55                 reg = <0x2a0000 0x1000
  56                         0x272000 0x1000
  57                         0x271040 0x40>;
  58                 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
  59                 clocks = <&clock 29>, <&clock 27>;
  60                 clock-names = "pcie", "pcie_bus";
  61                 #address-cells = <3>;
  62                 #size-cells = <2>;
  63                 device_type = "pci";
  64                 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
  65                           0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
  66                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
  67                 #interrupt-cells = <1>;
  68                 interrupt-map-mask = <0 0 0 0>;
  69                 interrupt-map = <0x0 0 &gic 56>;
  70                 num-lanes = <4>;
  71         };
  72
  73 Board specific DT Entry:
  74
  75         pcie@290000 {
  76                 reset-gpio = <&pin_ctrl 5 0>;
  77         };
  78
  79         pcie@2a0000 {
  80                 reset-gpio = <&pin_ctrl 22 0>;
  81         };