Merge tag 'driver-core-3.3-rc1-bugfixes' of git://git.kernel.org/pub/scm/linux/kernel...
authorLinus Torvalds <torvalds@linux-foundation.org>
Sun, 29 Jan 2012 02:20:48 +0000 (18:20 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sun, 29 Jan 2012 02:20:48 +0000 (18:20 -0800)
Here are some patches for the 3.3-rc1 tree.

It contains the removal of the sysdev code, now that all users of it are
gone, as well as some sysfs bugfixes that have been reported by users.
There are also some documentation updates here as well.

* tag 'driver-core-3.3-rc1-bugfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core:
  sysfs: Complain bitterly about attempts to remove files from nonexistent directories.
  stable: update documentation to ask for kernel version
  base/core.c:fix typo in comment in function device_add
  Documentation: devres: add allocation functions to list of supported calls
  Documentation update for the driver model core
  kernel-doc: fix new warnings in driver-core
  kernel-doc: fix new warnings in debugfs
  kernel-doc: fix new warnings in device.h
  driver core: remove drivers/base/sys.c and include/linux/sysdev.h

480 files changed:
Documentation/DocBook/device-drivers.tmpl
Documentation/DocBook/deviceiobook.tmpl
Documentation/feature-removal-schedule.txt
Documentation/power/basic-pm-debugging.txt
Documentation/power/freezing-of-tasks.txt
Documentation/thermal/sysfs-api.txt
Documentation/virtual/00-INDEX
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/common/gic.c
arch/arm/configs/imx_v6_v7_defconfig [new file with mode: 0644]
arch/arm/configs/mx3_defconfig [deleted file]
arch/arm/configs/mx5_defconfig [deleted file]
arch/arm/include/asm/assembler.h
arch/arm/include/asm/domain.h
arch/arm/include/asm/futex.h
arch/arm/include/asm/smp.h
arch/arm/include/asm/smp_plat.h
arch/arm/include/asm/uaccess.h
arch/arm/kernel/entry-common.S
arch/arm/kernel/setup.c
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/kernel/vmlinux.lds.S
arch/arm/lib/getuser.S
arch/arm/lib/putuser.S
arch/arm/lib/uaccess.S
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9_alt_reset.S
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9g45_reset.S [new file with mode: 0644]
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/include/mach/at91_rstc.h
arch/arm/mach-at91/include/mach/at91cap9.h
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h [deleted file]
arch/arm/mach-at91/include/mach/at91sam9260.h
arch/arm/mach-at91/include/mach/at91sam9261.h
arch/arm/mach-at91/include/mach/at91sam9263.h
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
arch/arm/mach-at91/include/mach/at91sam9g45.h
arch/arm/mach-at91/include/mach/at91sam9rl.h
arch/arm/mach-at91/include/mach/board.h
arch/arm/mach-at91/pm.c
arch/arm/mach-at91/pm.h
arch/arm/mach-at91/pm_slowclock.S
arch/arm/mach-at91/setup.c
arch/arm/mach-exynos/hotplug.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-highbank/highbank.c
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/Makefile.boot
arch/arm/mach-imx/clock-imx6q.c
arch/arm/mach-imx/clock-mx51-mx53.c [new file with mode: 0644]
arch/arm/mach-imx/cpu-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/cpu_op-mx51.c [new file with mode: 0644]
arch/arm/mach-imx/cpu_op-mx51.h [new file with mode: 0644]
arch/arm/mach-imx/crm-regs-imx5.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx50.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx51.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx53.h [new file with mode: 0644]
arch/arm/mach-imx/efika.h [new file with mode: 0644]
arch/arm/mach-imx/ehci-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/eukrea_mbimx51-baseboard.c [new file with mode: 0644]
arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c [new file with mode: 0644]
arch/arm/mach-imx/imx51-dt.c [new file with mode: 0644]
arch/arm/mach-imx/imx53-dt.c [new file with mode: 0644]
arch/arm/mach-imx/mach-cpuimx51.c [new file with mode: 0644]
arch/arm/mach-imx/mach-cpuimx51sd.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx50_rdp.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_3ds.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_babbage.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_efikamx.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_efikasb.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_ard.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_evk.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_loco.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_smd.c [new file with mode: 0644]
arch/arm/mach-imx/mm-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/mx51_efika.c [new file with mode: 0644]
arch/arm/mach-imx/pm-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/src.c
arch/arm/mach-msm/hotplug.c
arch/arm/mach-msm/platsmp.c
arch/arm/mach-mx5/Kconfig [deleted file]
arch/arm/mach-mx5/Makefile [deleted file]
arch/arm/mach-mx5/Makefile.boot [deleted file]
arch/arm/mach-mx5/board-cpuimx51.c [deleted file]
arch/arm/mach-mx5/board-cpuimx51sd.c [deleted file]
arch/arm/mach-mx5/board-mx50_rdp.c [deleted file]
arch/arm/mach-mx5/board-mx51_3ds.c [deleted file]
arch/arm/mach-mx5/board-mx51_babbage.c [deleted file]
arch/arm/mach-mx5/board-mx51_efikamx.c [deleted file]
arch/arm/mach-mx5/board-mx51_efikasb.c [deleted file]
arch/arm/mach-mx5/board-mx53_ard.c [deleted file]
arch/arm/mach-mx5/board-mx53_evk.c [deleted file]
arch/arm/mach-mx5/board-mx53_loco.c [deleted file]
arch/arm/mach-mx5/board-mx53_smd.c [deleted file]
arch/arm/mach-mx5/clock-mx51-mx53.c [deleted file]
arch/arm/mach-mx5/cpu.c [deleted file]
arch/arm/mach-mx5/cpu_op-mx51.c [deleted file]
arch/arm/mach-mx5/cpu_op-mx51.h [deleted file]
arch/arm/mach-mx5/crm_regs.h [deleted file]
arch/arm/mach-mx5/devices-imx50.h [deleted file]
arch/arm/mach-mx5/devices-imx51.h [deleted file]
arch/arm/mach-mx5/devices-imx53.h [deleted file]
arch/arm/mach-mx5/efika.h [deleted file]
arch/arm/mach-mx5/ehci.c [deleted file]
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c [deleted file]
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c [deleted file]
arch/arm/mach-mx5/imx51-dt.c [deleted file]
arch/arm/mach-mx5/imx53-dt.c [deleted file]
arch/arm/mach-mx5/mm.c [deleted file]
arch/arm/mach-mx5/mx51_efika.c [deleted file]
arch/arm/mach-mx5/pm-imx5.c [deleted file]
arch/arm/mach-mx5/system.c [deleted file]
arch/arm/mach-omap2/Kconfig
arch/arm/mach-pxa/devices.c
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/pxa300.c
arch/arm/mach-pxa/pxa320.c
arch/arm/mach-pxa/pxa3xx.c
arch/arm/mach-pxa/pxa95x.c
arch/arm/mach-realview/hotplug.c
arch/arm/mach-realview/include/mach/board-eb.h
arch/arm/mach-realview/include/mach/board-pb11mp.h
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mach-sa1100/assabet.c
arch/arm/mach-sa1100/cerf.c
arch/arm/mach-sa1100/clock.c
arch/arm/mach-sa1100/collie.c
arch/arm/mach-sa1100/cpu-sa1100.c
arch/arm/mach-sa1100/generic.c
arch/arm/mach-sa1100/include/mach/mcp.h
arch/arm/mach-sa1100/jornada720_ssp.c
arch/arm/mach-sa1100/lart.c
arch/arm/mach-sa1100/shannon.c
arch/arm/mach-sa1100/simpad.c
arch/arm/mach-shmobile/smp-r8a7779.c
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-ux500/Kconfig
arch/arm/mach-ux500/board-mop500-sdi.c
arch/arm/mach-ux500/cache-l2x0.c
arch/arm/mach-ux500/hotplug.c
arch/arm/mach-ux500/platsmp.c
arch/arm/mach-ux500/usb.c
arch/arm/mach-vexpress/ct-ca9x4.c
arch/arm/mach-vexpress/hotplug.c
arch/arm/mm/Kconfig
arch/arm/mm/init.c
arch/arm/mm/ioremap.c
arch/arm/mm/proc-v7.S
arch/arm/plat-mxc/Kconfig
arch/arm/plat-mxc/include/mach/iomux-v1.h
arch/arm/plat-versatile/platsmp.c
arch/m68k/atari/config.c
arch/m68k/include/asm/irq.h
arch/m68k/kernel/process_mm.c
arch/m68k/kernel/process_no.c
arch/m68k/kernel/traps.c
arch/m68k/mm/cache.c
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
arch/powerpc/boot/dts/p1020rdb.dtsi
arch/powerpc/boot/dts/p1021mds.dts
arch/powerpc/boot/dts/p2020ds.dtsi
arch/powerpc/boot/dts/p2020rdb.dts
arch/powerpc/kernel/crash.c
arch/powerpc/kernel/legacy_serial.c
arch/powerpc/platforms/85xx/p1022_ds.c
arch/powerpc/platforms/powernv/pci-ioda.c
arch/powerpc/platforms/pseries/Kconfig
arch/powerpc/sysdev/fsl_pci.c
arch/s390/include/asm/kexec.h
arch/score/kernel/entry.S
arch/sparc/kernel/sun4m_irq.c
arch/x86/Kconfig
arch/x86/boot/compressed/misc.c
arch/x86/include/asm/cpufeature.h
arch/x86/include/asm/uv/uv_hub.h
arch/x86/kernel/microcode_amd.c
arch/x86/net/bpf_jit_comp.c
arch/x86/platform/uv/tlb_uv.c
arch/x86/platform/uv/uv_irq.c
arch/x86/xen/spinlock.c
crypto/sha512_generic.c
drivers/acpi/Makefile
drivers/acpi/apei/apei-base.c
drivers/acpi/apei/einj.c
drivers/acpi/atomicio.c [deleted file]
drivers/acpi/osl.c
drivers/acpi/processor_driver.c
drivers/acpi/sleep.c
drivers/base/firmware_class.c
drivers/base/regmap/regmap.c
drivers/char/agp/backend.c
drivers/gpu/drm/drm_auth.c
drivers/gpu/drm/drm_fops.c
drivers/gpu/drm/exynos/Kconfig
drivers/gpu/drm/exynos/exynos_drm_fimd.c
drivers/gpu/drm/exynos/exynos_hdmi.c
drivers/gpu/drm/gma500/framebuffer.c
drivers/gpu/drm/gma500/gtt.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/intel_bios.h
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_sprite.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/nouveau/nouveau_bo.c
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/atombios_encoders.c
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_atpx_handler.c
drivers/gpu/drm/radeon/radeon_bios.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/sis/sis_drv.c
drivers/gpu/drm/ttm/ttm_bo.c
drivers/idle/intel_idle.c
drivers/leds/Kconfig
drivers/leds/Makefile
drivers/leds/leds-ot200.c [new file with mode: 0644]
drivers/media/dvb/dvb-usb/anysee.c
drivers/media/dvb/dvb-usb/cinergyT2-fe.c
drivers/media/dvb/frontends/cxd2820r.h
drivers/media/dvb/frontends/cxd2820r_core.c
drivers/media/video/atmel-isi.c
drivers/media/video/em28xx/em28xx-dvb.c
drivers/mfd/mcp-core.c
drivers/mfd/mcp-sa11x0.c
drivers/mfd/ucb1x00-core.c
drivers/mfd/ucb1x00-ts.c
drivers/net/bonding/bond_alb.c
drivers/net/dsa/mv88e6060.c
drivers/net/dsa/mv88e6123_61_65.c
drivers/net/dsa/mv88e6131.c
drivers/net/dsa/mv88e6xxx.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
drivers/net/ethernet/broadcom/tg3.c
drivers/net/ethernet/cisco/enic/enic.h
drivers/net/ethernet/cisco/enic/enic_main.c
drivers/net/ethernet/emulex/benet/be_main.c
drivers/net/ethernet/faraday/ftgmac100.c
drivers/net/ethernet/faraday/ftmac100.c
drivers/net/ethernet/intel/igb/Makefile
drivers/net/ethernet/intel/igb/e1000_82575.c
drivers/net/ethernet/intel/igb/e1000_82575.h
drivers/net/ethernet/intel/igb/e1000_defines.h
drivers/net/ethernet/intel/igb/e1000_hw.h
drivers/net/ethernet/intel/igb/e1000_mac.c
drivers/net/ethernet/intel/igb/e1000_mac.h
drivers/net/ethernet/intel/igb/e1000_mbx.c
drivers/net/ethernet/intel/igb/e1000_mbx.h
drivers/net/ethernet/intel/igb/e1000_nvm.c
drivers/net/ethernet/intel/igb/e1000_nvm.h
drivers/net/ethernet/intel/igb/e1000_phy.c
drivers/net/ethernet/intel/igb/e1000_phy.h
drivers/net/ethernet/intel/igb/e1000_regs.h
drivers/net/ethernet/intel/igb/igb.h
drivers/net/ethernet/intel/igb/igb_ethtool.c
drivers/net/ethernet/intel/igb/igb_main.c
drivers/net/ethernet/intel/igbvf/ethtool.c
drivers/net/ethernet/intel/igbvf/netdev.c
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
drivers/net/ethernet/intel/ixgbevf/ethtool.c
drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
drivers/net/ethernet/intel/ixgbevf/mbx.c
drivers/net/ethernet/intel/ixgbevf/vf.c
drivers/net/ethernet/intel/ixgbevf/vf.h
drivers/net/ethernet/marvell/mv643xx_eth.c
drivers/net/ethernet/marvell/skge.c
drivers/net/ethernet/mellanox/mlx4/cmd.c
drivers/net/ethernet/mellanox/mlx4/cq.c
drivers/net/ethernet/mellanox/mlx4/en_ethtool.c
drivers/net/ethernet/mellanox/mlx4/en_main.c
drivers/net/ethernet/mellanox/mlx4/en_netdev.c
drivers/net/ethernet/mellanox/mlx4/en_rx.c
drivers/net/ethernet/mellanox/mlx4/eq.c
drivers/net/ethernet/mellanox/mlx4/fw.c
drivers/net/ethernet/mellanox/mlx4/fw.h
drivers/net/ethernet/mellanox/mlx4/main.c
drivers/net/ethernet/mellanox/mlx4/mlx4.h
drivers/net/ethernet/mellanox/mlx4/mlx4_en.h
drivers/net/ethernet/mellanox/mlx4/mr.c
drivers/net/ethernet/mellanox/mlx4/pd.c
drivers/net/ethernet/mellanox/mlx4/port.c
drivers/net/ethernet/mellanox/mlx4/profile.c
drivers/net/ethernet/mellanox/mlx4/qp.c
drivers/net/ethernet/mellanox/mlx4/resource_tracker.c
drivers/net/ethernet/mellanox/mlx4/srq.c
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
drivers/net/hyperv/netvsc_drv.c
drivers/net/macvlan.c
drivers/net/phy/mdio_bus.c
drivers/net/team/team.c
drivers/net/wireless/b43/Kconfig
drivers/net/wireless/b43/main.c
drivers/net/wireless/brcm80211/brcmsmac/main.c
drivers/pci/pci.c
drivers/pcmcia/sa1111_generic.c
drivers/regulator/core.c
drivers/rtc/Kconfig
drivers/rtc/rtc-sa1100.c
drivers/scsi/mac_esp.c
drivers/scsi/mac_scsi.c
drivers/thermal/thermal_sys.c
drivers/usb/host/ohci-at91.c
drivers/video/backlight/adp8860_bl.c
drivers/video/backlight/adp8870_bl.c
drivers/video/backlight/l4f00242t03.c
drivers/video/macfb.c
drivers/virtio/virtio_ring.c
drivers/watchdog/dw_wdt.c
drivers/watchdog/iTCO_wdt.c
drivers/watchdog/imx2_wdt.c
drivers/watchdog/nuc900_wdt.c
drivers/watchdog/omap_wdt.c
drivers/watchdog/pnx4008_wdt.c
drivers/watchdog/stmp3xxx_wdt.c
drivers/watchdog/via_wdt.c
drivers/watchdog/wafer5823wdt.c
drivers/watchdog/wm8350_wdt.c
drivers/xen/grant-table.c
fs/btrfs/backref.c
fs/btrfs/check-integrity.c
fs/btrfs/disk-io.c
fs/btrfs/extent-tree.c
fs/btrfs/extent_io.c
fs/btrfs/free-space-cache.c
fs/btrfs/inode.c
fs/btrfs/ioctl.c
fs/btrfs/tree-log.c
fs/cifs/Kconfig
fs/cifs/cifs_debug.c
fs/cifs/cifs_spnego.c
fs/cifs/cifs_unicode.c
fs/cifs/cifs_unicode.h
fs/cifs/cifsacl.c
fs/cifs/cifsencrypt.c
fs/cifs/cifsglob.h
fs/cifs/cifssmb.c
fs/cifs/connect.c
fs/cifs/readdir.c
fs/cifs/sess.c
fs/cifs/smbencrypt.c
fs/ecryptfs/crypto.c
fs/ecryptfs/ecryptfs_kernel.h
fs/ecryptfs/inode.c
fs/ecryptfs/keystore.c
fs/ecryptfs/miscdev.c
fs/ecryptfs/mmap.c
fs/ecryptfs/read_write.c
fs/ext2/ioctl.c
fs/jbd/checkpoint.c
fs/jbd/recovery.c
fs/proc/task_mmu.c
fs/quota/dquot.c
fs/xfs/xfs_vnodeops.c
include/acpi/acpiosxf.h
include/acpi/atomicio.h [deleted file]
include/acpi/processor.h
include/drm/drmP.h
include/keys/user-type.h
include/linux/fs.h
include/linux/if_team.h
include/linux/kexec.h
include/linux/mfd/mcp.h
include/linux/mfd/ucb1x00.h
include/linux/migrate.h
include/linux/migrate_mode.h [new file with mode: 0644]
include/linux/mlx4/device.h
include/linux/mod_devicetable.h
include/linux/quota.h
include/linux/res_counter.h
include/linux/sched.h
include/linux/shmem_fs.h
include/linux/snmp.h
include/linux/suspend.h
include/linux/swap.h
include/linux/thermal.h
include/linux/usb.h
include/net/bluetooth/hci.h
include/net/cfg80211.h
include/net/netprio_cgroup.h
include/net/sock.h
ipc/mqueue.c
ipc/shm.c
kernel/auditsc.c
kernel/events/callchain.c
kernel/events/core.c
kernel/kprobes.c
kernel/power/snapshot.c
kernel/rcutorture.c
kernel/res_counter.c
kernel/sched/cpupri.c
mm/hugetlb.c
mm/memblock.c
mm/memcontrol.c
mm/memory.c
mm/page_alloc.c
mm/shmem.c
mm/vmscan.c
net/bluetooth/hci_core.c
net/core/ethtool.c
net/core/flow_dissector.c
net/core/pktgen.c
net/core/sock.c
net/ipv4/proc.c
net/ipv4/tcp_bic.c
net/ipv4/tcp_cubic.c
net/ipv4/tcp_input.c
net/ipv4/tcp_ipv4.c
net/ipv6/addrconf.c
net/ipv6/tcp_ipv6.c
net/llc/af_llc.c
net/mac80211/debugfs_key.c
net/mac80211/mesh_hwmp.c
net/mac80211/mesh_plink.c
net/mac80211/mlme.c
net/rds/af_rds.c
net/sched/sch_netem.c
scripts/kernel-doc
scripts/mod/file2alias.c
security/keys/internal.h
security/keys/key.c
security/keys/user_defined.c
sound/core/compress_offload.c
sound/pci/hda/alc880_quirks.c
sound/pci/hda/alc882_quirks.c
sound/pci/hda/hda_intel.c
sound/pci/hda/patch_conexant.c
sound/pci/hda/patch_realtek.c
sound/pci/hda/patch_sigmatel.c
sound/pci/ymfpci/ymfpci.c
sound/pci/ymfpci/ymfpci_main.c
sound/soc/codecs/sgtl5000.c
sound/soc/codecs/tlv320aic32x4.c
sound/soc/codecs/wm2000.c
sound/soc/codecs/wm5100.c
sound/soc/codecs/wm8958-dsp2.c
sound/soc/codecs/wm8996.c
sound/soc/codecs/wm8996.h
sound/soc/mxs/mxs-saif.c

index b638e50..2f7fd43 100644 (file)
@@ -50,7 +50,9 @@
 
      <sect1><title>Delaying, scheduling, and timer routines</title>
 !Iinclude/linux/sched.h
-!Ekernel/sched.c
+!Ekernel/sched/core.c
+!Ikernel/sched/cpupri.c
+!Ikernel/sched/fair.c
 !Iinclude/linux/completion.h
 !Ekernel/timer.c
      </sect1>
@@ -216,7 +218,6 @@ X!Isound/sound_firmware.c
 
   <chapter id="uart16x50">
      <title>16x50 UART Driver</title>
-!Iinclude/linux/serial_core.h
 !Edrivers/tty/serial/serial_core.c
 !Edrivers/tty/serial/8250.c
   </chapter>
index c1ed6a4..54199a0 100644 (file)
@@ -317,7 +317,7 @@ CPU B:  spin_unlock_irqrestore(&amp;dev_lock, flags)
   <chapter id="pubfunctions">
      <title>Public Functions Provided</title>
 !Iarch/x86/include/asm/io.h
-!Elib/iomap.c
+!Elib/pci_iomap.c
   </chapter>
 
 </book>
index 1bea46a..a0ffac0 100644 (file)
@@ -510,3 +510,17 @@ Why:       The pci_scan_bus_parented() interface creates a new root bus.  The
        convert to using pci_scan_root_bus() so they can supply a list of
        bus resources when the bus is created.
 Who:   Bjorn Helgaas <bhelgaas@google.com>
+
+----------------------------
+
+What:  The CAP9 SoC family will be removed
+When:  3.4
+Files: arch/arm/mach-at91/at91cap9.c
+       arch/arm/mach-at91/at91cap9_devices.c
+       arch/arm/mach-at91/include/mach/at91cap9.h
+       arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+       arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+       arch/arm/mach-at91/board-cap9adk.c
+Why:   The code is not actively maintained and platforms are now hard to find.
+Who:   Nicolas Ferre <nicolas.ferre@atmel.com>
+       Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
index 40a4c65..262acf5 100644 (file)
@@ -15,7 +15,7 @@ test at least a couple of times in a row for confidence.  [This is necessary,
 because some problems only show up on a second attempt at suspending and
 resuming the system.]  Moreover, hibernating in the "reboot" and "shutdown"
 modes causes the PM core to skip some platform-related callbacks which on ACPI
-systems might be necessary to make hibernation work.  Thus, if you machine fails
+systems might be necessary to make hibernation work.  Thus, if your machine fails
 to hibernate or resume in the "reboot" mode, you should try the "platform" mode:
 
 # echo platform > /sys/power/disk
index 6ccb68f..ebd7490 100644 (file)
@@ -120,10 +120,10 @@ So in practice, the 'at all' may become a 'why freeze kernel threads?' and
 freezing user threads I don't find really objectionable."
 
 Still, there are kernel threads that may want to be freezable.  For example, if
-a kernel that belongs to a device driver accesses the device directly, it in
-principle needs to know when the device is suspended, so that it doesn't try to
-access it at that time.  However, if the kernel thread is freezable, it will be
-frozen before the driver's .suspend() callback is executed and it will be
+a kernel thread that belongs to a device driver accesses the device directly, it
+in principle needs to know when the device is suspended, so that it doesn't try
+to access it at that time.  However, if the kernel thread is freezable, it will
+be frozen before the driver's .suspend() callback is executed and it will be
 thawed after the driver's .resume() callback has run, so it won't be accessing
 the device while it's suspended.
 
index b61e46f..1733ab9 100644 (file)
@@ -284,7 +284,7 @@ method, the sys I/F structure will be built like this:
 The framework includes a simple notification mechanism, in the form of a
 netlink event. Netlink socket initialization is done during the _init_
 of the framework. Drivers which intend to use the notification mechanism
-just need to call generate_netlink_event() with two arguments viz
+just need to call thermal_generate_netlink_event() with two arguments viz
 (originator, event). Typically the originator will be an integer assigned
 to a thermal_zone_device when it registers itself with the framework. The
 event will be one of:{THERMAL_AUX0, THERMAL_AUX1, THERMAL_CRITICAL,
index 8e60199..924bd46 100644 (file)
@@ -4,8 +4,6 @@ Virtualization support in the Linux kernel.
        - this file.
 kvm/
        - Kernel Virtual Machine.  See also http://linux-kvm.org
-lguest/
-       - Extremely simple hypervisor for experimental/educational use.
 uml/
        - User Mode Linux, builds/runs Linux kernel as a userspace program.
 virtio.txt
index 89b70df..1b6e835 100644 (file)
@@ -2246,6 +2246,17 @@ T:       git git://git.kernel.org/pub/scm/linux/kernel/git/teigland/dlm.git
 S:     Supported
 F:     fs/dlm/
 
+DMA BUFFER SHARING FRAMEWORK
+M:     Sumit Semwal <sumit.semwal@linaro.org>
+S:     Maintained
+L:     linux-media@vger.kernel.org
+L:     dri-devel@lists.freedesktop.org
+L:     linaro-mm-sig@lists.linaro.org
+F:     drivers/base/dma-buf*
+F:     include/linux/dma-buf*
+F:     Documentation/dma-buf-sharing.txt
+T:     git git://git.linaro.org/people/sumitsemwal/linux-dma-buf.git
+
 DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
 M:     Vinod Koul <vinod.koul@intel.com>
 M:     Dan Williams <dan.j.williams@intel.com>
@@ -2339,6 +2350,9 @@ F:        include/drm/i915*
 
 DRM DRIVERS FOR EXYNOS
 M:     Inki Dae <inki.dae@samsung.com>
+M:     Joonyoung Shim <jy0922.shim@samsung.com>
+M:     Seung-Woo Kim <sw0312.kim@samsung.com>
+M:     Kyungmin Park <kyungmin.park@samsung.com>
 L:     dri-devel@lists.freedesktop.org
 S:     Supported
 F:     drivers/gpu/drm/exynos
@@ -2391,7 +2405,7 @@ F:        net/bridge/netfilter/ebt*.c
 
 ECRYPT FILE SYSTEM
 M:     Tyler Hicks <tyhicks@canonical.com>
-M:     Dustin Kirkland <kirkland@canonical.com>
+M:     Dustin Kirkland <dustin.kirkland@gazzang.com>
 L:     ecryptfs@vger.kernel.org
 W:     https://launchpad.net/ecryptfs
 S:     Supported
index 24626b0..a48aecc 100644 (file)
@@ -754,7 +754,7 @@ config ARCH_SA1100
        select ARCH_HAS_CPUFREQ
        select CPU_FREQ
        select GENERIC_CLOCKEVENTS
-       select CLKDEV_LOOKUP
+       select HAVE_CLK
        select HAVE_SCHED_CLOCK
        select TICK_ONESHOT
        select ARCH_REQUIRE_GPIOLIB
@@ -825,7 +825,6 @@ config ARCH_S5PC100
        select HAVE_CLK
        select CLKDEV_LOOKUP
        select CPU_V7
-       select ARM_L1_CACHE_SHIFT_6
        select ARCH_USES_GETTIMEOFFSET
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C_RTC if RTC_CLASS
@@ -842,7 +841,6 @@ config ARCH_S5PV210
        select HAVE_CLK
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
-       select ARM_L1_CACHE_SHIFT_6
        select ARCH_HAS_CPUFREQ
        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
index 40319d9..1683bfb 100644 (file)
@@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM)          := msm
 machine-$(CONFIG_ARCH_MV78XX0)         := mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)       := imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)       := imx
-machine-$(CONFIG_ARCH_MX5)             := mx5
 machine-$(CONFIG_ARCH_MXS)             := mxs
 machine-$(CONFIG_ARCH_NETX)            := netx
 machine-$(CONFIG_ARCH_NOMADIK)         := nomadik
index b2dc2dd..c47d619 100644 (file)
@@ -41,6 +41,7 @@
 
 #include <asm/irq.h>
 #include <asm/exception.h>
+#include <asm/smp_plat.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
@@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        unsigned int gic_irqs = gic->gic_irqs;
        struct irq_domain *domain = &gic->domain;
        void __iomem *base = gic_data_dist_base(gic);
-       u32 cpu = 0;
-
-#ifdef CONFIG_SMP
-       cpu = cpu_logical_map(smp_processor_id());
-#endif
+       u32 cpu = cpu_logical_map(smp_processor_id());
 
        cpumask = 1 << cpu;
        cpumask |= cpumask << 8;
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
new file mode 100644 (file)
index 0000000..3a4fb2e
--- /dev/null
@@ -0,0 +1,193 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_RELAY=y
+CONFIG_EXPERT=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_MACH_MX31LILLY=y
+CONFIG_MACH_MX31LITE=y
+CONFIG_MACH_PCM037=y
+CONFIG_MACH_PCM037_EET=y
+CONFIG_MACH_MX31_3DS=y
+CONFIG_MACH_MX31MOBOARD=y
+CONFIG_MACH_QONG=y
+CONFIG_MACH_ARMADILLO5X0=y
+CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_PCM043=y
+CONFIG_MACH_MX35_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX35=y
+CONFIG_MACH_VPR200=y
+CONFIG_MACH_IMX51_DT=y
+CONFIG_MACH_MX51_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX51=y
+CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_MACH_MX51_EFIKAMX=y
+CONFIG_MACH_MX51_EFIKASB=y
+CONFIG_MACH_IMX53_DT=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_MXC_PWM=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_BINFMT_MISC=m
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CONNECTOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_PATA_IMX=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+CONFIG_FEC=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC91X=y
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_MC13XXX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_MC13892=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_MXC=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
deleted file mode 100644 (file)
index cb0717f..0000000
+++ /dev/null
@@ -1,144 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
-CONFIG_MACH_MX31ADS_WM1133_EV1=y
-CONFIG_MACH_MX31LILLY=y
-CONFIG_MACH_MX31LITE=y
-CONFIG_MACH_PCM037=y
-CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31_3DS=y
-CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_QONG=y
-CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_KZM_ARM11_01=y
-CONFIG_MACH_PCM043=y
-CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX35=y
-CONFIG_MXC_IRQ_PRIOR=y
-CONFIG_MXC_PWM=y
-CONFIG_ARM_ERRATA_411920=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
-CONFIG_VFP=y
-CONFIG_PM_DEBUG=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MXC=y
-CONFIG_MTD_UBI=y
-# CONFIG_BLK_DEV is not set
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT24=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-CONFIG_DNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_IMX=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-CONFIG_SPI=y
-CONFIG_W1=y
-CONFIG_W1_MASTER_MXC=y
-CONFIG_W1_SLAVE_THERM=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_IMX2_WDT=y
-CONFIG_MFD_WM8350_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM8350=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_RC_CORE is not set
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_MT9M001=y
-CONFIG_SOC_CAMERA_MT9M111=y
-CONFIG_SOC_CAMERA_MT9T031=y
-CONFIG_SOC_CAMERA_MT9V022=y
-CONFIG_SOC_CAMERA_TW9910=y
-CONFIG_SOC_CAMERA_OV772X=y
-CONFIG_VIDEO_MX3=y
-# CONFIG_RADIO_ADAPTERS is not set
-CONFIG_FB=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_MXC_SOC_WM1133_EV1=y
-CONFIG_SND_SOC_PHYCORE_AC97=y
-CONFIG_SND_SOC_EUKREA_TLV320=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_FSL_USB2=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_ULPI=y
-CONFIG_MMC=y
-CONFIG_MMC_MXC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MXC=y
-CONFIG_DMADEVICES=y
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mx5_defconfig b/arch/arm/configs/mx5_defconfig
deleted file mode 100644 (file)
index d0d8dfe..0000000
+++ /dev/null
@@ -1,184 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_RELAY=y
-CONFIG_EXPERT=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX5=y
-CONFIG_MACH_MX51_BABBAGE=y
-CONFIG_MACH_MX51_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX51=y
-CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_MX51_EFIKAMX=y
-CONFIG_MACH_MX51_EFIKASB=y
-CONFIG_MACH_MX53_EVK=y
-CONFIG_MACH_MX53_SMD=y
-CONFIG_MACH_MX53_LOCO=y
-CONFIG_MACH_MX53_ARD=y
-CONFIG_MXC_PWM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_VMSPLIT_2G=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=m
-CONFIG_PM_DEBUG=y
-CONFIG_PM_TEST_SUSPEND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-CONFIG_PATA_IMX=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_MICREL_PHY=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_MMA8450=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-CONFIG_I2C_IMX=y
-CONFIG_SPI=y
-CONFIG_SPI_IMX=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_IMX2_WDT=y
-CONFIG_MFD_MC13XXX=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_MC13892=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_MXC=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_SECURITYFS=y
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_LZO=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
index b6e65de..62f8095 100644 (file)
  */
 #ifdef CONFIG_THUMB2_KERNEL
 
-       .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
+       .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
 9999:
        .if     \inc == 1
        \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
 
 #else  /* !CONFIG_THUMB2_KERNEL */
 
-       .macro  usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
+       .macro  usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
        .rept   \rept
 9999:
        .if     \inc == 1
index af18cea..b5dc173 100644 (file)
@@ -83,9 +83,9 @@
  * instructions (inline assembly)
  */
 #ifdef CONFIG_CPU_USE_DOMAINS
-#define T(instr)       #instr "t"
+#define TUSER(instr)   #instr "t"
 #else
-#define T(instr)       #instr
+#define TUSER(instr)   #instr
 #endif
 
 #else /* __ASSEMBLY__ */
@@ -95,9 +95,9 @@
  * instructions
  */
 #ifdef CONFIG_CPU_USE_DOMAINS
-#define T(instr)       instr ## t
+#define TUSER(instr)   instr ## t
 #else
-#define T(instr)       instr
+#define TUSER(instr)   instr
 #endif
 
 #endif /* __ASSEMBLY__ */
index 253cc86..7be5469 100644 (file)
@@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 
 #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)        \
        __asm__ __volatile__(                                   \
-       "1:     " T(ldr) "      %1, [%3]\n"                     \
+       "1:     " TUSER(ldr) "  %1, [%3]\n"                     \
        "       " insn "\n"                                     \
-       "2:     " T(str) "      %0, [%3]\n"                     \
+       "2:     " TUSER(str) "  %0, [%3]\n"                     \
        "       mov     %0, #0\n"                               \
        __futex_atomic_ex_table("%5")                           \
        : "=&r" (ret), "=&r" (oldval), "=&r" (tmp)              \
@@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                return -EFAULT;
 
        __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
-       "1:     " T(ldr) "      %1, [%4]\n"
+       "1:     " TUSER(ldr) "  %1, [%4]\n"
        "       teq     %1, %2\n"
        "       it      eq      @ explicit IT needed for the 2b label\n"
-       "2:     " T(streq) "    %3, [%4]\n"
+       "2:     " TUSER(streq) "        %3, [%4]\n"
        __futex_atomic_ex_table("%5")
        : "+r" (ret), "=&r" (val)
        : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
index 1e5717a..ae29293 100644 (file)
@@ -70,12 +70,6 @@ extern void platform_secondary_init(unsigned int cpu);
  */
 extern void platform_smp_prepare_cpus(unsigned int);
 
-/*
- * Logical CPU mapping.
- */
-extern int __cpu_logical_map[NR_CPUS];
-#define cpu_logical_map(cpu)   __cpu_logical_map[cpu]
-
 /*
  * Initial data for bringing up a secondary CPU.
  */
index f24c1b9..558d6c8 100644 (file)
@@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void)
 }
 #endif
 
+/*
+ * Logical CPU mapping.
+ */
+extern int __cpu_logical_map[];
+#define cpu_logical_map(cpu)   __cpu_logical_map[cpu]
+
 #endif
index b293616..2958976 100644 (file)
@@ -227,7 +227,7 @@ do {                                                                        \
 
 #define __get_user_asm_byte(x,addr,err)                                \
        __asm__ __volatile__(                                   \
-       "1:     " T(ldrb) "     %1,[%2],#0\n"                   \
+       "1:     " TUSER(ldrb) " %1,[%2],#0\n"                   \
        "2:\n"                                                  \
        "       .pushsection .fixup,\"ax\"\n"                   \
        "       .align  2\n"                                    \
@@ -263,7 +263,7 @@ do {                                                                        \
 
 #define __get_user_asm_word(x,addr,err)                                \
        __asm__ __volatile__(                                   \
-       "1:     " T(ldr) "      %1,[%2],#0\n"                   \
+       "1:     " TUSER(ldr) "  %1,[%2],#0\n"                   \
        "2:\n"                                                  \
        "       .pushsection .fixup,\"ax\"\n"                   \
        "       .align  2\n"                                    \
@@ -308,7 +308,7 @@ do {                                                                        \
 
 #define __put_user_asm_byte(x,__pu_addr,err)                   \
        __asm__ __volatile__(                                   \
-       "1:     " T(strb) "     %1,[%2],#0\n"                   \
+       "1:     " TUSER(strb) " %1,[%2],#0\n"                   \
        "2:\n"                                                  \
        "       .pushsection .fixup,\"ax\"\n"                   \
        "       .align  2\n"                                    \
@@ -341,7 +341,7 @@ do {                                                                        \
 
 #define __put_user_asm_word(x,__pu_addr,err)                   \
        __asm__ __volatile__(                                   \
-       "1:     " T(str) "      %1,[%2],#0\n"                   \
+       "1:     " TUSER(str) "  %1,[%2],#0\n"                   \
        "2:\n"                                                  \
        "       .pushsection .fixup,\"ax\"\n"                   \
        "       .align  2\n"                                    \
@@ -366,10 +366,10 @@ do {                                                                      \
 
 #define __put_user_asm_dword(x,__pu_addr,err)                  \
        __asm__ __volatile__(                                   \
- ARM(  "1:     " T(str) "      " __reg_oper1 ", [%1], #4\n"    )       \
- ARM(  "2:     " T(str) "      " __reg_oper0 ", [%1]\n"        )       \
- THUMB(        "1:     " T(str) "      " __reg_oper1 ", [%1]\n"        )       \
- THUMB(        "2:     " T(str) "      " __reg_oper0 ", [%1, #4]\n"    )       \
+ ARM(  "1:     " TUSER(str) "  " __reg_oper1 ", [%1], #4\n"    ) \
+ ARM(  "2:     " TUSER(str) "  " __reg_oper0 ", [%1]\n"        ) \
+ THUMB(        "1:     " TUSER(str) "  " __reg_oper1 ", [%1]\n"        ) \
+ THUMB(        "2:     " TUSER(str) "  " __reg_oper0 ", [%1, #4]\n"    ) \
        "3:\n"                                                  \
        "       .pushsection .fixup,\"ax\"\n"                   \
        "       .align  2\n"                                    \
index 520889c..9fd0ba9 100644 (file)
@@ -149,6 +149,11 @@ ENDPROC(ret_from_fork)
 #endif
 #endif
 
+.macro mcount_adjust_addr rd, rn
+       bic     \rd, \rn, #1            @ clear the Thumb bit if present
+       sub     \rd, \rd, #MCOUNT_INSN_SIZE
+.endm
+
 .macro __mcount suffix
        mcount_enter
        ldr     r0, =ftrace_trace_function
@@ -173,8 +178,7 @@ ENDPROC(ret_from_fork)
        mcount_exit
 
 1:     mcount_get_lr   r1                      @ lr of instrumented func
-       mov     r0, lr                          @ instrumented function
-       sub     r0, r0, #MCOUNT_INSN_SIZE
+       mcount_adjust_addr      r0, lr          @ instrumented function
        adr     lr, BSYM(2f)
        mov     pc, r2
 2:     mcount_exit
@@ -184,8 +188,7 @@ ENDPROC(ret_from_fork)
        mcount_enter
 
        mcount_get_lr   r1                      @ lr of instrumented func
-       mov     r0, lr                          @ instrumented function
-       sub     r0, r0, #MCOUNT_INSN_SIZE
+       mcount_adjust_addr      r0, lr          @ instrumented function
 
        .globl ftrace_call\suffix
 ftrace_call\suffix:
@@ -205,11 +208,11 @@ ftrace_graph_call\suffix:
 #ifdef CONFIG_DYNAMIC_FTRACE
        @ called from __ftrace_caller, saved in mcount_enter
        ldr     r1, [sp, #16]           @ instrumented routine (func)
+       mcount_adjust_addr      r1, r1
 #else
        @ called from __mcount, untouched in lr
-       mov     r1, lr                  @ instrumented routine (func)
+       mcount_adjust_addr      r1, lr  @ instrumented routine (func)
 #endif
-       sub     r1, r1, #MCOUNT_INSN_SIZE
        mov     r2, fp                  @ frame pointer
        bl      prepare_ftrace_return
        mcount_exit
index 129fbd5..a255c39 100644 (file)
@@ -21,7 +21,6 @@
 #include <linux/init.h>
 #include <linux/kexec.h>
 #include <linux/of_fdt.h>
-#include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
@@ -160,7 +159,7 @@ static struct resource mem_res[] = {
                .flags = IORESOURCE_MEM
        },
        {
-               .name = "Kernel text",
+               .name = "Kernel code",
                .start = 0,
                .end = 0,
                .flags = IORESOURCE_MEM
@@ -427,6 +426,20 @@ void cpu_init(void)
            : "r14");
 }
 
+int __cpu_logical_map[NR_CPUS];
+
+void __init smp_setup_processor_id(void)
+{
+       int i;
+       u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
+
+       cpu_logical_map(0) = cpu;
+       for (i = 1; i < NR_CPUS; ++i)
+               cpu_logical_map(i) = i == cpu ? 0 : i;
+
+       printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
+}
+
 static void __init setup_processor(void)
 {
        struct proc_info_list *list;
index 57db122..cdeb727 100644 (file)
@@ -233,20 +233,6 @@ void __ref cpu_die(void)
 }
 #endif /* CONFIG_HOTPLUG_CPU */
 
-int __cpu_logical_map[NR_CPUS];
-
-void __init smp_setup_processor_id(void)
-{
-       int i;
-       u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
-
-       cpu_logical_map(0) = cpu;
-       for (i = 1; i < NR_CPUS; ++i)
-               cpu_logical_map(i) = i == cpu ? 0 : i;
-
-       printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
-}
-
 /*
  * Called by both boot and secondaries to move global data into
  * per-processor storage.
@@ -443,9 +429,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
 static void ipi_timer(void)
 {
        struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
-       irq_enter();
        evt->event_handler(evt);
-       irq_exit();
 }
 
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
@@ -548,7 +532,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
 
        switch (ipinr) {
        case IPI_TIMER:
+               irq_enter();
                ipi_timer();
+               irq_exit();
                break;
 
        case IPI_RESCHEDULE:
@@ -556,15 +542,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
                break;
 
        case IPI_CALL_FUNC:
+               irq_enter();
                generic_smp_call_function_interrupt();
+               irq_exit();
                break;
 
        case IPI_CALL_FUNC_SINGLE:
+               irq_enter();
                generic_smp_call_function_single_interrupt();
+               irq_exit();
                break;
 
        case IPI_CPU_STOP:
+               irq_enter();
                ipi_cpu_stop(cpu);
+               irq_exit();
                break;
 
        default:
index c8e9385..4285daa 100644 (file)
@@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        else
                twd_calibrate_rate();
 
+       __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+
        clk->name = "local_timer";
        clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
                        CLOCK_EVT_FEAT_C3STOP;
index f76e755..1e19691 100644 (file)
@@ -4,6 +4,7 @@
  */
 
 #include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/page.h>
@@ -181,7 +182,7 @@ SECTIONS
        }
 #endif
 
-       PERCPU_SECTION(32)
+       PERCPU_SECTION(L1_CACHE_BYTES)
 
 #ifdef CONFIG_XIP_KERNEL
        __data_loc = ALIGN(4);          /* location in binary */
@@ -212,13 +213,13 @@ SECTIONS
 #endif
 
                NOSAVE_DATA
-               CACHELINE_ALIGNED_DATA(32)
-               READ_MOSTLY_DATA(32)
+               CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
+               READ_MOSTLY_DATA(L1_CACHE_BYTES)
 
                /*
                 * The exception fixup table (might need resorting at runtime)
                 */
-               . = ALIGN(32);
+               . = ALIGN(4);
                __start___ex_table = .;
 #ifdef CONFIG_MMU
                *(__ex_table)
index 1b049cd..11093a7 100644 (file)
 #include <asm/domain.h>
 
 ENTRY(__get_user_1)
-1:     T(ldrb) r2, [r0]
+1: TUSER(ldrb) r2, [r0]
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
 #ifdef CONFIG_THUMB2_KERNEL
-2:     T(ldrb) r2, [r0]
-3:     T(ldrb) r3, [r0, #1]
+2: TUSER(ldrb) r2, [r0]
+3: TUSER(ldrb) r3, [r0, #1]
 #else
-2:     T(ldrb) r2, [r0], #1
-3:     T(ldrb) r3, [r0]
+2: TUSER(ldrb) r2, [r0], #1
+3: TUSER(ldrb) r3, [r0]
 #endif
 #ifndef __ARMEB__
        orr     r2, r2, r3, lsl #8
@@ -54,7 +54,7 @@ ENTRY(__get_user_2)
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
-4:     T(ldr)  r2, [r0]
+4: TUSER(ldr)  r2, [r0]
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__get_user_4)
index c023fc1..7db2599 100644 (file)
@@ -31,7 +31,7 @@
 #include <asm/domain.h>
 
 ENTRY(__put_user_1)
-1:     T(strb) r2, [r0]
+1: TUSER(strb) r2, [r0]
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__put_user_1)
@@ -40,19 +40,19 @@ ENTRY(__put_user_2)
        mov     ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
-2:     T(strb) r2, [r0]
-3:     T(strb) ip, [r0, #1]
+2: TUSER(strb) r2, [r0]
+3: TUSER(strb) ip, [r0, #1]
 #else
-2:     T(strb) ip, [r0]
-3:     T(strb) r2, [r0, #1]
+2: TUSER(strb) ip, [r0]
+3: TUSER(strb) r2, [r0, #1]
 #endif
 #else  /* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
-2:     T(strb) r2, [r0], #1
-3:     T(strb) ip, [r0]
+2: TUSER(strb) r2, [r0], #1
+3: TUSER(strb) ip, [r0]
 #else
-2:     T(strb) ip, [r0], #1
-3:     T(strb) r2, [r0]
+2: TUSER(strb) ip, [r0], #1
+3: TUSER(strb) r2, [r0]
 #endif
 #endif /* CONFIG_THUMB2_KERNEL */
        mov     r0, #0
@@ -60,18 +60,18 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
-4:     T(str)  r2, [r0]
+4: TUSER(str)  r2, [r0]
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
 #ifdef CONFIG_THUMB2_KERNEL
-5:     T(str)  r2, [r0]
-6:     T(str)  r3, [r0, #4]
+5: TUSER(str)  r2, [r0]
+6: TUSER(str)  r3, [r0, #4]
 #else
-5:     T(str)  r2, [r0], #4
-6:     T(str)  r3, [r0]
+5: TUSER(str)  r2, [r0], #4
+6: TUSER(str)  r3, [r0]
 #endif
        mov     r0, #0
        mov     pc, lr
index d0ece2a..5c908b1 100644 (file)
                rsb     ip, ip, #4
                cmp     ip, #2
                ldrb    r3, [r1], #1
-USER(          T(strb) r3, [r0], #1)                   @ May fault
+USER(  TUSER(  strb)   r3, [r0], #1)                   @ May fault
                ldrgeb  r3, [r1], #1
-USER(          T(strgeb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgeb) r3, [r0], #1)                   @ May fault
                ldrgtb  r3, [r1], #1
-USER(          T(strgtb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgtb) r3, [r0], #1)                   @ May fault
                sub     r2, r2, ip
                b       .Lc2u_dest_aligned
 
@@ -59,7 +59,7 @@ ENTRY(__copy_to_user)
                addmi   ip, r2, #4
                bmi     .Lc2u_0nowords
                ldr     r3, [r1], #4
-USER(          T(str)  r3, [r0], #4)                   @ May fault
+USER(  TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
                rsb     ip, ip, #0
                movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -88,18 +88,18 @@ USER(               T(str)  r3, [r0], #4)                   @ May fault
                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
                tst     ip, #4
                ldrne   r3, [r1], #4
-               T(strne) r3, [r0], #4                   @ Shouldnt fault
+       TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_0fupi
 .Lc2u_0nowords:        teq     ip, #0
                beq     .Lc2u_finished
 .Lc2u_nowords: cmp     ip, #2
                ldrb    r3, [r1], #1
-USER(          T(strb) r3, [r0], #1)                   @ May fault
+USER(  TUSER(  strb)   r3, [r0], #1)                   @ May fault
                ldrgeb  r3, [r1], #1
-USER(          T(strgeb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgeb) r3, [r0], #1)                   @ May fault
                ldrgtb  r3, [r1], #1
-USER(          T(strgtb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgtb) r3, [r0], #1)                   @ May fault
                b       .Lc2u_finished
 
 .Lc2u_not_enough:
@@ -120,7 +120,7 @@ USER(               T(strgtb) r3, [r0], #1)                 @ May fault
                mov     r3, r7, pull #8
                ldr     r7, [r1], #4
                orr     r3, r3, r7, push #24
-USER(          T(str)  r3, [r0], #4)                   @ May fault
+USER(  TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
                movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -155,18 +155,18 @@ USER(             T(str)  r3, [r0], #4)                   @ May fault
                movne   r3, r7, pull #8
                ldrne   r7, [r1], #4
                orrne   r3, r3, r7, push #24
-               T(strne) r3, [r0], #4                   @ Shouldnt fault
+       TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_1fupi
 .Lc2u_1nowords:        mov     r3, r7, get_byte_1
                teq     ip, #0
                beq     .Lc2u_finished
                cmp     ip, #2
-USER(          T(strb) r3, [r0], #1)                   @ May fault
+USER(  TUSER(  strb)   r3, [r0], #1)                   @ May fault
                movge   r3, r7, get_byte_2
-USER(          T(strgeb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgeb) r3, [r0], #1)                   @ May fault
                movgt   r3, r7, get_byte_3
-USER(          T(strgtb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgtb) r3, [r0], #1)                   @ May fault
                b       .Lc2u_finished
 
 .Lc2u_2fupi:   subs    r2, r2, #4
@@ -175,7 +175,7 @@ USER(               T(strgtb) r3, [r0], #1)                 @ May fault
                mov     r3, r7, pull #16
                ldr     r7, [r1], #4
                orr     r3, r3, r7, push #16
-USER(          T(str)  r3, [r0], #4)                   @ May fault
+USER(  TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
                movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -210,18 +210,18 @@ USER(             T(str)  r3, [r0], #4)                   @ May fault
                movne   r3, r7, pull #16
                ldrne   r7, [r1], #4
                orrne   r3, r3, r7, push #16
-               T(strne) r3, [r0], #4                   @ Shouldnt fault
+       TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_2fupi
 .Lc2u_2nowords:        mov     r3, r7, get_byte_2
                teq     ip, #0
                beq     .Lc2u_finished
                cmp     ip, #2
-USER(          T(strb) r3, [r0], #1)                   @ May fault
+USER(  TUSER(  strb)   r3, [r0], #1)                   @ May fault
                movge   r3, r7, get_byte_3
-USER(          T(strgeb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgeb) r3, [r0], #1)                   @ May fault
                ldrgtb  r3, [r1], #0
-USER(          T(strgtb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgtb) r3, [r0], #1)                   @ May fault
                b       .Lc2u_finished
 
 .Lc2u_3fupi:   subs    r2, r2, #4
@@ -230,7 +230,7 @@ USER(               T(strgtb) r3, [r0], #1)                 @ May fault
                mov     r3, r7, pull #24
                ldr     r7, [r1], #4
                orr     r3, r3, r7, push #8
-USER(          T(str)  r3, [r0], #4)                   @ May fault
+USER(  TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
                movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -265,18 +265,18 @@ USER(             T(str)  r3, [r0], #4)                   @ May fault
                movne   r3, r7, pull #24
                ldrne   r7, [r1], #4
                orrne   r3, r3, r7, push #8
-               T(strne) r3, [r0], #4                   @ Shouldnt fault
+       TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_3fupi
 .Lc2u_3nowords:        mov     r3, r7, get_byte_3
                teq     ip, #0
                beq     .Lc2u_finished
                cmp     ip, #2
-USER(          T(strb) r3, [r0], #1)                   @ May fault
+USER(  TUSER(  strb)   r3, [r0], #1)                   @ May fault
                ldrgeb  r3, [r1], #1
-USER(          T(strgeb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgeb) r3, [r0], #1)                   @ May fault
                ldrgtb  r3, [r1], #0
-USER(          T(strgtb) r3, [r0], #1)                 @ May fault
+USER(  TUSER(  strgtb) r3, [r0], #1)                   @ May fault
                b       .Lc2u_finished
 ENDPROC(__copy_to_user)
 
@@ -295,11 +295,11 @@ ENDPROC(__copy_to_user)
 .Lcfu_dest_not_aligned:
                rsb     ip, ip, #4
                cmp     ip, #2
-USER(          T(ldrb) r3, [r1], #1)                   @ May fault
+USER(  TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
                strb    r3, [r0], #1
-USER(          T(ldrgeb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
                strgeb  r3, [r0], #1
-USER(          T(ldrgtb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
                strgtb  r3, [r0], #1
                sub     r2, r2, ip
                b       .Lcfu_dest_aligned
@@ -322,7 +322,7 @@ ENTRY(__copy_from_user)
 .Lcfu_0fupi:   subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lcfu_0nowords
-USER(          T(ldr)  r3, [r1], #4)
+USER(  TUSER(  ldr)    r3, [r1], #4)
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
                rsb     ip, ip, #0
@@ -351,18 +351,18 @@ USER(             T(ldr)  r3, [r1], #4)
                ldmneia r1!, {r3 - r4}                  @ Shouldnt fault
                stmneia r0!, {r3 - r4}
                tst     ip, #4
-               T(ldrne) r3, [r1], #4                   @ Shouldnt fault
+       TUSER(  ldrne) r3, [r1], #4                     @ Shouldnt fault
                strne   r3, [r0], #4
                ands    ip, ip, #3
                beq     .Lcfu_0fupi
 .Lcfu_0nowords:        teq     ip, #0
                beq     .Lcfu_finished
 .Lcfu_nowords: cmp     ip, #2
-USER(          T(ldrb) r3, [r1], #1)                   @ May fault
+USER(  TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
                strb    r3, [r0], #1
-USER(          T(ldrgeb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
                strgeb  r3, [r0], #1
-USER(          T(ldrgtb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
                strgtb  r3, [r0], #1
                b       .Lcfu_finished
 
@@ -375,7 +375,7 @@ USER(               T(ldrgtb) r3, [r1], #1)                 @ May fault
 
 .Lcfu_src_not_aligned:
                bic     r1, r1, #3
-USER(          T(ldr)  r7, [r1], #4)                   @ May fault
+USER(  TUSER(  ldr)    r7, [r1], #4)                   @ May fault
                cmp     ip, #2
                bgt     .Lcfu_3fupi
                beq     .Lcfu_2fupi
@@ -383,7 +383,7 @@ USER(               T(ldr)  r7, [r1], #4)                   @ May fault
                addmi   ip, r2, #4
                bmi     .Lcfu_1nowords
                mov     r3, r7, pull #8
-USER(          T(ldr)  r7, [r1], #4)                   @ May fault
+USER(  TUSER(  ldr)    r7, [r1], #4)                   @ May fault
                orr     r3, r3, r7, push #24
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -418,7 +418,7 @@ USER(               T(ldr)  r7, [r1], #4)                   @ May fault
                stmneia r0!, {r3 - r4}
                tst     ip, #4
                movne   r3, r7, pull #8
-USER(          T(ldrne) r7, [r1], #4)                  @ May fault
+USER(  TUSER(  ldrne) r7, [r1], #4)                    @ May fault
                orrne   r3, r3, r7, push #24
                strne   r3, [r0], #4
                ands    ip, ip, #3
@@ -438,7 +438,7 @@ USER(               T(ldrne) r7, [r1], #4)                  @ May fault
                addmi   ip, r2, #4
                bmi     .Lcfu_2nowords
                mov     r3, r7, pull #16
-USER(          T(ldr)  r7, [r1], #4)                   @ May fault
+USER(  TUSER(  ldr)    r7, [r1], #4)                   @ May fault
                orr     r3, r3, r7, push #16
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -474,7 +474,7 @@ USER(               T(ldr)  r7, [r1], #4)                   @ May fault
                stmneia r0!, {r3 - r4}
                tst     ip, #4
                movne   r3, r7, pull #16
-USER(          T(ldrne) r7, [r1], #4)                  @ May fault
+USER(  TUSER(  ldrne) r7, [r1], #4)                    @ May fault
                orrne   r3, r3, r7, push #16
                strne   r3, [r0], #4
                ands    ip, ip, #3
@@ -486,7 +486,7 @@ USER(               T(ldrne) r7, [r1], #4)                  @ May fault
                strb    r3, [r0], #1
                movge   r3, r7, get_byte_3
                strgeb  r3, [r0], #1
-USER(          T(ldrgtb) r3, [r1], #0)                 @ May fault
+USER(  TUSER(  ldrgtb) r3, [r1], #0)                   @ May fault
                strgtb  r3, [r0], #1
                b       .Lcfu_finished
 
@@ -494,7 +494,7 @@ USER(               T(ldrgtb) r3, [r1], #0)                 @ May fault
                addmi   ip, r2, #4
                bmi     .Lcfu_3nowords
                mov     r3, r7, pull #24
-USER(          T(ldr)  r7, [r1], #4)                   @ May fault
+USER(  TUSER(  ldr)    r7, [r1], #4)                   @ May fault
                orr     r3, r3, r7, push #8
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -529,7 +529,7 @@ USER(               T(ldr)  r7, [r1], #4)                   @ May fault
                stmneia r0!, {r3 - r4}
                tst     ip, #4
                movne   r3, r7, pull #24
-USER(          T(ldrne) r7, [r1], #4)                  @ May fault
+USER(  TUSER(  ldrne) r7, [r1], #4)                    @ May fault
                orrne   r3, r3, r7, push #8
                strne   r3, [r0], #4
                ands    ip, ip, #3
@@ -539,9 +539,9 @@ USER(               T(ldrne) r7, [r1], #4)                  @ May fault
                beq     .Lcfu_finished
                cmp     ip, #2
                strb    r3, [r0], #1
-USER(          T(ldrgeb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
                strgeb  r3, [r0], #1
-USER(          T(ldrgtb) r3, [r1], #1)                 @ May fault
+USER(  TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
                strgtb  r3, [r0], #1
                b       .Lcfu_finished
 ENDPROC(__copy_from_user)
index 4f991f2..71feb00 100644 (file)
@@ -18,6 +18,12 @@ config HAVE_AT91_USART4
 config HAVE_AT91_USART5
        bool
 
+config AT91_SAM9_ALT_RESET
+       bool
+
+config AT91_SAM9G45_RESET
+       bool
+
 menu "Atmel AT91 System-on-Chip"
 
 choice
@@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
        select HAVE_AT91_USART4
        select HAVE_AT91_USART5
        select HAVE_NET_MACB
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9261
        bool "AT91SAM9261"
@@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
        select HAVE_AT91_DBGU0
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G10
        bool "AT91SAM9G10"
@@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9263
        bool "AT91SAM9263"
@@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
        select HAVE_AT91_DBGU1
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9RL
        bool "AT91SAM9RL"
@@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
        select HAVE_AT91_USART3
        select HAVE_FB_ATMEL
        select HAVE_AT91_DBGU0
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G20
        bool "AT91SAM9G20"
@@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
        select HAVE_AT91_USART4
        select HAVE_AT91_USART5
        select HAVE_NET_MACB
+       select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G45
        bool "AT91SAM9G45"
@@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
        select HAVE_AT91_DBGU1
+       select AT91_SAM9G45_RESET
 
 config ARCH_AT91CAP9
        bool "AT91CAP9"
@@ -96,6 +109,7 @@ config ARCH_AT91CAP9
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
        select HAVE_AT91_DBGU1
+       select AT91_SAM9G45_RESET
 
 config ARCH_AT91X40
        bool "AT91x40"
index 242174f..705e1fb 100644 (file)
@@ -8,15 +8,17 @@ obj-n         :=
 obj-           :=
 
 obj-$(CONFIG_AT91_PMC_UNIT)    += clock.o
+obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
+obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
 
 # CPU-specific support
 obj-$(CONFIG_ARCH_AT91RM9200)  += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)    += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)     += at91x40.o at91x40_time.o
index edb879a..a42edc2 100644 (file)
@@ -21,7 +21,6 @@
 #include <mach/cpu.h>
 #include <mach/at91cap9.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
        }
 };
 
-static void at91cap9_restart(char mode, const char *cmd)
-{
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
 /* --------------------------------------------------------------------
  *  AT91CAP9 processor initialization
  * -------------------------------------------------------------------- */
@@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
 static void __init at91cap9_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
+       at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
 }
 
 static void __init at91cap9_initialize(void)
 {
-       arm_pm_restart = at91cap9_restart;
+       arm_pm_restart = at91sam9g45_restart;
        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 
        /* Register GPIO subsystem */
index 5e46e4a..d4036ba 100644 (file)
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
 static void __init at91sam9260_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
+       at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 }
index b85b9ea..023c2ff 100644 (file)
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
 static void __init at91sam9261_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
+       at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 }
index 79e3669..75e876c 100644 (file)
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
 static void __init at91sam9263_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
+       at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
index d3f931c..518e423 100644 (file)
@@ -23,7 +23,8 @@
                        .globl  at91sam9_alt_restart
 
 at91sam9_alt_restart:  ldr     r0, .at91_va_base_sdramc        @ preload constants
-                       ldr     r1, .at91_va_base_rstc_cr
+                       ldr     r1, =at91_rstc_base
+                       ldr     r1, [r1]
 
                        mov     r2, #1
                        mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -33,11 +34,9 @@ at91sam9_alt_restart:        ldr     r0, .at91_va_base_sdramc        @ preload constants
 
                        str     r2, [r0, #AT91_SDRAMC_TR]       @ disable SDRAM access
                        str     r3, [r0, #AT91_SDRAMC_LPR]      @ power down SDRAM
-                       str     r4, [r1]                        @ reset processor
+                       str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                        b       .
 
 .at91_va_base_sdramc:
        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
-.at91_va_base_rstc_cr:
-       .word AT91_VA_BASE_SYS + AT91_RSTC_CR
index 7032dd3..1cb6a96 100644 (file)
@@ -18,7 +18,6 @@
 #include <asm/mach/map.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
 #include <mach/cpu.h>
 
 #include "soc.h"
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
        }
 };
 
-static void at91sam9g45_restart(char mode, const char *cmd)
-{
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
 /* --------------------------------------------------------------------
  *  AT91SAM9G45 processor initialization
  * -------------------------------------------------------------------- */
@@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
 static void __init at91sam9g45_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
+       at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
 }
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
new file mode 100644 (file)
index 0000000..0468be1
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * reset AT91SAM9G45 as per errata
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ *
+ * GPLv2 Only
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_rstc.h>
+
+                       .arm
+
+                       .globl  at91sam9g45_restart
+
+at91sam9g45_restart:
+                       ldr     r0, .at91_va_base_sdramc0       @ preload constants
+                       ldr     r1, =at91_rstc_base
+                       ldr     r1, [r1]
+
+                       mov     r2, #1
+                       mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
+                       ldr     r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
+
+                       .balign 32                              @ align to cache line
+
+                       str     r2, [r0, #AT91_DDRSDRC_RTR]     @ disable DDR0 access
+                       str     r3, [r0, #AT91_DDRSDRC_LPR]     @ power down DDR0
+                       str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
+
+                       b       .
+
+.at91_va_base_sdramc0:
+       .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
index d6bcb1d..d2c91a8 100644 (file)
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
 static void __init at91sam9rl_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
+       at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 }
index 4866b81..5941334 100644 (file)
@@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 
 /* reset */
+extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
+extern void at91sam9g45_restart(char, const char *);
 
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
index cbd2bf0..875fa33 100644 (file)
 #ifndef AT91_RSTC_H
 #define AT91_RSTC_H
 
-#define AT91_RSTC_CR           (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_rstc_base;
+
+#define at91_rstc_read(field) \
+       __raw_readl(at91_rstc_base + field)
+
+#define at91_rstc_write(field, value) \
+       __raw_writel(value, at91_rstc_base + field);
+#else
+.extern at91_rstc_base
+#endif
+
+#define AT91_RSTC_CR           0x00                    /* Reset Controller Control Register */
 #define                AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
 #define                AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
 #define                AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
 #define                AT91_RSTC_KEY           (0xa5 << 24)            /* KEY Password */
 
-#define AT91_RSTC_SR           (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
+#define AT91_RSTC_SR           0x04                    /* Reset Controller Status Register */
 #define                AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
 #define                AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
 #define                        AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
@@ -33,7 +45,7 @@
 #define                AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
 #define                AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
 
-#define AT91_RSTC_MR           (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
+#define AT91_RSTC_MR           0x08                    /* Reset Controller Mode Register */
 #define                AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
 #define                AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
 #define                AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
index 4c0e2f6..61d9529 100644 (file)
@@ -83,7 +83,6 @@
 #define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_GPBR      (cpu_is_at91cap9_revB() ?       \
                        (0xfffffd50 - AT91_BASE_SYS) :  \
                        (0xfffffd60 - AT91_BASE_SYS))
@@ -96,6 +95,7 @@
 #define AT91CAP9_BASE_PIOB     0xfffff400
 #define AT91CAP9_BASE_PIOC     0xfffff600
 #define AT91CAP9_BASE_PIOD     0xfffff800
+#define AT91CAP9_BASE_RSTC     0xfffffd00
 #define AT91CAP9_BASE_SHDWC    0xfffffd10
 #define AT91CAP9_BASE_RTT      0xfffffd20
 #define AT91CAP9_BASE_PIT      0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644 (file)
index 976f4a6..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
- *
- *  (C) 2008 Andrew Victor
- *
- * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_DDRSDR_H
-#define AT91CAP9_DDRSDR_H
-
-#define AT91_DDRSDRC_MR                0x00    /* Mode Register */
-#define                AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
-#define                        AT91_DDRSDRC_MODE_NORMAL                0
-#define                        AT91_DDRSDRC_MODE_NOP           1
-#define                        AT91_DDRSDRC_MODE_PRECHARGE     2
-#define                        AT91_DDRSDRC_MODE_LMR           3
-#define                        AT91_DDRSDRC_MODE_REFRESH       4
-#define                        AT91_DDRSDRC_MODE_EXT_LMR       5
-#define                        AT91_DDRSDRC_MODE_DEEP          6
-
-#define AT91_DDRSDRC_RTR       0x04    /* Refresh Timer Register */
-#define                AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
-
-#define AT91_DDRSDRC_CR                0x08    /* Configuration Register */
-#define                AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
-#define                        AT91_DDRSDRC_NC_SDR8    (0 << 0)
-#define                        AT91_DDRSDRC_NC_SDR9    (1 << 0)
-#define                        AT91_DDRSDRC_NC_SDR10   (2 << 0)
-#define                        AT91_DDRSDRC_NC_SDR11   (3 << 0)
-#define                        AT91_DDRSDRC_NC_DDR9    (0 << 0)
-#define                        AT91_DDRSDRC_NC_DDR10   (1 << 0)
-#define                        AT91_DDRSDRC_NC_DDR11   (2 << 0)
-#define                        AT91_DDRSDRC_NC_DDR12   (3 << 0)
-#define                AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
-#define                        AT91_DDRSDRC_NR_11      (0 << 2)
-#define                        AT91_DDRSDRC_NR_12      (1 << 2)
-#define                        AT91_DDRSDRC_NR_13      (2 << 2)
-#define                AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
-#define                        AT91_DDRSDRC_CAS_2      (2 << 4)
-#define                        AT91_DDRSDRC_CAS_3      (3 << 4)
-#define                        AT91_DDRSDRC_CAS_25     (6 << 4)
-#define                AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
-#define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
-
-#define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
-#define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
-#define                AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
-#define                AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
-#define                AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
-#define                AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
-#define                AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
-#define                AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
-#define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
-
-#define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
-#define                AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
-#define                AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
-#define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
-#define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
-
-#define AT91_DDRSDRC_LPR       0x18    /* Low Power Register */
-#define                AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
-#define                        AT91_DDRSDRC_LPCB_DISABLE               0
-#define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
-#define                        AT91_DDRSDRC_LPCB_POWER_DOWN            2
-#define                        AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
-#define                AT91_DDRSDRC_CLKFR              (1 << 2)        /* Clock Frozen */
-#define                AT91_DDRSDRC_PASR               (7 << 4)        /* Partial Array Self Refresh */
-#define                AT91_DDRSDRC_TCSR               (3 << 8)        /* Temperature Compensated Self Refresh */
-#define                AT91_DDRSDRC_DS                 (3 << 10)       /* Drive Strength */
-#define                AT91_DDRSDRC_TIMEOUT            (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                        AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
-#define                        AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
-#define                        AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
-
-#define AT91_DDRSDRC_MDR       0x1C    /* Memory Device Register */
-#define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
-#define                        AT91_DDRSDRC_MD_SDR             0
-#define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
-#define                        AT91_DDRSDRC_MD_DDR             2
-#define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
-
-#define AT91_DDRSDRC_DLLR      0x20    /* DLL Information Register */
-#define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
-#define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
-#define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
-#define                AT91_DDRSDRC_SDCOVF     (1 << 3)                /* Slave Delay Correction Overflow */
-#define                AT91_DDRSDRC_SDCUDF     (1 << 4)                /* Slave Delay Correction Underflow */
-#define                AT91_DDRSDRC_SDERF      (1 << 5)                /* Slave Delay Correction error */
-#define                AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
-#define                AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
-#define                AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
-
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-       at91_sys_read(AT91_DDRSDRC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-       at91_sys_write(AT91_DDRSDRC##num + reg, value)
-
-
-#endif
index f937c47..fa5ca27 100644 (file)
@@ -83,7 +83,6 @@
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
 
 #define AT91SAM9260_BASE_ECC   0xffffe800
@@ -92,6 +91,7 @@
 #define AT91SAM9260_BASE_PIOA  0xfffff400
 #define AT91SAM9260_BASE_PIOB  0xfffff600
 #define AT91SAM9260_BASE_PIOC  0xfffff800
+#define AT91SAM9260_BASE_RSTC  0xfffffd00
 #define AT91SAM9260_BASE_SHDWC 0xfffffd10
 #define AT91SAM9260_BASE_RTT   0xfffffd20
 #define AT91SAM9260_BASE_PIT   0xfffffd30
index 175604e..7cde2d3 100644 (file)
@@ -68,7 +68,6 @@
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
 
 #define AT91SAM9261_BASE_SMC   0xffffec00
@@ -76,6 +75,7 @@
 #define AT91SAM9261_BASE_PIOA  0xfffff400
 #define AT91SAM9261_BASE_PIOB  0xfffff600
 #define AT91SAM9261_BASE_PIOC  0xfffff800
+#define AT91SAM9261_BASE_RSTC  0xfffffd00
 #define AT91SAM9261_BASE_SHDWC 0xfffffd10
 #define AT91SAM9261_BASE_RTT   0xfffffd20
 #define AT91SAM9261_BASE_PIT   0xfffffd30
index 80c9150..5949abd 100644 (file)
@@ -78,7 +78,6 @@
 #define AT91_SDRAMC1   (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffec00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
 
 #define AT91SAM9263_BASE_ECC0  0xffffe000
@@ -91,6 +90,7 @@
 #define AT91SAM9263_BASE_PIOC  0xfffff600
 #define AT91SAM9263_BASE_PIOD  0xfffff800
 #define AT91SAM9263_BASE_PIOE  0xfffffa00
+#define AT91SAM9263_BASE_RSTC  0xfffffd00
 #define AT91SAM9263_BASE_SHDWC 0xfffffd10
 #define AT91SAM9263_BASE_RTT0  0xfffffd20
 #define AT91SAM9263_BASE_PIT   0xfffffd30
index d27b15b..e2f8da8 100644 (file)
 #define                        AT91_DDRSDRC_CAS_25     (6 << 4)
 #define                AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
 #define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
-#define                AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL */
-#define                AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver */
-#define                AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared */
-#define                AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y */
+#define                AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL [SAM9 Only] */
+#define                AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver [SAM9 Only] */
+#define                AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared [SAM9 Only] */
+#define                AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
 
 #define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
 #define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
@@ -59,7 +59,8 @@
 #define                AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
 #define                AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
 #define                AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
-#define                AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay */
+#define                AT91CAP9_DDRSDRC_TWTR   (1   << 24)             /* Internal Write to Read delay */
+#define                AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
 #define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
 #define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
 #define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
 #define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
 
-#define AT91_DDRSDRC_T2PR      0x14    /* Timing 2 Register */
+#define AT91_DDRSDRC_T2PR      0x14    /* Timing 2 Register [SAM9 Only] */
 #define                AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
 #define                AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
 #define                AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
 #define                AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
 
 #define AT91_DDRSDRC_LPR       0x1C    /* Low Power Register */
+#define AT91CAP9_DDRSDRC_LPR   0x18    /* Low Power Register */
 #define                AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
 #define                        AT91_DDRSDRC_LPCB_DISABLE               0
 #define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
 #define                AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
 
 #define AT91_DDRSDRC_MDR       0x20    /* Memory Device Register */
+#define AT91CAP9_DDRSDRC_MDR   0x1C    /* Memory Device Register */
 #define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                        AT91_DDRSDRC_MD_SDR             0
 #define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                        AT91CAP9_DDRSDRC_MD_DDR         2
 #define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
-#define                        AT91_DDRSDRC_MD_DDR2            6
+#define                        AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
 #define                AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
 #define                        AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
 #define                        AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
 
 #define AT91_DDRSDRC_DLL       0x24    /* DLL Information Register */
+#define AT91CAP9_DDRSDRC_DLL   0x20    /* DLL Information Register */
 #define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define                AT91CAP9_DDRSDRC_SDCOVF (1 << 3)                /* Slave Delay Correction Overflow */
+#define                AT91CAP9_DDRSDRC_SDCUDF (1 << 4)                /* Slave Delay Correction Underflow */
+#define                AT91CAP9_DDRSDRC_SDERF  (1 << 5)                /* Slave Delay Correction error */
 #define                AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+#define                AT91CAP9_DDRSDRC_SDVAL  (0xff << 16)            /* Slave Delay value */
+#define                AT91CAP9_DDRSDRC_SDCVAL (0xff << 24)            /* Slave Delay Correction value */
 
-#define AT91_DDRSDRC_HS                0x2C    /* High Speed Register */
+#define AT91_DDRSDRC_HS                0x2C    /* High Speed Register [SAM9 Only] */
 #define                AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
 
 #define AT91_DDRSDRC_DELAY(n)  (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
 
-#define AT91_DDRSDRC_WPMR      0xE4    /* Write Protect Mode Register */
+#define AT91_DDRSDRC_WPMR      0xE4    /* Write Protect Mode Register [SAM9 Only] */
 #define                AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
 #define                AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
 #define                AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
 
-#define AT91_DDRSDRC_WPSR      0xE8    /* Write Protect Status Register */
+#define AT91_DDRSDRC_WPSR      0xE8    /* Write Protect Status Register [SAM9 Only] */
 #define                AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
 #define                AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
 
index f0c23c9..dd9c95e 100644 (file)
@@ -90,7 +90,6 @@
 #define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
 
 #define AT91SAM9G45_BASE_ECC   0xffffe200
 #define AT91SAM9G45_BASE_PIOC  0xfffff600
 #define AT91SAM9G45_BASE_PIOD  0xfffff800
 #define AT91SAM9G45_BASE_PIOE  0xfffffa00
+#define AT91SAM9G45_BASE_RSTC  0xfffffd00
 #define AT91SAM9G45_BASE_SHDWC 0xfffffd10
 #define AT91SAM9G45_BASE_RTT   0xfffffd20
 #define AT91SAM9G45_BASE_PIT   0xfffffd30
index 2bb359e..d7bead7 100644 (file)
@@ -72,7 +72,6 @@
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
 #define AT91_SCKCR     (0xfffffd50 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
 
@@ -84,6 +83,7 @@
 #define AT91SAM9RL_BASE_PIOB   0xfffff600
 #define AT91SAM9RL_BASE_PIOC   0xfffff800
 #define AT91SAM9RL_BASE_PIOD   0xfffffa00
+#define AT91SAM9RL_BASE_RSTC   0xfffffd00
 #define AT91SAM9RL_BASE_SHDWC  0xfffffd10
 #define AT91SAM9RL_BASE_RTT    0xfffffd20
 #define AT91SAM9RL_BASE_PIT    0xfffffd30
index d0b377b..3b33f07 100644 (file)
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
 struct at91_usbh_data {
        u8              ports;          /* number of ports on root hub */
        int             vbus_pin[2];    /* port power-control pin */
-       u8              vbus_pin_inverted;
+       u8              vbus_pin_active_low[2];
        u8              overcurrent_supported;
        int             overcurrent_pin[2];
        u8              overcurrent_status[2];
index 62ad955..1606379 100644 (file)
@@ -34,7 +34,6 @@
 /*
  * Show the reason for the previous system reset.
  */
-#if defined(AT91_RSTC)
 
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
@@ -58,10 +57,10 @@ static void __init show_reset_status(void)
        char *reason, *r2 = reset;
        u32 reset_type, wake_type;
 
-       if (!at91_shdwc_base)
+       if (!at91_shdwc_base || !at91_rstc_base)
                return;
 
-       reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+       reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
        wake_type = at91_shdwc_read(AT91_SHDW_SR);
 
        switch (reset_type) {
@@ -102,10 +101,6 @@ static void __init show_reset_status(void)
        }
        pr_info("AT91: Starting after %s %s\n", reason, r2);
 }
-#else
-static void __init show_reset_status(void) {}
-#endif
-
 
 static int at91_pm_valid_state(suspend_state_t state)
 {
index ce9a206..7eb40d2 100644 (file)
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
                                                                : : "r" (0))
 
 #elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_ddrsdr.h>
+#include <mach/at91sam9_ddrsdr.h>
 
 
 static inline u32 sdram_selfrefresh_enable(void)
 {
        u32 saved_lpr, lpr;
 
-       saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+       saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
 
        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+       at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
        return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
 #define wait_for_interrupt_enable()            cpu_do_idle()
 
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
index f7922a4..92dfb84 100644 (file)
@@ -18,9 +18,8 @@
 
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200_mc.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_ddrsdr.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
 #include <mach/at91sam9_ddrsdr.h>
 #else
 #include <mach/at91sam9_sdramc.h>
index 8bdcc3c..69d3fc4 100644 (file)
@@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
 void __init at91rm9200_set_type(int type)
 {
        if (type == ARCH_REVISON_9200_PQFP)
-               at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
-       else
                at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
+       else
+               at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
+
+       pr_info("AT91: filled in soc subtype: %s\n",
+               at91_get_soc_subtype(&at91_soc_initdata));
 }
 
 void __init at91_init_irq_default(void)
@@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
        pm_power_off = at91sam9_poweroff;
 }
 
+void __iomem *at91_rstc_base;
+
+void __init at91_ioremap_rstc(u32 base_addr)
+{
+       at91_rstc_base = ioremap(base_addr, 16);
+       if (!at91_rstc_base)
+               panic("Impossible to ioremap at91_rstc_base\n");
+}
+
 void __init at91_initialize(unsigned long main_clock)
 {
        at91_boot_soc.ioremap_registers();
index da70e7e..dd1ad55 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
 
 #include <mach/regs-pmu.h>
 
index 683aec7..0f2035a 100644 (file)
@@ -23,6 +23,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/gic.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 
 #include <mach/hardware.h>
index 7afbe1e..8394d51 100644 (file)
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
@@ -72,9 +73,7 @@ static void __init highbank_map_io(void)
 
 void highbank_set_cpu_jump(int cpu, void *jump_addr)
 {
-#ifdef CONFIG_SMP
        cpu = cpu_logical_map(cpu);
-#endif
        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
index 0e6de36..4defb97 100644 (file)
@@ -22,6 +22,18 @@ config ARCH_MX25
 config MACH_MX27
        bool
 
+config ARCH_MX5
+       bool
+
+config ARCH_MX50
+       bool
+
+config ARCH_MX51
+       bool
+
+config ARCH_MX53
+       bool
+
 config SOC_IMX1
        bool
        select ARCH_MX1
@@ -73,6 +85,31 @@ config SOC_IMX35
        select MXC_AVIC
        select SMP_ON_UP if SMP
 
+config SOC_IMX5
+       select CPU_V7
+       select MXC_TZIC
+       select ARCH_MXC_IOMUX_V3
+       select ARCH_MXC_AUDMUX_V2
+       select ARCH_HAS_CPUFREQ
+       select ARCH_MX5
+       bool
+
+config SOC_IMX50
+       bool
+       select SOC_IMX5
+       select ARCH_MX50
+
+config SOC_IMX51
+       bool
+       select SOC_IMX5
+       select ARCH_MX5
+       select ARCH_MX51
+
+config SOC_IMX53
+       bool
+       select SOC_IMX5
+       select ARCH_MX5
+       select ARCH_MX53
 
 if ARCH_IMX_V4_V5
 
@@ -592,6 +629,207 @@ config MACH_VPR200
          Include support for VPR200 platform. This includes specific
          configurations for the board and its peripherals.
 
+comment "i.MX5 platforms:"
+
+config MACH_MX50_RDP
+       bool "Support MX50 reference design platform"
+       depends on BROKEN
+       select SOC_IMX50
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for MX50 reference design platform (RDP) board. This
+         includes specific configurations for the board and its peripherals.
+
+comment "i.MX51 machines:"
+
+config MACH_IMX51_DT
+       bool "Support i.MX51 platforms from device tree"
+       select SOC_IMX51
+       select USE_OF
+       select MACH_MX51_BABBAGE
+       help
+         Include support for Freescale i.MX51 based platforms
+         using the device tree for discovery
+
+config MACH_MX51_BABBAGE
+       bool "Support MX51 BABBAGE platforms"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for MX51 Babbage platform, also known as MX51EVK in
+         u-boot. This includes specific configurations for the board and its
+         peripherals.
+
+config MACH_MX51_3DS
+       bool "Support MX51PDK (3DS)"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_KEYPAD
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select MXC_DEBUG_BOARD
+       help
+         Include support for MX51PDK (3DS) platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+       bool "Support Eukrea CPUIMX51 module"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for Eukrea CPUIMX51 platform. This includes
+         specific configurations for the module and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX51
+       default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+       prompt "Eukrea MBIMX51 development board"
+       bool
+       select IMX_HAVE_PLATFORM_IMX_KEYPAD
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMX51 evaluation board.
+
+endchoice
+
+config MACH_EUKREA_CPUIMX51SD
+       bool "Support Eukrea CPUIMX51SD module"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for Eukrea CPUIMX51SD platform. This includes
+         specific configurations for the module and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX51SD
+       default MACH_EUKREA_MBIMXSD51_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD51_BASEBOARD
+       prompt "Eukrea MBIMXSD development board"
+       bool
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMXSD evaluation board.
+
+endchoice
+
+config MX51_EFIKA_COMMON
+       bool
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_PATA_IMX
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select MXC_ULPI if USB_ULPI
+
+config MACH_MX51_EFIKAMX
+       bool "Support MX51 Genesi Efika MX nettop"
+       select LEDS_GPIO_REGISTER
+       select MX51_EFIKA_COMMON
+       help
+         Include support for Genesi Efika MX nettop. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX51_EFIKASB
+       bool "Support MX51 Genesi Efika Smartbook"
+       select LEDS_GPIO_REGISTER
+       select MX51_EFIKA_COMMON
+       help
+         Include support for Genesi Efika Smartbook. This includes specific
+         configurations for the board and its peripherals.
+
+comment "i.MX53 machines:"
+
+config MACH_IMX53_DT
+       bool "Support i.MX53 platforms from device tree"
+       select SOC_IMX53
+       select USE_OF
+       select MACH_MX53_ARD
+       select MACH_MX53_EVK
+       select MACH_MX53_LOCO
+       select MACH_MX53_SMD
+       help
+         Include support for Freescale i.MX53 based platforms
+         using the device tree for discovery
+
+config MACH_MX53_EVK
+       bool "Support MX53 EVK platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         Include support for MX53 EVK platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_SMD
+       bool "Support MX53 SMD platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       help
+         Include support for MX53 SMD platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_LOCO
+       bool "Support MX53 LOCO platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_GPIO_KEYS
+       select LEDS_GPIO_REGISTER
+       help
+         Include support for MX53 LOCO platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_ARD
+       bool "Support MX53 ARD platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_GPIO_KEYS
+       help
+         Include support for MX53 ARD platform. This includes specific
+         configurations for the board and its peripherals.
+
 comment "i.MX6 family:"
 
 config SOC_IMX6Q
index f5920c2..55db9c4 100644 (file)
@@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
 
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
 
@@ -75,3 +77,22 @@ obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
 endif
+
+# i.MX5 based machines
+obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
+obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
+obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
+obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
+obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
+
+obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
index 5f4d06a..6dfdbcc 100644 (file)
@@ -22,6 +22,18 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
 params_phys-$(CONFIG_SOC_IMX35)        := 0x80000100
 initrd_phys-$(CONFIG_SOC_IMX35)        := 0x80800000
 
+zreladdr-$(CONFIG_SOC_IMX50)   += 0x70008000
+params_phys-$(CONFIG_SOC_IMX50)        := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX50)        := 0x70800000
+
+zreladdr-$(CONFIG_SOC_IMX51)   += 0x90008000
+params_phys-$(CONFIG_SOC_IMX51)        := 0x90000100
+initrd_phys-$(CONFIG_SOC_IMX51)        := 0x90800000
+
+zreladdr-$(CONFIG_SOC_IMX53)   += 0x70008000
+params_phys-$(CONFIG_SOC_IMX53)        := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX53)        := 0x70800000
+
 zreladdr-$(CONFIG_SOC_IMX6Q)   += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q)        := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q)        := 0x10800000
index 9273c2a..2d88f8b 100644 (file)
@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
 DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
 DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
 
+static unsigned long twd_clk_get_rate(struct clk *clk)
+{
+       return clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk twd_clk = {
+       .parent = &arm_clk,
+       .get_rate = twd_clk_get_rate,
+};
+
 static unsigned long pll2_200m_get_rate(struct clk *clk)
 {
        return clk_get_rate(clk->parent) / 2;
@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
        _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
        _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
+       _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
        _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
        _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
        _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c
new file mode 100644 (file)
index 0000000..0847050
--- /dev/null
@@ -0,0 +1,1675 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+
+#include <asm/div64.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+
+#include "crm-regs-imx5.h"
+
+/* External clock values passed-in by the board code */
+static unsigned long external_high_reference, external_low_reference;
+static unsigned long oscillator_reference, ckih2_reference;
+
+static struct clk osc_clk;
+static struct clk pll1_main_clk;
+static struct clk pll1_sw_clk;
+static struct clk pll2_sw_clk;
+static struct clk pll3_sw_clk;
+static struct clk mx53_pll4_sw_clk;
+static struct clk lp_apm_clk;
+static struct clk periph_apm_clk;
+static struct clk ahb_clk;
+static struct clk ipg_clk;
+static struct clk usboh3_clk;
+static struct clk emi_fast_clk;
+static struct clk ipu_clk;
+static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
+
+#define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
+
+/* calculate best pre and post dividers to get the required divider */
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
+       u32 max_pre, u32 max_post)
+{
+       if (div >= max_pre * max_post) {
+               *pre = max_pre;
+               *post = max_post;
+       } else if (div >= max_pre) {
+               u32 min_pre, temp_pre, old_err, err;
+               min_pre = DIV_ROUND_UP(div, max_post);
+               old_err = max_pre;
+               for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
+                       err = div % temp_pre;
+                       if (err == 0) {
+                               *pre = temp_pre;
+                               break;
+                       }
+                       err = temp_pre - err;
+                       if (err < old_err) {
+                               old_err = err;
+                               *pre = temp_pre;
+                       }
+               }
+               *post = DIV_ROUND_UP(div, *pre);
+       } else {
+               *pre = div;
+               *post = 1;
+       }
+}
+
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
+{
+       u32 reg = __raw_readl(clk->enable_reg);
+
+       reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+       reg |= mode << clk->enable_shift;
+
+       __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_ccgr_enable(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
+       return 0;
+}
+
+static void _clk_ccgr_disable(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
+
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+       return 0;
+}
+
+static void _clk_ccgr_disable_inwait(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+}
+
+/*
+ * For the 4-to-1 muxed input clock
+ */
+static inline u32 _get_mux(struct clk *parent, struct clk *m0,
+                          struct clk *m1, struct clk *m2, struct clk *m3)
+{
+       if (parent == m0)
+               return 0;
+       else if (parent == m1)
+               return 1;
+       else if (parent == m2)
+               return 2;
+       else if (parent == m3)
+               return 3;
+       else
+               BUG();
+
+       return -EINVAL;
+}
+
+static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
+{
+       if (pll == &pll1_main_clk)
+               return MX51_DPLL1_BASE;
+       else if (pll == &pll2_sw_clk)
+               return MX51_DPLL2_BASE;
+       else if (pll == &pll3_sw_clk)
+               return MX51_DPLL3_BASE;
+       else
+               BUG();
+
+       return NULL;
+}
+
+static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
+{
+       if (pll == &pll1_main_clk)
+               return MX53_DPLL1_BASE;
+       else if (pll == &pll2_sw_clk)
+               return MX53_DPLL2_BASE;
+       else if (pll == &pll3_sw_clk)
+               return MX53_DPLL3_BASE;
+       else if (pll == &mx53_pll4_sw_clk)
+               return MX53_DPLL4_BASE;
+       else
+               BUG();
+
+       return NULL;
+}
+
+static inline void __iomem *_get_pll_base(struct clk *pll)
+{
+       if (cpu_is_mx51())
+               return _mx51_get_pll_base(pll);
+       else
+               return _mx53_get_pll_base(pll);
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+       long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+       unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+       void __iomem *pllbase;
+       s64 temp;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       pllbase = _get_pll_base(clk);
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+       if (pll_hfsm == 0) {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+       } else {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+       pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+       mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+       mfi = (mfi <= 5) ? 5 : mfi;
+       mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+       mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+       /* Sign extend to 32-bits */
+       if (mfn >= 0x04000000) {
+               mfn |= 0xFC000000;
+               mfn_abs = -mfn;
+       }
+
+       ref_clk = 2 * parent_rate;
+       if (dbl != 0)
+               ref_clk *= 2;
+
+       ref_clk /= (pdf + 1);
+       temp = (u64) ref_clk * mfn_abs;
+       do_div(temp, mfd + 1);
+       if (mfn < 0)
+               temp = -temp;
+       temp = (ref_clk * mfi) + temp;
+
+       return temp;
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg;
+       void __iomem *pllbase;
+
+       long mfi, pdf, mfn, mfd = 999999;
+       s64 temp64;
+       unsigned long quad_parent_rate;
+       unsigned long pll_hfsm, dp_ctl;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       pllbase = _get_pll_base(clk);
+
+       quad_parent_rate = 4 * parent_rate;
+       pdf = mfi = -1;
+       while (++pdf < 16 && mfi < 5)
+               mfi = rate * (pdf+1) / quad_parent_rate;
+       if (mfi > 15)
+               return -EINVAL;
+       pdf--;
+
+       temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
+       do_div(temp64, quad_parent_rate/1000000);
+       mfn = (long)temp64;
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       /* use dpdck0_2 */
+       __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       if (pll_hfsm == 0) {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+       } else {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+
+       return 0;
+}
+
+static int _clk_pll_enable(struct clk *clk)
+{
+       u32 reg;
+       void __iomem *pllbase;
+       int i = 0;
+
+       pllbase = _get_pll_base(clk);
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       if (reg & MXC_PLL_DP_CTL_UPEN)
+               return 0;
+
+       reg |= MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+               if (reg & MXC_PLL_DP_CTL_LRF)
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: pll locking failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static void _clk_pll_disable(struct clk *clk)
+{
+       u32 reg;
+       void __iomem *pllbase;
+
+       pllbase = _get_pll_base(clk);
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg, step;
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       /* When switching from pll_main_clk to a bypass clock, first select a
+        * multiplexed clock in 'step_sel', then shift the glitchless mux
+        * 'pll1_sw_clk_sel'.
+        *
+        * When switching back, do it in reverse order
+        */
+       if (parent == &pll1_main_clk) {
+               /* Switch to pll1_main_clk */
+               reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+               __raw_writel(reg, MXC_CCM_CCSR);
+               /* step_clk mux switched to lp_apm, to save power. */
+               reg = __raw_readl(MXC_CCM_CCSR);
+               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
+               reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
+                               MXC_CCM_CCSR_STEP_SEL_OFFSET);
+       } else {
+               if (parent == &lp_apm_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
+               } else  if (parent == &pll2_sw_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
+               } else  if (parent == &pll3_sw_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
+               } else
+                       return -EINVAL;
+
+               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
+               reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+
+               __raw_writel(reg, MXC_CCM_CCSR);
+               /* Switch to step_clk */
+               reg = __raw_readl(MXC_CCM_CCSR);
+               reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+       }
+       __raw_writel(reg, MXC_CCM_CCSR);
+       return 0;
+}
+
+static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       if (clk->parent == &pll2_sw_clk) {
+               div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
+                      MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
+       } else if (clk->parent == &pll3_sw_clk) {
+               div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
+                      MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
+       } else
+               div = 1;
+       return parent_rate / div;
+}
+
+static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       if (parent == &pll2_sw_clk)
+               reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+       else
+               reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+
+       __raw_writel(reg, MXC_CCM_CCSR);
+       return 0;
+}
+
+static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       if (parent == &osc_clk)
+               reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
+       else
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CCSR);
+
+       return 0;
+}
+
+static unsigned long clk_cpu_get_rate(struct clk *clk)
+{
+       u32 cacrr, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+       cacrr = __raw_readl(MXC_CCM_CACRR);
+       div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
+
+       return parent_rate / div;
+}
+
+static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, cpu_podf;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+       cpu_podf = parent_rate / rate - 1;
+       /* use post divider to change freq */
+       reg = __raw_readl(MXC_CCM_CACRR);
+       reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+       reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CACRR);
+
+       return 0;
+}
+
+static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg, mux;
+       int i = 0;
+
+       mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
+
+       reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
+       reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCMR);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(MXC_CCM_CDHIPR);
+               if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: Set parent for periph_apm clock failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+
+       if (parent == &pll2_sw_clk)
+               reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+       else if (parent == &periph_apm_clk)
+               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+       else
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       return 0;
+}
+
+static struct clk main_bus_clk = {
+       .parent = &pll2_sw_clk,
+       .set_parent = _clk_main_bus_set_parent,
+};
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+              MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+       return parent_rate / div;
+}
+
+
+static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+       int i = 0;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       div = parent_rate / rate;
+       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+               return -EINVAL;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
+       reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(MXC_CCM_CDHIPR);
+               if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: clk_ahb_set_rate failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static unsigned long _clk_ahb_round_rate(struct clk *clk,
+                                               unsigned long rate)
+{
+       u32 div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       div = parent_rate / rate;
+       if (div > 8)
+               div = 8;
+       else if (div == 0)
+               div++;
+       return parent_rate / div;
+}
+
+
+static int _clk_max_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+
+       /* Handshake with MAX when LPM is entered. */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       if (cpu_is_mx51())
+               reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       else if (cpu_is_mx53())
+               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void _clk_max_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable_inwait(clk);
+
+       /* No Handshake with MAX when LPM is entered as its disabled. */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       if (cpu_is_mx51())
+               reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       else if (cpu_is_mx53())
+               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+              MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+
+       return parent_rate / div;
+}
+
+static unsigned long clk_ipg_per_get_rate(struct clk *clk)
+{
+       u32 reg, prediv1, prediv2, podf;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
+               /* the main_bus_clk is the one before the DVFS engine */
+               reg = __raw_readl(MXC_CCM_CBCDR);
+               prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+                          MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
+               prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+                          MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
+               podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+                       MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
+               return parent_rate / (prediv1 * prediv2 * podf);
+       } else if (clk->parent == &ipg_clk)
+               return parent_rate;
+       else
+               BUG();
+}
+
+static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CBCMR);
+
+       reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+       reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+
+       if (parent == &ipg_clk)
+               reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+       else if (parent == &lp_apm_clk)
+               reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+       else if (parent != &main_bus_clk)
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CBCMR);
+
+       return 0;
+}
+
+#define clk_nfc_set_parent     NULL
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+       unsigned long rate;
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+              MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+       rate = clk_get_rate(clk->parent) / div;
+       WARN_ON(rate == 0);
+       return rate;
+}
+
+static unsigned long clk_nfc_round_rate(struct clk *clk,
+                                               unsigned long rate)
+{
+       u32 div;
+       unsigned long parent_rate = clk_get_rate(clk->parent);
+
+       if (!rate)
+               return -EINVAL;
+
+       div = parent_rate / rate;
+
+       if (parent_rate % rate)
+               div++;
+
+       if (div > 8)
+               return -EINVAL;
+
+       return parent_rate / div;
+
+}
+
+static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, div;
+
+       div = clk_get_rate(clk->parent) / rate;
+       if (div == 0)
+               div++;
+       if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
+               return -EINVAL;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+       reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       while (__raw_readl(MXC_CCM_CDHIPR) &
+                       MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+       }
+
+       return 0;
+}
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+       return external_high_reference;
+}
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+       return external_low_reference;
+}
+
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+       return oscillator_reference;
+}
+
+static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
+{
+       return ckih2_reference;
+}
+
+static unsigned long clk_emi_slow_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+              MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+
+       return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
+{
+       unsigned long rate;
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
+               MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
+       rate = clk_get_rate(clk->parent) / div;
+
+       return rate;
+}
+
+/* External high frequency clock */
+static struct clk ckih_clk = {
+       .get_rate = get_high_reference_clock_rate,
+};
+
+static struct clk ckih2_clk = {
+       .get_rate = get_ckih2_reference_clock_rate,
+};
+
+static struct clk osc_clk = {
+       .get_rate = get_oscillator_reference_clock_rate,
+};
+
+/* External low frequency (32kHz) clock */
+static struct clk ckil_clk = {
+       .get_rate = get_low_reference_clock_rate,
+};
+
+static struct clk pll1_main_clk = {
+       .parent = &osc_clk,
+       .get_rate = clk_pll_get_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* Clock tree block diagram (WIP):
+ *     CCM: Clock Controller Module
+ *
+ * PLL output -> |
+ *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
+ * PLL bypass -> |
+ *
+ */
+
+/* PLL1 SW supplies to ARM core */
+static struct clk pll1_sw_clk = {
+       .parent = &pll1_main_clk,
+       .set_parent = _clk_pll1_sw_set_parent,
+       .get_rate = clk_pll1_sw_get_rate,
+};
+
+/* PLL2 SW supplies to AXI/AHB/IP buses */
+static struct clk pll2_sw_clk = {
+       .parent = &osc_clk,
+       .get_rate = clk_pll_get_rate,
+       .set_rate = _clk_pll_set_rate,
+       .set_parent = _clk_pll2_sw_set_parent,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
+static struct clk pll3_sw_clk = {
+       .parent = &osc_clk,
+       .set_rate = _clk_pll_set_rate,
+       .get_rate = clk_pll_get_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
+static struct clk mx53_pll4_sw_clk = {
+       .parent = &osc_clk,
+       .set_rate = _clk_pll_set_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* Low-power Audio Playback Mode clock */
+static struct clk lp_apm_clk = {
+       .parent = &osc_clk,
+       .set_parent = _clk_lp_apm_set_parent,
+};
+
+static struct clk periph_apm_clk = {
+       .parent = &pll1_sw_clk,
+       .set_parent = _clk_periph_apm_set_parent,
+};
+
+static struct clk cpu_clk = {
+       .parent = &pll1_sw_clk,
+       .get_rate = clk_cpu_get_rate,
+       .set_rate = clk_cpu_set_rate,
+};
+
+static struct clk ahb_clk = {
+       .parent = &main_bus_clk,
+       .get_rate = clk_ahb_get_rate,
+       .set_rate = _clk_ahb_set_rate,
+       .round_rate = _clk_ahb_round_rate,
+};
+
+static struct clk iim_clk = {
+       .parent = &ipg_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+};
+
+/* Main IP interface clock for access to registers */
+static struct clk ipg_clk = {
+       .parent = &ahb_clk,
+       .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ipg_perclk = {
+       .parent = &lp_apm_clk,
+       .get_rate = clk_ipg_per_get_rate,
+       .set_parent = _clk_ipg_per_set_parent,
+};
+
+static struct clk ahb_max_clk = {
+       .parent = &ahb_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+       .enable = _clk_max_enable,
+       .disable = _clk_max_disable,
+};
+
+static struct clk aips_tz1_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk aips_tz2_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk gpc_dvfs_clk = {
+       .enable_reg = MXC_CCM_CCGR5,
+       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+};
+
+static struct clk gpt_32k_clk = {
+       .id = 0,
+       .parent = &ckil_clk,
+};
+
+static struct clk dummy_clk = {
+       .id = 0,
+};
+
+static struct clk emi_slow_clk = {
+       .parent = &pll2_sw_clk,
+       .enable_reg = MXC_CCM_CCGR5,
+       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+       .get_rate = clk_emi_slow_get_rate,
+};
+
+static int clk_ipu_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+
+       /* Enable handshake with IPU when certain clock rates are changed */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       /* Enable handshake with IPU when LPM is entered */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void clk_ipu_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable(clk);
+
+       /* Disable handshake with IPU whe dividers are changed */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       /* Disable handshake with IPU when LPM is entered */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk ahbmux1_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk ipu_sec_clk = {
+       .parent = &emi_fast_clk,
+       .secondary = &ahbmux1_clk,
+};
+
+static struct clk ddr_hf_clk = {
+       .parent = &pll1_sw_clk,
+       .get_rate = _clk_ddr_hf_get_rate,
+};
+
+static struct clk ddr_clk = {
+       .parent = &ddr_hf_clk,
+};
+
+/* clock definitions for MIPI HSC unit which has been removed
+ * from documentation, but not from hardware
+ */
+static int _clk_hsc_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+       /* Handshake with IPU when certain clock rates are changed. */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void _clk_hsc_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable(clk);
+       /* No handshake with HSC as its not enabled. */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk mipi_hsp_clk = {
+       .parent = &ipu_clk,
+       .enable_reg = MXC_CCM_CCGR4,
+       .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+       .enable = _clk_hsc_enable,
+       .disable = _clk_hsc_disable,
+       .secondary = &mipi_hsc1_clk,
+};
+
+#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)  \
+       static struct clk name = {                      \
+               .id             = i,                    \
+               .enable_reg     = er,                   \
+               .enable_shift   = es,                   \
+               .get_rate       = pfx##_get_rate,       \
+               .set_rate       = pfx##_set_rate,       \
+               .round_rate     = pfx##_round_rate,     \
+               .set_parent     = pfx##_set_parent,     \
+               .enable         = _clk_ccgr_enable,     \
+               .disable        = _clk_ccgr_disable,    \
+               .parent         = p,                    \
+               .secondary      = s,                    \
+       }
+
+#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)   \
+       static struct clk name = {                      \
+               .id             = i,                    \
+               .enable_reg     = er,                   \
+               .enable_shift   = es,                   \
+               .get_rate       = pfx##_get_rate,       \
+               .set_rate       = pfx##_set_rate,       \
+               .set_parent     = pfx##_set_parent,     \
+               .enable         = _clk_max_enable,      \
+               .disable        = _clk_max_disable,     \
+               .parent         = p,                    \
+               .secondary      = s,                    \
+       }
+
+#define CLK_GET_RATE(name, nr, bitsname)                               \
+static unsigned long clk_##name##_get_rate(struct clk *clk)            \
+{                                                                      \
+       u32 reg, pred, podf;                                            \
+                                                                       \
+       reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
+       pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
+               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
+       podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
+               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
+                                                                       \
+       return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
+                       (pred + 1) * (podf + 1));                       \
+}
+
+#define CLK_SET_PARENT(name, nr, bitsname)                             \
+static int clk_##name##_set_parent(struct clk *clk, struct clk *parent)        \
+{                                                                      \
+       u32 reg, mux;                                                   \
+                                                                       \
+       mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
+                       &pll3_sw_clk, &lp_apm_clk);                     \
+       reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
+               ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
+       reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
+       __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
+                                                                       \
+       return 0;                                                       \
+}
+
+#define CLK_SET_RATE(name, nr, bitsname)                               \
+static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)  \
+{                                                                      \
+       u32 reg, div, parent_rate;                                      \
+       u32 pre = 0, post = 0;                                          \
+                                                                       \
+       parent_rate = clk_get_rate(clk->parent);                        \
+       div = parent_rate / rate;                                       \
+                                                                       \
+       if ((parent_rate / div) != rate)                                \
+               return -EINVAL;                                         \
+                                                                       \
+       __calc_pre_post_dividers(div, &pre, &post,                      \
+               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
+               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
+                                                                       \
+       /* Set sdhc1 clock divider */                                   \
+       reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
+               ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
+               | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
+       reg |= (post - 1) <<                                            \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
+       reg |= (pre - 1) <<                                             \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
+       __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
+                                                                       \
+       return 0;                                                       \
+}
+
+/* UART */
+CLK_GET_RATE(uart, 1, UART)
+CLK_SET_PARENT(uart, 1, UART)
+
+static struct clk uart_root_clk = {
+       .parent = &pll2_sw_clk,
+       .get_rate = clk_uart_get_rate,
+       .set_parent = clk_uart_set_parent,
+};
+
+/* USBOH3 */
+CLK_GET_RATE(usboh3, 1, USBOH3)
+CLK_SET_PARENT(usboh3, 1, USBOH3)
+
+static struct clk usboh3_clk = {
+       .parent = &pll2_sw_clk,
+       .get_rate = clk_usboh3_get_rate,
+       .set_parent = clk_usboh3_set_parent,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+};
+
+static struct clk usb_ahb_clk = {
+       .parent = &ipg_clk,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+};
+
+static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+
+       if (parent == &pll3_sw_clk)
+               reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
+
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+static struct clk usb_phy1_clk = {
+       .parent = &pll3_sw_clk,
+       .set_parent = clk_usb_phy1_set_parent,
+       .enable = _clk_ccgr_enable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+       .disable = _clk_ccgr_disable,
+};
+
+/* eCSPI */
+CLK_GET_RATE(ecspi, 2, CSPI)
+CLK_SET_PARENT(ecspi, 1, CSPI)
+
+static struct clk ecspi_main_clk = {
+       .parent = &pll3_sw_clk,
+       .get_rate = clk_ecspi_get_rate,
+       .set_parent = clk_ecspi_set_parent,
+};
+
+/* eSDHC */
+CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+
+/* mx51 specific */
+CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+       else if (parent == &esdhc2_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else if (parent == &esdhc2_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+       else if (parent == &esdhc3_mx53_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else if (parent == &esdhc3_mx53_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)         \
+       static struct clk name = {                                      \
+               .id             = i,                                    \
+               .enable_reg     = er,                                   \
+               .enable_shift   = es,                                   \
+               .get_rate       = gr,                                   \
+               .set_rate       = sr,                                   \
+               .enable         = e,                                    \
+               .disable        = d,                                    \
+               .parent         = p,                                    \
+               .secondary      = s,                                    \
+       }
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                    \
+       DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
+
+/* Shared peripheral bus arbiter */
+DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+
+/* UART */
+DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
+       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
+DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
+DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
+DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
+DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
+
+/* GPT */
+DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
+
+DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+
+/* I2C */
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+
+/* FEC */
+DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+
+/* NFC */
+DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
+       clk_nfc, &emi_slow_clk, NULL);
+
+/* SSI */
+DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
+DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
+
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+               &ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+               NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+               &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+               NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+               NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+               NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
+/* SDMA */
+DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
+               NULL, NULL, &ahb_clk, NULL);
+
+/* eSDHC */
+DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
+       clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
+DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
+DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
+       clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc3_clk = {
+       .id = 2,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc3_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+       .id = 3,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc4_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+       .id = 2,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc2_mx53_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+       clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+       .id = 3,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc4_mx53_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc4_ipg_clk,
+};
+
+static struct clk sata_clk = {
+       .parent = &ipg_clk,
+       .enable = _clk_max_enable,
+       .enable_reg = MXC_CCM_CCGR4,
+       .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+       .disable = _clk_max_disable,
+};
+
+static struct clk ahci_phy_clk = {
+       .parent = &usb_phy1_clk,
+};
+
+static struct clk ahci_dma_clk = {
+       .parent = &ahb_clk,
+};
+
+DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
+
+/* IPU */
+DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
+
+DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
+               NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
+               &ddr_clk, NULL);
+
+DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
+               NULL, NULL, &pll3_sw_clk, NULL);
+DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
+               NULL, NULL, &pll3_sw_clk, NULL);
+
+/* PATA */
+DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
+               NULL, NULL, &ipg_clk, &spba_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+       { \
+               .dev_id = d, \
+               .con_id = n, \
+               .clk = &c,   \
+       },
+
+static struct clk_lookup mx51_lookups[] = {
+       /* i.mx51 has the i.mx21 type uart */
+       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+       /* i.mx51 has the i.mx27 type fec */
+       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
+       _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
+       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+       _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
+       _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
+       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
+       _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
+       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+       /* i.mx51 has the i.mx35 type sdma */
+       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+       _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+       _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
+       _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
+       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+       /* i.mx51 has the i.mx35 type cspi */
+       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
+       _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+       _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
+       _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
+       _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
+       _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
+       _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
+       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
+};
+
+static struct clk_lookup mx53_lookups[] = {
+       /* i.mx53 has the i.mx21 type uart */
+       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+       /* i.mx53 has the i.mx25 type fec */
+       _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
+       /* i.mx53 has the i.mx51 type ecspi */
+       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+       /* i.mx53 has the i.mx25 type cspi */
+       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
+       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+       /* i.mx53 has the i.mx35 type sdma */
+       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
+       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
+};
+
+static void clk_tree_init(void)
+{
+       u32 reg;
+
+       ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
+
+       /*
+        * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
+        * 8MHz, its derived from lp_apm.
+        *
+        * FIXME: Verify if true for all boards
+        */
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
+       reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
+       __raw_writel(reg, MXC_CCM_CBCDR);
+}
+
+int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
+                       unsigned long ckih1, unsigned long ckih2)
+{
+       int i;
+
+       external_low_reference = ckil;
+       external_high_reference = ckih1;
+       ckih2_reference = ckih2;
+       oscillator_reference = osc;
+
+       for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
+               clkdev_add(&mx51_lookups[i]);
+
+       clk_tree_init();
+
+       clk_enable(&cpu_clk);
+       clk_enable(&main_bus_clk);
+
+       clk_enable(&iim_clk);
+       imx_print_silicon_rev("i.MX51", mx51_revision());
+       clk_disable(&iim_clk);
+
+       /* move usb_phy_clk to 24MHz */
+       clk_set_parent(&usb_phy1_clk, &osc_clk);
+
+       /* set the usboh3_clk parent to pll2_sw_clk */
+       clk_set_parent(&usboh3_clk, &pll2_sw_clk);
+
+       /* Set SDHC parents to be PLL2 */
+       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+       clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
+
+       /* set SDHC root clock as 166.25MHZ*/
+       clk_set_rate(&esdhc1_clk, 166250000);
+       clk_set_rate(&esdhc2_clk, 166250000);
+
+       /* System timer */
+       mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+               MX51_INT_GPT);
+       return 0;
+}
+
+int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
+                       unsigned long ckih1, unsigned long ckih2)
+{
+       int i;
+
+       external_low_reference = ckil;
+       external_high_reference = ckih1;
+       ckih2_reference = ckih2;
+       oscillator_reference = osc;
+
+       for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
+               clkdev_add(&mx53_lookups[i]);
+
+       clk_tree_init();
+
+       clk_set_parent(&uart_root_clk, &pll3_sw_clk);
+       clk_enable(&cpu_clk);
+       clk_enable(&main_bus_clk);
+
+       clk_enable(&iim_clk);
+       imx_print_silicon_rev("i.MX53", mx53_revision());
+       clk_disable(&iim_clk);
+
+       /* Set SDHC parents to be PLL2 */
+       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+       clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+       /* set SDHC root clock as 200MHZ*/
+       clk_set_rate(&esdhc1_clk, 200000000);
+       clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
+       /* System timer */
+       mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+               MX53_INT_GPT);
+       return 0;
+}
+
+#ifdef CONFIG_OF
+static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+                                  unsigned long *ckih1, unsigned long *ckih2)
+{
+       struct device_node *np;
+
+       /* retrieve the freqency of fixed clocks from device tree */
+       for_each_compatible_node(np, NULL, "fixed-clock") {
+               u32 rate;
+               if (of_property_read_u32(np, "clock-frequency", &rate))
+                       continue;
+
+               if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                       *ckil = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                       *osc = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                       *ckih1 = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+                       *ckih2 = rate;
+       }
+}
+
+int __init mx51_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+}
+
+int __init mx53_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+}
+#endif
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
new file mode 100644 (file)
index 0000000..5e2e7a8
--- /dev/null
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * This file contains the CPU initialization code.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <mach/hardware.h>
+#include <linux/io.h>
+
+static int mx5_cpu_rev = -1;
+
+#define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG 0xB0
+
+static int get_mx51_srev(void)
+{
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+       switch (rev) {
+       case 0x0:
+               return IMX_CHIP_REVISION_2_0;
+       case 0x10:
+               return IMX_CHIP_REVISION_3_0;
+       default:
+               return IMX_CHIP_REVISION_UNKNOWN;
+       }
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx51
+ */
+int mx51_revision(void)
+{
+       if (!cpu_is_mx51())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx51_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx51_revision);
+
+#ifdef CONFIG_NEON
+
+/*
+ * All versions of the silicon before Rev. 3 have broken NEON implementations.
+ * Dependent on link order - so the assumption is that vfp_init is called
+ * before us.
+ */
+static int __init mx51_neon_fixup(void)
+{
+       if (!cpu_is_mx51())
+               return 0;
+
+       if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
+                       (elf_hwcap & HWCAP_NEON)) {
+               elf_hwcap &= ~HWCAP_NEON;
+               pr_info("Turning off NEON support, detected broken NEON implementation\n");
+       }
+       return 0;
+}
+
+late_initcall(mx51_neon_fixup);
+#endif
+
+static int get_mx53_srev(void)
+{
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+       switch (rev) {
+       case 0x0:
+               return IMX_CHIP_REVISION_1_0;
+       case 0x2:
+               return IMX_CHIP_REVISION_2_0;
+       case 0x3:
+               return IMX_CHIP_REVISION_2_1;
+       default:
+               return IMX_CHIP_REVISION_UNKNOWN;
+       }
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx53
+ */
+int mx53_revision(void)
+{
+       if (!cpu_is_mx53())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx53_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx53_revision);
+
+static int get_mx50_srev(void)
+{
+       void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+       u32 rev;
+
+       if (!anatop) {
+               mx5_cpu_rev = -EINVAL;
+               return 0;
+       }
+
+       rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+       rev &= 0xff;
+
+       iounmap(anatop);
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_1_0;
+       else if (rev == 0x1)
+               return IMX_CHIP_REVISION_1_1;
+       return 0;
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+       if (!cpu_is_mx50())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx50_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
+static int __init post_cpu_init(void)
+{
+       unsigned int reg;
+       void __iomem *base;
+
+       if (cpu_is_mx51() || cpu_is_mx53()) {
+               if (cpu_is_mx51())
+                       base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
+               else
+                       base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
+
+               __raw_writel(0x0, base + 0x40);
+               __raw_writel(0x0, base + 0x44);
+               __raw_writel(0x0, base + 0x48);
+               __raw_writel(0x0, base + 0x4C);
+               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+               __raw_writel(reg, base + 0x50);
+
+               if (cpu_is_mx51())
+                       base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
+               else
+                       base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
+
+               __raw_writel(0x0, base + 0x40);
+               __raw_writel(0x0, base + 0x44);
+               __raw_writel(0x0, base + 0x48);
+               __raw_writel(0x0, base + 0x4C);
+               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+               __raw_writel(reg, base + 0x50);
+       }
+
+       return 0;
+}
+
+postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
new file mode 100644 (file)
index 0000000..9d34c3d
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <mach/hardware.h>
+#include <linux/kernel.h>
+
+static struct cpu_op mx51_cpu_op[] = {
+       {
+       .cpu_rate = 160000000,},
+       {
+       .cpu_rate = 800000000,},
+};
+
+struct cpu_op *mx51_get_cpu_op(int *op)
+{
+       *op = ARRAY_SIZE(mx51_cpu_op);
+       return mx51_cpu_op;
+}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
new file mode 100644 (file)
index 0000000..97477fe
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h
new file mode 100644 (file)
index 0000000..5e11ba7
--- /dev/null
@@ -0,0 +1,600 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MX51_CCM_BASE          MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+#define MX51_DPLL1_BASE                MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
+#define MX51_DPLL2_BASE                MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
+#define MX51_DPLL3_BASE                MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
+#define MX51_CORTEXA8_BASE     MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
+#define MX51_GPC_BASE          MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
+
+/*MX53*/
+#define MX53_CCM_BASE          MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
+#define MX53_DPLL1_BASE                MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+#define MX53_DPLL2_BASE                MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+#define MX53_DPLL3_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                 0x00
+#define MXC_PLL_DP_CONFIG              0x04
+#define MXC_PLL_DP_OP                  0x08
+#define MXC_PLL_DP_MFD                 0x0C
+#define MXC_PLL_DP_MFN                 0x10
+#define MXC_PLL_DP_MFNMINUS            0x14
+#define MXC_PLL_DP_MFNPLUS             0x18
+#define MXC_PLL_DP_HFS_OP              0x1C
+#define MXC_PLL_DP_HFS_MFD             0x20
+#define MXC_PLL_DP_HFS_MFN             0x24
+#define MXC_PLL_DP_MFN_TOGC            0x28
+#define MXC_PLL_DP_DESTAT              0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL                0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN     0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE             0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV     0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK        (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET      8
+#define MXC_PLL_DP_CTL_HFSM            0x80
+#define MXC_PLL_DP_CTL_PRE             0x40
+#define MXC_PLL_DP_CTL_UPEN            0x20
+#define MXC_PLL_DP_CTL_RST             0x10
+#define MXC_PLL_DP_CTL_RCP             0x8
+#define MXC_PLL_DP_CTL_PLM             0x4
+#define MXC_PLL_DP_CTL_BRM0            0x2
+#define MXC_PLL_DP_CTL_LRF             0x1
+
+#define MXC_PLL_DP_CONFIG_BIST         0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE       0x4
+#define MXC_PLL_DP_CONFIG_AREN         0x2
+#define MXC_PLL_DP_CONFIG_LDREQ                0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET       4
+#define MXC_PLL_DP_OP_MFI_MASK         (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET       0
+#define MXC_PLL_DP_OP_PDF_MASK         0xF
+
+#define MXC_PLL_DP_MFD_OFFSET          0
+#define MXC_PLL_DP_MFD_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET          0x0
+#define MXC_PLL_DP_MFN_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS    (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN     (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK   0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL      (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN          0x07FFFFFF
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR            (MX51_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR           (MX51_CCM_BASE + 0x04)
+#define MXC_CCM_CSR            (MX51_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR           (MX51_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR          (MX51_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR          (MX51_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR          (MX51_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1         (MX51_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2         (MX51_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1         (MX51_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR         (MX51_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR         (MX51_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR          (MX51_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR         (MX51_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2         (MX51_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3         (MX51_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4         (MX51_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR           (MX51_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR         (MX51_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR           (MX51_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR           (MX51_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR          (MX51_CCM_BASE + 0x54)
+#define MXC_CCM_CISR           (MX51_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR           (MX51_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR          (MX51_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR           (MX51_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0          (MX51_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1          (MX51_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2          (MX51_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3          (MX51_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4          (MX51_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5          (MX51_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6          (MX51_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7          (MX51_CCM_BASE + 0x84)
+
+#define MXC_CCM_CMEOR          (MX51_CCM_BASE + 0x84)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN            (1 << 12)
+#define MXC_CCM_CCR_FPM_MULT_MASK      (1 << 11)
+#define MXC_CCM_CCR_CAMP2_EN           (1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN           (1 << 9)
+#define MXC_CCM_CCR_FPM_EN             (1 << 8)
+#define MXC_CCM_CCR_OSCNT_OFFSET       (0)
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_HSC_HS_MASK       (0x1 << 18)
+#define MXC_CCM_CCDR_IPU_HS_MASK       (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK       (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE  (1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY        (1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY        (1 << 2)
+#define MXC_CCM_CSR_FPM_READY  (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B   (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL                (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET   (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK     (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL_LP_APM      0
+#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
+#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
+#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET  (5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK    (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET  (3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK    (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL   (1 << 2) /* 0: pll1_main_clk,
+                                                   1: step_clk */
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL   (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL   (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET  (0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK    (0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL              (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL           (0x1 << 25)
+#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET                (30)
+#define MXC_CCM_CBCDR_DDR_HF_SEL               (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET          (27)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET          (22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK            (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET                (19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK          (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET                (16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK          (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET          (13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK            (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET          (10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK            (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET          (8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK            (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET      (6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK                (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET      (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK                (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET       (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK         (0x7)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET   (14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK     (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET    (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK      (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET       (10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK         (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET   (8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK     (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET   (6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK     (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET       (4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK         (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET     (14)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK       (0x3 << 14)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL    (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL       (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET         (30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK           (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET         (28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK           (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET          (26)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                 (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET             (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK               (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET           (22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK             (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET     (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK       (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                  (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL       (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                  (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET     (16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK       (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET      (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK                (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK               (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                    (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                    (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET          (8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK            (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL                     (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                 (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET             (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK               (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET            (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK              (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL            (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL            (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)            (26+n*3)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)              (0x7 << (26+n*3))
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET                (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK          (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET                (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK          (0x3 << 22)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET              (20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                        (0x3 << 20)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET             (18)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK               (0x3 << 18)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET             (16)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK               (0x3 << 16)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET            (14)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK              (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET             (12)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK               (0x3 << 12)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET              (10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                        (0x3 << 10)
+#define MXC_CCM_CSCMR2_SLIMBUS_COM                     (0x1 << 9)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET          (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK            (0x7 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM                      (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM                      (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET           (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK             (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET           (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK             (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET    (22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK      (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET    (19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK      (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET     (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK       (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET     (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK       (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET    (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK      (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET             (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK               (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET    (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK      (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          (8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          (6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET            (3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET                (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET                (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              (0x3F)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET                (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET                (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET              (28)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                        (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           (25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x3F << 19)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET           (16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET           (9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET               (6)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                 (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET              (3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                        (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET              (0)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                        (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET            (12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK              (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET            (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK              (0x3F << 6)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET           (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK             (0x7 << 3)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET           (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK             (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET            (25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK              (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET            (19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK              (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET             (16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK               (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET             (9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK               (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET         (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK               (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET             (0)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK               (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET           (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK             (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET           (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK              (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET       (16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK         (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET       (9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK         (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET       (6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK         (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET       (0)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK         (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
+#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY             (1 << 8)
+#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                   (1 << 7)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                        (1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY       (1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                   (1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                 (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                 (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER            (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET       (0)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK         (0x3)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS                (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS                (0x1 << 22)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 21)
+#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS       (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS                (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS       (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS       (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN             (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                (9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK          (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY                    (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC              (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS                    (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM       (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET      (3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET               (0)
+#define MXC_CCM_CLPCR_LPM_MASK                 (0x3)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED                   (0x1 << 25)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED       (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED                   (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED                   (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED                 (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED                 (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED                    (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY                                (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY                       (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY                                (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY                         (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3                          (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2                          (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1                          (0x1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED  (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED              (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED            (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED            (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED            (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED               (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY                   (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CKIH_READY                   (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_FPM_READY                    (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3                     (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2                     (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1                     (0x1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                  (21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                  (16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                  (4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                  (0)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    (0xF)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL                           (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET           (0)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK             (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGRx_CG_MASK                          0x3
+#define MXC_CCM_CCGRx_MOD_OFF                          0x0
+#define MXC_CCM_CCGRx_MOD_ON                           0x3
+#define MXC_CCM_CCGRx_MOD_IDLE                         0x1
+
+#define MXC_CCM_CCGRx_CG15_MASK                                (0x3 << 30)
+#define MXC_CCM_CCGRx_CG14_MASK                                (0x3 << 28)
+#define MXC_CCM_CCGRx_CG13_MASK                                (0x3 << 26)
+#define MXC_CCM_CCGRx_CG12_MASK                                (0x3 << 24)
+#define MXC_CCM_CCGRx_CG11_MASK                                (0x3 << 22)
+#define MXC_CCM_CCGRx_CG10_MASK                                (0x3 << 20)
+#define MXC_CCM_CCGRx_CG9_MASK                         (0x3 << 18)
+#define MXC_CCM_CCGRx_CG8_MASK                         (0x3 << 16)
+#define MXC_CCM_CCGRx_CG5_MASK                         (0x3 << 10)
+#define MXC_CCM_CCGRx_CG4_MASK                         (0x3 << 8)
+#define MXC_CCM_CCGRx_CG3_MASK                         (0x3 << 6)
+#define MXC_CCM_CCGRx_CG2_MASK                         (0x3 << 4)
+#define MXC_CCM_CCGRx_CG1_MASK                         (0x3 << 2)
+#define MXC_CCM_CCGRx_CG0_MASK                         (0x3 << 0)
+
+#define MXC_CCM_CCGRx_CG15_OFFSET                      30
+#define MXC_CCM_CCGRx_CG14_OFFSET                      28
+#define MXC_CCM_CCGRx_CG13_OFFSET                      26
+#define MXC_CCM_CCGRx_CG12_OFFSET                      24
+#define MXC_CCM_CCGRx_CG11_OFFSET                      22
+#define MXC_CCM_CCGRx_CG10_OFFSET                      20
+#define MXC_CCM_CCGRx_CG9_OFFSET                       18
+#define MXC_CCM_CCGRx_CG8_OFFSET                       16
+#define MXC_CCM_CCGRx_CG7_OFFSET                       14
+#define MXC_CCM_CCGRx_CG6_OFFSET                       12
+#define MXC_CCM_CCGRx_CG5_OFFSET                       10
+#define MXC_CCM_CCGRx_CG4_OFFSET                       8
+#define MXC_CCM_CCGRx_CG3_OFFSET                       6
+#define MXC_CCM_CCGRx_CG2_OFFSET                       4
+#define MXC_CCM_CCGRx_CG1_OFFSET                       2
+#define MXC_CCM_CCGRx_CG0_OFFSET                       0
+
+#define MXC_DPTC_LP_BASE       (MX51_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE       (MX51_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE     (MX51_GPC_BASE + 0x180)
+#define MXC_DPTC_PER_BASE      (MX51_GPC_BASE + 0x1C0)
+#define MXC_PGC_IPU_BASE       (MX51_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE       (MX51_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE       (MX51_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE     (MX51_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE      (MX51_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE   (MX51_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE   (MX51_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE  (MX51_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE      (MX51_GPC_BASE + 0x300)
+
+/* CORTEXA8 platform */
+#define MXC_CORTEXA8_PLAT_PVID         (MX51_CORTEXA8_BASE + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC          (MX51_CORTEXA8_BASE + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC          (MX51_CORTEXA8_BASE + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC          (MX51_CORTEXA8_BASE + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC     (MX51_CORTEXA8_BASE + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC         (MX51_CORTEXA8_BASE + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC          (MX51_CORTEXA8_BASE + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC          (MX51_CORTEXA8_BASE + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS          (MX51_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS           (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN           (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1           (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0           (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0           (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1           (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT           (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC           (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR           (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0         (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1         (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0         (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1         (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0            (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1            (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2            (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3            (MXC_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MXC_GPC_CNTR           (MX51_GPC_BASE + 0x0)
+#define MXC_GPC_PGR            (MX51_GPC_BASE + 0x4)
+#define MXC_GPC_VCR            (MX51_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU         (MX51_GPC_BASE + 0xC)
+#define MXC_GPC_NEON           (MX51_GPC_BASE + 0x10)
+#define MXC_GPC_PGR_ARMPG_OFFSET       8
+#define MXC_GPC_PGR_ARMPG_MASK         (3 << 8)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR       (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR       (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR       (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR       (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR       (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR       (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR           1
+#define MXC_SRPGCR_PCR         1
+#define MXC_EMPGCR_PCR         1
+#define MXC_PGSR_PSR           1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM      (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM  (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR   (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR   (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR   (MXC_S