PCI: rockchip: Mark RC as common clock architecture
authorShawn Lin <shawn.lin@rock-chips.com>
Wed, 7 Dec 2016 21:05:58 +0000 (15:05 -0600)
committerBjorn Helgaas <bhelgaas@google.com>
Wed, 7 Dec 2016 21:05:58 +0000 (15:05 -0600)
commitb8ab8e041cc0356323c1e4aee8047ea479650340
treeea3ee0e51fb9849440427e86196eb42d58738e4c
parent4816c4c7b82b55bb46cb9b85ef8e6780fc618592
PCI: rockchip: Mark RC as common clock architecture

The default value of common clock configuration is zero indicating
Rockchip's RC is using asynchronous clock architecture but actually we are
using common clock.  This will confuse some EP drivers if they need some
different settings referring to this value.

Set the Common Clock Configuration bit in the Link Control Register.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/host/pcie-rockchip.c