Merge branch 'async-scsi-resume' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / arch / arm / boot / dts / stih416-pinctrl.dtsi
index 8863c38d35b844c19b36befcbc7a5267d3b8240f..aeea304086eb3b57c5682539643f0d6ca4540c0d 100644 (file)
                                st,retime-pin-mask = <0x7f>;
                        };
 
+                       rc{
+                               pinctrl_ir: ir0 {
+                                       st,pins {
+                                               ir = <&PIO4 0 ALT2 IN>;
+                                       };
+                               };
+                       };
                        sbc_serial1 {
                                pinctrl_sbc_serial1: sbc_serial1 {
                                        st,pins {
                                        };
                                };
                        };
+
+                       gmac1 {
+                               pinctrl_mii1: mii1 {
+                                       st,pins {
+                                               txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+                                               col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
+
+                                               mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
+                                               mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                               crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
+                                               mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+                                               rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+                                               rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                               rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+                                               phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+                                       };
+                               };
+                               pinctrl_rgmii1: rgmii1-0 {
+                                       st,pins {
+                                               txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+                                               txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+                                               txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+                                               txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+                                               txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
+                                               txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
+
+                                               mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+                                               mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
+                                               rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+                                               rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+                                               rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+                                               rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+                                               rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
+                                               rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
+                                               phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
+
+                                               clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+                                       };
+                               };
+                       };
                };
 
                pin-controller-front {
                                        };
                                };
                        };
+
+                       fsm {
+                               pinctrl_fsm: fsm {
+                                       st,pins {
+                                               spi-fsm-clk  = <&PIO12 2 ALT1 OUT>;
+                                               spi-fsm-cs   = <&PIO12 3 ALT1 OUT>;
+                                               spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
+                                               spi-fsm-miso = <&PIO12 5 ALT1 IN>;
+                                               spi-fsm-hol  = <&PIO12 6 ALT1 OUT>;
+                                               spi-fsm-wp   = <&PIO12 7 ALT1 OUT>;
+                                       };
+                               };
+                       };
                };
 
                pin-controller-rear {
                                        };
                                };
                        };
+
+                       gmac0 {
+                               pinctrl_mii0: mii0 {
+                                       st,pins {
+                                               mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
+                                               txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                               txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                               txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+                                               txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
+                                               txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                               crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
+                                               col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
+                                               mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+                                               mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
+
+                                               rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                               rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+                                               phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+                                       };
+                               };
+
+                               pinctrl_gmii0: gmii0 {
+                                       st,pins {
+                                               };
+                               };
+                               pinctrl_rgmii0: rgmii0 {
+                                       st,pins {
+                                                phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
+                                                txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+                                                txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+                                                txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+                                                txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+                                                txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+                                                txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+
+                                                mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+                                                mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+                                                rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+                                                rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
+                                                rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
+                                                rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
+                                                rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+                                                rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+
+                                                clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+                                       };
+                               };
+                       };
                };
 
                pin-controller-fvdp-fe {