18e12a3f7fc302399167bd32712a5ed66fe8fd36
[linux.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25
26 /* Version Information */
27 #define DRIVER_VERSION "v1.06.0 (2014/03/03)"
28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
30 #define MODULENAME "r8152"
31
32 #define R8152_PHY_ID            32
33
34 #define PLA_IDR                 0xc000
35 #define PLA_RCR                 0xc010
36 #define PLA_RMS                 0xc016
37 #define PLA_RXFIFO_CTRL0        0xc0a0
38 #define PLA_RXFIFO_CTRL1        0xc0a4
39 #define PLA_RXFIFO_CTRL2        0xc0a8
40 #define PLA_FMC                 0xc0b4
41 #define PLA_CFG_WOL             0xc0b6
42 #define PLA_TEREDO_CFG          0xc0bc
43 #define PLA_MAR                 0xcd00
44 #define PLA_BACKUP              0xd000
45 #define PAL_BDC_CR              0xd1a0
46 #define PLA_TEREDO_TIMER        0xd2cc
47 #define PLA_REALWOW_TIMER       0xd2e8
48 #define PLA_LEDSEL              0xdd90
49 #define PLA_LED_FEATURE         0xdd92
50 #define PLA_PHYAR               0xde00
51 #define PLA_BOOT_CTRL           0xe004
52 #define PLA_GPHY_INTR_IMR       0xe022
53 #define PLA_EEE_CR              0xe040
54 #define PLA_EEEP_CR             0xe080
55 #define PLA_MAC_PWR_CTRL        0xe0c0
56 #define PLA_MAC_PWR_CTRL2       0xe0ca
57 #define PLA_MAC_PWR_CTRL3       0xe0cc
58 #define PLA_MAC_PWR_CTRL4       0xe0ce
59 #define PLA_WDT6_CTRL           0xe428
60 #define PLA_TCR0                0xe610
61 #define PLA_TCR1                0xe612
62 #define PLA_TXFIFO_CTRL         0xe618
63 #define PLA_RSTTALLY            0xe800
64 #define PLA_CR                  0xe813
65 #define PLA_CRWECR              0xe81c
66 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
67 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
68 #define PLA_CONFIG5             0xe822
69 #define PLA_PHY_PWR             0xe84c
70 #define PLA_OOB_CTRL            0xe84f
71 #define PLA_CPCR                0xe854
72 #define PLA_MISC_0              0xe858
73 #define PLA_MISC_1              0xe85a
74 #define PLA_OCP_GPHY_BASE       0xe86c
75 #define PLA_TALLYCNT            0xe890
76 #define PLA_SFF_STS_7           0xe8de
77 #define PLA_PHYSTATUS           0xe908
78 #define PLA_BP_BA               0xfc26
79 #define PLA_BP_0                0xfc28
80 #define PLA_BP_1                0xfc2a
81 #define PLA_BP_2                0xfc2c
82 #define PLA_BP_3                0xfc2e
83 #define PLA_BP_4                0xfc30
84 #define PLA_BP_5                0xfc32
85 #define PLA_BP_6                0xfc34
86 #define PLA_BP_7                0xfc36
87 #define PLA_BP_EN               0xfc38
88
89 #define USB_U2P3_CTRL           0xb460
90 #define USB_DEV_STAT            0xb808
91 #define USB_USB_CTRL            0xd406
92 #define USB_PHY_CTRL            0xd408
93 #define USB_TX_AGG              0xd40a
94 #define USB_RX_BUF_TH           0xd40c
95 #define USB_USB_TIMER           0xd428
96 #define USB_RX_EARLY_AGG        0xd42c
97 #define USB_PM_CTRL_STATUS      0xd432
98 #define USB_TX_DMA              0xd434
99 #define USB_TOLERANCE           0xd490
100 #define USB_LPM_CTRL            0xd41a
101 #define USB_UPS_CTRL            0xd800
102 #define USB_MISC_0              0xd81a
103 #define USB_POWER_CUT           0xd80a
104 #define USB_AFE_CTRL2           0xd824
105 #define USB_WDT11_CTRL          0xe43c
106 #define USB_BP_BA               0xfc26
107 #define USB_BP_0                0xfc28
108 #define USB_BP_1                0xfc2a
109 #define USB_BP_2                0xfc2c
110 #define USB_BP_3                0xfc2e
111 #define USB_BP_4                0xfc30
112 #define USB_BP_5                0xfc32
113 #define USB_BP_6                0xfc34
114 #define USB_BP_7                0xfc36
115 #define USB_BP_EN               0xfc38
116
117 /* OCP Registers */
118 #define OCP_ALDPS_CONFIG        0x2010
119 #define OCP_EEE_CONFIG1         0x2080
120 #define OCP_EEE_CONFIG2         0x2092
121 #define OCP_EEE_CONFIG3         0x2094
122 #define OCP_BASE_MII            0xa400
123 #define OCP_EEE_AR              0xa41a
124 #define OCP_EEE_DATA            0xa41c
125 #define OCP_PHY_STATUS          0xa420
126 #define OCP_POWER_CFG           0xa430
127 #define OCP_EEE_CFG             0xa432
128 #define OCP_SRAM_ADDR           0xa436
129 #define OCP_SRAM_DATA           0xa438
130 #define OCP_DOWN_SPEED          0xa442
131 #define OCP_EEE_CFG2            0xa5d0
132 #define OCP_ADC_CFG             0xbc06
133
134 /* SRAM Register */
135 #define SRAM_LPF_CFG            0x8012
136 #define SRAM_10M_AMP1           0x8080
137 #define SRAM_10M_AMP2           0x8082
138 #define SRAM_IMPEDANCE          0x8084
139
140 /* PLA_RCR */
141 #define RCR_AAP                 0x00000001
142 #define RCR_APM                 0x00000002
143 #define RCR_AM                  0x00000004
144 #define RCR_AB                  0x00000008
145 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
146
147 /* PLA_RXFIFO_CTRL0 */
148 #define RXFIFO_THR1_NORMAL      0x00080002
149 #define RXFIFO_THR1_OOB         0x01800003
150
151 /* PLA_RXFIFO_CTRL1 */
152 #define RXFIFO_THR2_FULL        0x00000060
153 #define RXFIFO_THR2_HIGH        0x00000038
154 #define RXFIFO_THR2_OOB         0x0000004a
155 #define RXFIFO_THR2_NORMAL      0x00a0
156
157 /* PLA_RXFIFO_CTRL2 */
158 #define RXFIFO_THR3_FULL        0x00000078
159 #define RXFIFO_THR3_HIGH        0x00000048
160 #define RXFIFO_THR3_OOB         0x0000005a
161 #define RXFIFO_THR3_NORMAL      0x0110
162
163 /* PLA_TXFIFO_CTRL */
164 #define TXFIFO_THR_NORMAL       0x00400008
165 #define TXFIFO_THR_NORMAL2      0x01000008
166
167 /* PLA_FMC */
168 #define FMC_FCR_MCU_EN          0x0001
169
170 /* PLA_EEEP_CR */
171 #define EEEP_CR_EEEP_TX         0x0002
172
173 /* PLA_WDT6_CTRL */
174 #define WDT6_SET_MODE           0x0010
175
176 /* PLA_TCR0 */
177 #define TCR0_TX_EMPTY           0x0800
178 #define TCR0_AUTO_FIFO          0x0080
179
180 /* PLA_TCR1 */
181 #define VERSION_MASK            0x7cf0
182
183 /* PLA_RSTTALLY */
184 #define TALLY_RESET             0x0001
185
186 /* PLA_CR */
187 #define CR_RST                  0x10
188 #define CR_RE                   0x08
189 #define CR_TE                   0x04
190
191 /* PLA_CRWECR */
192 #define CRWECR_NORAML           0x00
193 #define CRWECR_CONFIG           0xc0
194
195 /* PLA_OOB_CTRL */
196 #define NOW_IS_OOB              0x80
197 #define TXFIFO_EMPTY            0x20
198 #define RXFIFO_EMPTY            0x10
199 #define LINK_LIST_READY         0x02
200 #define DIS_MCU_CLROOB          0x01
201 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
202
203 /* PLA_MISC_1 */
204 #define RXDY_GATED_EN           0x0008
205
206 /* PLA_SFF_STS_7 */
207 #define RE_INIT_LL              0x8000
208 #define MCU_BORW_EN             0x4000
209
210 /* PLA_CPCR */
211 #define CPCR_RX_VLAN            0x0040
212
213 /* PLA_CFG_WOL */
214 #define MAGIC_EN                0x0001
215
216 /* PLA_TEREDO_CFG */
217 #define TEREDO_SEL              0x8000
218 #define TEREDO_WAKE_MASK        0x7f00
219 #define TEREDO_RS_EVENT_MASK    0x00fe
220 #define OOB_TEREDO_EN           0x0001
221
222 /* PAL_BDC_CR */
223 #define ALDPS_PROXY_MODE        0x0001
224
225 /* PLA_CONFIG34 */
226 #define LINK_ON_WAKE_EN         0x0010
227 #define LINK_OFF_WAKE_EN        0x0008
228
229 /* PLA_CONFIG5 */
230 #define BWF_EN                  0x0040
231 #define MWF_EN                  0x0020
232 #define UWF_EN                  0x0010
233 #define LAN_WAKE_EN             0x0002
234
235 /* PLA_LED_FEATURE */
236 #define LED_MODE_MASK           0x0700
237
238 /* PLA_PHY_PWR */
239 #define TX_10M_IDLE_EN          0x0080
240 #define PFM_PWM_SWITCH          0x0040
241
242 /* PLA_MAC_PWR_CTRL */
243 #define D3_CLK_GATED_EN         0x00004000
244 #define MCU_CLK_RATIO           0x07010f07
245 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
246 #define ALDPS_SPDWN_RATIO       0x0f87
247
248 /* PLA_MAC_PWR_CTRL2 */
249 #define EEE_SPDWN_RATIO         0x8007
250
251 /* PLA_MAC_PWR_CTRL3 */
252 #define PKT_AVAIL_SPDWN_EN      0x0100
253 #define SUSPEND_SPDWN_EN        0x0004
254 #define U1U2_SPDWN_EN           0x0002
255 #define L1_SPDWN_EN             0x0001
256
257 /* PLA_MAC_PWR_CTRL4 */
258 #define PWRSAVE_SPDWN_EN        0x1000
259 #define RXDV_SPDWN_EN           0x0800
260 #define TX10MIDLE_EN            0x0100
261 #define TP100_SPDWN_EN          0x0020
262 #define TP500_SPDWN_EN          0x0010
263 #define TP1000_SPDWN_EN         0x0008
264 #define EEE_SPDWN_EN            0x0001
265
266 /* PLA_GPHY_INTR_IMR */
267 #define GPHY_STS_MSK            0x0001
268 #define SPEED_DOWN_MSK          0x0002
269 #define SPDWN_RXDV_MSK          0x0004
270 #define SPDWN_LINKCHG_MSK       0x0008
271
272 /* PLA_PHYAR */
273 #define PHYAR_FLAG              0x80000000
274
275 /* PLA_EEE_CR */
276 #define EEE_RX_EN               0x0001
277 #define EEE_TX_EN               0x0002
278
279 /* PLA_BOOT_CTRL */
280 #define AUTOLOAD_DONE           0x0002
281
282 /* USB_DEV_STAT */
283 #define STAT_SPEED_MASK         0x0006
284 #define STAT_SPEED_HIGH         0x0000
285 #define STAT_SPEED_FULL         0x0001
286
287 /* USB_TX_AGG */
288 #define TX_AGG_MAX_THRESHOLD    0x03
289
290 /* USB_RX_BUF_TH */
291 #define RX_THR_SUPPER           0x0c350180
292 #define RX_THR_HIGH             0x7a120180
293 #define RX_THR_SLOW             0xffff0180
294
295 /* USB_TX_DMA */
296 #define TEST_MODE_DISABLE       0x00000001
297 #define TX_SIZE_ADJUST1         0x00000100
298
299 /* USB_UPS_CTRL */
300 #define POWER_CUT               0x0100
301
302 /* USB_PM_CTRL_STATUS */
303 #define RESUME_INDICATE         0x0001
304
305 /* USB_USB_CTRL */
306 #define RX_AGG_DISABLE          0x0010
307
308 /* USB_U2P3_CTRL */
309 #define U2P3_ENABLE             0x0001
310
311 /* USB_POWER_CUT */
312 #define PWR_EN                  0x0001
313 #define PHASE2_EN               0x0008
314
315 /* USB_MISC_0 */
316 #define PCUT_STATUS             0x0001
317
318 /* USB_RX_EARLY_AGG */
319 #define EARLY_AGG_SUPPER        0x0e832981
320 #define EARLY_AGG_HIGH          0x0e837a12
321 #define EARLY_AGG_SLOW          0x0e83ffff
322
323 /* USB_WDT11_CTRL */
324 #define TIMER11_EN              0x0001
325
326 /* USB_LPM_CTRL */
327 #define LPM_TIMER_MASK          0x0c
328 #define LPM_TIMER_500MS         0x04    /* 500 ms */
329 #define LPM_TIMER_500US         0x0c    /* 500 us */
330
331 /* USB_AFE_CTRL2 */
332 #define SEN_VAL_MASK            0xf800
333 #define SEN_VAL_NORMAL          0xa000
334 #define SEL_RXIDLE              0x0100
335
336 /* OCP_ALDPS_CONFIG */
337 #define ENPWRSAVE               0x8000
338 #define ENPDNPS                 0x0200
339 #define LINKENA                 0x0100
340 #define DIS_SDSAVE              0x0010
341
342 /* OCP_PHY_STATUS */
343 #define PHY_STAT_MASK           0x0007
344 #define PHY_STAT_LAN_ON         3
345 #define PHY_STAT_PWRDN          5
346
347 /* OCP_POWER_CFG */
348 #define EEE_CLKDIV_EN           0x8000
349 #define EN_ALDPS                0x0004
350 #define EN_10M_PLLOFF           0x0001
351
352 /* OCP_EEE_CONFIG1 */
353 #define RG_TXLPI_MSK_HFDUP      0x8000
354 #define RG_MATCLR_EN            0x4000
355 #define EEE_10_CAP              0x2000
356 #define EEE_NWAY_EN             0x1000
357 #define TX_QUIET_EN             0x0200
358 #define RX_QUIET_EN             0x0100
359 #define SDRISETIME              0x0010  /* bit 4 ~ 6 */
360 #define RG_RXLPI_MSK_HFDUP      0x0008
361 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
362
363 /* OCP_EEE_CONFIG2 */
364 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
365 #define RG_DACQUIET_EN          0x0400
366 #define RG_LDVQUIET_EN          0x0200
367 #define RG_CKRSEL               0x0020
368 #define RG_EEEPRG_EN            0x0010
369
370 /* OCP_EEE_CONFIG3 */
371 #define FST_SNR_EYE_R           0x1500  /* bit 7 ~ 15 */
372 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
373 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
374
375 /* OCP_EEE_AR */
376 /* bit[15:14] function */
377 #define FUN_ADDR                0x0000
378 #define FUN_DATA                0x4000
379 /* bit[4:0] device addr */
380 #define DEVICE_ADDR             0x0007
381
382 /* OCP_EEE_DATA */
383 #define EEE_ADDR                0x003C
384 #define EEE_DATA                0x0002
385
386 /* OCP_EEE_CFG */
387 #define CTAP_SHORT_EN           0x0040
388 #define EEE10_EN                0x0010
389
390 /* OCP_DOWN_SPEED */
391 #define EN_10M_BGOFF            0x0080
392
393 /* OCP_EEE_CFG2 */
394 #define MY1000_EEE              0x0004
395 #define MY100_EEE               0x0002
396
397 /* OCP_ADC_CFG */
398 #define CKADSEL_L               0x0100
399 #define ADC_EN                  0x0080
400 #define EN_EMI_L                0x0040
401
402 /* SRAM_LPF_CFG */
403 #define LPF_AUTO_TUNE           0x8000
404
405 /* SRAM_10M_AMP1 */
406 #define GDAC_IB_UPALL           0x0008
407
408 /* SRAM_10M_AMP2 */
409 #define AMP_DN                  0x0200
410
411 /* SRAM_IMPEDANCE */
412 #define RX_DRIVING_MASK         0x6000
413
414 enum rtl_register_content {
415         _1000bps        = 0x10,
416         _100bps         = 0x08,
417         _10bps          = 0x04,
418         LINK_STATUS     = 0x02,
419         FULL_DUP        = 0x01,
420 };
421
422 #define RTL8152_MAX_TX          10
423 #define RTL8152_MAX_RX          10
424 #define INTBUFSIZE              2
425 #define CRC_SIZE                4
426 #define TX_ALIGN                4
427 #define RX_ALIGN                8
428
429 #define INTR_LINK               0x0004
430
431 #define RTL8152_REQT_READ       0xc0
432 #define RTL8152_REQT_WRITE      0x40
433 #define RTL8152_REQ_GET_REGS    0x05
434 #define RTL8152_REQ_SET_REGS    0x05
435
436 #define BYTE_EN_DWORD           0xff
437 #define BYTE_EN_WORD            0x33
438 #define BYTE_EN_BYTE            0x11
439 #define BYTE_EN_SIX_BYTES       0x3f
440 #define BYTE_EN_START_MASK      0x0f
441 #define BYTE_EN_END_MASK        0xf0
442
443 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
444 #define RTL8152_TX_TIMEOUT      (HZ)
445
446 /* rtl8152 flags */
447 enum rtl8152_flags {
448         RTL8152_UNPLUG = 0,
449         RTL8152_SET_RX_MODE,
450         WORK_ENABLE,
451         RTL8152_LINK_CHG,
452         SELECTIVE_SUSPEND,
453         PHY_RESET,
454         SCHEDULE_TASKLET,
455 };
456
457 /* Define these values to match your device */
458 #define VENDOR_ID_REALTEK               0x0bda
459 #define PRODUCT_ID_RTL8152              0x8152
460 #define PRODUCT_ID_RTL8153              0x8153
461
462 #define VENDOR_ID_SAMSUNG               0x04e8
463 #define PRODUCT_ID_SAMSUNG              0xa101
464
465 #define MCU_TYPE_PLA                    0x0100
466 #define MCU_TYPE_USB                    0x0000
467
468 #define REALTEK_USB_DEVICE(vend, prod)  \
469         USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
470
471 struct tally_counter {
472         __le64  tx_packets;
473         __le64  rx_packets;
474         __le64  tx_errors;
475         __le32  rx_errors;
476         __le16  rx_missed;
477         __le16  align_errors;
478         __le32  tx_one_collision;
479         __le32  tx_multi_collision;
480         __le64  rx_unicast;
481         __le64  rx_broadcast;
482         __le32  rx_multicast;
483         __le16  tx_aborted;
484         __le16  tx_underun;
485 };
486
487 struct rx_desc {
488         __le32 opts1;
489 #define RX_LEN_MASK                     0x7fff
490
491         __le32 opts2;
492 #define RD_UDP_CS                       (1 << 23)
493 #define RD_TCP_CS                       (1 << 22)
494 #define RD_IPV6_CS                      (1 << 20)
495 #define RD_IPV4_CS                      (1 << 19)
496
497         __le32 opts3;
498 #define IPF                             (1 << 23) /* IP checksum fail */
499 #define UDPF                            (1 << 22) /* UDP checksum fail */
500 #define TCPF                            (1 << 21) /* TCP checksum fail */
501
502         __le32 opts4;
503         __le32 opts5;
504         __le32 opts6;
505 };
506
507 struct tx_desc {
508         __le32 opts1;
509 #define TX_FS                   (1 << 31) /* First segment of a packet */
510 #define TX_LS                   (1 << 30) /* Final segment of a packet */
511 #define GTSENDV4                (1 << 28)
512 #define GTSENDV6                (1 << 27)
513 #define GTTCPHO_SHIFT           18
514 #define GTTCPHO_MAX             0x7fU
515 #define TX_LEN_MAX              0x3ffffU
516
517         __le32 opts2;
518 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
519 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
520 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
521 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
522 #define MSS_SHIFT               17
523 #define MSS_MAX                 0x7ffU
524 #define TCPHO_SHIFT             17
525 #define TCPHO_MAX               0x7ffU
526 };
527
528 struct r8152;
529
530 struct rx_agg {
531         struct list_head list;
532         struct urb *urb;
533         struct r8152 *context;
534         void *buffer;
535         void *head;
536 };
537
538 struct tx_agg {
539         struct list_head list;
540         struct urb *urb;
541         struct r8152 *context;
542         void *buffer;
543         void *head;
544         u32 skb_num;
545         u32 skb_len;
546 };
547
548 struct r8152 {
549         unsigned long flags;
550         struct usb_device *udev;
551         struct tasklet_struct tl;
552         struct usb_interface *intf;
553         struct net_device *netdev;
554         struct urb *intr_urb;
555         struct tx_agg tx_info[RTL8152_MAX_TX];
556         struct rx_agg rx_info[RTL8152_MAX_RX];
557         struct list_head rx_done, tx_free;
558         struct sk_buff_head tx_queue;
559         spinlock_t rx_lock, tx_lock;
560         struct delayed_work schedule;
561         struct mii_if_info mii;
562
563         struct rtl_ops {
564                 void (*init)(struct r8152 *);
565                 int (*enable)(struct r8152 *);
566                 void (*disable)(struct r8152 *);
567                 void (*up)(struct r8152 *);
568                 void (*down)(struct r8152 *);
569                 void (*unload)(struct r8152 *);
570         } rtl_ops;
571
572         int intr_interval;
573         u32 saved_wolopts;
574         u32 msg_enable;
575         u32 tx_qlen;
576         u16 ocp_base;
577         u8 *intr_buff;
578         u8 version;
579         u8 speed;
580 };
581
582 enum rtl_version {
583         RTL_VER_UNKNOWN = 0,
584         RTL_VER_01,
585         RTL_VER_02,
586         RTL_VER_03,
587         RTL_VER_04,
588         RTL_VER_05,
589         RTL_VER_MAX
590 };
591
592 enum tx_csum_stat {
593         TX_CSUM_SUCCESS = 0,
594         TX_CSUM_TSO,
595         TX_CSUM_NONE
596 };
597
598 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
599  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
600  */
601 static const int multicast_filter_limit = 32;
602 static unsigned int rx_buf_sz = 16384;
603
604 #define RTL_LIMITED_TSO_SIZE    (rx_buf_sz - sizeof(struct tx_desc) - \
605                                  VLAN_ETH_HLEN - VLAN_HLEN)
606
607 static
608 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
609 {
610         int ret;
611         void *tmp;
612
613         tmp = kmalloc(size, GFP_KERNEL);
614         if (!tmp)
615                 return -ENOMEM;
616
617         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
618                                RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
619                                value, index, tmp, size, 500);
620
621         memcpy(data, tmp, size);
622         kfree(tmp);
623
624         return ret;
625 }
626
627 static
628 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
629 {
630         int ret;
631         void *tmp;
632
633         tmp = kmalloc(size, GFP_KERNEL);
634         if (!tmp)
635                 return -ENOMEM;
636
637         memcpy(tmp, data, size);
638
639         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
640                                RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
641                                value, index, tmp, size, 500);
642
643         kfree(tmp);
644
645         return ret;
646 }
647
648 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
649                                 void *data, u16 type)
650 {
651         u16 limit = 64;
652         int ret = 0;
653
654         if (test_bit(RTL8152_UNPLUG, &tp->flags))
655                 return -ENODEV;
656
657         /* both size and indix must be 4 bytes align */
658         if ((size & 3) || !size || (index & 3) || !data)
659                 return -EPERM;
660
661         if ((u32)index + (u32)size > 0xffff)
662                 return -EPERM;
663
664         while (size) {
665                 if (size > limit) {
666                         ret = get_registers(tp, index, type, limit, data);
667                         if (ret < 0)
668                                 break;
669
670                         index += limit;
671                         data += limit;
672                         size -= limit;
673                 } else {
674                         ret = get_registers(tp, index, type, size, data);
675                         if (ret < 0)
676                                 break;
677
678                         index += size;
679                         data += size;
680                         size = 0;
681                         break;
682                 }
683         }
684
685         return ret;
686 }
687
688 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
689                                 u16 size, void *data, u16 type)
690 {
691         int ret;
692         u16 byteen_start, byteen_end, byen;
693         u16 limit = 512;
694
695         if (test_bit(RTL8152_UNPLUG, &tp->flags))
696                 return -ENODEV;
697
698         /* both size and indix must be 4 bytes align */
699         if ((size & 3) || !size || (index & 3) || !data)
700                 return -EPERM;
701
702         if ((u32)index + (u32)size > 0xffff)
703                 return -EPERM;
704
705         byteen_start = byteen & BYTE_EN_START_MASK;
706         byteen_end = byteen & BYTE_EN_END_MASK;
707
708         byen = byteen_start | (byteen_start << 4);
709         ret = set_registers(tp, index, type | byen, 4, data);
710         if (ret < 0)
711                 goto error1;
712
713         index += 4;
714         data += 4;
715         size -= 4;
716
717         if (size) {
718                 size -= 4;
719
720                 while (size) {
721                         if (size > limit) {
722                                 ret = set_registers(tp, index,
723                                         type | BYTE_EN_DWORD,
724                                         limit, data);
725                                 if (ret < 0)
726                                         goto error1;
727
728                                 index += limit;
729                                 data += limit;
730                                 size -= limit;
731                         } else {
732                                 ret = set_registers(tp, index,
733                                         type | BYTE_EN_DWORD,
734                                         size, data);
735                                 if (ret < 0)
736                                         goto error1;
737
738                                 index += size;
739                                 data += size;
740                                 size = 0;
741                                 break;
742                         }
743                 }
744
745                 byen = byteen_end | (byteen_end >> 4);
746                 ret = set_registers(tp, index, type | byen, 4, data);
747                 if (ret < 0)
748                         goto error1;
749         }
750
751 error1:
752         return ret;
753 }
754
755 static inline
756 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
757 {
758         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
759 }
760
761 static inline
762 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
763 {
764         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
765 }
766
767 static inline
768 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
769 {
770         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
771 }
772
773 static inline
774 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
775 {
776         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
777 }
778
779 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
780 {
781         __le32 data;
782
783         generic_ocp_read(tp, index, sizeof(data), &data, type);
784
785         return __le32_to_cpu(data);
786 }
787
788 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
789 {
790         __le32 tmp = __cpu_to_le32(data);
791
792         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
793 }
794
795 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
796 {
797         u32 data;
798         __le32 tmp;
799         u8 shift = index & 2;
800
801         index &= ~3;
802
803         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
804
805         data = __le32_to_cpu(tmp);
806         data >>= (shift * 8);
807         data &= 0xffff;
808
809         return (u16)data;
810 }
811
812 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
813 {
814         u32 mask = 0xffff;
815         __le32 tmp;
816         u16 byen = BYTE_EN_WORD;
817         u8 shift = index & 2;
818
819         data &= mask;
820
821         if (index & 2) {
822                 byen <<= shift;
823                 mask <<= (shift * 8);
824                 data <<= (shift * 8);
825                 index &= ~3;
826         }
827
828         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
829
830         data |= __le32_to_cpu(tmp) & ~mask;
831         tmp = __cpu_to_le32(data);
832
833         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
834 }
835
836 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
837 {
838         u32 data;
839         __le32 tmp;
840         u8 shift = index & 3;
841
842         index &= ~3;
843
844         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
845
846         data = __le32_to_cpu(tmp);
847         data >>= (shift * 8);
848         data &= 0xff;
849
850         return (u8)data;
851 }
852
853 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
854 {
855         u32 mask = 0xff;
856         __le32 tmp;
857         u16 byen = BYTE_EN_BYTE;
858         u8 shift = index & 3;
859
860         data &= mask;
861
862         if (index & 3) {
863                 byen <<= shift;
864                 mask <<= (shift * 8);
865                 data <<= (shift * 8);
866                 index &= ~3;
867         }
868
869         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
870
871         data |= __le32_to_cpu(tmp) & ~mask;
872         tmp = __cpu_to_le32(data);
873
874         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
875 }
876
877 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
878 {
879         u16 ocp_base, ocp_index;
880
881         ocp_base = addr & 0xf000;
882         if (ocp_base != tp->ocp_base) {
883                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
884                 tp->ocp_base = ocp_base;
885         }
886
887         ocp_index = (addr & 0x0fff) | 0xb000;
888         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
889 }
890
891 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
892 {
893         u16 ocp_base, ocp_index;
894
895         ocp_base = addr & 0xf000;
896         if (ocp_base != tp->ocp_base) {
897                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
898                 tp->ocp_base = ocp_base;
899         }
900
901         ocp_index = (addr & 0x0fff) | 0xb000;
902         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
903 }
904
905 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
906 {
907         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
908 }
909
910 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
911 {
912         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
913 }
914
915 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
916 {
917         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
918         ocp_reg_write(tp, OCP_SRAM_DATA, data);
919 }
920
921 static u16 sram_read(struct r8152 *tp, u16 addr)
922 {
923         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
924         return ocp_reg_read(tp, OCP_SRAM_DATA);
925 }
926
927 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
928 {
929         struct r8152 *tp = netdev_priv(netdev);
930         int ret;
931
932         if (phy_id != R8152_PHY_ID)
933                 return -EINVAL;
934
935         ret = usb_autopm_get_interface(tp->intf);
936         if (ret < 0)
937                 goto out;
938
939         ret = r8152_mdio_read(tp, reg);
940
941         usb_autopm_put_interface(tp->intf);
942
943 out:
944         return ret;
945 }
946
947 static
948 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
949 {
950         struct r8152 *tp = netdev_priv(netdev);
951
952         if (phy_id != R8152_PHY_ID)
953                 return;
954
955         if (usb_autopm_get_interface(tp->intf) < 0)
956                 return;
957
958         r8152_mdio_write(tp, reg, val);
959
960         usb_autopm_put_interface(tp->intf);
961 }
962
963 static
964 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
965
966 static inline void set_ethernet_addr(struct r8152 *tp)
967 {
968         struct net_device *dev = tp->netdev;
969         int ret;
970         u8 node_id[8] = {0};
971
972         if (tp->version == RTL_VER_01)
973                 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
974         else
975                 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
976
977         if (ret < 0) {
978                 netif_notice(tp, probe, dev, "inet addr fail\n");
979         } else {
980                 if (tp->version != RTL_VER_01) {
981                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
982                                        CRWECR_CONFIG);
983                         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
984                                       sizeof(node_id), node_id);
985                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
986                                        CRWECR_NORAML);
987                 }
988
989                 memcpy(dev->dev_addr, node_id, dev->addr_len);
990                 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
991         }
992 }
993
994 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
995 {
996         struct r8152 *tp = netdev_priv(netdev);
997         struct sockaddr *addr = p;
998
999         if (!is_valid_ether_addr(addr->sa_data))
1000                 return -EADDRNOTAVAIL;
1001
1002         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1003
1004         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1005         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1006         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1007
1008         return 0;
1009 }
1010
1011 static void read_bulk_callback(struct urb *urb)
1012 {
1013         struct net_device *netdev;
1014         int status = urb->status;
1015         struct rx_agg *agg;
1016         struct r8152 *tp;
1017         int result;
1018
1019         agg = urb->context;
1020         if (!agg)
1021                 return;
1022
1023         tp = agg->context;
1024         if (!tp)
1025                 return;
1026
1027         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1028                 return;
1029
1030         if (!test_bit(WORK_ENABLE, &tp->flags))
1031                 return;
1032
1033         netdev = tp->netdev;
1034
1035         /* When link down, the driver would cancel all bulks. */
1036         /* This avoid the re-submitting bulk */
1037         if (!netif_carrier_ok(netdev))
1038                 return;
1039
1040         usb_mark_last_busy(tp->udev);
1041
1042         switch (status) {
1043         case 0:
1044                 if (urb->actual_length < ETH_ZLEN)
1045                         break;
1046
1047                 spin_lock(&tp->rx_lock);
1048                 list_add_tail(&agg->list, &tp->rx_done);
1049                 spin_unlock(&tp->rx_lock);
1050                 tasklet_schedule(&tp->tl);
1051                 return;
1052         case -ESHUTDOWN:
1053                 set_bit(RTL8152_UNPLUG, &tp->flags);
1054                 netif_device_detach(tp->netdev);
1055                 return;
1056         case -ENOENT:
1057                 return; /* the urb is in unlink state */
1058         case -ETIME:
1059                 if (net_ratelimit())
1060                         netdev_warn(netdev, "maybe reset is needed?\n");
1061                 break;
1062         default:
1063                 if (net_ratelimit())
1064                         netdev_warn(netdev, "Rx status %d\n", status);
1065                 break;
1066         }
1067
1068         result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1069         if (result == -ENODEV) {
1070                 netif_device_detach(tp->netdev);
1071         } else if (result) {
1072                 spin_lock(&tp->rx_lock);
1073                 list_add_tail(&agg->list, &tp->rx_done);
1074                 spin_unlock(&tp->rx_lock);
1075                 tasklet_schedule(&tp->tl);
1076         }
1077 }
1078
1079 static void write_bulk_callback(struct urb *urb)
1080 {
1081         struct net_device_stats *stats;
1082         struct net_device *netdev;
1083         struct tx_agg *agg;
1084         struct r8152 *tp;
1085         int status = urb->status;
1086
1087         agg = urb->context;
1088         if (!agg)
1089                 return;
1090
1091         tp = agg->context;
1092         if (!tp)
1093                 return;
1094
1095         netdev = tp->netdev;
1096         stats = &netdev->stats;
1097         if (status) {
1098                 if (net_ratelimit())
1099                         netdev_warn(netdev, "Tx status %d\n", status);
1100                 stats->tx_errors += agg->skb_num;
1101         } else {
1102                 stats->tx_packets += agg->skb_num;
1103                 stats->tx_bytes += agg->skb_len;
1104         }
1105
1106         spin_lock(&tp->tx_lock);
1107         list_add_tail(&agg->list, &tp->tx_free);
1108         spin_unlock(&tp->tx_lock);
1109
1110         usb_autopm_put_interface_async(tp->intf);
1111
1112         if (!netif_carrier_ok(netdev))
1113                 return;
1114
1115         if (!test_bit(WORK_ENABLE, &tp->flags))
1116                 return;
1117
1118         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119                 return;
1120
1121         if (!skb_queue_empty(&tp->tx_queue))
1122                 tasklet_schedule(&tp->tl);
1123 }
1124
1125 static void intr_callback(struct urb *urb)
1126 {
1127         struct r8152 *tp;
1128         __le16 *d;
1129         int status = urb->status;
1130         int res;
1131
1132         tp = urb->context;
1133         if (!tp)
1134                 return;
1135
1136         if (!test_bit(WORK_ENABLE, &tp->flags))
1137                 return;
1138
1139         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1140                 return;
1141
1142         switch (status) {
1143         case 0:                 /* success */
1144                 break;
1145         case -ECONNRESET:       /* unlink */
1146         case -ESHUTDOWN:
1147                 netif_device_detach(tp->netdev);
1148         case -ENOENT:
1149                 return;
1150         case -EOVERFLOW:
1151                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1152                 goto resubmit;
1153         /* -EPIPE:  should clear the halt */
1154         default:
1155                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1156                 goto resubmit;
1157         }
1158
1159         d = urb->transfer_buffer;
1160         if (INTR_LINK & __le16_to_cpu(d[0])) {
1161                 if (!(tp->speed & LINK_STATUS)) {
1162                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1163                         schedule_delayed_work(&tp->schedule, 0);
1164                 }
1165         } else {
1166                 if (tp->speed & LINK_STATUS) {
1167                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1168                         schedule_delayed_work(&tp->schedule, 0);
1169                 }
1170         }
1171
1172 resubmit:
1173         res = usb_submit_urb(urb, GFP_ATOMIC);
1174         if (res == -ENODEV)
1175                 netif_device_detach(tp->netdev);
1176         else if (res)
1177                 netif_err(tp, intr, tp->netdev,
1178                           "can't resubmit intr, status %d\n", res);
1179 }
1180
1181 static inline void *rx_agg_align(void *data)
1182 {
1183         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1184 }
1185
1186 static inline void *tx_agg_align(void *data)
1187 {
1188         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1189 }
1190
1191 static void free_all_mem(struct r8152 *tp)
1192 {
1193         int i;
1194
1195         for (i = 0; i < RTL8152_MAX_RX; i++) {
1196                 usb_free_urb(tp->rx_info[i].urb);
1197                 tp->rx_info[i].urb = NULL;
1198
1199                 kfree(tp->rx_info[i].buffer);
1200                 tp->rx_info[i].buffer = NULL;
1201                 tp->rx_info[i].head = NULL;
1202         }
1203
1204         for (i = 0; i < RTL8152_MAX_TX; i++) {
1205                 usb_free_urb(tp->tx_info[i].urb);
1206                 tp->tx_info[i].urb = NULL;
1207
1208                 kfree(tp->tx_info[i].buffer);
1209                 tp->tx_info[i].buffer = NULL;
1210                 tp->tx_info[i].head = NULL;
1211         }
1212
1213         usb_free_urb(tp->intr_urb);
1214         tp->intr_urb = NULL;
1215
1216         kfree(tp->intr_buff);
1217         tp->intr_buff = NULL;
1218 }
1219
1220 static int alloc_all_mem(struct r8152 *tp)
1221 {
1222         struct net_device *netdev = tp->netdev;
1223         struct usb_interface *intf = tp->intf;
1224         struct usb_host_interface *alt = intf->cur_altsetting;
1225         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1226         struct urb *urb;
1227         int node, i;
1228         u8 *buf;
1229
1230         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1231
1232         spin_lock_init(&tp->rx_lock);
1233         spin_lock_init(&tp->tx_lock);
1234         INIT_LIST_HEAD(&tp->rx_done);
1235         INIT_LIST_HEAD(&tp->tx_free);
1236         skb_queue_head_init(&tp->tx_queue);
1237
1238         for (i = 0; i < RTL8152_MAX_RX; i++) {
1239                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1240                 if (!buf)
1241                         goto err1;
1242
1243                 if (buf != rx_agg_align(buf)) {
1244                         kfree(buf);
1245                         buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1246                                            node);
1247                         if (!buf)
1248                                 goto err1;
1249                 }
1250
1251                 urb = usb_alloc_urb(0, GFP_KERNEL);
1252                 if (!urb) {
1253                         kfree(buf);
1254                         goto err1;
1255                 }
1256
1257                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1258                 tp->rx_info[i].context = tp;
1259                 tp->rx_info[i].urb = urb;
1260                 tp->rx_info[i].buffer = buf;
1261                 tp->rx_info[i].head = rx_agg_align(buf);
1262         }
1263
1264         for (i = 0; i < RTL8152_MAX_TX; i++) {
1265                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1266                 if (!buf)
1267                         goto err1;
1268
1269                 if (buf != tx_agg_align(buf)) {
1270                         kfree(buf);
1271                         buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1272                                            node);
1273                         if (!buf)
1274                                 goto err1;
1275                 }
1276
1277                 urb = usb_alloc_urb(0, GFP_KERNEL);
1278                 if (!urb) {
1279                         kfree(buf);
1280                         goto err1;
1281                 }
1282
1283                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1284                 tp->tx_info[i].context = tp;
1285                 tp->tx_info[i].urb = urb;
1286                 tp->tx_info[i].buffer = buf;
1287                 tp->tx_info[i].head = tx_agg_align(buf);
1288
1289                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1290         }
1291
1292         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1293         if (!tp->intr_urb)
1294                 goto err1;
1295
1296         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1297         if (!tp->intr_buff)
1298                 goto err1;
1299
1300         tp->intr_interval = (int)ep_intr->desc.bInterval;
1301         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1302                      tp->intr_buff, INTBUFSIZE, intr_callback,
1303                      tp, tp->intr_interval);
1304
1305         return 0;
1306
1307 err1:
1308         free_all_mem(tp);
1309         return -ENOMEM;
1310 }
1311
1312 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1313 {
1314         struct tx_agg *agg = NULL;
1315         unsigned long flags;
1316
1317         if (list_empty(&tp->tx_free))
1318                 return NULL;
1319
1320         spin_lock_irqsave(&tp->tx_lock, flags);
1321         if (!list_empty(&tp->tx_free)) {
1322                 struct list_head *cursor;
1323
1324                 cursor = tp->tx_free.next;
1325                 list_del_init(cursor);
1326                 agg = list_entry(cursor, struct tx_agg, list);
1327         }
1328         spin_unlock_irqrestore(&tp->tx_lock, flags);
1329
1330         return agg;
1331 }
1332
1333 static inline __be16 get_protocol(struct sk_buff *skb)
1334 {
1335         __be16 protocol;
1336
1337         if (skb->protocol == htons(ETH_P_8021Q))
1338                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1339         else
1340                 protocol = skb->protocol;
1341
1342         return protocol;
1343 }
1344
1345 /*
1346  * r8152_csum_workaround()
1347  * The hw limites the value the transport offset. When the offset is out of the
1348  * range, calculate the checksum by sw.
1349  */
1350 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1351                                   struct sk_buff_head *list)
1352 {
1353         if (skb_shinfo(skb)->gso_size) {
1354                 netdev_features_t features = tp->netdev->features;
1355                 struct sk_buff_head seg_list;
1356                 struct sk_buff *segs, *nskb;
1357
1358                 features &= ~(NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO);
1359                 segs = skb_gso_segment(skb, features);
1360                 if (IS_ERR(segs) || !segs)
1361                         goto drop;
1362
1363                 __skb_queue_head_init(&seg_list);
1364
1365                 do {
1366                         nskb = segs;
1367                         segs = segs->next;
1368                         nskb->next = NULL;
1369                         __skb_queue_tail(&seg_list, nskb);
1370                 } while (segs);
1371
1372                 skb_queue_splice(&seg_list, list);
1373                 dev_kfree_skb(skb);
1374         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1375                 if (skb_checksum_help(skb) < 0)
1376                         goto drop;
1377
1378                 __skb_queue_head(list, skb);
1379         } else {
1380                 struct net_device_stats *stats;
1381
1382 drop:
1383                 stats = &tp->netdev->stats;
1384                 stats->tx_dropped++;
1385                 dev_kfree_skb(skb);
1386         }
1387 }
1388
1389 /*
1390  * msdn_giant_send_check()
1391  * According to the document of microsoft, the TCP Pseudo Header excludes the
1392  * packet length for IPv6 TCP large packets.
1393  */
1394 static int msdn_giant_send_check(struct sk_buff *skb)
1395 {
1396         const struct ipv6hdr *ipv6h;
1397         struct tcphdr *th;
1398         int ret;
1399
1400         ret = skb_cow_head(skb, 0);
1401         if (ret)
1402                 return ret;
1403
1404         ipv6h = ipv6_hdr(skb);
1405         th = tcp_hdr(skb);
1406
1407         th->check = 0;
1408         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1409
1410         return ret;
1411 }
1412
1413 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1414                          struct sk_buff *skb, u32 len, u32 transport_offset)
1415 {
1416         u32 mss = skb_shinfo(skb)->gso_size;
1417         u32 opts1, opts2 = 0;
1418         int ret = TX_CSUM_SUCCESS;
1419
1420         WARN_ON_ONCE(len > TX_LEN_MAX);
1421
1422         opts1 = len | TX_FS | TX_LS;
1423
1424         if (mss) {
1425                 if (transport_offset > GTTCPHO_MAX) {
1426                         netif_warn(tp, tx_err, tp->netdev,
1427                                    "Invalid transport offset 0x%x for TSO\n",
1428                                    transport_offset);
1429                         ret = TX_CSUM_TSO;
1430                         goto unavailable;
1431                 }
1432
1433                 switch (get_protocol(skb)) {
1434                 case htons(ETH_P_IP):
1435                         opts1 |= GTSENDV4;
1436                         break;
1437
1438                 case htons(ETH_P_IPV6):
1439                         if (msdn_giant_send_check(skb)) {
1440                                 ret = TX_CSUM_TSO;
1441                                 goto unavailable;
1442                         }
1443                         opts1 |= GTSENDV6;
1444                         break;
1445
1446                 default:
1447                         WARN_ON_ONCE(1);
1448                         break;
1449                 }
1450
1451                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1452                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1453         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1454                 u8 ip_protocol;
1455
1456                 if (transport_offset > TCPHO_MAX) {
1457                         netif_warn(tp, tx_err, tp->netdev,
1458                                    "Invalid transport offset 0x%x\n",
1459                                    transport_offset);
1460                         ret = TX_CSUM_NONE;
1461                         goto unavailable;
1462                 }
1463
1464                 switch (get_protocol(skb)) {
1465                 case htons(ETH_P_IP):
1466                         opts2 |= IPV4_CS;
1467                         ip_protocol = ip_hdr(skb)->protocol;
1468                         break;
1469
1470                 case htons(ETH_P_IPV6):
1471                         opts2 |= IPV6_CS;
1472                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1473                         break;
1474
1475                 default:
1476                         ip_protocol = IPPROTO_RAW;
1477                         break;
1478                 }
1479
1480                 if (ip_protocol == IPPROTO_TCP)
1481                         opts2 |= TCP_CS;
1482                 else if (ip_protocol == IPPROTO_UDP)
1483                         opts2 |= UDP_CS;
1484                 else
1485                         WARN_ON_ONCE(1);
1486
1487                 opts2 |= transport_offset << TCPHO_SHIFT;
1488         }
1489
1490         desc->opts2 = cpu_to_le32(opts2);
1491         desc->opts1 = cpu_to_le32(opts1);
1492
1493 unavailable:
1494         return ret;
1495 }
1496
1497 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1498 {
1499         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1500         int remain, ret;
1501         u8 *tx_data;
1502
1503         __skb_queue_head_init(&skb_head);
1504         spin_lock(&tx_queue->lock);
1505         skb_queue_splice_init(tx_queue, &skb_head);
1506         spin_unlock(&tx_queue->lock);
1507
1508         tx_data = agg->head;
1509         agg->skb_num = agg->skb_len = 0;
1510         remain = rx_buf_sz;
1511
1512         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1513                 struct tx_desc *tx_desc;
1514                 struct sk_buff *skb;
1515                 unsigned int len;
1516                 u32 offset;
1517
1518                 skb = __skb_dequeue(&skb_head);
1519                 if (!skb)
1520                         break;
1521
1522                 len = skb->len + sizeof(*tx_desc);
1523
1524                 if (len > remain) {
1525                         __skb_queue_head(&skb_head, skb);
1526                         break;
1527                 }
1528
1529                 tx_data = tx_agg_align(tx_data);
1530                 tx_desc = (struct tx_desc *)tx_data;
1531
1532                 offset = (u32)skb_transport_offset(skb);
1533
1534                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1535                         r8152_csum_workaround(tp, skb, &skb_head);
1536                         continue;
1537                 }
1538
1539                 tx_data += sizeof(*tx_desc);
1540
1541                 len = skb->len;
1542                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1543                         struct net_device_stats *stats = &tp->netdev->stats;
1544
1545                         stats->tx_dropped++;
1546                         dev_kfree_skb_any(skb);
1547                         tx_data -= sizeof(*tx_desc);
1548                         continue;
1549                 }
1550
1551                 tx_data += len;
1552                 agg->skb_len += len;
1553                 agg->skb_num++;
1554
1555                 dev_kfree_skb_any(skb);
1556
1557                 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1558         }
1559
1560         if (!skb_queue_empty(&skb_head)) {
1561                 spin_lock(&tx_queue->lock);
1562                 skb_queue_splice(&skb_head, tx_queue);
1563                 spin_unlock(&tx_queue->lock);
1564         }
1565
1566         netif_tx_lock(tp->netdev);
1567
1568         if (netif_queue_stopped(tp->netdev) &&
1569             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1570                 netif_wake_queue(tp->netdev);
1571
1572         netif_tx_unlock(tp->netdev);
1573
1574         ret = usb_autopm_get_interface_async(tp->intf);
1575         if (ret < 0)
1576                 goto out_tx_fill;
1577
1578         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1579                           agg->head, (int)(tx_data - (u8 *)agg->head),
1580                           (usb_complete_t)write_bulk_callback, agg);
1581
1582         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1583         if (ret < 0)
1584                 usb_autopm_put_interface_async(tp->intf);
1585
1586 out_tx_fill:
1587         return ret;
1588 }
1589
1590 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1591 {
1592         u8 checksum = CHECKSUM_NONE;
1593         u32 opts2, opts3;
1594
1595         if (tp->version == RTL_VER_01)
1596                 goto return_result;
1597
1598         opts2 = le32_to_cpu(rx_desc->opts2);
1599         opts3 = le32_to_cpu(rx_desc->opts3);
1600
1601         if (opts2 & RD_IPV4_CS) {
1602                 if (opts3 & IPF)
1603                         checksum = CHECKSUM_NONE;
1604                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1605                         checksum = CHECKSUM_NONE;
1606                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1607                         checksum = CHECKSUM_NONE;
1608                 else
1609                         checksum = CHECKSUM_UNNECESSARY;
1610         } else if (RD_IPV6_CS) {
1611                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1612                         checksum = CHECKSUM_UNNECESSARY;
1613                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1614                         checksum = CHECKSUM_UNNECESSARY;
1615         }
1616
1617 return_result:
1618         return checksum;
1619 }
1620
1621 static void rx_bottom(struct r8152 *tp)
1622 {
1623         unsigned long flags;
1624         struct list_head *cursor, *next, rx_queue;
1625
1626         if (list_empty(&tp->rx_done))
1627                 return;
1628
1629         INIT_LIST_HEAD(&rx_queue);
1630         spin_lock_irqsave(&tp->rx_lock, flags);
1631         list_splice_init(&tp->rx_done, &rx_queue);
1632         spin_unlock_irqrestore(&tp->rx_lock, flags);
1633
1634         list_for_each_safe(cursor, next, &rx_queue) {
1635                 struct rx_desc *rx_desc;
1636                 struct rx_agg *agg;
1637                 int len_used = 0;
1638                 struct urb *urb;
1639                 u8 *rx_data;
1640                 int ret;
1641
1642                 list_del_init(cursor);
1643
1644                 agg = list_entry(cursor, struct rx_agg, list);
1645                 urb = agg->urb;
1646                 if (urb->actual_length < ETH_ZLEN)
1647                         goto submit;
1648
1649                 rx_desc = agg->head;
1650                 rx_data = agg->head;
1651                 len_used += sizeof(struct rx_desc);
1652
1653                 while (urb->actual_length > len_used) {
1654                         struct net_device *netdev = tp->netdev;
1655                         struct net_device_stats *stats = &netdev->stats;
1656                         unsigned int pkt_len;
1657                         struct sk_buff *skb;
1658
1659                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1660                         if (pkt_len < ETH_ZLEN)
1661                                 break;
1662
1663                         len_used += pkt_len;
1664                         if (urb->actual_length < len_used)
1665                                 break;
1666
1667                         pkt_len -= CRC_SIZE;
1668                         rx_data += sizeof(struct rx_desc);
1669
1670                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1671                         if (!skb) {
1672                                 stats->rx_dropped++;
1673                                 goto find_next_rx;
1674                         }
1675
1676                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1677                         memcpy(skb->data, rx_data, pkt_len);
1678                         skb_put(skb, pkt_len);
1679                         skb->protocol = eth_type_trans(skb, netdev);
1680                         netif_receive_skb(skb);
1681                         stats->rx_packets++;
1682                         stats->rx_bytes += pkt_len;
1683
1684 find_next_rx:
1685                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1686                         rx_desc = (struct rx_desc *)rx_data;
1687                         len_used = (int)(rx_data - (u8 *)agg->head);
1688                         len_used += sizeof(struct rx_desc);
1689                 }
1690
1691 submit:
1692                 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1693                 if (ret && ret != -ENODEV) {
1694                         spin_lock_irqsave(&tp->rx_lock, flags);
1695                         list_add_tail(&agg->list, &tp->rx_done);
1696                         spin_unlock_irqrestore(&tp->rx_lock, flags);
1697                         tasklet_schedule(&tp->tl);
1698                 }
1699         }
1700 }
1701
1702 static void tx_bottom(struct r8152 *tp)
1703 {
1704         int res;
1705
1706         do {
1707                 struct tx_agg *agg;
1708
1709                 if (skb_queue_empty(&tp->tx_queue))
1710                         break;
1711
1712                 agg = r8152_get_tx_agg(tp);
1713                 if (!agg)
1714                         break;
1715
1716                 res = r8152_tx_agg_fill(tp, agg);
1717                 if (res) {
1718                         struct net_device *netdev = tp->netdev;
1719
1720                         if (res == -ENODEV) {
1721                                 netif_device_detach(netdev);
1722                         } else {
1723                                 struct net_device_stats *stats = &netdev->stats;
1724                                 unsigned long flags;
1725
1726                                 netif_warn(tp, tx_err, netdev,
1727                                            "failed tx_urb %d\n", res);
1728                                 stats->tx_dropped += agg->skb_num;
1729
1730                                 spin_lock_irqsave(&tp->tx_lock, flags);
1731                                 list_add_tail(&agg->list, &tp->tx_free);
1732                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1733                         }
1734                 }
1735         } while (res == 0);
1736 }
1737
1738 static void bottom_half(unsigned long data)
1739 {
1740         struct r8152 *tp;
1741
1742         tp = (struct r8152 *)data;
1743
1744         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1745                 return;
1746
1747         if (!test_bit(WORK_ENABLE, &tp->flags))
1748                 return;
1749
1750         /* When link down, the driver would cancel all bulks. */
1751         /* This avoid the re-submitting bulk */
1752         if (!netif_carrier_ok(tp->netdev))
1753                 return;
1754
1755         rx_bottom(tp);
1756         tx_bottom(tp);
1757 }
1758
1759 static
1760 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1761 {
1762         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1763                       agg->head, rx_buf_sz,
1764                       (usb_complete_t)read_bulk_callback, agg);
1765
1766         return usb_submit_urb(agg->urb, mem_flags);
1767 }
1768
1769 static void rtl_drop_queued_tx(struct r8152 *tp)
1770 {
1771         struct net_device_stats *stats = &tp->netdev->stats;
1772         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1773         struct sk_buff *skb;
1774
1775         if (skb_queue_empty(tx_queue))
1776                 return;
1777
1778         __skb_queue_head_init(&skb_head);
1779         spin_lock_bh(&tx_queue->lock);
1780         skb_queue_splice_init(tx_queue, &skb_head);
1781         spin_unlock_bh(&tx_queue->lock);
1782
1783         while ((skb = __skb_dequeue(&skb_head))) {
1784                 dev_kfree_skb(skb);
1785                 stats->tx_dropped++;
1786         }
1787 }
1788
1789 static void rtl8152_tx_timeout(struct net_device *netdev)
1790 {
1791         struct r8152 *tp = netdev_priv(netdev);
1792         int i;
1793
1794         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1795         for (i = 0; i < RTL8152_MAX_TX; i++)
1796                 usb_unlink_urb(tp->tx_info[i].urb);
1797 }
1798
1799 static void rtl8152_set_rx_mode(struct net_device *netdev)
1800 {
1801         struct r8152 *tp = netdev_priv(netdev);
1802
1803         if (tp->speed & LINK_STATUS) {
1804                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1805                 schedule_delayed_work(&tp->schedule, 0);
1806         }
1807 }
1808
1809 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1810 {
1811         struct r8152 *tp = netdev_priv(netdev);
1812         u32 mc_filter[2];       /* Multicast hash filter */
1813         __le32 tmp[2];
1814         u32 ocp_data;
1815
1816         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1817         netif_stop_queue(netdev);
1818         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1819         ocp_data &= ~RCR_ACPT_ALL;
1820         ocp_data |= RCR_AB | RCR_APM;
1821
1822         if (netdev->flags & IFF_PROMISC) {
1823                 /* Unconditionally log net taps. */
1824                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1825                 ocp_data |= RCR_AM | RCR_AAP;
1826                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1827         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1828                    (netdev->flags & IFF_ALLMULTI)) {
1829                 /* Too many to filter perfectly -- accept all multicasts. */
1830                 ocp_data |= RCR_AM;
1831                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1832         } else {
1833                 struct netdev_hw_addr *ha;
1834
1835                 mc_filter[1] = mc_filter[0] = 0;
1836                 netdev_for_each_mc_addr(ha, netdev) {
1837                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1838                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1839                         ocp_data |= RCR_AM;
1840                 }
1841         }
1842
1843         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1844         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1845
1846         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1847         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1848         netif_wake_queue(netdev);
1849 }
1850
1851 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1852                                         struct net_device *netdev)
1853 {
1854         struct r8152 *tp = netdev_priv(netdev);
1855
1856         skb_tx_timestamp(skb);
1857
1858         skb_queue_tail(&tp->tx_queue, skb);
1859
1860         if (!list_empty(&tp->tx_free)) {
1861                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1862                         set_bit(SCHEDULE_TASKLET, &tp->flags);
1863                         schedule_delayed_work(&tp->schedule, 0);
1864                 } else {
1865                         usb_mark_last_busy(tp->udev);
1866                         tasklet_schedule(&tp->tl);
1867                 }
1868         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1869                 netif_stop_queue(netdev);
1870
1871         return NETDEV_TX_OK;
1872 }
1873
1874 static void r8152b_reset_packet_filter(struct r8152 *tp)
1875 {
1876         u32     ocp_data;
1877
1878         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1879         ocp_data &= ~FMC_FCR_MCU_EN;
1880         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1881         ocp_data |= FMC_FCR_MCU_EN;
1882         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1883 }
1884
1885 static void rtl8152_nic_reset(struct r8152 *tp)
1886 {
1887         int     i;
1888
1889         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1890
1891         for (i = 0; i < 1000; i++) {
1892                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1893                         break;
1894                 udelay(100);
1895         }
1896 }
1897
1898 static void set_tx_qlen(struct r8152 *tp)
1899 {
1900         struct net_device *netdev = tp->netdev;
1901
1902         tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1903                                    sizeof(struct tx_desc));
1904 }
1905
1906 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1907 {
1908         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1909 }
1910
1911 static void rtl_set_eee_plus(struct r8152 *tp)
1912 {
1913         u32 ocp_data;
1914         u8 speed;
1915
1916         speed = rtl8152_get_speed(tp);
1917         if (speed & _10bps) {
1918                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1919                 ocp_data |= EEEP_CR_EEEP_TX;
1920                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1921         } else {
1922                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1923                 ocp_data &= ~EEEP_CR_EEEP_TX;
1924                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1925         }
1926 }
1927
1928 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1929 {
1930         u32 ocp_data;
1931
1932         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1933         if (enable)
1934                 ocp_data |= RXDY_GATED_EN;
1935         else
1936                 ocp_data &= ~RXDY_GATED_EN;
1937         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1938 }
1939
1940 static int rtl_enable(struct r8152 *tp)
1941 {
1942         u32 ocp_data;
1943         int i, ret;
1944
1945         r8152b_reset_packet_filter(tp);
1946
1947         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1948         ocp_data |= CR_RE | CR_TE;
1949         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1950
1951         rxdy_gated_en(tp, false);
1952
1953         INIT_LIST_HEAD(&tp->rx_done);
1954         ret = 0;
1955         for (i = 0; i < RTL8152_MAX_RX; i++) {
1956                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1957                 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1958         }
1959
1960         return ret;
1961 }
1962
1963 static int rtl8152_enable(struct r8152 *tp)
1964 {
1965         set_tx_qlen(tp);
1966         rtl_set_eee_plus(tp);
1967
1968         return rtl_enable(tp);
1969 }
1970
1971 static void r8153_set_rx_agg(struct r8152 *tp)
1972 {
1973         u8 speed;
1974
1975         speed = rtl8152_get_speed(tp);
1976         if (speed & _1000bps) {
1977                 if (tp->udev->speed == USB_SPEED_SUPER) {
1978                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1979                                         RX_THR_SUPPER);
1980                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1981                                         EARLY_AGG_SUPPER);
1982                 } else {
1983                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1984                                         RX_THR_HIGH);
1985                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1986                                         EARLY_AGG_HIGH);
1987                 }
1988         } else {
1989                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1990                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1991                                 EARLY_AGG_SLOW);
1992         }
1993 }
1994
1995 static int rtl8153_enable(struct r8152 *tp)
1996 {
1997         set_tx_qlen(tp);
1998         rtl_set_eee_plus(tp);
1999         r8153_set_rx_agg(tp);
2000
2001         return rtl_enable(tp);
2002 }
2003
2004 static void rtl8152_disable(struct r8152 *tp)
2005 {
2006         u32 ocp_data;
2007         int i;
2008
2009         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2010         ocp_data &= ~RCR_ACPT_ALL;
2011         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2012
2013         rtl_drop_queued_tx(tp);
2014
2015         for (i = 0; i < RTL8152_MAX_TX; i++)
2016                 usb_kill_urb(tp->tx_info[i].urb);
2017
2018         rxdy_gated_en(tp, true);
2019
2020         for (i = 0; i < 1000; i++) {
2021                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2022                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2023                         break;
2024                 mdelay(1);
2025         }
2026
2027         for (i = 0; i < 1000; i++) {
2028                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2029                         break;
2030                 mdelay(1);
2031         }
2032
2033         for (i = 0; i < RTL8152_MAX_RX; i++)
2034                 usb_kill_urb(tp->rx_info[i].urb);
2035
2036         rtl8152_nic_reset(tp);
2037 }
2038
2039 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2040 {
2041         u32 ocp_data;
2042
2043         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2044         if (enable)
2045                 ocp_data |= POWER_CUT;
2046         else
2047                 ocp_data &= ~POWER_CUT;
2048         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2049
2050         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2051         ocp_data &= ~RESUME_INDICATE;
2052         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2053 }
2054
2055 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2056
2057 static u32 __rtl_get_wol(struct r8152 *tp)
2058 {
2059         u32 ocp_data;
2060         u32 wolopts = 0;
2061
2062         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2063         if (!(ocp_data & LAN_WAKE_EN))
2064                 return 0;
2065
2066         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2067         if (ocp_data & LINK_ON_WAKE_EN)
2068                 wolopts |= WAKE_PHY;
2069
2070         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2071         if (ocp_data & UWF_EN)
2072                 wolopts |= WAKE_UCAST;
2073         if (ocp_data & BWF_EN)
2074                 wolopts |= WAKE_BCAST;
2075         if (ocp_data & MWF_EN)
2076                 wolopts |= WAKE_MCAST;
2077
2078         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2079         if (ocp_data & MAGIC_EN)
2080                 wolopts |= WAKE_MAGIC;
2081
2082         return wolopts;
2083 }
2084
2085 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2086 {
2087         u32 ocp_data;
2088
2089         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2090
2091         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2092         ocp_data &= ~LINK_ON_WAKE_EN;
2093         if (wolopts & WAKE_PHY)
2094                 ocp_data |= LINK_ON_WAKE_EN;
2095         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2096
2097         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2098         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2099         if (wolopts & WAKE_UCAST)
2100                 ocp_data |= UWF_EN;
2101         if (wolopts & WAKE_BCAST)
2102                 ocp_data |= BWF_EN;
2103         if (wolopts & WAKE_MCAST)
2104                 ocp_data |= MWF_EN;
2105         if (wolopts & WAKE_ANY)
2106                 ocp_data |= LAN_WAKE_EN;
2107         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2108
2109         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2110
2111         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2112         ocp_data &= ~MAGIC_EN;
2113         if (wolopts & WAKE_MAGIC)
2114                 ocp_data |= MAGIC_EN;
2115         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2116
2117         if (wolopts & WAKE_ANY)
2118                 device_set_wakeup_enable(&tp->udev->dev, true);
2119         else
2120                 device_set_wakeup_enable(&tp->udev->dev, false);
2121 }
2122
2123 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2124 {
2125         if (enable) {
2126                 u32 ocp_data;
2127
2128                 __rtl_set_wol(tp, WAKE_ANY);
2129
2130                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2131
2132                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2133                 ocp_data |= LINK_OFF_WAKE_EN;
2134                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2135
2136                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2137         } else {
2138                 __rtl_set_wol(tp, tp->saved_wolopts);
2139         }
2140 }
2141
2142 static void rtl_phy_reset(struct r8152 *tp)
2143 {
2144         u16 data;
2145         int i;
2146
2147         clear_bit(PHY_RESET, &tp->flags);
2148
2149         data = r8152_mdio_read(tp, MII_BMCR);
2150
2151         /* don't reset again before the previous one complete */
2152         if (data & BMCR_RESET)
2153                 return;
2154
2155         data |= BMCR_RESET;
2156         r8152_mdio_write(tp, MII_BMCR, data);
2157
2158         for (i = 0; i < 50; i++) {
2159                 msleep(20);
2160                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2161                         break;
2162         }
2163 }
2164
2165 static void rtl_clear_bp(struct r8152 *tp)
2166 {
2167         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2168         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2169         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2170         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2171         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2172         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2173         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2174         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2175         mdelay(3);
2176         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2177         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2178 }
2179
2180 static void r8153_clear_bp(struct r8152 *tp)
2181 {
2182         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2183         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2184         rtl_clear_bp(tp);
2185 }
2186
2187 static void r8153_teredo_off(struct r8152 *tp)
2188 {
2189         u32 ocp_data;
2190
2191         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2192         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2193         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2194
2195         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2196         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2197         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2198 }
2199
2200 static void r8152b_disable_aldps(struct r8152 *tp)
2201 {
2202         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2203         msleep(20);
2204 }
2205
2206 static inline void r8152b_enable_aldps(struct r8152 *tp)
2207 {
2208         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2209                                             LINKENA | DIS_SDSAVE);
2210 }
2211
2212 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2213 {
2214         u16 data;
2215
2216         data = r8152_mdio_read(tp, MII_BMCR);
2217         if (data & BMCR_PDOWN) {
2218                 data &= ~BMCR_PDOWN;
2219                 r8152_mdio_write(tp, MII_BMCR, data);
2220         }
2221
2222         r8152b_disable_aldps(tp);
2223
2224         rtl_clear_bp(tp);
2225
2226         r8152b_enable_aldps(tp);
2227         set_bit(PHY_RESET, &tp->flags);
2228 }
2229
2230 static void r8152b_exit_oob(struct r8152 *tp)
2231 {
2232         u32 ocp_data;
2233         int i;
2234
2235         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2236         ocp_data &= ~RCR_ACPT_ALL;
2237         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2238
2239         rxdy_gated_en(tp, true);
2240         r8153_teredo_off(tp);
2241         r8152b_hw_phy_cfg(tp);
2242
2243         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2244         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2245
2246         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2247         ocp_data &= ~NOW_IS_OOB;
2248         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2249
2250         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2251         ocp_data &= ~MCU_BORW_EN;
2252         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2253
2254         for (i = 0; i < 1000; i++) {
2255                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2256                 if (ocp_data & LINK_LIST_READY)
2257                         break;
2258                 mdelay(1);
2259         }
2260
2261         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2262         ocp_data |= RE_INIT_LL;
2263         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2264
2265         for (i = 0; i < 1000; i++) {
2266                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2267                 if (ocp_data & LINK_LIST_READY)
2268                         break;
2269                 mdelay(1);
2270         }
2271
2272         rtl8152_nic_reset(tp);
2273
2274         /* rx share fifo credit full threshold */
2275         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2276
2277         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
2278         ocp_data &= STAT_SPEED_MASK;
2279         if (ocp_data == STAT_SPEED_FULL) {
2280                 /* rx share fifo credit near full threshold */
2281                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2282                                 RXFIFO_THR2_FULL);
2283                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2284                                 RXFIFO_THR3_FULL);
2285         } else {
2286                 /* rx share fifo credit near full threshold */
2287                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2288                                 RXFIFO_THR2_HIGH);
2289                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2290                                 RXFIFO_THR3_HIGH);
2291         }
2292
2293         /* TX share fifo free credit full threshold */
2294         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2295
2296         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2297         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2298         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2299                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2300
2301         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2302         ocp_data &= ~CPCR_RX_VLAN;
2303         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2304
2305         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2306
2307         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2308         ocp_data |= TCR0_AUTO_FIFO;
2309         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2310 }
2311
2312 static void r8152b_enter_oob(struct r8152 *tp)
2313 {
2314         u32 ocp_data;
2315         int i;
2316
2317         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2318         ocp_data &= ~NOW_IS_OOB;
2319         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2320
2321         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2322         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2323         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2324
2325         rtl8152_disable(tp);
2326
2327         for (i = 0; i < 1000; i++) {
2328                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2329                 if (ocp_data & LINK_LIST_READY)
2330                         break;
2331                 mdelay(1);
2332         }
2333
2334         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2335         ocp_data |= RE_INIT_LL;
2336         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2337
2338         for (i = 0; i < 1000; i++) {
2339                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2340                 if (ocp_data & LINK_LIST_READY)
2341                         break;
2342                 mdelay(1);
2343         }
2344
2345         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2346
2347         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2348         ocp_data |= CPCR_RX_VLAN;
2349         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2350
2351         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2352         ocp_data |= ALDPS_PROXY_MODE;
2353         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2354
2355         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2356         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2357         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2358
2359         rxdy_gated_en(tp, false);
2360
2361         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2362         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2363         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2364 }
2365
2366 static void r8153_hw_phy_cfg(struct r8152 *tp)
2367 {
2368         u32 ocp_data;
2369         u16 data;
2370
2371         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2372         data = r8152_mdio_read(tp, MII_BMCR);
2373         if (data & BMCR_PDOWN) {
2374                 data &= ~BMCR_PDOWN;
2375                 r8152_mdio_write(tp, MII_BMCR, data);
2376         }
2377
2378         r8153_clear_bp(tp);
2379
2380         if (tp->version == RTL_VER_03) {
2381                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2382                 data &= ~CTAP_SHORT_EN;
2383                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2384         }
2385
2386         data = ocp_reg_read(tp, OCP_POWER_CFG);
2387         data |= EEE_CLKDIV_EN;
2388         ocp_reg_write(tp, OCP_POWER_CFG, data);
2389
2390         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2391         data |= EN_10M_BGOFF;
2392         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2393         data = ocp_reg_read(tp, OCP_POWER_CFG);
2394         data |= EN_10M_PLLOFF;
2395         ocp_reg_write(tp, OCP_POWER_CFG, data);
2396         data = sram_read(tp, SRAM_IMPEDANCE);
2397         data &= ~RX_DRIVING_MASK;
2398         sram_write(tp, SRAM_IMPEDANCE, data);
2399
2400         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2401         ocp_data |= PFM_PWM_SWITCH;
2402         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2403
2404         data = sram_read(tp, SRAM_LPF_CFG);
2405         data |= LPF_AUTO_TUNE;
2406         sram_write(tp, SRAM_LPF_CFG, data);
2407
2408         data = sram_read(tp, SRAM_10M_AMP1);
2409         data |= GDAC_IB_UPALL;
2410         sram_write(tp, SRAM_10M_AMP1, data);
2411         data = sram_read(tp, SRAM_10M_AMP2);
2412         data |= AMP_DN;
2413         sram_write(tp, SRAM_10M_AMP2, data);
2414
2415         set_bit(PHY_RESET, &tp->flags);
2416 }
2417
2418 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2419 {
2420         u8 u1u2[8];
2421
2422         if (enable)
2423                 memset(u1u2, 0xff, sizeof(u1u2));
2424         else
2425                 memset(u1u2, 0x00, sizeof(u1u2));
2426
2427         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2428 }
2429
2430 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2431 {
2432         u32 ocp_data;
2433
2434         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2435         if (enable)
2436                 ocp_data |= U2P3_ENABLE;
2437         else
2438                 ocp_data &= ~U2P3_ENABLE;
2439         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2440 }
2441
2442 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2443 {
2444         u32 ocp_data;
2445
2446         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2447         if (enable)
2448                 ocp_data |= PWR_EN | PHASE2_EN;
2449         else
2450                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2451         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2452
2453         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2454         ocp_data &= ~PCUT_STATUS;
2455         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2456 }
2457
2458 static void r8153_first_init(struct r8152 *tp)
2459 {
2460         u32 ocp_data;
2461         int i;
2462
2463         rxdy_gated_en(tp, true);
2464         r8153_teredo_off(tp);
2465
2466         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2467         ocp_data &= ~RCR_ACPT_ALL;
2468         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2469
2470         r8153_hw_phy_cfg(tp);
2471
2472         rtl8152_nic_reset(tp);
2473
2474         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2475         ocp_data &= ~NOW_IS_OOB;
2476         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2477
2478         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2479         ocp_data &= ~MCU_BORW_EN;
2480         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2481
2482         for (i = 0; i < 1000; i++) {
2483                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2484                 if (ocp_data & LINK_LIST_READY)
2485                         break;
2486                 mdelay(1);
2487         }
2488
2489         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2490         ocp_data |= RE_INIT_LL;
2491         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2492
2493         for (i = 0; i < 1000; i++) {
2494                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2495                 if (ocp_data & LINK_LIST_READY)
2496                         break;
2497                 mdelay(1);
2498         }
2499
2500         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2501         ocp_data &= ~CPCR_RX_VLAN;
2502         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2503
2504         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2505
2506         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2507         ocp_data |= TCR0_AUTO_FIFO;
2508         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2509
2510         rtl8152_nic_reset(tp);
2511
2512         /* rx share fifo credit full threshold */
2513         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2514         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2515         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2516         /* TX share fifo free credit full threshold */
2517         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2518
2519         /* rx aggregation */
2520         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2521         ocp_data &= ~RX_AGG_DISABLE;
2522         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2523 }
2524
2525 static void r8153_enter_oob(struct r8152 *tp)
2526 {
2527         u32 ocp_data;
2528         int i;
2529
2530         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2531         ocp_data &= ~NOW_IS_OOB;
2532         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2533
2534         rtl8152_disable(tp);
2535
2536         for (i = 0; i < 1000; i++) {
2537                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2538                 if (ocp_data & LINK_LIST_READY)
2539                         break;
2540                 mdelay(1);
2541         }
2542
2543         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2544         ocp_data |= RE_INIT_LL;
2545         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2546
2547         for (i = 0; i < 1000; i++) {
2548                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2549                 if (ocp_data & LINK_LIST_READY)
2550                         break;
2551                 mdelay(1);
2552         }
2553
2554         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2555
2556         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2557         ocp_data &= ~TEREDO_WAKE_MASK;
2558         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2559
2560         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2561         ocp_data |= CPCR_RX_VLAN;
2562         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2563
2564         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2565         ocp_data |= ALDPS_PROXY_MODE;
2566         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2567
2568         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2569         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2570         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2571
2572         rxdy_gated_en(tp, false);
2573
2574         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2575         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2576         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2577 }
2578
2579 static void r8153_disable_aldps(struct r8152 *tp)
2580 {
2581         u16 data;
2582
2583         data = ocp_reg_read(tp, OCP_POWER_CFG);
2584         data &= ~EN_ALDPS;
2585         ocp_reg_write(tp, OCP_POWER_CFG, data);
2586         msleep(20);
2587 }
2588
2589 static void r8153_enable_aldps(struct r8152 *tp)
2590 {
2591         u16 data;
2592
2593         data = ocp_reg_read(tp, OCP_POWER_CFG);
2594         data |= EN_ALDPS;
2595         ocp_reg_write(tp, OCP_POWER_CFG, data);
2596 }
2597
2598 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2599 {
2600         u16 bmcr, anar, gbcr;
2601         int ret = 0;
2602
2603         cancel_delayed_work_sync(&tp->schedule);
2604         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2605         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2606                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2607         if (tp->mii.supports_gmii) {
2608                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2609                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2610         } else {
2611                 gbcr = 0;
2612         }
2613
2614         if (autoneg == AUTONEG_DISABLE) {
2615                 if (speed == SPEED_10) {
2616                         bmcr = 0;
2617                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2618                 } else if (speed == SPEED_100) {
2619                         bmcr = BMCR_SPEED100;
2620                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2621                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2622                         bmcr = BMCR_SPEED1000;
2623                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2624                 } else {
2625                         ret = -EINVAL;
2626                         goto out;
2627                 }
2628
2629                 if (duplex == DUPLEX_FULL)
2630                         bmcr |= BMCR_FULLDPLX;
2631         } else {
2632                 if (speed == SPEED_10) {
2633                         if (duplex == DUPLEX_FULL)
2634                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2635                         else
2636                                 anar |= ADVERTISE_10HALF;
2637                 } else if (speed == SPEED_100) {
2638                         if (duplex == DUPLEX_FULL) {
2639                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2640                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2641                         } else {
2642                                 anar |= ADVERTISE_10HALF;
2643                                 anar |= ADVERTISE_100HALF;
2644                         }
2645                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2646                         if (duplex == DUPLEX_FULL) {
2647                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2648                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2649                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2650                         } else {
2651                                 anar |= ADVERTISE_10HALF;
2652                                 anar |= ADVERTISE_100HALF;
2653                                 gbcr |= ADVERTISE_1000HALF;
2654                         }
2655                 } else {
2656                         ret = -EINVAL;
2657                         goto out;
2658                 }
2659
2660                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2661         }
2662
2663         if (test_bit(PHY_RESET, &tp->flags))
2664                 bmcr |= BMCR_RESET;
2665
2666         if (tp->mii.supports_gmii)
2667                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2668
2669         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2670         r8152_mdio_write(tp, MII_BMCR, bmcr);
2671
2672         if (test_bit(PHY_RESET, &tp->flags)) {
2673                 int i;
2674
2675                 clear_bit(PHY_RESET, &tp->flags);
2676                 for (i = 0; i < 50; i++) {
2677                         msleep(20);
2678                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2679                                 break;
2680                 }
2681         }
2682
2683 out:
2684
2685         return ret;
2686 }
2687
2688 static void rtl8152_down(struct r8152 *tp)
2689 {
2690         r8152_power_cut_en(tp, false);
2691         r8152b_disable_aldps(tp);
2692         r8152b_enter_oob(tp);
2693         r8152b_enable_aldps(tp);
2694 }
2695
2696 static void rtl8153_down(struct r8152 *tp)
2697 {
2698         r8153_u1u2en(tp, false);
2699         r8153_power_cut_en(tp, false);
2700         r8153_disable_aldps(tp);
2701         r8153_enter_oob(tp);
2702         r8153_enable_aldps(tp);
2703 }
2704
2705 static void set_carrier(struct r8152 *tp)
2706 {
2707         struct net_device *netdev = tp->netdev;
2708         u8 speed;
2709
2710         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2711         speed = rtl8152_get_speed(tp);
2712
2713         if (speed & LINK_STATUS) {
2714                 if (!(tp->speed & LINK_STATUS)) {
2715                         tp->rtl_ops.enable(tp);
2716                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2717                         netif_carrier_on(netdev);
2718                 }
2719         } else {
2720                 if (tp->speed & LINK_STATUS) {
2721                         netif_carrier_off(netdev);
2722                         tasklet_disable(&tp->tl);
2723                         tp->rtl_ops.disable(tp);
2724                         tasklet_enable(&tp->tl);
2725                 }
2726         }
2727         tp->speed = speed;
2728 }
2729
2730 static void rtl_work_func_t(struct work_struct *work)
2731 {
2732         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2733
2734         if (usb_autopm_get_interface(tp->intf) < 0)
2735                 return;
2736
2737         if (!test_bit(WORK_ENABLE, &tp->flags))
2738                 goto out1;
2739
2740         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2741                 goto out1;
2742
2743         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2744                 set_carrier(tp);
2745
2746         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2747                 _rtl8152_set_rx_mode(tp->netdev);
2748
2749         if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2750             (tp->speed & LINK_STATUS)) {
2751                 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2752                 tasklet_schedule(&tp->tl);
2753         }
2754
2755         if (test_bit(PHY_RESET, &tp->flags))
2756                 rtl_phy_reset(tp);
2757
2758 out1:
2759         usb_autopm_put_interface(tp->intf);
2760 }
2761
2762 static int rtl8152_open(struct net_device *netdev)
2763 {
2764         struct r8152 *tp = netdev_priv(netdev);
2765         int res = 0;
2766
2767         res = alloc_all_mem(tp);
2768         if (res)
2769                 goto out;
2770
2771         res = usb_autopm_get_interface(tp->intf);
2772         if (res < 0) {
2773                 free_all_mem(tp);
2774                 goto out;
2775         }
2776
2777         /* The WORK_ENABLE may be set when autoresume occurs */
2778         if (test_bit(WORK_ENABLE, &tp->flags)) {
2779                 clear_bit(WORK_ENABLE, &tp->flags);
2780                 usb_kill_urb(tp->intr_urb);
2781                 cancel_delayed_work_sync(&tp->schedule);
2782                 if (tp->speed & LINK_STATUS)
2783                         tp->rtl_ops.disable(tp);
2784         }
2785
2786         tp->rtl_ops.up(tp);
2787
2788         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2789                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2790                           DUPLEX_FULL);
2791         tp->speed = 0;
2792         netif_carrier_off(netdev);
2793         netif_start_queue(netdev);
2794         set_bit(WORK_ENABLE, &tp->flags);
2795
2796         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2797         if (res) {
2798                 if (res == -ENODEV)
2799                         netif_device_detach(tp->netdev);
2800                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2801                            res);
2802                 free_all_mem(tp);
2803         }
2804
2805         usb_autopm_put_interface(tp->intf);
2806
2807 out:
2808         return res;
2809 }
2810
2811 static int rtl8152_close(struct net_device *netdev)
2812 {
2813         struct r8152 *tp = netdev_priv(netdev);
2814         int res = 0;
2815
2816         clear_bit(WORK_ENABLE, &tp->flags);
2817         usb_kill_urb(tp->intr_urb);
2818         cancel_delayed_work_sync(&tp->schedule);
2819         netif_stop_queue(netdev);
2820
2821         res = usb_autopm_get_interface(tp->intf);
2822         if (res < 0) {
2823                 rtl_drop_queued_tx(tp);
2824         } else {
2825                 /*
2826                  * The autosuspend may have been enabled and wouldn't
2827                  * be disable when autoresume occurs, because the
2828                  * netif_running() would be false.
2829                  */
2830                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2831                         rtl_runtime_suspend_enable(tp, false);
2832                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2833                 }
2834
2835                 tasklet_disable(&tp->tl);
2836                 tp->rtl_ops.down(tp);
2837                 tasklet_enable(&tp->tl);
2838                 usb_autopm_put_interface(tp->intf);
2839         }
2840
2841         free_all_mem(tp);
2842
2843         return res;
2844 }
2845
2846 static void r8152b_enable_eee(struct r8152 *tp)
2847 {
2848         u32 ocp_data;
2849
2850         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2851         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2852         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2853         ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2854                                            EEE_10_CAP | EEE_NWAY_EN |
2855                                            TX_QUIET_EN | RX_QUIET_EN |
2856                                            SDRISETIME | RG_RXLPI_MSK_HFDUP |
2857                                            SDFALLTIME);
2858         ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2859                                            RG_LDVQUIET_EN | RG_CKRSEL |
2860                                            RG_EEEPRG_EN);
2861         ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2862         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2863         ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2864         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2865         ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2866         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2867 }
2868
2869 static void r8153_enable_eee(struct r8152 *tp)
2870 {
2871         u32 ocp_data;
2872         u16 data;
2873
2874         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2875         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2876         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2877         data = ocp_reg_read(tp, OCP_EEE_CFG);
2878         data |= EEE10_EN;
2879         ocp_reg_write(tp, OCP_EEE_CFG, data);
2880         data = ocp_reg_read(tp, OCP_EEE_CFG2);
2881         data |= MY1000_EEE | MY100_EEE;
2882         ocp_reg_write(tp, OCP_EEE_CFG2, data);
2883 }
2884
2885 static void r8152b_enable_fc(struct r8152 *tp)
2886 {
2887         u16 anar;
2888
2889         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2890         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2891         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2892 }
2893
2894 static void rtl_tally_reset(struct r8152 *tp)
2895 {
2896         u32 ocp_data;
2897
2898         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
2899         ocp_data |= TALLY_RESET;
2900         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
2901 }
2902
2903 static void r8152b_init(struct r8152 *tp)
2904 {
2905         u32 ocp_data;
2906
2907         if (tp->version == RTL_VER_01) {
2908                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2909                 ocp_data &= ~LED_MODE_MASK;
2910                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2911         }
2912
2913         r8152_power_cut_en(tp, false);
2914
2915         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2916         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2917         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2918         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2919         ocp_data &= ~MCU_CLK_RATIO_MASK;
2920         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2921         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2922         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2923                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2924         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2925
2926         r8152b_enable_eee(tp);
2927         r8152b_enable_aldps(tp);
2928         r8152b_enable_fc(tp);
2929         rtl_tally_reset(tp);
2930
2931         /* enable rx aggregation */
2932         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2933         ocp_data &= ~RX_AGG_DISABLE;
2934         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2935 }
2936
2937 static void r8153_init(struct r8152 *tp)
2938 {
2939         u32 ocp_data;
2940         int i;
2941
2942         r8153_u1u2en(tp, false);
2943
2944         for (i = 0; i < 500; i++) {
2945                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2946                     AUTOLOAD_DONE)
2947                         break;
2948                 msleep(20);
2949         }
2950
2951         for (i = 0; i < 500; i++) {
2952                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2953                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2954                         break;
2955                 msleep(20);
2956         }
2957
2958         r8153_u2p3en(tp, false);
2959
2960         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2961         ocp_data &= ~TIMER11_EN;
2962         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2963
2964         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2965         ocp_data &= ~LED_MODE_MASK;
2966         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2967
2968         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2969         ocp_data &= ~LPM_TIMER_MASK;
2970         if (tp->udev->speed == USB_SPEED_SUPER)
2971                 ocp_data |= LPM_TIMER_500US;
2972         else
2973                 ocp_data |= LPM_TIMER_500MS;
2974         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2975
2976         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2977         ocp_data &= ~SEN_VAL_MASK;
2978         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2979         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2980
2981         r8153_power_cut_en(tp, false);
2982         r8153_u1u2en(tp, true);
2983
2984         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2985         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2986         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2987                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2988                        U1U2_SPDWN_EN | L1_SPDWN_EN);
2989         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2990                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2991                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2992                        EEE_SPDWN_EN);
2993
2994         r8153_enable_eee(tp);
2995         r8153_enable_aldps(tp);
2996         r8152b_enable_fc(tp);
2997         rtl_tally_reset(tp);
2998 }
2999
3000 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3001 {
3002         struct r8152 *tp = usb_get_intfdata(intf);
3003
3004         if (PMSG_IS_AUTO(message))
3005                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3006         else
3007                 netif_device_detach(tp->netdev);
3008
3009         if (netif_running(tp->netdev)) {
3010                 clear_bit(WORK_ENABLE, &tp->flags);
3011                 usb_kill_urb(tp->intr_urb);
3012                 cancel_delayed_work_sync(&tp->schedule);
3013                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3014                         rtl_runtime_suspend_enable(tp, true);
3015                 } else {
3016                         tasklet_disable(&tp->tl);
3017                         tp->rtl_ops.down(tp);
3018                         tasklet_enable(&tp->tl);
3019                 }
3020         }
3021
3022         return 0;
3023 }
3024
3025 static int rtl8152_resume(struct usb_interface *intf)
3026 {
3027         struct r8152 *tp = usb_get_intfdata(intf);
3028
3029         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3030                 tp->rtl_ops.init(tp);
3031                 netif_device_attach(tp->netdev);
3032         }
3033
3034         if (netif_running(tp->netdev)) {
3035                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3036                         rtl_runtime_suspend_enable(tp, false);
3037                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3038                         if (tp->speed & LINK_STATUS)
3039                                 tp->rtl_ops.disable(tp);
3040                 } else {
3041                         tp->rtl_ops.up(tp);
3042                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3043                                 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3044                                 DUPLEX_FULL);
3045                 }
3046                 tp->speed = 0;
3047                 netif_carrier_off(tp->netdev);
3048                 set_bit(WORK_ENABLE, &tp->flags);
3049                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3050         }
3051
3052         return 0;
3053 }
3054
3055 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3056 {
3057         struct r8152 *tp = netdev_priv(dev);
3058
3059         if (usb_autopm_get_interface(tp->intf) < 0)
3060                 return;
3061
3062         wol->supported = WAKE_ANY;
3063         wol->wolopts = __rtl_get_wol(tp);
3064
3065         usb_autopm_put_interface(tp->intf);
3066 }
3067
3068 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3069 {
3070         struct r8152 *tp = netdev_priv(dev);
3071         int ret;
3072
3073         ret = usb_autopm_get_interface(tp->intf);
3074         if (ret < 0)
3075                 goto out_set_wol;
3076
3077         __rtl_set_wol(tp, wol->wolopts);
3078         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3079
3080         usb_autopm_put_interface(tp->intf);
3081
3082 out_set_wol:
3083         return ret;
3084 }
3085
3086 static u32 rtl8152_get_msglevel(struct net_device *dev)
3087 {
3088         struct r8152 *tp = netdev_priv(dev);
3089
3090         return tp->msg_enable;
3091 }
3092
3093 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3094 {
3095         struct r8152 *tp = netdev_priv(dev);
3096
3097         tp->msg_enable = value;
3098 }
3099
3100 static void rtl8152_get_drvinfo(struct net_device *netdev,
3101                                 struct ethtool_drvinfo *info)
3102 {
3103         struct r8152 *tp = netdev_priv(netdev);
3104
3105         strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
3106         strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
3107         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3108 }
3109
3110 static
3111 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3112 {
3113         struct r8152 *tp = netdev_priv(netdev);
3114
3115         if (!tp->mii.mdio_read)
3116                 return -EOPNOTSUPP;
3117
3118         return mii_ethtool_gset(&tp->mii, cmd);
3119 }
3120
3121 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3122 {
3123         struct r8152 *tp = netdev_priv(dev);
3124         int ret;
3125
3126         ret = usb_autopm_get_interface(tp->intf);
3127         if (ret < 0)
3128                 goto out;
3129
3130         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3131
3132         usb_autopm_put_interface(tp->intf);
3133
3134 out:
3135         return ret;
3136 }
3137
3138 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3139         "tx_packets",
3140         "rx_packets",
3141         "tx_errors",
3142         "rx_errors",
3143         "rx_missed",
3144         "align_errors",
3145         "tx_single_collisions",
3146         "tx_multi_collisions",
3147         "rx_unicast",
3148         "rx_broadcast",
3149         "rx_multicast",
3150         "tx_aborted",
3151         "tx_underrun",
3152 };
3153
3154 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3155 {
3156         switch (sset) {
3157         case ETH_SS_STATS:
3158                 return ARRAY_SIZE(rtl8152_gstrings);
3159         default:
3160                 return -EOPNOTSUPP;
3161         }
3162 }
3163
3164 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3165                                       struct ethtool_stats *stats, u64 *data)
3166 {
3167         struct r8152 *tp = netdev_priv(dev);
3168         struct tally_counter tally;
3169
3170         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3171
3172         data[0] = le64_to_cpu(tally.tx_packets);
3173         data[1] = le64_to_cpu(tally.rx_packets);
3174         data[2] = le64_to_cpu(tally.tx_errors);
3175         data[3] = le32_to_cpu(tally.rx_errors);
3176         data[4] = le16_to_cpu(tally.rx_missed);
3177         data[5] = le16_to_cpu(tally.align_errors);
3178         data[6] = le32_to_cpu(tally.tx_one_collision);
3179         data[7] = le32_to_cpu(tally.tx_multi_collision);
3180         data[8] = le64_to_cpu(tally.rx_unicast);
3181         data[9] = le64_to_cpu(tally.rx_broadcast);
3182         data[10] = le32_to_cpu(tally.rx_multicast);
3183         data[11] = le16_to_cpu(tally.tx_aborted);
3184         data[12] = le16_to_cpu(tally.tx_underun);
3185 }
3186
3187 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3188 {
3189         switch (stringset) {
3190         case ETH_SS_STATS:
3191                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3192                 break;
3193         }
3194 }
3195
3196 static struct ethtool_ops ops = {
3197         .get_drvinfo = rtl8152_get_drvinfo,
3198         .get_settings = rtl8152_get_settings,
3199         .set_settings = rtl8152_set_settings,
3200         .get_link = ethtool_op_get_link,
3201         .get_msglevel = rtl8152_get_msglevel,
3202         .set_msglevel = rtl8152_set_msglevel,
3203         .get_wol = rtl8152_get_wol,
3204         .set_wol = rtl8152_set_wol,
3205         .get_strings = rtl8152_get_strings,
3206         .get_sset_count = rtl8152_get_sset_count,
3207         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3208 };
3209
3210 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3211 {
3212         struct r8152 *tp = netdev_priv(netdev);
3213         struct mii_ioctl_data *data = if_mii(rq);
3214         int res;
3215
3216         res = usb_autopm_get_interface(tp->intf);
3217         if (res < 0)
3218                 goto out;
3219
3220         switch (cmd) {
3221         case SIOCGMIIPHY:
3222                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3223                 break;
3224
3225         case SIOCGMIIREG:
3226                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3227                 break;
3228
3229         case SIOCSMIIREG:
3230                 if (!capable(CAP_NET_ADMIN)) {
3231                         res = -EPERM;
3232                         break;
3233                 }
3234                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3235                 break;
3236
3237         default:
3238                 res = -EOPNOTSUPP;
3239         }
3240
3241         usb_autopm_put_interface(tp->intf);
3242
3243 out:
3244         return res;
3245 }
3246
3247 static const struct net_device_ops rtl8152_netdev_ops = {
3248         .ndo_open               = rtl8152_open,
3249         .ndo_stop               = rtl8152_close,
3250         .ndo_do_ioctl           = rtl8152_ioctl,
3251         .ndo_start_xmit         = rtl8152_start_xmit,
3252         .ndo_tx_timeout         = rtl8152_tx_timeout,
3253         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3254         .ndo_set_mac_address    = rtl8152_set_mac_address,
3255
3256         .ndo_change_mtu         = eth_change_mtu,
3257         .ndo_validate_addr      = eth_validate_addr,
3258 };
3259
3260 static void r8152b_get_version(struct r8152 *tp)
3261 {
3262         u32     ocp_data;
3263         u16     version;
3264
3265         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3266         version = (u16)(ocp_data & VERSION_MASK);
3267
3268         switch (version) {
3269         case 0x4c00:
3270                 tp->version = RTL_VER_01;
3271                 break;
3272         case 0x4c10:
3273                 tp->version = RTL_VER_02;
3274                 break;
3275         case 0x5c00:
3276                 tp->version = RTL_VER_03;
3277                 tp->mii.supports_gmii = 1;
3278                 break;
3279         case 0x5c10:
3280                 tp->version = RTL_VER_04;
3281                 tp->mii.supports_gmii = 1;
3282                 break;
3283         case 0x5c20:
3284                 tp->version = RTL_VER_05;
3285                 tp->mii.supports_gmii = 1;
3286                 break;
3287         default:
3288                 netif_info(tp, probe, tp->netdev,
3289                            "Unknown version 0x%04x\n", version);
3290                 break;
3291         }
3292 }
3293
3294 static void rtl8152_unload(struct r8152 *tp)
3295 {
3296         if (tp->version != RTL_VER_01)
3297                 r8152_power_cut_en(tp, true);
3298 }
3299
3300 static void rtl8153_unload(struct r8152 *tp)
3301 {
3302         r8153_power_cut_en(tp, true);
3303 }
3304
3305 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3306 {
3307         struct rtl_ops *ops = &tp->rtl_ops;
3308         int ret = -ENODEV;
3309
3310         switch (id->idVendor) {
3311         case VENDOR_ID_REALTEK:
3312                 switch (id->idProduct) {
3313                 case PRODUCT_ID_RTL8152:
3314                         ops->init               = r8152b_init;
3315                         ops->enable             = rtl8152_enable;
3316                         ops->disable            = rtl8152_disable;
3317                         ops->up                 = r8152b_exit_oob;
3318                         ops->down               = rtl8152_down;
3319                         ops->unload             = rtl8152_unload;
3320                         ret = 0;
3321                         break;
3322                 case PRODUCT_ID_RTL8153:
3323                         ops->init               = r8153_init;
3324                         ops->enable             = rtl8153_enable;
3325                         ops->disable            = rtl8152_disable;
3326                         ops->up                 = r8153_first_init;
3327                         ops->down               = rtl8153_down;
3328                         ops->unload             = rtl8153_unload;
3329                         ret = 0;
3330                         break;
3331                 default:
3332                         break;
3333                 }
3334                 break;
3335
3336         case VENDOR_ID_SAMSUNG:
3337                 switch (id->idProduct) {
3338                 case PRODUCT_ID_SAMSUNG:
3339                         ops->init               = r8153_init;
3340                         ops->enable             = rtl8153_enable;
3341                         ops->disable            = rtl8152_disable;
3342                         ops->up                 = r8153_first_init;
3343                         ops->down               = rtl8153_down;
3344                         ops->unload             = rtl8153_unload;
3345                         ret = 0;
3346                         break;
3347                 default:
3348                         break;
3349                 }
3350                 break;
3351
3352         default:
3353                 break;
3354         }
3355
3356         if (ret)
3357                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3358
3359         return ret;
3360 }
3361
3362 static int rtl8152_probe(struct usb_interface *intf,
3363                          const struct usb_device_id *id)
3364 {
3365         struct usb_device *udev = interface_to_usbdev(intf);
3366         struct r8152 *tp;
3367         struct net_device *netdev;
3368         int ret;
3369
3370         if (udev->actconfig->desc.bConfigurationValue != 1) {
3371                 usb_driver_set_configuration(udev, 1);
3372                 return -ENODEV;
3373         }
3374
3375         usb_reset_device(udev);
3376         netdev = alloc_etherdev(sizeof(struct r8152));
3377         if (!netdev) {
3378                 dev_err(&intf->dev, "Out of memory\n");
3379                 return -ENOMEM;
3380         }
3381
3382         SET_NETDEV_DEV(netdev, &intf->dev);
3383         tp = netdev_priv(netdev);
3384         tp->msg_enable = 0x7FFF;
3385
3386         tp->udev = udev;
3387         tp->netdev = netdev;
3388         tp->intf = intf;
3389
3390         ret = rtl_ops_init(tp, id);
3391         if (ret)
3392                 goto out;
3393
3394         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3395         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3396
3397         netdev->netdev_ops = &rtl8152_netdev_ops;
3398         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3399
3400         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3401                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3402                             NETIF_F_TSO6;
3403         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3404                               NETIF_F_TSO | NETIF_F_FRAGLIST |
3405                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3406
3407         SET_ETHTOOL_OPS(netdev, &ops);
3408         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3409
3410         tp->mii.dev = netdev;
3411         tp->mii.mdio_read = read_mii_word;
3412         tp->mii.mdio_write = write_mii_word;
3413         tp->mii.phy_id_mask = 0x3f;
3414         tp->mii.reg_num_mask = 0x1f;
3415         tp->mii.phy_id = R8152_PHY_ID;
3416         tp->mii.supports_gmii = 0;
3417
3418         intf->needs_remote_wakeup = 1;
3419
3420         r8152b_get_version(tp);
3421         tp->rtl_ops.init(tp);
3422         set_ethernet_addr(tp);
3423
3424         usb_set_intfdata(intf, tp);
3425
3426         ret = register_netdev(netdev);
3427         if (ret != 0) {
3428                 netif_err(tp, probe, netdev, "couldn't register the device\n");
3429                 goto out1;
3430         }
3431
3432         tp->saved_wolopts = __rtl_get_wol(tp);
3433         if (tp->saved_wolopts)
3434                 device_set_wakeup_enable(&udev->dev, true);
3435         else
3436                 device_set_wakeup_enable(&udev->dev, false);
3437
3438         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3439
3440         return 0;
3441
3442 out1:
3443         usb_set_intfdata(intf, NULL);
3444 out:
3445         free_netdev(netdev);
3446         return ret;
3447 }
3448
3449 static void rtl8152_disconnect(struct usb_interface *intf)
3450 {
3451         struct r8152 *tp = usb_get_intfdata(intf);
3452
3453         usb_set_intfdata(intf, NULL);
3454         if (tp) {
3455                 set_bit(RTL8152_UNPLUG, &tp->flags);
3456                 tasklet_kill(&tp->tl);
3457                 unregister_netdev(tp->netdev);
3458                 tp->rtl_ops.unload(tp);
3459                 free_netdev(tp->netdev);
3460         }
3461 }
3462
3463 /* table of devices that work with this driver */
3464 static struct usb_device_id rtl8152_table[] = {
3465         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3466         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3467         {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3468         {}
3469 };
3470
3471 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3472
3473 static struct usb_driver rtl8152_driver = {
3474         .name =         MODULENAME,
3475         .id_table =     rtl8152_table,
3476         .probe =        rtl8152_probe,
3477         .disconnect =   rtl8152_disconnect,
3478         .suspend =      rtl8152_suspend,
3479         .resume =       rtl8152_resume,
3480         .reset_resume = rtl8152_resume,
3481         .supports_autosuspend = 1,
3482         .disable_hub_initiated_lpm = 1,
3483 };
3484
3485 module_usb_driver(rtl8152_driver);
3486
3487 MODULE_AUTHOR(DRIVER_AUTHOR);
3488 MODULE_DESCRIPTION(DRIVER_DESC);
3489 MODULE_LICENSE("GPL");