2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/idr.h>
42 #include "qib_common.h"
45 * min buffers we want to have per context, after driver
47 #define QIB_MIN_USER_CTXT_BUFCNT 7
49 #define QLOGIC_IB_R_SOFTWARE_MASK 0xFF
50 #define QLOGIC_IB_R_SOFTWARE_SHIFT 24
51 #define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62)
54 * Number of ctxts we are configured to use (to allow for more pio
55 * buffers per ctxt, etc.) Zero means use chip value.
58 module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
59 MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use");
62 * If set, do not write to any regs if avoidable, hack to allow
63 * check for deranged default register values.
66 module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
67 MODULE_PARM_DESC(mini_init, "If set, do minimal diag init");
69 unsigned qib_n_krcv_queues;
70 module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO);
71 MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port");
74 * qib_wc_pat parameter:
77 * If PAT initialization fails, code reverts back to MTRR
79 unsigned qib_wc_pat = 1; /* default (1) is to use PAT, not MTRR */
80 module_param_named(wc_pat, qib_wc_pat, uint, S_IRUGO);
81 MODULE_PARM_DESC(wc_pat, "enable write-combining via PAT mechanism");
83 struct workqueue_struct *qib_cq_wq;
85 static void verify_interrupt(unsigned long);
87 static struct idr qib_unit_table;
88 u32 qib_cpulist_count;
89 unsigned long *qib_cpulist;
91 /* set number of contexts we'll actually use */
92 void qib_set_ctxtcnt(struct qib_devdata *dd)
95 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
96 if (dd->cfgctxts > dd->ctxtcnt)
97 dd->cfgctxts = dd->ctxtcnt;
98 } else if (qib_cfgctxts < dd->num_pports)
99 dd->cfgctxts = dd->ctxtcnt;
100 else if (qib_cfgctxts <= dd->ctxtcnt)
101 dd->cfgctxts = qib_cfgctxts;
103 dd->cfgctxts = dd->ctxtcnt;
107 * Common code for creating the receive context array.
109 int qib_create_ctxts(struct qib_devdata *dd)
115 * Allocate full ctxtcnt array, rather than just cfgctxts, because
116 * cleanup iterates across all possible ctxts.
118 dd->rcd = kzalloc(sizeof(*dd->rcd) * dd->ctxtcnt, GFP_KERNEL);
120 qib_dev_err(dd, "Unable to allocate ctxtdata array, "
126 /* create (one or more) kctxt */
127 for (i = 0; i < dd->first_user_ctxt; ++i) {
128 struct qib_pportdata *ppd;
129 struct qib_ctxtdata *rcd;
131 if (dd->skip_kctxt_mask & (1 << i))
134 ppd = dd->pport + (i % dd->num_pports);
135 rcd = qib_create_ctxtdata(ppd, i);
137 qib_dev_err(dd, "Unable to allocate ctxtdata"
138 " for Kernel ctxt, failing\n");
142 rcd->pkeys[0] = QIB_DEFAULT_P_KEY;
151 * Common code for user and kernel context setup.
153 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt)
155 struct qib_devdata *dd = ppd->dd;
156 struct qib_ctxtdata *rcd;
158 rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
160 INIT_LIST_HEAD(&rcd->qp_wait_list);
167 dd->f_init_ctxt(rcd);
170 * To avoid wasting a lot of memory, we allocate 32KB chunks
171 * of physically contiguous memory, advance through it until
172 * used up and then allocate more. Of course, we need
173 * memory to store those extra pointers, now. 32KB seems to
174 * be the most that is "safe" under memory pressure
175 * (creating large files and then copying them over
176 * NFS while doing lots of MPI jobs). The OOM killer can
177 * get invoked, even though we say we can sleep and this can
178 * cause significant system problems....
180 rcd->rcvegrbuf_size = 0x8000;
181 rcd->rcvegrbufs_perchunk =
182 rcd->rcvegrbuf_size / dd->rcvegrbufsize;
183 rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt +
184 rcd->rcvegrbufs_perchunk - 1) /
185 rcd->rcvegrbufs_perchunk;
186 BUG_ON(!is_power_of_2(rcd->rcvegrbufs_perchunk));
187 rcd->rcvegrbufs_perchunk_shift =
188 ilog2(rcd->rcvegrbufs_perchunk);
194 * Common code for initializing the physical port structure.
196 void qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
200 ppd->hw_pidx = hw_pidx;
201 ppd->port = port; /* IB port number, not index */
203 spin_lock_init(&ppd->sdma_lock);
204 spin_lock_init(&ppd->lflags_lock);
205 init_waitqueue_head(&ppd->state_wait);
207 init_timer(&ppd->symerr_clear_timer);
208 ppd->symerr_clear_timer.function = qib_clear_symerror_on_linkup;
209 ppd->symerr_clear_timer.data = (unsigned long)ppd;
212 static int init_pioavailregs(struct qib_devdata *dd)
217 dd->pioavailregs_dma = dma_alloc_coherent(
218 &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys,
220 if (!dd->pioavailregs_dma) {
221 qib_dev_err(dd, "failed to allocate PIOavail reg area "
228 * We really want L2 cache aligned, but for current CPUs of
229 * interest, they are the same.
231 status_page = (u64 *)
232 ((char *) dd->pioavailregs_dma +
233 ((2 * L1_CACHE_BYTES +
234 dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
235 /* device status comes first, for backwards compatibility */
236 dd->devstatusp = status_page;
238 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
239 dd->pport[pidx].statusp = status_page;
244 * Setup buffer to hold freeze and other messages, accessible to
245 * apps, following statusp. This is per-unit, not per port.
247 dd->freezemsg = (char *) status_page;
249 /* length of msg buffer is "whatever is left" */
250 ret = (char *) status_page - (char *) dd->pioavailregs_dma;
251 dd->freezelen = PAGE_SIZE - ret;
260 * init_shadow_tids - allocate the shadow TID array
261 * @dd: the qlogic_ib device
263 * allocate the shadow TID array, so we can qib_munlock previous
264 * entries. It may make more sense to move the pageshadow to the
265 * ctxt data structure, so we only allocate memory for ctxts actually
266 * in use, since we at 8k per ctxt, now.
267 * We don't want failures here to prevent use of the driver/chip,
268 * so no return value.
270 static void init_shadow_tids(struct qib_devdata *dd)
275 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *));
277 qib_dev_err(dd, "failed to allocate shadow page * "
278 "array, no expected sends!\n");
282 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t));
284 qib_dev_err(dd, "failed to allocate shadow dma handle "
285 "array, no expected sends!\n");
289 dd->pageshadow = pages;
290 dd->physshadow = addrs;
296 dd->pageshadow = NULL;
300 * Do initialization for device that is only needed on
301 * first detect, not on resets.
303 static int loadtime_init(struct qib_devdata *dd)
307 if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) &
308 QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) {
309 qib_dev_err(dd, "Driver only handles version %d, "
310 "chip swversion is %d (%llx), failng\n",
312 (int)(dd->revision >>
313 QLOGIC_IB_R_SOFTWARE_SHIFT) &
314 QLOGIC_IB_R_SOFTWARE_MASK,
315 (unsigned long long) dd->revision);
320 if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK)
321 qib_devinfo(dd->pcidev, "%s", dd->boardversion);
323 spin_lock_init(&dd->pioavail_lock);
324 spin_lock_init(&dd->sendctrl_lock);
325 spin_lock_init(&dd->uctxt_lock);
326 spin_lock_init(&dd->qib_diag_trans_lock);
327 spin_lock_init(&dd->eep_st_lock);
328 mutex_init(&dd->eep_lock);
333 ret = init_pioavailregs(dd);
334 init_shadow_tids(dd);
336 qib_get_eeprom_info(dd);
338 /* setup time (don't start yet) to verify we got interrupt */
339 init_timer(&dd->intrchk_timer);
340 dd->intrchk_timer.function = verify_interrupt;
341 dd->intrchk_timer.data = (unsigned long) dd;
348 * init_after_reset - re-initialize after a reset
349 * @dd: the qlogic_ib device
351 * sanity check at least some of the values after reset, and
352 * ensure no receive or transmit (explicitly, in case reset
355 static int init_after_reset(struct qib_devdata *dd)
360 * Ensure chip does no sends or receives, tail updates, or
361 * pioavail updates while we re-initialize. This is mostly
362 * for the driver data structures, not chip registers.
364 for (i = 0; i < dd->num_pports; ++i) {
366 * ctxt == -1 means "all contexts". Only really safe for
367 * _dis_abling things, as here.
369 dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS |
370 QIB_RCVCTRL_INTRAVAIL_DIS |
371 QIB_RCVCTRL_TAILUPD_DIS, -1);
372 /* Redundant across ports for some, but no big deal. */
373 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS |
374 QIB_SENDCTRL_AVAIL_DIS);
380 static void enable_chip(struct qib_devdata *dd)
386 * Enable PIO send, and update of PIOavail regs to memory.
388 for (i = 0; i < dd->num_pports; ++i)
389 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB |
390 QIB_SENDCTRL_AVAIL_ENB);
392 * Enable kernel ctxts' receive and receive interrupt.
393 * Other ctxts done as user opens and inits them.
395 rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB;
396 rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ?
397 QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB;
398 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
399 struct qib_ctxtdata *rcd = dd->rcd[i];
402 dd->f_rcvctrl(rcd->ppd, rcvmask, i);
404 dd->freectxts = dd->cfgctxts - dd->first_user_ctxt;
407 static void verify_interrupt(unsigned long opaque)
409 struct qib_devdata *dd = (struct qib_devdata *) opaque;
412 return; /* being torn down */
415 * If we don't have a lid or any interrupts, let the user know and
416 * don't bother checking again.
418 if (dd->int_counter == 0) {
419 if (!dd->f_intr_fallback(dd))
420 dev_err(&dd->pcidev->dev, "No interrupts detected, "
422 else /* re-arm the timer to see if fallback works */
423 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
427 static void init_piobuf_state(struct qib_devdata *dd)
433 * Ensure all buffers are free, and fifos empty. Buffers
434 * are common, so only do once for port 0.
436 * After enable and qib_chg_pioavailkernel so we can safely
437 * enable pioavail updates and PIOENABLE. After this, packets
438 * are ready and able to go out.
440 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL);
441 for (pidx = 0; pidx < dd->num_pports; ++pidx)
442 dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH);
445 * If not all sendbufs are used, add the one to each of the lower
446 * numbered contexts. pbufsctxt and lastctxt_piobuf are
447 * calculated in chip-specific code because it may cause some
448 * chip-specific adjustments to be made.
450 uctxts = dd->cfgctxts - dd->first_user_ctxt;
451 dd->ctxts_extrabuf = dd->pbufsctxt ?
452 dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0;
455 * Set up the shadow copies of the piobufavail registers,
456 * which we compare against the chip registers for now, and
457 * the in memory DMA'ed copies of the registers.
458 * By now pioavail updates to memory should have occurred, so
459 * copy them into our working/shadow registers; this is in
460 * case something went wrong with abort, but mostly to get the
461 * initial values of the generation bit correct.
463 for (i = 0; i < dd->pioavregs; i++) {
466 tmp = dd->pioavailregs_dma[i];
468 * Don't need to worry about pioavailkernel here
469 * because we will call qib_chg_pioavailkernel() later
470 * in initialization, to busy out buffers as needed.
472 dd->pioavailshadow[i] = le64_to_cpu(tmp);
474 while (i < ARRAY_SIZE(dd->pioavailshadow))
475 dd->pioavailshadow[i++] = 0; /* for debugging sanity */
477 /* after pioavailshadow is setup */
478 qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k,
479 TXCHK_CHG_TYPE_KERN, NULL);
480 dd->f_initvl15_bufs(dd);
484 * qib_init - do the actual initialization sequence on the chip
485 * @dd: the qlogic_ib device
486 * @reinit: reinitializing, so don't allocate new memory
488 * Do the actual initialization sequence on the chip. This is done
489 * both from the init routine called from the PCI infrastructure, and
490 * when we reset the chip, or detect that it was reset internally,
491 * or it's administratively re-enabled.
493 * Memory allocation here and in called routines is only done in
494 * the first case (reinit == 0). We have to be careful, because even
495 * without memory allocation, we need to re-write all the chip registers
496 * TIDs, etc. after the reset or enable has completed.
498 int qib_init(struct qib_devdata *dd, int reinit)
500 int ret = 0, pidx, lastfail = 0;
503 struct qib_ctxtdata *rcd;
504 struct qib_pportdata *ppd;
507 /* Set linkstate to unknown, so we can watch for a transition. */
508 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
509 ppd = dd->pport + pidx;
510 spin_lock_irqsave(&ppd->lflags_lock, flags);
511 ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED |
512 QIBL_LINKDOWN | QIBL_LINKINIT |
514 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
518 ret = init_after_reset(dd);
520 ret = loadtime_init(dd);
524 /* Bypass most chip-init, to get to device creation */
528 ret = dd->f_late_initreg(dd);
532 /* dd->rcd can be NULL if early init failed */
533 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
535 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
536 * re-init, the simplest way to handle this is to free
537 * existing, and re-allocate.
538 * Need to re-create rest of ctxt 0 ctxtdata as well.
544 lastfail = qib_create_rcvhdrq(dd, rcd);
546 lastfail = qib_setup_eagerbufs(rcd);
548 qib_dev_err(dd, "failed to allocate kernel ctxt's "
549 "rcvhdrq and/or egr bufs\n");
554 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
558 ppd = dd->pport + pidx;
559 mtu = ib_mtu_enum_to_int(qib_ibmtu);
561 mtu = QIB_DEFAULT_MTU;
562 qib_ibmtu = 0; /* don't leave invalid value */
564 /* set max we can ever have for this driver load */
565 ppd->init_ibmaxlen = min(mtu > 2048 ?
566 dd->piosize4k : dd->piosize2k,
568 (dd->rcvhdrentsize << 2));
570 * Have to initialize ibmaxlen, but this will normally
571 * change immediately in qib_set_mtu().
573 ppd->ibmaxlen = ppd->init_ibmaxlen;
574 qib_set_mtu(ppd, mtu);
576 spin_lock_irqsave(&ppd->lflags_lock, flags);
577 ppd->lflags |= QIBL_IB_LINK_DISABLED;
578 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
580 lastfail = dd->f_bringup_serdes(ppd);
582 qib_devinfo(dd->pcidev,
583 "Failed to bringup IB port %u\n", ppd->port);
584 lastfail = -ENETDOWN;
588 /* let link come up, and enable IBC */
589 spin_lock_irqsave(&ppd->lflags_lock, flags);
590 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
591 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
596 /* none of the ports initialized */
597 if (!ret && lastfail)
601 /* but continue on, so we can debug cause */
606 init_piobuf_state(dd);
610 /* chip is OK for user apps; mark it as initialized */
611 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
612 ppd = dd->pport + pidx;
614 * Set status even if port serdes is not initialized
615 * so that diags will work.
617 *ppd->statusp |= QIB_STATUS_CHIP_PRESENT |
619 if (!ppd->link_speed_enabled)
621 if (dd->flags & QIB_HAS_SEND_DMA)
622 ret = qib_setup_sdma(ppd);
623 init_timer(&ppd->hol_timer);
624 ppd->hol_timer.function = qib_hol_event;
625 ppd->hol_timer.data = (unsigned long)ppd;
626 ppd->hol_state = QIB_HOL_UP;
629 /* now we can enable all interrupts from the chip */
630 dd->f_set_intr_state(dd, 1);
633 * Setup to verify we get an interrupt, and fallback
634 * to an alternate if necessary and possible.
636 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
637 /* start stats retrieval timer */
638 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
641 /* if ret is non-zero, we probably should do some cleanup here... */
646 * These next two routines are placeholders in case we don't have per-arch
647 * code for controlling write combining. If explicit control of write
648 * combining is not available, performance will probably be awful.
651 int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd)
656 void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd)
660 static inline struct qib_devdata *__qib_lookup(int unit)
662 return idr_find(&qib_unit_table, unit);
665 struct qib_devdata *qib_lookup(int unit)
667 struct qib_devdata *dd;
670 spin_lock_irqsave(&qib_devs_lock, flags);
671 dd = __qib_lookup(unit);
672 spin_unlock_irqrestore(&qib_devs_lock, flags);
678 * Stop the timers during unit shutdown, or after an error late
681 static void qib_stop_timers(struct qib_devdata *dd)
683 struct qib_pportdata *ppd;
686 if (dd->stats_timer.data) {
687 del_timer_sync(&dd->stats_timer);
688 dd->stats_timer.data = 0;
690 if (dd->intrchk_timer.data) {
691 del_timer_sync(&dd->intrchk_timer);
692 dd->intrchk_timer.data = 0;
694 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
695 ppd = dd->pport + pidx;
696 if (ppd->hol_timer.data)
697 del_timer_sync(&ppd->hol_timer);
698 if (ppd->led_override_timer.data) {
699 del_timer_sync(&ppd->led_override_timer);
700 atomic_set(&ppd->led_override_timer_active, 0);
702 if (ppd->symerr_clear_timer.data)
703 del_timer_sync(&ppd->symerr_clear_timer);
708 * qib_shutdown_device - shut down a device
709 * @dd: the qlogic_ib device
711 * This is called to make the device quiet when we are about to
712 * unload the driver, and also when the device is administratively
713 * disabled. It does not free any data structures.
714 * Everything it does has to be setup again by qib_init(dd, 1)
716 static void qib_shutdown_device(struct qib_devdata *dd)
718 struct qib_pportdata *ppd;
721 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
722 ppd = dd->pport + pidx;
724 spin_lock_irq(&ppd->lflags_lock);
725 ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT |
726 QIBL_LINKARMED | QIBL_LINKACTIVE |
728 spin_unlock_irq(&ppd->lflags_lock);
729 *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY);
731 dd->flags &= ~QIB_INITTED;
733 /* mask interrupts, but not errors */
734 dd->f_set_intr_state(dd, 0);
736 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
737 ppd = dd->pport + pidx;
738 dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS |
739 QIB_RCVCTRL_CTXT_DIS |
740 QIB_RCVCTRL_INTRAVAIL_DIS |
741 QIB_RCVCTRL_PKEY_ENB, -1);
743 * Gracefully stop all sends allowing any in progress to
746 dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR);
750 * Enough for anything that's going to trickle out to have actually
755 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
756 ppd = dd->pport + pidx;
757 dd->f_setextled(ppd, 0); /* make sure LEDs are off */
759 if (dd->flags & QIB_HAS_SEND_DMA)
760 qib_teardown_sdma(ppd);
762 dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS |
763 QIB_SENDCTRL_SEND_DIS);
765 * Clear SerdesEnable.
766 * We can't count on interrupts since we are stopping.
768 dd->f_quiet_serdes(ppd);
771 qib_update_eeprom_log(dd);
775 * qib_free_ctxtdata - free a context's allocated data
776 * @dd: the qlogic_ib device
777 * @rcd: the ctxtdata structure
779 * free up any allocated data for a context
780 * This should not touch anything that would affect a simultaneous
781 * re-allocation of context data, because it is called after qib_mutex
782 * is released (and can be called from reinit as well).
783 * It should never change any chip state, or global driver state.
785 void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
791 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
792 rcd->rcvhdrq, rcd->rcvhdrq_phys);
794 if (rcd->rcvhdrtail_kvaddr) {
795 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
796 rcd->rcvhdrtail_kvaddr,
797 rcd->rcvhdrqtailaddr_phys);
798 rcd->rcvhdrtail_kvaddr = NULL;
801 if (rcd->rcvegrbuf) {
804 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
805 void *base = rcd->rcvegrbuf[e];
806 size_t size = rcd->rcvegrbuf_size;
808 dma_free_coherent(&dd->pcidev->dev, size,
809 base, rcd->rcvegrbuf_phys[e]);
811 kfree(rcd->rcvegrbuf);
812 rcd->rcvegrbuf = NULL;
813 kfree(rcd->rcvegrbuf_phys);
814 rcd->rcvegrbuf_phys = NULL;
815 rcd->rcvegrbuf_chunks = 0;
818 kfree(rcd->tid_pg_list);
819 vfree(rcd->user_event_mask);
820 vfree(rcd->subctxt_uregbase);
821 vfree(rcd->subctxt_rcvegrbuf);
822 vfree(rcd->subctxt_rcvhdr_base);
827 * Perform a PIO buffer bandwidth write test, to verify proper system
828 * configuration. Even when all the setup calls work, occasionally
829 * BIOS or other issues can prevent write combining from working, or
830 * can cause other bandwidth problems to the chip.
832 * This test simply writes the same buffer over and over again, and
833 * measures close to the peak bandwidth to the chip (not testing
834 * data bandwidth to the wire). On chips that use an address-based
835 * trigger to send packets to the wire, this is easy. On chips that
836 * use a count to trigger, we want to make sure that the packet doesn't
837 * go out on the wire, or trigger flow control checks.
839 static void qib_verify_pioperf(struct qib_devdata *dd)
841 u32 pbnum, cnt, lcnt;
846 piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum);
848 qib_devinfo(dd->pcidev,
849 "No PIObufs for checking perf, skipping\n");
854 * Enough to give us a reasonable test, less than piobuf size, and
855 * likely multiple of store buffer length.
861 qib_devinfo(dd->pcidev,
862 "Couldn't get memory for checking PIO perf,"
867 preempt_disable(); /* we want reasonably accurate elapsed time */
868 msecs = 1 + jiffies_to_msecs(jiffies);
869 for (lcnt = 0; lcnt < 10000U; lcnt++) {
870 /* wait until we cross msec boundary */
871 if (jiffies_to_msecs(jiffies) >= msecs)
876 dd->f_set_armlaunch(dd, 0);
879 * length 0, no dwords actually sent
885 * This is only roughly accurate, since even with preempt we
886 * still take interrupts that could take a while. Running for
887 * >= 5 msec seems to get us "close enough" to accurate values.
889 msecs = jiffies_to_msecs(jiffies);
890 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
891 qib_pio_copy(piobuf + 64, addr, cnt >> 2);
892 emsecs = jiffies_to_msecs(jiffies) - msecs;
895 /* 1 GiB/sec, slightly over IB SDR line rate */
896 if (lcnt < (emsecs * 1024U))
898 "Performance problem: bandwidth to PIO buffers is "
900 lcnt / (u32) emsecs);
907 /* disarm piobuf, so it's available again */
908 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum));
909 qib_sendbuf_done(dd, pbnum);
910 dd->f_set_armlaunch(dd, 1);
914 void qib_free_devdata(struct qib_devdata *dd)
918 spin_lock_irqsave(&qib_devs_lock, flags);
919 idr_remove(&qib_unit_table, dd->unit);
921 spin_unlock_irqrestore(&qib_devs_lock, flags);
923 ib_dealloc_device(&dd->verbs_dev.ibdev);
927 * Allocate our primary per-unit data structure. Must be done via verbs
928 * allocator, because the verbs cleanup process both does cleanup and
929 * free of the data structure.
930 * "extra" is for chip-specific data.
932 * Use the idr mechanism to get a unit number for this unit.
934 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
937 struct qib_devdata *dd;
940 if (!idr_pre_get(&qib_unit_table, GFP_KERNEL)) {
941 dd = ERR_PTR(-ENOMEM);
945 dd = (struct qib_devdata *) ib_alloc_device(sizeof(*dd) + extra);
947 dd = ERR_PTR(-ENOMEM);
951 spin_lock_irqsave(&qib_devs_lock, flags);
952 ret = idr_get_new(&qib_unit_table, dd, &dd->unit);
954 list_add(&dd->list, &qib_dev_list);
955 spin_unlock_irqrestore(&qib_devs_lock, flags);
958 qib_early_err(&pdev->dev,
959 "Could not allocate unit ID: error %d\n", -ret);
960 ib_dealloc_device(&dd->verbs_dev.ibdev);
965 if (!qib_cpulist_count) {
966 u32 count = num_online_cpus();
967 qib_cpulist = kzalloc(BITS_TO_LONGS(count) *
968 sizeof(long), GFP_KERNEL);
970 qib_cpulist_count = count;
972 qib_early_err(&pdev->dev, "Could not alloc cpulist "
973 "info, cpu affinity might be wrong\n");
981 * Called from freeze mode handlers, and from PCI error
982 * reporting code. Should be paranoid about state of
983 * system and data structures.
985 void qib_disable_after_error(struct qib_devdata *dd)
987 if (dd->flags & QIB_INITTED) {
990 dd->flags &= ~QIB_INITTED;
992 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
993 struct qib_pportdata *ppd;
995 ppd = dd->pport + pidx;
996 if (dd->flags & QIB_PRESENT) {
997 qib_set_linkstate(ppd,
998 QIB_IB_LINKDOWN_DISABLE);
999 dd->f_setextled(ppd, 0);
1001 *ppd->statusp &= ~QIB_STATUS_IB_READY;
1006 * Mark as having had an error for driver, and also
1007 * for /sys and status word mapped to user programs.
1008 * This marks unit as not usable, until reset.
1011 *dd->devstatusp |= QIB_STATUS_HWERROR;
1014 static void __devexit qib_remove_one(struct pci_dev *);
1015 static int __devinit qib_init_one(struct pci_dev *,
1016 const struct pci_device_id *);
1018 #define DRIVER_LOAD_MSG "QLogic " QIB_DRV_NAME " loaded: "
1019 #define PFX QIB_DRV_NAME ": "
1021 static const struct pci_device_id qib_pci_tbl[] = {
1022 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) },
1028 MODULE_DEVICE_TABLE(pci, qib_pci_tbl);
1030 struct pci_driver qib_driver = {
1031 .name = QIB_DRV_NAME,
1032 .probe = qib_init_one,
1033 .remove = __devexit_p(qib_remove_one),
1034 .id_table = qib_pci_tbl,
1035 .err_handler = &qib_pci_err_handler,
1039 * Do all the generic driver unit- and chip-independent memory
1040 * allocation and initialization.
1042 static int __init qlogic_ib_init(void)
1046 ret = qib_dev_init();
1050 qib_cq_wq = create_singlethread_workqueue("qib_cq");
1057 * These must be called before the driver is registered with
1058 * the PCI subsystem.
1060 idr_init(&qib_unit_table);
1061 if (!idr_pre_get(&qib_unit_table, GFP_KERNEL)) {
1062 printk(KERN_ERR QIB_DRV_NAME ": idr_pre_get() failed\n");
1067 ret = pci_register_driver(&qib_driver);
1069 printk(KERN_ERR QIB_DRV_NAME
1070 ": Unable to register driver: error %d\n", -ret);
1074 /* not fatal if it doesn't work */
1075 if (qib_init_qibfs())
1076 printk(KERN_ERR QIB_DRV_NAME ": Unable to register ipathfs\n");
1077 goto bail; /* all OK */
1080 idr_destroy(&qib_unit_table);
1082 destroy_workqueue(qib_cq_wq);
1089 module_init(qlogic_ib_init);
1092 * Do the non-unit driver cleanup, memory free, etc. at unload.
1094 static void __exit qlogic_ib_cleanup(void)
1098 ret = qib_exit_qibfs();
1100 printk(KERN_ERR QIB_DRV_NAME ": "
1101 "Unable to cleanup counter filesystem: "
1102 "error %d\n", -ret);
1104 pci_unregister_driver(&qib_driver);
1106 destroy_workqueue(qib_cq_wq);
1108 qib_cpulist_count = 0;
1111 idr_destroy(&qib_unit_table);
1115 module_exit(qlogic_ib_cleanup);
1117 /* this can only be called after a successful initialization */
1118 static void cleanup_device_data(struct qib_devdata *dd)
1122 struct qib_ctxtdata **tmp;
1123 unsigned long flags;
1125 /* users can't do anything more with chip */
1126 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1127 if (dd->pport[pidx].statusp)
1128 *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT;
1133 if (dd->pioavailregs_dma) {
1134 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1135 (void *) dd->pioavailregs_dma,
1136 dd->pioavailregs_phys);
1137 dd->pioavailregs_dma = NULL;
1140 if (dd->pageshadow) {
1141 struct page **tmpp = dd->pageshadow;
1142 dma_addr_t *tmpd = dd->physshadow;
1145 for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) {
1146 int ctxt_tidbase = ctxt * dd->rcvtidcnt;
1147 int maxtid = ctxt_tidbase + dd->rcvtidcnt;
1149 for (i = ctxt_tidbase; i < maxtid; i++) {
1152 pci_unmap_page(dd->pcidev, tmpd[i],
1153 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1154 qib_release_user_pages(&tmpp[i], 1);
1160 tmpp = dd->pageshadow;
1161 dd->pageshadow = NULL;
1166 * Free any resources still in use (usually just kernel contexts)
1167 * at unload; we do for ctxtcnt, because that's what we allocate.
1168 * We acquire lock to be really paranoid that rcd isn't being
1169 * accessed from some interrupt-related code (that should not happen,
1170 * but best to be sure).
1172 spin_lock_irqsave(&dd->uctxt_lock, flags);
1175 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1176 for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) {
1177 struct qib_ctxtdata *rcd = tmp[ctxt];
1179 tmp[ctxt] = NULL; /* debugging paranoia */
1180 qib_free_ctxtdata(dd, rcd);
1183 kfree(dd->boardname);
1187 * Clean up on unit shutdown, or error during unit load after
1188 * successful initialization.
1190 static void qib_postinit_cleanup(struct qib_devdata *dd)
1193 * Clean up chip-specific stuff.
1194 * We check for NULL here, because it's outside
1195 * the kregbase check, and we need to call it
1196 * after the free_irq. Thus it's possible that
1197 * the function pointers were never initialized.
1202 qib_pcie_ddcleanup(dd);
1204 cleanup_device_data(dd);
1206 qib_free_devdata(dd);
1209 static int __devinit qib_init_one(struct pci_dev *pdev,
1210 const struct pci_device_id *ent)
1212 int ret, j, pidx, initfail;
1213 struct qib_devdata *dd = NULL;
1215 ret = qib_pcie_init(pdev, ent);
1220 * Do device-specific initialiation, function table setup, dd
1223 switch (ent->device) {
1224 case PCI_DEVICE_ID_QLOGIC_IB_6120:
1225 #ifdef CONFIG_PCI_MSI
1226 dd = qib_init_iba6120_funcs(pdev, ent);
1228 qib_early_err(&pdev->dev, "QLogic PCIE device 0x%x cannot "
1229 "work if CONFIG_PCI_MSI is not enabled\n",
1231 dd = ERR_PTR(-ENODEV);
1235 case PCI_DEVICE_ID_QLOGIC_IB_7220:
1236 dd = qib_init_iba7220_funcs(pdev, ent);
1239 case PCI_DEVICE_ID_QLOGIC_IB_7322:
1240 dd = qib_init_iba7322_funcs(pdev, ent);
1244 qib_early_err(&pdev->dev, "Failing on unknown QLogic "
1245 "deviceid 0x%x\n", ent->device);
1252 goto bail; /* error already printed */
1254 /* do the generic initialization */
1255 initfail = qib_init(dd, 0);
1257 ret = qib_register_ib_device(dd);
1260 * Now ready for use. this should be cleared whenever we
1261 * detect a reset, or initiate one. If earlier failure,
1262 * we still create devices, so diags, etc. can be used
1263 * to determine cause of problem.
1265 if (!qib_mini_init && !initfail && !ret)
1266 dd->flags |= QIB_INITTED;
1268 j = qib_device_create(dd);
1270 qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1273 qib_dev_err(dd, "Failed filesystem setup for counters: %d\n",
1276 if (qib_mini_init || initfail || ret) {
1277 qib_stop_timers(dd);
1278 flush_workqueue(ib_wq);
1279 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1280 dd->f_quiet_serdes(dd->pport + pidx);
1284 (void) qibfs_remove(dd);
1285 qib_device_remove(dd);
1288 qib_unregister_ib_device(dd);
1289 qib_postinit_cleanup(dd);
1296 ret = qib_enable_wc(dd);
1298 qib_dev_err(dd, "Write combining not enabled "
1299 "(err %d): performance may be poor\n",
1305 qib_verify_pioperf(dd);
1310 static void __devexit qib_remove_one(struct pci_dev *pdev)
1312 struct qib_devdata *dd = pci_get_drvdata(pdev);
1315 /* unregister from IB core */
1316 qib_unregister_ib_device(dd);
1319 * Disable the IB link, disable interrupts on the device,
1320 * clear dma engines, etc.
1323 qib_shutdown_device(dd);
1325 qib_stop_timers(dd);
1327 /* wait until all of our (qsfp) queue_work() calls complete */
1328 flush_workqueue(ib_wq);
1330 ret = qibfs_remove(dd);
1332 qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n",
1335 qib_device_remove(dd);
1337 qib_postinit_cleanup(dd);
1341 * qib_create_rcvhdrq - create a receive header queue
1342 * @dd: the qlogic_ib device
1343 * @rcd: the context data
1345 * This must be contiguous memory (from an i/o perspective), and must be
1346 * DMA'able (which means for some systems, it will go through an IOMMU,
1347 * or be forced into a low address range).
1349 int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
1353 if (!rcd->rcvhdrq) {
1354 dma_addr_t phys_hdrqtail;
1357 amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1358 sizeof(u32), PAGE_SIZE);
1359 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1360 GFP_USER : GFP_KERNEL;
1361 rcd->rcvhdrq = dma_alloc_coherent(
1362 &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1363 gfp_flags | __GFP_COMP);
1365 if (!rcd->rcvhdrq) {
1366 qib_dev_err(dd, "attempt to allocate %d bytes "
1367 "for ctxt %u rcvhdrq failed\n",
1372 if (rcd->ctxt >= dd->first_user_ctxt) {
1373 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1374 if (!rcd->user_event_mask)
1375 goto bail_free_hdrq;
1378 if (!(dd->flags & QIB_NODMA_RTAIL)) {
1379 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(
1380 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1382 if (!rcd->rcvhdrtail_kvaddr)
1384 rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1387 rcd->rcvhdrq_size = amt;
1390 /* clear for security and sanity on each use */
1391 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
1392 if (rcd->rcvhdrtail_kvaddr)
1393 memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1397 qib_dev_err(dd, "attempt to allocate 1 page for ctxt %u "
1398 "rcvhdrqtailaddr failed\n", rcd->ctxt);
1399 vfree(rcd->user_event_mask);
1400 rcd->user_event_mask = NULL;
1402 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1404 rcd->rcvhdrq = NULL;
1410 * allocate eager buffers, both kernel and user contexts.
1411 * @rcd: the context we are setting up.
1413 * Allocate the eager TID buffers and program them into hip.
1414 * They are no longer completely contiguous, we do multiple allocation
1415 * calls. Otherwise we get the OOM code involved, by asking for too
1416 * much per call, with disastrous results on some kernels.
1418 int qib_setup_eagerbufs(struct qib_ctxtdata *rcd)
1420 struct qib_devdata *dd = rcd->dd;
1421 unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff;
1426 * GFP_USER, but without GFP_FS, so buffer cache can be
1427 * coalesced (we hope); otherwise, even at order 4,
1428 * heavy filesystem activity makes these fail, and we can
1429 * use compound pages.
1431 gfp_flags = __GFP_WAIT | __GFP_IO | __GFP_COMP;
1433 egrcnt = rcd->rcvegrcnt;
1434 egroff = rcd->rcvegr_tid_base;
1435 egrsize = dd->rcvegrbufsize;
1437 chunk = rcd->rcvegrbuf_chunks;
1438 egrperchunk = rcd->rcvegrbufs_perchunk;
1439 size = rcd->rcvegrbuf_size;
1440 if (!rcd->rcvegrbuf) {
1442 kzalloc(chunk * sizeof(rcd->rcvegrbuf[0]),
1444 if (!rcd->rcvegrbuf)
1447 if (!rcd->rcvegrbuf_phys) {
1448 rcd->rcvegrbuf_phys =
1449 kmalloc(chunk * sizeof(rcd->rcvegrbuf_phys[0]),
1451 if (!rcd->rcvegrbuf_phys)
1452 goto bail_rcvegrbuf;
1454 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
1455 if (rcd->rcvegrbuf[e])
1458 dma_alloc_coherent(&dd->pcidev->dev, size,
1459 &rcd->rcvegrbuf_phys[e],
1461 if (!rcd->rcvegrbuf[e])
1462 goto bail_rcvegrbuf_phys;
1465 rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0];
1467 for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) {
1468 dma_addr_t pa = rcd->rcvegrbuf_phys[chunk];
1471 /* clear for security and sanity on each use */
1472 memset(rcd->rcvegrbuf[chunk], 0, size);
1474 for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) {
1475 dd->f_put_tid(dd, e + egroff +
1480 RCVHQ_RCV_TYPE_EAGER, pa);
1483 cond_resched(); /* don't hog the cpu */
1488 bail_rcvegrbuf_phys:
1489 for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++)
1490 dma_free_coherent(&dd->pcidev->dev, size,
1491 rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]);
1492 kfree(rcd->rcvegrbuf_phys);
1493 rcd->rcvegrbuf_phys = NULL;
1495 kfree(rcd->rcvegrbuf);
1496 rcd->rcvegrbuf = NULL;
1502 * Note: Changes to this routine should be mirrored
1503 * for the diagnostics routine qib_remap_ioaddr32().
1504 * There is also related code for VL15 buffers in qib_init_7322_variables().
1505 * The teardown code that unmaps is in qib_pcie_ddcleanup()
1507 int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen)
1509 u64 __iomem *qib_kregbase = NULL;
1510 void __iomem *qib_piobase = NULL;
1511 u64 __iomem *qib_userbase = NULL;
1513 u64 qib_pio2koffset = dd->piobufbase & 0xffffffff;
1514 u64 qib_pio4koffset = dd->piobufbase >> 32;
1515 u64 qib_pio2klen = dd->piobcnt2k * dd->palign;
1516 u64 qib_pio4klen = dd->piobcnt4k * dd->align4k;
1517 u64 qib_physaddr = dd->physaddr;
1519 u64 qib_userlen = 0;
1522 * Free the old mapping because the kernel will try to reuse the
1523 * old mapping and not create a new mapping with the
1524 * write combining attribute.
1526 iounmap(dd->kregbase);
1527 dd->kregbase = NULL;
1530 * Assumes chip address space looks like:
1531 * - kregs + sregs + cregs + uregs (in any order)
1532 * - piobufs (2K and 4K bufs in either order)
1534 * - kregs + sregs + cregs (in any order)
1535 * - piobufs (2K and 4K bufs in either order)
1538 if (dd->piobcnt4k == 0) {
1539 qib_kreglen = qib_pio2koffset;
1540 qib_piolen = qib_pio2klen;
1541 } else if (qib_pio2koffset < qib_pio4koffset) {
1542 qib_kreglen = qib_pio2koffset;
1543 qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen;
1545 qib_kreglen = qib_pio4koffset;
1546 qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen;
1548 qib_piolen += vl15buflen;
1549 /* Map just the configured ports (not all hw ports) */
1550 if (dd->uregbase > qib_kreglen)
1551 qib_userlen = dd->ureg_align * dd->cfgctxts;
1553 /* Sanity checks passed, now create the new mappings */
1554 qib_kregbase = ioremap_nocache(qib_physaddr, qib_kreglen);
1558 qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen);
1563 qib_userbase = ioremap_nocache(qib_physaddr + dd->uregbase,
1569 dd->kregbase = qib_kregbase;
1570 dd->kregend = (u64 __iomem *)
1571 ((char __iomem *) qib_kregbase + qib_kreglen);
1572 dd->piobase = qib_piobase;
1573 dd->pio2kbase = (void __iomem *)
1574 (((char __iomem *) dd->piobase) +
1575 qib_pio2koffset - qib_kreglen);
1577 dd->pio4kbase = (void __iomem *)
1578 (((char __iomem *) dd->piobase) +
1579 qib_pio4koffset - qib_kreglen);
1581 /* ureg will now be accessed relative to dd->userbase */
1582 dd->userbase = qib_userbase;
1586 iounmap(qib_piobase);
1588 iounmap(qib_kregbase);