2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
47 #include "qib_7322_regs.h"
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata *, int);
75 static int serdes_7322_init_old(struct qib_pportdata *);
76 static int serdes_7322_init_new(struct qib_pportdata *);
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
80 /* LE2 serdes values for different cases */
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout = 375;
90 static const unsigned rcv_int_count = 16;
91 static const unsigned sdma_idle_cnt = 64;
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
100 ushort qib_num_cfg_vls = 2;
101 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
104 static ushort qib_chase = 1;
105 module_param_named(chase, qib_chase, ushort, S_IRUGO);
106 MODULE_PARM_DESC(chase, "Enable state chase handling");
108 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110 MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
113 static ushort qib_singleport;
114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
118 * Receive header queue sizes
120 static unsigned qib_rcvhdrcnt;
121 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
122 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
124 static unsigned qib_rcvhdrsize;
125 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
126 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
128 static unsigned qib_rcvhdrentsize;
129 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
130 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
132 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
133 /* for read back, default index is ~5m copper cable */
134 static char txselect_list[MAX_ATTEN_LEN] = "10";
135 static struct kparam_string kp_txselect = {
136 .string = txselect_list,
137 .maxlen = MAX_ATTEN_LEN
139 static int setup_txselect(const char *, struct kernel_param *);
140 module_param_call(txselect, setup_txselect, param_get_string,
141 &kp_txselect, S_IWUSR | S_IRUGO);
142 MODULE_PARM_DESC(txselect, \
143 "Tx serdes indices (for no QSFP or invalid QSFP data)");
145 #define BOARD_QME7342 5
146 #define BOARD_QMH7342 6
147 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
149 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
152 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
154 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
156 #define MASK_ACROSS(lsb, msb) \
157 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
159 #define SYM_RMASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK)
162 #define SYM_MASK(regname, fldname) ((u64) \
163 QIB_7322_##regname##_##fldname##_RMASK << \
164 QIB_7322_##regname##_##fldname##_LSB)
166 #define SYM_FIELD(value, regname, fldname) ((u64) \
167 (((value) >> SYM_LSB(regname, fldname)) & \
168 SYM_RMASK(regname, fldname)))
170 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
171 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
172 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
174 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
175 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
176 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
177 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
178 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
179 /* Below because most, but not all, fields of IntMask have that full suffix */
180 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
183 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
186 * the size bits give us 2^N, in KB units. 0 marks as invalid,
187 * and 7 is reserved. We currently use only 2KB and 4KB
189 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
190 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
191 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
192 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
194 #define SendIBSLIDAssignMask \
195 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
196 #define SendIBSLMCMask \
197 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
199 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
200 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
201 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
202 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
203 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
204 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
206 #define _QIB_GPIO_SDA_NUM 1
207 #define _QIB_GPIO_SCL_NUM 0
208 #define QIB_EEPROM_WEN_NUM 14
209 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
211 /* HW counter clock is at 4nsec */
212 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
214 /* full speed IB port 1 only */
215 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
216 #define PORT_SPD_CAP_SHIFT 3
218 /* full speed featuremask, both ports */
219 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
222 * This file contains almost all the chip-specific register information and
223 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
226 /* Use defines to tie machine-generated names to lower-case names */
227 #define kr_contextcnt KREG_IDX(ContextCnt)
228 #define kr_control KREG_IDX(Control)
229 #define kr_counterregbase KREG_IDX(CntrRegBase)
230 #define kr_errclear KREG_IDX(ErrClear)
231 #define kr_errmask KREG_IDX(ErrMask)
232 #define kr_errstatus KREG_IDX(ErrStatus)
233 #define kr_extctrl KREG_IDX(EXTCtrl)
234 #define kr_extstatus KREG_IDX(EXTStatus)
235 #define kr_gpio_clear KREG_IDX(GPIOClear)
236 #define kr_gpio_mask KREG_IDX(GPIOMask)
237 #define kr_gpio_out KREG_IDX(GPIOOut)
238 #define kr_gpio_status KREG_IDX(GPIOStatus)
239 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
240 #define kr_debugportval KREG_IDX(DebugPortValueReg)
241 #define kr_fmask KREG_IDX(feature_mask)
242 #define kr_act_fmask KREG_IDX(active_feature_mask)
243 #define kr_hwerrclear KREG_IDX(HwErrClear)
244 #define kr_hwerrmask KREG_IDX(HwErrMask)
245 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
246 #define kr_intclear KREG_IDX(IntClear)
247 #define kr_intmask KREG_IDX(IntMask)
248 #define kr_intredirect KREG_IDX(IntRedirect0)
249 #define kr_intstatus KREG_IDX(IntStatus)
250 #define kr_pagealign KREG_IDX(PageAlign)
251 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
252 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
253 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
254 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
255 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
256 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
257 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
258 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
259 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
260 #define kr_revision KREG_IDX(Revision)
261 #define kr_scratch KREG_IDX(Scratch)
262 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
263 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
264 #define kr_sendctrl KREG_IDX(SendCtrl)
265 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
266 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
267 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
268 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
269 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
270 #define kr_sendpiosize KREG_IDX(SendBufSize)
271 #define kr_sendregbase KREG_IDX(SendRegBase)
272 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
273 #define kr_userregbase KREG_IDX(UserRegBase)
274 #define kr_intgranted KREG_IDX(Int_Granted)
275 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
276 #define kr_intblocked KREG_IDX(IntBlocked)
277 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
280 * per-port kernel registers. Access only with qib_read_kreg_port()
281 * or qib_write_kreg_port()
283 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
284 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
285 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
286 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
287 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
288 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
289 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
290 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
291 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
292 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
293 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
294 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
295 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
296 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
297 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
298 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
299 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
300 #define krp_psstart KREG_IBPORT_IDX(PSStart)
301 #define krp_psstat KREG_IBPORT_IDX(PSStat)
302 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
303 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
304 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
305 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
306 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
307 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
308 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
309 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
310 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
311 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
312 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
313 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
314 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
315 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
316 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
317 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
318 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
319 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
320 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
321 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
322 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
323 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
324 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
325 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
326 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
327 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
328 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
329 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
330 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
331 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
332 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
335 * Per-context kernel registers. Acess only with qib_read_kreg_ctxt()
336 * or qib_write_kreg_ctxt()
338 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
339 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
342 * TID Flow table, per context. Reduces
343 * number of hdrq updates to one per flow (or on errors).
344 * context 0 and 1 share same memory, but have distinct
345 * addresses. Since for now, we never use expected sends
346 * on kernel contexts, we don't worry about that (we initialize
347 * those entries for ctxt 0/1 on driver load twice, for example).
349 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
350 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
352 /* these are the error bits in the tid flows, and are W1C */
353 #define TIDFLOW_ERRBITS ( \
354 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
355 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
356 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
357 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
359 /* Most (not all) Counters are per-IBport.
360 * Requires LBIntCnt is at offset 0 in the group
362 #define CREG_IDX(regname) \
363 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
365 #define crp_badformat CREG_IDX(RxVersionErrCnt)
366 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
367 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
368 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
369 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
370 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
371 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
372 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
373 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
374 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
375 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
376 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
377 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
378 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
379 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
380 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
381 #define crp_pktsend CREG_IDX(TxDataPktCnt)
382 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
383 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
384 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
385 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
386 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
387 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
388 #define crp_rcvebp CREG_IDX(RxEBPCnt)
389 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
390 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
391 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
392 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
393 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
394 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
395 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
396 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
397 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
398 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
399 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
400 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
401 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
402 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
403 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
404 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
405 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
406 #define crp_wordrcv CREG_IDX(RxDwordCnt)
407 #define crp_wordsend CREG_IDX(TxDwordCnt)
408 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
410 /* these are the (few) counters that are not port-specific */
411 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
412 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
413 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
414 #define cr_lbint CREG_DEVIDX(LBIntCnt)
415 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
416 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
417 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
418 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
419 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
421 /* no chip register for # of IB ports supported, so define */
422 #define NUM_IB_PORTS 2
424 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
425 #define NUM_VL15_BUFS NUM_IB_PORTS
428 * context 0 and 1 are special, and there is no chip register that
429 * defines this value, so we have to define it here.
430 * These are all allocated to either 0 or 1 for single port
431 * hardware configuration, otherwise each gets half
433 #define KCTXT0_EGRCNT 2048
435 /* values for vl and port fields in PBC, 7322-specific */
436 #define PBC_PORT_SEL_LSB 26
437 #define PBC_PORT_SEL_RMASK 1
438 #define PBC_VL_NUM_LSB 27
439 #define PBC_VL_NUM_RMASK 7
440 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
441 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
443 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
444 [IB_RATE_2_5_GBPS] = 16,
445 [IB_RATE_5_GBPS] = 8,
446 [IB_RATE_10_GBPS] = 4,
447 [IB_RATE_20_GBPS] = 2,
448 [IB_RATE_30_GBPS] = 2,
449 [IB_RATE_40_GBPS] = 1
452 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
453 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
455 /* link training states, from IBC */
456 #define IB_7322_LT_STATE_DISABLED 0x00
457 #define IB_7322_LT_STATE_LINKUP 0x01
458 #define IB_7322_LT_STATE_POLLACTIVE 0x02
459 #define IB_7322_LT_STATE_POLLQUIET 0x03
460 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
461 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
462 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
463 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
464 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
465 #define IB_7322_LT_STATE_CFGIDLE 0x0b
466 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
467 #define IB_7322_LT_STATE_TXREVLANES 0x0d
468 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
469 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
470 #define IB_7322_LT_STATE_CFGENH 0x10
471 #define IB_7322_LT_STATE_CFGTEST 0x11
473 /* link state machine states from IBC */
474 #define IB_7322_L_STATE_DOWN 0x0
475 #define IB_7322_L_STATE_INIT 0x1
476 #define IB_7322_L_STATE_ARM 0x2
477 #define IB_7322_L_STATE_ACTIVE 0x3
478 #define IB_7322_L_STATE_ACT_DEFER 0x4
480 static const u8 qib_7322_physportstate[0x20] = {
481 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
482 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
483 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
484 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
485 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
486 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
487 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
488 [IB_7322_LT_STATE_CFGRCVFCFG] =
489 IB_PHYSPORTSTATE_CFG_TRAIN,
490 [IB_7322_LT_STATE_CFGWAITRMT] =
491 IB_PHYSPORTSTATE_CFG_TRAIN,
492 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
493 [IB_7322_LT_STATE_RECOVERRETRAIN] =
494 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
495 [IB_7322_LT_STATE_RECOVERWAITRMT] =
496 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
497 [IB_7322_LT_STATE_RECOVERIDLE] =
498 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
499 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
500 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
501 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
502 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH,
503 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
505 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
506 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
509 struct qib_chip_specific {
510 u64 __iomem *cregbase;
512 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
513 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
514 u64 main_int_mask; /* clear bits which have dedicated handlers */
515 u64 int_enable_mask; /* for per port interrupts in single port mode */
518 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
519 u64 gpio_mask; /* shadow the gpio mask register */
520 u64 extctrl; /* shadow the gpio output enable, etc... */
527 u32 updthresh; /* current AvailUpdThld */
528 u32 updthresh_dflt; /* default AvailUpdThld */
531 u32 num_msix_entries;
535 u32 recovery_ports_initted;
536 struct msix_entry *msix_entries;
538 unsigned long *sendchkenable;
539 unsigned long *sendgrhchk;
540 unsigned long *sendibchk;
541 u32 rcvavail_timeout[18];
542 char emsgbuf[128]; /* for device error interrupt msg buffer */
545 /* Table of entries in "human readable" form Tx Emphasis. */
553 struct vendor_txdds_ent {
554 u8 oui[QSFP_VOUI_LEN];
556 struct txdds_ent sdr;
557 struct txdds_ent ddr;
558 struct txdds_ent qdr;
561 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
563 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
564 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
565 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
566 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
568 #define H1_FORCE_VAL 8
569 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
570 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
572 /* The static and dynamic registers are paired, and the pairs indexed by spd */
573 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
576 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
577 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
578 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
579 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
580 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
582 struct qib_chippport_specific {
583 u64 __iomem *kpregbase;
584 u64 __iomem *cpregbase;
586 struct qib_pportdata *ppd;
587 wait_queue_head_t autoneg_wait;
588 struct delayed_work autoneg_work;
589 struct delayed_work ipg_work;
590 struct timer_list chase_timer;
592 * these 5 fields are used to establish deltas for IB symbol
593 * errors and linkrecovery errors. They can be reported on
594 * some chips during link negotiation prior to INIT, and with
595 * DDR when faking DDR negotiations with non-IBTA switches.
596 * The chip counters are adjusted at driver unload if there is
608 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
609 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
617 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
618 * entry zero is unused, to simplify indexing
621 u8 no_eep; /* txselect table index to use if no qsfp info */
624 struct qib_qsfp_data qsfp_data;
625 char epmsgbuf[192]; /* for port error interrupt msg buffer */
630 irq_handler_t handler;
632 int port; /* 0 if not port-specific, else port # */
634 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
635 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
636 SYM_LSB(IntStatus, SendBufAvail), 0 },
637 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
638 SYM_LSB(IntStatus, SDmaInt_0), 1 },
639 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
640 SYM_LSB(IntStatus, SDmaInt_1), 2 },
641 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
642 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
643 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
644 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
645 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
646 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
647 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
648 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
649 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
650 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
651 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
652 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
656 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
657 /* cycle through TS1/TS2 till OK */
658 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
659 /* wait for TS1, then go on */
660 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
661 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
663 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
664 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
665 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
667 #define BLOB_7322_IBCHG 0x101
669 static inline void qib_write_kreg(const struct qib_devdata *dd,
670 const u32 regno, u64 value);
671 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
672 static void write_7322_initregs(struct qib_devdata *);
673 static void write_7322_init_portregs(struct qib_pportdata *);
674 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
675 static void check_7322_rxe_status(struct qib_pportdata *);
676 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
679 * qib_read_ureg32 - read 32-bit virtualized per-context register
681 * @regno: register number
682 * @ctxt: context number
684 * Return the contents of a register that is virtualized to be per context.
685 * Returns -1 on errors (not distinguishable from valid contents at
686 * runtime; we may add a separate error variable at some point).
688 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
689 enum qib_ureg regno, int ctxt)
691 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
693 return readl(regno + (u64 __iomem *)(
694 (dd->ureg_align * ctxt) + (dd->userbase ?
695 (char __iomem *)dd->userbase :
696 (char __iomem *)dd->kregbase + dd->uregbase)));
700 * qib_read_ureg - read virtualized per-context register
702 * @regno: register number
703 * @ctxt: context number
705 * Return the contents of a register that is virtualized to be per context.
706 * Returns -1 on errors (not distinguishable from valid contents at
707 * runtime; we may add a separate error variable at some point).
709 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
710 enum qib_ureg regno, int ctxt)
713 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
715 return readq(regno + (u64 __iomem *)(
716 (dd->ureg_align * ctxt) + (dd->userbase ?
717 (char __iomem *)dd->userbase :
718 (char __iomem *)dd->kregbase + dd->uregbase)));
722 * qib_write_ureg - write virtualized per-context register
724 * @regno: register number
728 * Write the contents of a register that is virtualized to be per context.
730 static inline void qib_write_ureg(const struct qib_devdata *dd,
731 enum qib_ureg regno, u64 value, int ctxt)
735 ubase = (u64 __iomem *)
736 ((char __iomem *) dd->userbase +
737 dd->ureg_align * ctxt);
739 ubase = (u64 __iomem *)
741 (char __iomem *) dd->kregbase +
742 dd->ureg_align * ctxt);
744 if (dd->kregbase && (dd->flags & QIB_PRESENT))
745 writeq(value, &ubase[regno]);
748 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
751 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
753 return readl((u32 __iomem *) &dd->kregbase[regno]);
756 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
759 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
761 return readq(&dd->kregbase[regno]);
764 static inline void qib_write_kreg(const struct qib_devdata *dd,
765 const u32 regno, u64 value)
767 if (dd->kregbase && (dd->flags & QIB_PRESENT))
768 writeq(value, &dd->kregbase[regno]);
772 * not many sanity checks for the port-specific kernel register routines,
773 * since they are only used when it's known to be safe.
775 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
778 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
780 return readq(&ppd->cpspec->kpregbase[regno]);
783 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
784 const u16 regno, u64 value)
786 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
787 (ppd->dd->flags & QIB_PRESENT))
788 writeq(value, &ppd->cpspec->kpregbase[regno]);
792 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
793 * @dd: the qlogic_ib device
794 * @regno: the register number to write
795 * @ctxt: the context containing the register
796 * @value: the value to write
798 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
799 const u16 regno, unsigned ctxt,
802 qib_write_kreg(dd, regno + ctxt, value);
805 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
807 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
809 return readq(&dd->cspec->cregbase[regno]);
814 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
816 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
818 return readl(&dd->cspec->cregbase[regno]);
823 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
824 u16 regno, u64 value)
826 if (ppd->cpspec && ppd->cpspec->cpregbase &&
827 (ppd->dd->flags & QIB_PRESENT))
828 writeq(value, &ppd->cpspec->cpregbase[regno]);
831 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
834 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
835 !(ppd->dd->flags & QIB_PRESENT))
837 return readq(&ppd->cpspec->cpregbase[regno]);
840 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
843 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
844 !(ppd->dd->flags & QIB_PRESENT))
846 return readl(&ppd->cpspec->cpregbase[regno]);
849 /* bits in Control register */
850 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
851 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
853 /* bits in general interrupt regs */
854 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
855 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
856 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
857 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
858 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
859 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
860 #define QIB_I_C_ERROR INT_MASK(Err)
862 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
863 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
864 #define QIB_I_GPIO INT_MASK(AssertGPIO)
865 #define QIB_I_P_SDMAINT(pidx) \
866 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
867 INT_MASK_P(SDmaProgress, pidx) | \
868 INT_MASK_PM(SDmaCleanupDone, pidx))
870 /* Interrupt bits that are "per port" */
871 #define QIB_I_P_BITSEXTANT(pidx) \
872 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
873 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
874 INT_MASK_P(SDmaProgress, pidx) | \
875 INT_MASK_PM(SDmaCleanupDone, pidx))
877 /* Interrupt bits that are common to a device */
878 /* currently unused: QIB_I_SPIOSENT */
879 #define QIB_I_C_BITSEXTANT \
880 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
882 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
884 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
885 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
888 * Error bits that are "per port".
890 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
891 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
892 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
893 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
894 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
895 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
896 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
897 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
898 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
899 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
900 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
901 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
902 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
903 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
904 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
905 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
906 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
907 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
908 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
909 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
910 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
911 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
912 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
913 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
914 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
915 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
916 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
917 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
919 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
920 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
921 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
922 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
923 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
924 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
925 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
926 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
927 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
928 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
929 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
931 /* Error bits that are common to a device */
932 #define QIB_E_RESET ERR_MASK(ResetNegated)
933 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
934 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
938 * Per chip (rather than per-port) errors. Most either do
939 * nothing but trigger a print (because they self-recover, or
940 * always occur in tandem with other errors that handle the
941 * issue), or because they indicate errors with no recovery,
942 * but we want to know that they happened.
944 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
945 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
946 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
947 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
948 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
949 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
950 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
951 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
953 /* SDMA chip errors (not per port)
954 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
955 * the SDMAHALT error immediately, so we just print the dup error via the
956 * E_AUTO mechanism. This is true of most of the per-port fatal errors
957 * as well, but since this is port-independent, by definition, it's
958 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
959 * packet send errors, and so are handled in the same manner as other
962 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
963 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
964 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
967 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
968 * it is used to print "common" packet errors.
970 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
971 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
972 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
973 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
976 /* Error Bits that Packet-related (Receive, per-port) */
977 #define QIB_E_P_RPKTERRS (\
978 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
979 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
980 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
981 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
982 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
983 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
986 * Error bits that are Send-related (per port)
987 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
988 * All of these potentially need to have a buffer disarmed
990 #define QIB_E_P_SPKTERRS (\
991 QIB_E_P_SUNEXP_PKTNUM |\
992 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
993 QIB_E_P_SMAXPKTLEN |\
994 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
995 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
996 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
998 #define QIB_E_SPKTERRS ( \
999 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1000 ERR_MASK_N(SendUnsupportedVLErr) | \
1001 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1003 #define QIB_E_P_SDMAERRS ( \
1004 QIB_E_P_SDMAHALT | \
1005 QIB_E_P_SDMADESCADDRMISALIGN | \
1006 QIB_E_P_SDMAUNEXPDATA | \
1007 QIB_E_P_SDMAMISSINGDW | \
1008 QIB_E_P_SDMADWEN | \
1009 QIB_E_P_SDMARPYTAG | \
1010 QIB_E_P_SDMA1STDESC | \
1011 QIB_E_P_SDMABASE | \
1012 QIB_E_P_SDMATAILOUTOFBOUND | \
1013 QIB_E_P_SDMAOUTOFBOUND | \
1014 QIB_E_P_SDMAGENMISMATCH)
1017 * This sets some bits more than once, but makes it more obvious which
1018 * bits are not handled under other categories, and the repeat definition
1021 #define QIB_E_P_BITSEXTANT ( \
1022 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1023 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1024 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1025 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1029 * These are errors that can occur when the link
1030 * changes state while a packet is being sent or received. This doesn't
1031 * cover things like EBP or VCRC that can be the result of a sending
1032 * having the link change state, so we receive a "known bad" packet.
1033 * All of these are "per port", so renamed:
1035 #define QIB_E_P_LINK_PKTERRS (\
1036 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1037 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1038 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1042 * This sets some bits more than once, but makes it more obvious which
1043 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1044 * and the repeat definition is not a problem.
1046 #define QIB_E_C_BITSEXTANT (\
1047 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1048 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1049 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1051 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1052 #define E_SPKT_ERRS_IGNORE 0
1054 #define QIB_EXTS_MEMBIST_DISABLED \
1055 SYM_MASK(EXTStatus, MemBISTDisabled)
1056 #define QIB_EXTS_MEMBIST_ENDTEST \
1057 SYM_MASK(EXTStatus, MemBISTEndTest)
1059 #define QIB_E_SPIOARMLAUNCH \
1060 ERR_MASK(SendArmLaunchErr)
1062 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1063 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1066 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1067 * and also if forced QDR (only QDR enabled). It's enabled for the
1068 * forced QDR case so that scrambling will be enabled by the TS3
1069 * exchange, when supported by both sides of the link.
1071 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1072 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1073 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1074 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1075 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1076 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1077 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1078 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1080 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1081 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1083 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1084 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1085 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1087 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1088 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1089 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1090 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1091 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1092 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1093 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1095 #define IBA7322_REDIRECT_VEC_PER_REG 12
1097 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1098 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1099 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1100 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1101 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1103 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1105 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1107 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1108 fldname##Mask##_##port), .msg = #fldname }
1109 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1110 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1111 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1112 HWE_AUTO(PCIESerdesPClkNotDetect),
1113 HWE_AUTO(PowerOnBISTFailed),
1114 HWE_AUTO(TempsenseTholdReached),
1115 HWE_AUTO(MemoryErr),
1116 HWE_AUTO(PCIeBusParityErr),
1117 HWE_AUTO(PcieCplTimeout),
1118 HWE_AUTO(PciePoisonedTLP),
1119 HWE_AUTO_P(SDmaMemReadErr, 1),
1120 HWE_AUTO_P(SDmaMemReadErr, 0),
1121 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1122 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1123 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1124 HWE_AUTO(statusValidNoEop),
1125 HWE_AUTO(LATriggered),
1129 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1131 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1133 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1134 E_AUTO(ResetNegated),
1135 E_AUTO(HardwareErr),
1136 E_AUTO(InvalidAddrErr),
1137 E_AUTO(SDmaVL15Err),
1138 E_AUTO(SBufVL15MisUseErr),
1139 E_AUTO(InvalidEEPCmd),
1140 E_AUTO(RcvContextShareErr),
1141 E_AUTO(SendVLMismatchErr),
1142 E_AUTO(SendArmLaunchErr),
1143 E_AUTO(SendSpecialTriggerErr),
1144 E_AUTO(SDmaWrongPortErr),
1145 E_AUTO(SDmaBufMaskDuplicateErr),
1146 E_AUTO(RcvHdrFullErr),
1147 E_AUTO(RcvEgrFullErr),
1151 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1152 E_P_AUTO(IBStatusChanged),
1153 E_P_AUTO(SHeadersErr),
1154 E_P_AUTO(VL15BufMisuseErr),
1156 * SDmaHaltErr is not really an error, make it clearer;
1158 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1159 E_P_AUTO(SDmaDescAddrMisalignErr),
1160 E_P_AUTO(SDmaUnexpDataErr),
1161 E_P_AUTO(SDmaMissingDwErr),
1162 E_P_AUTO(SDmaDwEnErr),
1163 E_P_AUTO(SDmaRpyTagErr),
1164 E_P_AUTO(SDma1stDescErr),
1165 E_P_AUTO(SDmaBaseErr),
1166 E_P_AUTO(SDmaTailOutOfBoundErr),
1167 E_P_AUTO(SDmaOutOfBoundErr),
1168 E_P_AUTO(SDmaGenMismatchErr),
1169 E_P_AUTO(SendBufMisuseErr),
1170 E_P_AUTO(SendUnsupportedVLErr),
1171 E_P_AUTO(SendUnexpectedPktNumErr),
1172 E_P_AUTO(SendDroppedDataPktErr),
1173 E_P_AUTO(SendDroppedSmpPktErr),
1174 E_P_AUTO(SendPktLenErr),
1175 E_P_AUTO(SendUnderRunErr),
1176 E_P_AUTO(SendMaxPktLenErr),
1177 E_P_AUTO(SendMinPktLenErr),
1178 E_P_AUTO(RcvIBLostLinkErr),
1179 E_P_AUTO(RcvHdrErr),
1180 E_P_AUTO(RcvHdrLenErr),
1181 E_P_AUTO(RcvBadTidErr),
1182 E_P_AUTO(RcvBadVersionErr),
1183 E_P_AUTO(RcvIBFlowErr),
1184 E_P_AUTO(RcvEBPErr),
1185 E_P_AUTO(RcvUnsupportedVLErr),
1186 E_P_AUTO(RcvUnexpectedCharErr),
1187 E_P_AUTO(RcvShortPktLenErr),
1188 E_P_AUTO(RcvLongPktLenErr),
1189 E_P_AUTO(RcvMaxPktLenErr),
1190 E_P_AUTO(RcvMinPktLenErr),
1191 E_P_AUTO(RcvICRCErr),
1192 E_P_AUTO(RcvVCRCErr),
1193 E_P_AUTO(RcvFormatErr),
1198 * Below generates "auto-message" for interrupts not specific to any port or
1201 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1203 /* Below generates "auto-message" for interrupts specific to a port */
1204 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1205 SYM_LSB(IntMask, fldname##Mask##_0), \
1206 SYM_LSB(IntMask, fldname##Mask##_1)), \
1207 .msg = #fldname "_P" }
1208 /* For some reason, the SerDesTrimDone bits are reversed */
1209 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1210 SYM_LSB(IntMask, fldname##Mask##_1), \
1211 SYM_LSB(IntMask, fldname##Mask##_0)), \
1212 .msg = #fldname "_P" }
1214 * Below generates "auto-message" for interrupts specific to a context,
1215 * with ctxt-number appended
1217 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##0IntMask), \
1219 SYM_LSB(IntMask, fldname##17IntMask)), \
1220 .msg = #fldname "_C"}
1222 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1223 INTR_AUTO_P(SDmaInt),
1224 INTR_AUTO_P(SDmaProgressInt),
1225 INTR_AUTO_P(SDmaIdleInt),
1226 INTR_AUTO_P(SDmaCleanupDone),
1227 INTR_AUTO_C(RcvUrg),
1228 INTR_AUTO_P(ErrInt),
1229 INTR_AUTO(ErrInt), /* non-port-specific errs */
1230 INTR_AUTO(AssertGPIOInt),
1231 INTR_AUTO_P(SendDoneInt),
1232 INTR_AUTO(SendBufAvailInt),
1233 INTR_AUTO_C(RcvAvail),
1237 #define TXSYMPTOM_AUTO_P(fldname) \
1238 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1239 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1240 TXSYMPTOM_AUTO_P(NonKeyPacket),
1241 TXSYMPTOM_AUTO_P(GRHFail),
1242 TXSYMPTOM_AUTO_P(PkeyFail),
1243 TXSYMPTOM_AUTO_P(QPFail),
1244 TXSYMPTOM_AUTO_P(SLIDFail),
1245 TXSYMPTOM_AUTO_P(RawIPV6),
1246 TXSYMPTOM_AUTO_P(PacketTooSmall),
1250 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1253 * Called when we might have an error that is specific to a particular
1254 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1255 * because we don't need to force the update of pioavail
1257 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1259 struct qib_devdata *dd = ppd->dd;
1262 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1263 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1264 unsigned long sbuf[4];
1267 * It's possible that sendbuffererror could have bits set; might
1268 * have already done this as a result of hardware error handling.
1271 for (i = 0; i < regcnt; ++i) {
1272 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1275 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1280 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1283 /* No txe_recover yet, if ever */
1285 /* No decode__errors yet */
1286 static void err_decode(char *msg, size_t len, u64 errs,
1287 const struct qib_hwerror_msgs *msp)
1290 int took, multi, n = 0;
1292 while (msp && msp->mask) {
1293 multi = (msp->mask & (msp->mask - 1));
1294 while (errs & msp->mask) {
1295 these = (errs & msp->mask);
1296 lmask = (these & (these - 1)) ^ these;
1299 /* separate the strings */
1303 took = scnprintf(msg, len, "%s", msp->msg);
1309 /* More than one bit this mask */
1312 while (lmask & msp->mask) {
1316 took = scnprintf(msg, len, "_%d", idx);
1323 /* If some bits are left, show in hex. */
1325 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1326 (unsigned long long) errs);
1329 /* only called if r1 set */
1330 static void flush_fifo(struct qib_pportdata *ppd)
1332 struct qib_devdata *dd = ppd->dd;
1333 u32 __iomem *piobuf;
1337 const unsigned hdrwords = 7;
1338 static struct qib_ib_header ibhdr = {
1339 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1340 .lrh[1] = IB_LID_PERMISSIVE,
1341 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1342 .lrh[3] = IB_LID_PERMISSIVE,
1343 .u.oth.bth[0] = cpu_to_be32(
1344 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1345 .u.oth.bth[1] = cpu_to_be32(0),
1346 .u.oth.bth[2] = cpu_to_be32(0),
1347 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1348 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1352 * Send a dummy VL15 packet to flush the launch FIFO.
1353 * This will not actually be sent since the TxeBypassIbc bit is set.
1355 pbc = PBC_7322_VL15_SEND |
1356 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1357 (hdrwords + SIZE_OF_CRC);
1358 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1361 writeq(pbc, piobuf);
1362 hdr = (u32 *) &ibhdr;
1363 if (dd->flags & QIB_PIO_FLUSH_WC) {
1365 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1367 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1370 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1371 qib_sendbuf_done(dd, bufn);
1375 * This is called with interrupts disabled and sdma_lock held.
1377 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1379 struct qib_devdata *dd = ppd->dd;
1380 u64 set_sendctrl = 0;
1381 u64 clr_sendctrl = 0;
1383 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1384 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1386 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1388 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1389 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1391 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1393 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1394 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1396 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1398 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1399 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1400 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1401 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1403 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1404 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1405 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1407 spin_lock(&dd->sendctrl_lock);
1409 /* If we are draining everything, block sends first */
1410 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1411 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1412 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1413 qib_write_kreg(dd, kr_scratch, 0);
1416 ppd->p_sendctrl |= set_sendctrl;
1417 ppd->p_sendctrl &= ~clr_sendctrl;
1419 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1420 qib_write_kreg_port(ppd, krp_sendctrl,
1422 SYM_MASK(SendCtrl_0, SDmaCleanup));
1424 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1425 qib_write_kreg(dd, kr_scratch, 0);
1427 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1428 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1429 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1430 qib_write_kreg(dd, kr_scratch, 0);
1433 spin_unlock(&dd->sendctrl_lock);
1435 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1439 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1441 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1444 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1447 * Set SendDmaLenGen and clear and set
1448 * the MSB of the generation count to enable generation checking
1449 * and load the internal generation counter.
1451 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1452 qib_write_kreg_port(ppd, krp_senddmalengen,
1453 ppd->sdma_descq_cnt |
1454 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1458 * Must be called with sdma_lock held, or before init finished.
1460 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1462 /* Commit writes to memory and advance the tail on the chip */
1464 ppd->sdma_descq_tail = tail;
1465 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1469 * This is called with interrupts disabled and sdma_lock held.
1471 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1475 * The hardware doesn't require this but we do it so that verbs
1476 * and user applications don't wait for link active to send stale
1479 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1481 qib_sdma_7322_setlengen(ppd);
1482 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1483 ppd->sdma_head_dma[0] = 0;
1484 qib_7322_sdma_sendctrl(ppd,
1485 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1488 #define DISABLES_SDMA ( \
1489 QIB_E_P_SDMAHALT | \
1490 QIB_E_P_SDMADESCADDRMISALIGN | \
1491 QIB_E_P_SDMAMISSINGDW | \
1492 QIB_E_P_SDMADWEN | \
1493 QIB_E_P_SDMARPYTAG | \
1494 QIB_E_P_SDMA1STDESC | \
1495 QIB_E_P_SDMABASE | \
1496 QIB_E_P_SDMATAILOUTOFBOUND | \
1497 QIB_E_P_SDMAOUTOFBOUND | \
1498 QIB_E_P_SDMAGENMISMATCH)
1500 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1502 unsigned long flags;
1503 struct qib_devdata *dd = ppd->dd;
1505 errs &= QIB_E_P_SDMAERRS;
1507 if (errs & QIB_E_P_SDMAUNEXPDATA)
1508 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1511 spin_lock_irqsave(&ppd->sdma_lock, flags);
1513 switch (ppd->sdma_state.current_state) {
1514 case qib_sdma_state_s00_hw_down:
1517 case qib_sdma_state_s10_hw_start_up_wait:
1518 if (errs & QIB_E_P_SDMAHALT)
1519 __qib_sdma_process_event(ppd,
1520 qib_sdma_event_e20_hw_started);
1523 case qib_sdma_state_s20_idle:
1526 case qib_sdma_state_s30_sw_clean_up_wait:
1529 case qib_sdma_state_s40_hw_clean_up_wait:
1530 if (errs & QIB_E_P_SDMAHALT)
1531 __qib_sdma_process_event(ppd,
1532 qib_sdma_event_e50_hw_cleaned);
1535 case qib_sdma_state_s50_hw_halt_wait:
1536 if (errs & QIB_E_P_SDMAHALT)
1537 __qib_sdma_process_event(ppd,
1538 qib_sdma_event_e60_hw_halted);
1541 case qib_sdma_state_s99_running:
1542 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1543 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1547 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1551 * handle per-device errors (not per-port errors)
1553 static noinline void handle_7322_errors(struct qib_devdata *dd)
1561 qib_stats.sps_errints++;
1562 errs = qib_read_kreg64(dd, kr_errstatus);
1564 qib_devinfo(dd->pcidev, "device error interrupt, "
1565 "but no error bits set!\n");
1569 /* don't report errors that are masked */
1570 errs &= dd->cspec->errormask;
1571 msg = dd->cspec->emsgbuf;
1573 /* do these first, they are most important */
1574 if (errs & QIB_E_HARDWARE) {
1576 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1578 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1579 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1580 qib_inc_eeprom_err(dd, log_idx, 1);
1582 if (errs & QIB_E_SPKTERRS) {
1583 qib_disarm_7322_senderrbufs(dd->pport);
1584 qib_stats.sps_txerrs++;
1585 } else if (errs & QIB_E_INVALIDADDR)
1586 qib_stats.sps_txerrs++;
1587 else if (errs & QIB_E_ARMLAUNCH) {
1588 qib_stats.sps_txerrs++;
1589 qib_disarm_7322_senderrbufs(dd->pport);
1591 qib_write_kreg(dd, kr_errclear, errs);
1594 * The ones we mask off are handled specially below
1595 * or above. Also mask SDMADISABLED by default as it
1598 mask = QIB_E_HARDWARE;
1601 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1602 qib_7322error_msgs);
1605 * Getting reset is a tragedy for all ports. Mark the device
1606 * _and_ the ports as "offline" in way meaningful to each.
1608 if (errs & QIB_E_RESET) {
1611 qib_dev_err(dd, "Got reset, requires re-init "
1612 "(unload and reload driver)\n");
1613 dd->flags &= ~QIB_INITTED; /* needs re-init */
1614 /* mark as having had error */
1615 *dd->devstatusp |= QIB_STATUS_HWERROR;
1616 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1617 if (dd->pport[pidx].link_speed_supported)
1618 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1622 qib_dev_err(dd, "%s error\n", msg);
1625 * If there were hdrq or egrfull errors, wake up any processes
1626 * waiting in poll. We used to try to check which contexts had
1627 * the overflow, but given the cost of that and the chip reads
1628 * to support it, it's better to just wake everybody up if we
1629 * get an overflow; waiters can poll again if it's not them.
1631 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1632 qib_handle_urcv(dd, ~0U);
1633 if (errs & ERR_MASK(RcvEgrFullErr))
1634 qib_stats.sps_buffull++;
1636 qib_stats.sps_hdrfull++;
1643 static void reenable_chase(unsigned long opaque)
1645 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1647 ppd->cpspec->chase_timer.expires = 0;
1648 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1649 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1652 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1654 ppd->cpspec->chase_end = 0;
1659 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1660 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1661 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1662 add_timer(&ppd->cpspec->chase_timer);
1665 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1670 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1673 * Detect and handle the state chase issue, where we can
1674 * get stuck if we are unlucky on timing on both sides of
1675 * the link. If we are, we disable, set a timer, and
1679 case IB_7322_LT_STATE_CFGRCVFCFG:
1680 case IB_7322_LT_STATE_CFGWAITRMT:
1681 case IB_7322_LT_STATE_TXREVLANES:
1682 case IB_7322_LT_STATE_CFGENH:
1683 tnow = get_jiffies_64();
1684 if (ppd->cpspec->chase_end &&
1685 time_after64(tnow, ppd->cpspec->chase_end))
1686 disable_chase(ppd, tnow, ibclt);
1687 else if (!ppd->cpspec->chase_end)
1688 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1691 ppd->cpspec->chase_end = 0;
1695 if (ibclt == IB_7322_LT_STATE_CFGTEST &&
1696 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1698 ppd->cpspec->qdr_reforce = 1;
1699 if (!ppd->dd->cspec->r1)
1700 serdes_7322_los_enable(ppd, 0);
1701 } else if (ppd->cpspec->qdr_reforce &&
1702 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1703 (ibclt == IB_7322_LT_STATE_CFGENH ||
1704 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1705 ibclt == IB_7322_LT_STATE_LINKUP))
1708 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1709 ppd->link_speed_enabled == QIB_IB_QDR &&
1710 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1711 ibclt == IB_7322_LT_STATE_CFGENH ||
1712 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1713 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1716 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1717 u8 ltstate = qib_7322_phys_portstate(ibcst);
1718 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1720 if (!ppd->dd->cspec->r1 &&
1721 pibclt == IB_7322_LT_STATE_LINKUP &&
1722 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1723 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1724 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1725 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1726 /* If the link went down (but no into recovery,
1727 * turn LOS back on */
1728 serdes_7322_los_enable(ppd, 1);
1729 if (!ppd->cpspec->qdr_dfe_on &&
1730 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1731 ppd->cpspec->qdr_dfe_on = 1;
1732 ppd->cpspec->qdr_dfe_time = 0;
1733 /* On link down, reenable QDR adaptation */
1734 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1735 ppd->dd->cspec->r1 ?
1736 QDR_STATIC_ADAPT_DOWN_R1 :
1737 QDR_STATIC_ADAPT_DOWN);
1738 printk(KERN_INFO QIB_DRV_NAME
1739 " IB%u:%u re-enabled QDR adaptation "
1740 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1746 * This is per-pport error handling.
1747 * will likely get it's own MSIx interrupt (one for each port,
1748 * although just a single handler).
1750 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1753 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1754 struct qib_devdata *dd = ppd->dd;
1756 /* do this as soon as possible */
1757 fmask = qib_read_kreg64(dd, kr_act_fmask);
1759 check_7322_rxe_status(ppd);
1761 errs = qib_read_kreg_port(ppd, krp_errstatus);
1763 qib_devinfo(dd->pcidev,
1764 "Port%d error interrupt, but no error bits set!\n",
1767 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1771 msg = ppd->cpspec->epmsgbuf;
1774 if (errs & ~QIB_E_P_BITSEXTANT) {
1775 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1776 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1778 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1780 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1781 " errors 0x%016Lx set (and %s)\n",
1782 (errs & ~QIB_E_P_BITSEXTANT), msg);
1786 if (errs & QIB_E_P_SHDR) {
1789 /* determine cause, then write to clear */
1790 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1791 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1792 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1795 /* senderrbuf cleared in SPKTERRS below */
1798 if (errs & QIB_E_P_SPKTERRS) {
1799 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1800 !(ppd->lflags & QIBL_LINKACTIVE)) {
1802 * This can happen when trying to bring the link
1803 * up, but the IB link changes state at the "wrong"
1804 * time. The IB logic then complains that the packet
1805 * isn't valid. We don't want to confuse people, so
1806 * we just don't print them, except at debug
1808 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1809 (errs & QIB_E_P_LINK_PKTERRS),
1810 qib_7322p_error_msgs);
1812 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1814 qib_disarm_7322_senderrbufs(ppd);
1815 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1816 !(ppd->lflags & QIBL_LINKACTIVE)) {
1818 * This can happen when SMA is trying to bring the link
1819 * up, but the IB link changes state at the "wrong" time.
1820 * The IB logic then complains that the packet isn't
1821 * valid. We don't want to confuse people, so we just
1822 * don't print them, except at debug
1824 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1825 qib_7322p_error_msgs);
1826 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1830 qib_write_kreg_port(ppd, krp_errclear, errs);
1832 errs &= ~ignore_this_time;
1836 if (errs & QIB_E_P_RPKTERRS)
1837 qib_stats.sps_rcverrs++;
1838 if (errs & QIB_E_P_SPKTERRS)
1839 qib_stats.sps_txerrs++;
1841 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1843 if (errs & QIB_E_P_SDMAERRS)
1844 sdma_7322_p_errors(ppd, errs);
1846 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1850 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1851 ltstate = qib_7322_phys_portstate(ibcs);
1853 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1854 handle_serdes_issues(ppd, ibcs);
1855 if (!(ppd->cpspec->ibcctrl_a &
1856 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1858 * We got our interrupt, so init code should be
1859 * happy and not try alternatives. Now squelch
1860 * other "chatter" from link-negotiation (pre Init)
1862 ppd->cpspec->ibcctrl_a |=
1863 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1864 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1865 ppd->cpspec->ibcctrl_a);
1868 /* Update our picture of width and speed from chip */
1869 ppd->link_width_active =
1870 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1871 IB_WIDTH_4X : IB_WIDTH_1X;
1872 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1873 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1874 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1875 QIB_IB_DDR : QIB_IB_SDR;
1877 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1878 IB_PHYSPORTSTATE_DISABLED)
1879 qib_set_ib_7322_lstate(ppd, 0,
1880 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1883 * Since going into a recovery state causes the link
1884 * state to go down and since recovery is transitory,
1885 * it is better if we "miss" ever seeing the link
1886 * training state go into recovery (i.e., ignore this
1887 * transition for link state special handling purposes)
1888 * without updating lastibcstat.
1890 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1891 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1892 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1893 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1894 qib_handle_e_ibstatuschanged(ppd, ibcs);
1897 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1899 if (ppd->state_wanted & ppd->lflags)
1900 wake_up_interruptible(&ppd->state_wait);
1905 /* enable/disable chip from delivering interrupts */
1906 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1909 if (dd->flags & QIB_BADINTR)
1911 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1912 /* cause any pending enabled interrupts to be re-delivered */
1913 qib_write_kreg(dd, kr_intclear, 0ULL);
1914 if (dd->cspec->num_msix_entries) {
1915 /* and same for MSIx */
1916 u64 val = qib_read_kreg64(dd, kr_intgranted);
1918 qib_write_kreg(dd, kr_intgranted, val);
1921 qib_write_kreg(dd, kr_intmask, 0ULL);
1925 * Try to cleanup as much as possible for anything that might have gone
1926 * wrong while in freeze mode, such as pio buffers being written by user
1927 * processes (causing armlaunch), send errors due to going into freeze mode,
1928 * etc., and try to avoid causing extra interrupts while doing so.
1929 * Forcibly update the in-memory pioavail register copies after cleanup
1930 * because the chip won't do it while in freeze mode (the register values
1931 * themselves are kept correct).
1932 * Make sure that we don't lose any important interrupts by using the chip
1933 * feature that says that writing 0 to a bit in *clear that is set in
1934 * *status will cause an interrupt to be generated again (if allowed by
1936 * This is in chip-specific code because of all of the register accesses,
1937 * even though the details are similar on most chips.
1939 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1943 /* disable error interrupts, to avoid confusion */
1944 qib_write_kreg(dd, kr_errmask, 0ULL);
1946 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1947 if (dd->pport[pidx].link_speed_supported)
1948 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1951 /* also disable interrupts; errormask is sometimes overwriten */
1952 qib_7322_set_intr_state(dd, 0);
1954 /* clear the freeze, and be sure chip saw it */
1955 qib_write_kreg(dd, kr_control, dd->control);
1956 qib_read_kreg32(dd, kr_scratch);
1959 * Force new interrupt if any hwerr, error or interrupt bits are
1960 * still set, and clear "safe" send packet errors related to freeze
1961 * and cancelling sends. Re-enable error interrupts before possible
1962 * force of re-interrupt on pending interrupts.
1964 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1965 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1966 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1967 /* We need to purge per-port errs and reset mask, too */
1968 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1969 if (!dd->pport[pidx].link_speed_supported)
1971 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1972 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1974 qib_7322_set_intr_state(dd, 1);
1977 /* no error handling to speak of */
1979 * qib_7322_handle_hwerrors - display hardware errors.
1980 * @dd: the qlogic_ib device
1981 * @msg: the output buffer
1982 * @msgl: the size of the output buffer
1984 * Use same msg buffer as regular errors to avoid excessive stack
1985 * use. Most hardware errors are catastrophic, but for right now,
1986 * we'll print them and continue. We reuse the same message buffer as
1987 * qib_handle_errors() to avoid excessive stack usage.
1989 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
1996 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1999 if (hwerrs == ~0ULL) {
2000 qib_dev_err(dd, "Read of hardware error status failed "
2001 "(all bits set); ignoring\n");
2004 qib_stats.sps_hwerrs++;
2006 /* Always clear the error status register, except BIST fail */
2007 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2008 ~HWE_MASK(PowerOnBISTFailed));
2010 hwerrs &= dd->cspec->hwerrmask;
2012 /* no EEPROM logging, yet */
2015 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2016 "(cleared)\n", (unsigned long long) hwerrs);
2018 ctrl = qib_read_kreg32(dd, kr_control);
2019 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2021 * No recovery yet...
2023 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2024 dd->cspec->stay_in_freeze) {
2026 * If any set that we aren't ignoring only make the
2027 * complaint once, in case it's stuck or recurring,
2028 * and we get here multiple times
2029 * Force link down, so switch knows, and
2030 * LEDs are turned off.
2032 if (dd->flags & QIB_INITTED)
2035 qib_7322_clear_freeze(dd);
2038 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2040 strlcpy(msg, "[Memory BIST test failed, "
2041 "InfiniPath hardware unusable]", msgl);
2042 /* ignore from now on, so disable until driver reloaded */
2043 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2044 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2047 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2049 /* Ignore esoteric PLL failures et al. */
2051 qib_dev_err(dd, "%s hardware error\n", msg);
2053 if (isfatal && !dd->diag_client) {
2054 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2055 " usable, SN %.16s\n", dd->serial);
2057 * for /sys status file and user programs to print; if no
2058 * trailing brace is copied, we'll know it was truncated.
2061 snprintf(dd->freezemsg, dd->freezelen,
2063 qib_disable_after_error(dd);
2069 * qib_7322_init_hwerrors - enable hardware errors
2070 * @dd: the qlogic_ib device
2072 * now that we have finished initializing everything that might reasonably
2073 * cause a hardware error, and cleared those errors bits as they occur,
2074 * we can enable hardware errors in the mask (potentially enabling
2075 * freeze mode), and enable hardware errors as errors (along with
2076 * everything else) in errormask
2078 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2083 extsval = qib_read_kreg64(dd, kr_extstatus);
2084 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2085 QIB_EXTS_MEMBIST_ENDTEST)))
2086 qib_dev_err(dd, "MemBIST did not complete!\n");
2088 /* never clear BIST failure, so reported on each driver load */
2089 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2090 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2093 qib_write_kreg(dd, kr_errclear, ~0ULL);
2094 /* enable errors that are masked, at least this first time. */
2095 qib_write_kreg(dd, kr_errmask, ~0ULL);
2096 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2097 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2098 if (dd->pport[pidx].link_speed_supported)
2099 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2104 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2105 * on chips that are count-based, rather than trigger-based. There is no
2106 * reference counting, but that's also fine, given the intended use.
2107 * Only chip-specific because it's all register accesses
2109 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2112 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2113 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2115 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2116 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2120 * Formerly took parameter <which> in pre-shifted,
2121 * pre-merged form with LinkCmd and LinkInitCmd
2122 * together, and assuming the zero was NOP.
2124 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2128 struct qib_devdata *dd = ppd->dd;
2129 unsigned long flags;
2131 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2133 * If we are told to disable, note that so link-recovery
2134 * code does not attempt to bring us back up.
2135 * Also reset everything that we can, so we start
2136 * completely clean when re-enabled (before we
2137 * actually issue the disable to the IBC)
2139 qib_7322_mini_pcs_reset(ppd);
2140 spin_lock_irqsave(&ppd->lflags_lock, flags);
2141 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2142 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2143 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2145 * Any other linkinitcmd will lead to LINKDOWN and then
2146 * to INIT (if all is well), so clear flag to let
2147 * link-recovery code attempt to bring us back up.
2149 spin_lock_irqsave(&ppd->lflags_lock, flags);
2150 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2151 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2153 * Clear status change interrupt reduction so the
2154 * new state is seen.
2156 ppd->cpspec->ibcctrl_a &=
2157 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2160 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2161 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2163 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2165 /* write to chip to prevent back-to-back writes of ibc reg */
2166 qib_write_kreg(dd, kr_scratch, 0);
2171 * The total RCV buffer memory is 64KB, used for both ports, and is
2172 * in units of 64 bytes (same as IB flow control credit unit).
2173 * The consumedVL unit in the same registers are in 32 byte units!
2174 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2175 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2176 * in krp_rxcreditvl15, rather than 10.
2178 #define RCV_BUF_UNITSZ 64
2179 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2181 static void set_vls(struct qib_pportdata *ppd)
2183 int i, numvls, totcred, cred_vl, vl0extra;
2184 struct qib_devdata *dd = ppd->dd;
2187 numvls = qib_num_vls(ppd->vls_operational);
2190 * Set up per-VL credits. Below is kluge based on these assumptions:
2191 * 1) port is disabled at the time early_init is called.
2192 * 2) give VL15 17 credits, for two max-plausible packets.
2193 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2195 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2196 totcred = NUM_RCV_BUF_UNITS(dd);
2197 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2199 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2200 cred_vl = totcred / numvls;
2201 vl0extra = totcred - cred_vl * numvls;
2202 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2203 for (i = 1; i < numvls; i++)
2204 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2205 for (; i < 8; i++) /* no buffer space for other VLs */
2206 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2208 /* Notify IBC that credits need to be recalculated */
2209 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2210 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2211 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2212 qib_write_kreg(dd, kr_scratch, 0ULL);
2213 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2214 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2216 for (i = 0; i < numvls; i++)
2217 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2218 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2220 /* Change the number of operational VLs */
2221 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2222 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2223 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2224 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2225 qib_write_kreg(dd, kr_scratch, 0ULL);
2229 * The code that deals with actual SerDes is in serdes_7322_init().
2230 * Compared to the code for iba7220, it is minimal.
2232 static int serdes_7322_init(struct qib_pportdata *ppd);
2235 * qib_7322_bringup_serdes - bring up the serdes
2236 * @ppd: physical port on the qlogic_ib device
2238 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2240 struct qib_devdata *dd = ppd->dd;
2242 unsigned long flags;
2246 * SerDes model not in Pd, but still need to
2247 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2250 /* Put IBC in reset, sends disabled (should be in reset already) */
2251 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2252 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2253 qib_write_kreg(dd, kr_scratch, 0ULL);
2255 if (qib_compat_ddr_negotiate) {
2256 ppd->cpspec->ibdeltainprog = 1;
2257 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2259 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2260 crp_iblinkerrrecov);
2263 /* flowcontrolwatermark is in units of KBytes */
2264 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2266 * Flow control is sent this often, even if no changes in
2267 * buffer space occur. Units are 128ns for this chip.
2270 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2271 /* max error tolerance */
2272 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2273 /* IB credit flow control. */
2274 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2276 * set initial max size pkt IBC will send, including ICRC; it's the
2277 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2279 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2280 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2281 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2283 /* initially come up waiting for TS1, without sending anything. */
2284 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2285 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2288 * Reset the PCS interface to the serdes (and also ibc, which is still
2289 * in reset from above). Writes new value of ibcctrl_a as last step.
2291 qib_7322_mini_pcs_reset(ppd);
2292 qib_write_kreg(dd, kr_scratch, 0ULL);
2294 if (!ppd->cpspec->ibcctrl_b) {
2295 unsigned lse = ppd->link_speed_enabled;
2298 * Not on re-init after reset, establish shadow
2299 * and force initial config.
2301 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2303 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2304 IBA7322_IBC_SPEED_DDR |
2305 IBA7322_IBC_SPEED_SDR |
2306 IBA7322_IBC_WIDTH_AUTONEG |
2307 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2308 if (lse & (lse - 1)) /* Muliple speeds enabled */
2309 ppd->cpspec->ibcctrl_b |=
2310 (lse << IBA7322_IBC_SPEED_LSB) |
2311 IBA7322_IBC_IBTA_1_2_MASK |
2312 IBA7322_IBC_MAX_SPEED_MASK;
2314 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2315 IBA7322_IBC_SPEED_QDR |
2316 IBA7322_IBC_IBTA_1_2_MASK :
2317 (lse == QIB_IB_DDR) ?
2318 IBA7322_IBC_SPEED_DDR :
2319 IBA7322_IBC_SPEED_SDR;
2320 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2321 (IB_WIDTH_1X | IB_WIDTH_4X))
2322 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2324 ppd->cpspec->ibcctrl_b |=
2325 ppd->link_width_enabled == IB_WIDTH_4X ?
2326 IBA7322_IBC_WIDTH_4X_ONLY :
2327 IBA7322_IBC_WIDTH_1X_ONLY;
2329 /* always enable these on driver reload, not sticky */
2330 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2331 IBA7322_IBC_HRTBT_MASK);
2333 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2335 /* setup so we have more time at CFGTEST to change H1 */
2336 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2337 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2338 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2339 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2341 serdes_7322_init(ppd);
2343 guid = be64_to_cpu(ppd->guid);
2346 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2347 ppd->guid = cpu_to_be64(guid);
2350 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2351 /* write to chip to prevent back-to-back writes of ibc reg */
2352 qib_write_kreg(dd, kr_scratch, 0);
2355 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2358 /* be paranoid against later code motion, etc. */
2359 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2360 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2361 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2362 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2364 /* Also enable IBSTATUSCHG interrupt. */
2365 val = qib_read_kreg_port(ppd, krp_errmask);
2366 qib_write_kreg_port(ppd, krp_errmask,
2367 val | ERR_MASK_N(IBStatusChanged));
2369 /* Always zero until we start messing with SerDes for real */
2374 * qib_7322_quiet_serdes - set serdes to txidle
2375 * @dd: the qlogic_ib device
2376 * Called when driver is being unloaded
2378 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2381 unsigned long flags;
2383 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2385 spin_lock_irqsave(&ppd->lflags_lock, flags);
2386 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2387 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2388 wake_up(&ppd->cpspec->autoneg_wait);
2389 cancel_delayed_work(&ppd->cpspec->autoneg_work);
2390 if (ppd->dd->cspec->r1)
2391 cancel_delayed_work(&ppd->cpspec->ipg_work);
2392 flush_scheduled_work();
2394 ppd->cpspec->chase_end = 0;
2395 if (ppd->cpspec->chase_timer.data) /* if initted */
2396 del_timer_sync(&ppd->cpspec->chase_timer);
2399 * Despite the name, actually disables IBC as well. Do it when
2400 * we are as sure as possible that no more packets can be
2401 * received, following the down and the PCS reset.
2402 * The actual disabling happens in qib_7322_mini_pci_reset(),
2403 * along with the PCS being reset.
2405 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2406 qib_7322_mini_pcs_reset(ppd);
2409 * Update the adjusted counters so the adjustment persists
2410 * across driver reload.
2412 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2413 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2414 struct qib_devdata *dd = ppd->dd;
2417 /* enable counter writes */
2418 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2419 qib_write_kreg(dd, kr_hwdiagctrl,
2420 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2422 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2423 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2424 if (ppd->cpspec->ibdeltainprog)
2425 val -= val - ppd->cpspec->ibsymsnap;
2426 val -= ppd->cpspec->ibsymdelta;
2427 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2429 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2430 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2431 if (ppd->cpspec->ibdeltainprog)
2432 val -= val - ppd->cpspec->iblnkerrsnap;
2433 val -= ppd->cpspec->iblnkerrdelta;
2434 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2436 if (ppd->cpspec->iblnkdowndelta) {
2437 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2438 val += ppd->cpspec->iblnkdowndelta;
2439 write_7322_creg_port(ppd, crp_iblinkdown, val);
2442 * No need to save ibmalfdelta since IB perfcounters
2443 * are cleared on driver reload.
2446 /* and disable counter writes */
2447 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2452 * qib_setup_7322_setextled - set the state of the two external LEDs
2453 * @ppd: physical port on the qlogic_ib device
2454 * @on: whether the link is up or not
2456 * The exact combo of LEDs if on is true is determined by looking
2459 * These LEDs indicate the physical and logical state of IB link.
2460 * For this chip (at least with recommended board pinouts), LED1
2461 * is Yellow (logical state) and LED2 is Green (physical state),
2463 * Note: We try to match the Mellanox HCA LED behavior as best
2464 * we can. Green indicates physical link state is OK (something is
2465 * plugged in, and we can train).
2466 * Amber indicates the link is logically up (ACTIVE).
2467 * Mellanox further blinks the amber LED to indicate data packet
2468 * activity, but we have no hardware support for that, so it would
2469 * require waking up every 10-20 msecs and checking the counters
2470 * on the chip, and then turning the LED off if appropriate. That's
2471 * visible overhead, so not something we will do.
2473 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2475 struct qib_devdata *dd = ppd->dd;
2476 u64 extctl, ledblink = 0, val;
2477 unsigned long flags;
2481 * The diags use the LED to indicate diag info, so we leave
2482 * the external LED alone when the diags are running.
2484 if (dd->diag_client)
2487 /* Allow override of LED display for, e.g. Locating system in rack */
2488 if (ppd->led_override) {
2489 grn = (ppd->led_override & QIB_LED_PHYS);
2490 yel = (ppd->led_override & QIB_LED_LOG);
2492 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2493 grn = qib_7322_phys_portstate(val) ==
2494 IB_PHYSPORTSTATE_LINKUP;
2495 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2501 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2502 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2503 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2505 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2507 * Counts are in chip clock (4ns) periods.
2508 * This is 1/16 sec (66.6ms) on,
2509 * 3/16 sec (187.5 ms) off, with packets rcvd.
2511 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2512 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2515 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2516 dd->cspec->extctrl = extctl;
2517 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2518 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2520 if (ledblink) /* blink the LED on packet receive */
2521 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2525 * Disable MSIx interrupt if enabled, call generic MSIx code
2526 * to cleanup, and clear pending MSIx interrupts.
2527 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2529 static void qib_7322_nomsix(struct qib_devdata *dd)
2534 dd->cspec->main_int_mask = ~0ULL;
2535 n = dd->cspec->num_msix_entries;
2539 dd->cspec->num_msix_entries = 0;
2540 for (i = 0; i < n; i++)
2541 free_irq(dd->cspec->msix_entries[i].vector,
2542 dd->cspec->msix_arg[i]);
2545 /* make sure no MSIx interrupts are left pending */
2546 intgranted = qib_read_kreg64(dd, kr_intgranted);
2548 qib_write_kreg(dd, kr_intgranted, intgranted);
2551 static void qib_7322_free_irq(struct qib_devdata *dd)
2553 if (dd->cspec->irq) {
2554 free_irq(dd->cspec->irq, dd);
2557 qib_7322_nomsix(dd);
2560 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2564 qib_7322_free_irq(dd);
2565 kfree(dd->cspec->cntrs);
2566 kfree(dd->cspec->sendchkenable);
2567 kfree(dd->cspec->sendgrhchk);
2568 kfree(dd->cspec->sendibchk);
2569 kfree(dd->cspec->msix_entries);
2570 kfree(dd->cspec->msix_arg);
2571 for (i = 0; i < dd->num_pports; i++) {
2572 unsigned long flags;
2573 u32 mask = QSFP_GPIO_MOD_PRS_N |
2574 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2576 kfree(dd->pport[i].cpspec->portcntrs);
2577 if (dd->flags & QIB_HAS_QSFP) {
2578 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2579 dd->cspec->gpio_mask &= ~mask;
2580 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2581 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2582 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2584 if (dd->pport[i].ibport_data.smi_ah)
2585 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2589 /* handle SDMA interrupts */
2590 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2592 struct qib_pportdata *ppd0 = &dd->pport[0];
2593 struct qib_pportdata *ppd1 = &dd->pport[1];
2594 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2595 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2596 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2597 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2600 qib_sdma_intr(ppd0);
2602 qib_sdma_intr(ppd1);
2604 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2605 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2606 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2607 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2611 * Set or clear the Send buffer available interrupt enable bit.
2613 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2615 unsigned long flags;
2617 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2619 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2621 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2622 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2623 qib_write_kreg(dd, kr_scratch, 0ULL);
2624 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2628 * Somehow got an interrupt with reserved bits set in interrupt status.
2629 * Print a message so we know it happened, then clear them.
2630 * keep mainline interrupt handler cache-friendly
2632 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2637 kills = istat & ~QIB_I_BITSEXTANT;
2638 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2639 " %s\n", (unsigned long long) kills, msg);
2640 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2643 /* keep mainline interrupt handler cache-friendly */
2644 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2651 * Boards for this chip currently don't use GPIO interrupts,
2652 * so clear by writing GPIOstatus to GPIOclear, and complain
2653 * to developer. To avoid endless repeats, clear
2654 * the bits in the mask, since there is some kind of
2655 * programming error or chip problem.
2657 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2659 * In theory, writing GPIOstatus to GPIOclear could
2660 * have a bad side-effect on some diagnostic that wanted
2661 * to poll for a status-change, but the various shadows
2662 * make that problematic at best. Diags will just suppress
2663 * all GPIO interrupts during such tests.
2665 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2667 * Check for QSFP MOD_PRS changes
2668 * only works for single port if IB1 != pidx1
2670 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2672 struct qib_pportdata *ppd;
2673 struct qib_qsfp_data *qd;
2675 if (!dd->pport[pidx].link_speed_supported)
2677 mask = QSFP_GPIO_MOD_PRS_N;
2678 ppd = dd->pport + pidx;
2679 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2680 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2682 qd = &ppd->cpspec->qsfp_data;
2683 gpiostatus &= ~mask;
2684 pins = qib_read_kreg64(dd, kr_extstatus);
2685 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2686 if (!(pins & mask)) {
2688 qd->t_insert = get_jiffies_64();
2689 schedule_work(&qd->work);
2694 if (gpiostatus && !handled) {
2695 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2696 u32 gpio_irq = mask & gpiostatus;
2699 * Clear any troublemakers, and update chip from shadow
2701 dd->cspec->gpio_mask &= ~gpio_irq;
2702 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2707 * Handle errors and unusual events first, separate function
2708 * to improve cache hits for fast path interrupt handling.
2710 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2712 if (istat & ~QIB_I_BITSEXTANT)
2713 unknown_7322_ibits(dd, istat);
2714 if (istat & QIB_I_GPIO)
2715 unknown_7322_gpio_intr(dd);
2716 if (istat & QIB_I_C_ERROR)
2717 handle_7322_errors(dd);
2718 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2719 handle_7322_p_errors(dd->rcd[0]->ppd);
2720 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2721 handle_7322_p_errors(dd->rcd[1]->ppd);
2725 * Dynamically adjust the rcv int timeout for a context based on incoming
2728 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2730 struct qib_devdata *dd = rcd->dd;
2731 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2734 * Dynamically adjust idle timeout on chip
2735 * based on number of packets processed.
2737 if (npkts < rcv_int_count && timeout > 2)
2739 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2740 timeout = min(timeout << 1, rcv_int_timeout);
2744 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2745 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2749 * This is the main interrupt handler.
2750 * It will normally only be used for low frequency interrupts but may
2751 * have to handle all interrupts if INTx is enabled or fewer than normal
2752 * MSIx interrupts were allocated.
2753 * This routine should ignore the interrupt bits for any of the
2754 * dedicated MSIx handlers.
2756 static irqreturn_t qib_7322intr(int irq, void *data)
2758 struct qib_devdata *dd = data;
2766 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2768 * This return value is not great, but we do not want the
2769 * interrupt core code to remove our interrupt handler
2770 * because we don't appear to be handling an interrupt
2771 * during a chip reset.
2777 istat = qib_read_kreg64(dd, kr_intstatus);
2779 if (unlikely(istat == ~0ULL)) {
2780 qib_bad_intrstatus(dd);
2781 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2782 /* don't know if it was our interrupt or not */
2787 istat &= dd->cspec->main_int_mask;
2788 if (unlikely(!istat)) {
2789 /* already handled, or shared and not us */
2794 qib_stats.sps_ints++;
2795 if (dd->int_counter != (u32) -1)
2798 /* handle "errors" of various kinds first, device ahead of port */
2799 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2800 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2801 INT_MASK_P(Err, 1))))
2802 unlikely_7322_intr(dd, istat);
2805 * Clear the interrupt bits we found set, relatively early, so we
2806 * "know" know the chip will have seen this by the time we process
2807 * the queue, and will re-interrupt if necessary. The processor
2808 * itself won't take the interrupt again until we return.
2810 qib_write_kreg(dd, kr_intclear, istat);
2813 * Handle kernel receive queues before checking for pio buffers
2814 * available since receives can overflow; piobuf waiters can afford
2815 * a few extra cycles, since they were waiting anyway.
2817 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2819 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2820 (1ULL << QIB_I_RCVURG_LSB);
2821 for (i = 0; i < dd->first_user_ctxt; i++) {
2822 if (ctxtrbits & rmask) {
2823 ctxtrbits &= ~rmask;
2825 qib_kreceive(dd->rcd[i], NULL, &npkts);
2826 adjust_rcv_timeout(dd->rcd[i], npkts);
2832 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2833 (ctxtrbits >> QIB_I_RCVURG_LSB);
2834 qib_handle_urcv(dd, ctxtrbits);
2838 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2839 sdma_7322_intr(dd, istat);
2841 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2842 qib_ib_piobufavail(dd);
2850 * Dedicated receive packet available interrupt handler.
2852 static irqreturn_t qib_7322pintr(int irq, void *data)
2854 struct qib_ctxtdata *rcd = data;
2855 struct qib_devdata *dd = rcd->dd;
2858 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2860 * This return value is not great, but we do not want the
2861 * interrupt core code to remove our interrupt handler
2862 * because we don't appear to be handling an interrupt
2863 * during a chip reset.
2867 qib_stats.sps_ints++;
2868 if (dd->int_counter != (u32) -1)
2871 /* Clear the interrupt bit we expect to be set. */
2872 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2873 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2875 qib_kreceive(rcd, NULL, &npkts);
2876 adjust_rcv_timeout(rcd, npkts);
2882 * Dedicated Send buffer available interrupt handler.
2884 static irqreturn_t qib_7322bufavail(int irq, void *data)
2886 struct qib_devdata *dd = data;
2888 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2890 * This return value is not great, but we do not want the
2891 * interrupt core code to remove our interrupt handler
2892 * because we don't appear to be handling an interrupt
2893 * during a chip reset.
2897 qib_stats.sps_ints++;
2898 if (dd->int_counter != (u32) -1)
2901 /* Clear the interrupt bit we expect to be set. */
2902 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2904 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2905 if (dd->flags & QIB_INITTED)
2906 qib_ib_piobufavail(dd);
2908 qib_wantpiobuf_7322_intr(dd, 0);
2914 * Dedicated Send DMA interrupt handler.
2916 static irqreturn_t sdma_intr(int irq, void *data)
2918 struct qib_pportdata *ppd = data;
2919 struct qib_devdata *dd = ppd->dd;
2921 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2923 * This return value is not great, but we do not want the
2924 * interrupt core code to remove our interrupt handler
2925 * because we don't appear to be handling an interrupt
2926 * during a chip reset.
2930 qib_stats.sps_ints++;
2931 if (dd->int_counter != (u32) -1)
2934 /* Clear the interrupt bit we expect to be set. */
2935 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2936 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2943 * Dedicated Send DMA idle interrupt handler.
2945 static irqreturn_t sdma_idle_intr(int irq, void *data)
2947 struct qib_pportdata *ppd = data;
2948 struct qib_devdata *dd = ppd->dd;
2950 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2952 * This return value is not great, but we do not want the
2953 * interrupt core code to remove our interrupt handler
2954 * because we don't appear to be handling an interrupt
2955 * during a chip reset.
2959 qib_stats.sps_ints++;
2960 if (dd->int_counter != (u32) -1)
2963 /* Clear the interrupt bit we expect to be set. */
2964 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2965 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2972 * Dedicated Send DMA progress interrupt handler.
2974 static irqreturn_t sdma_progress_intr(int irq, void *data)
2976 struct qib_pportdata *ppd = data;
2977 struct qib_devdata *dd = ppd->dd;
2979 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2981 * This return value is not great, but we do not want the
2982 * interrupt core code to remove our interrupt handler
2983 * because we don't appear to be handling an interrupt
2984 * during a chip reset.
2988 qib_stats.sps_ints++;
2989 if (dd->int_counter != (u32) -1)
2992 /* Clear the interrupt bit we expect to be set. */
2993 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2994 INT_MASK_P(SDmaProgress, 1) :
2995 INT_MASK_P(SDmaProgress, 0));
3002 * Dedicated Send DMA cleanup interrupt handler.
3004 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3006 struct qib_pportdata *ppd = data;
3007 struct qib_devdata *dd = ppd->dd;
3009 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3011 * This return value is not great, but we do not want the
3012 * interrupt core code to remove our interrupt handler
3013 * because we don't appear to be handling an interrupt
3014 * during a chip reset.
3018 qib_stats.sps_ints++;
3019 if (dd->int_counter != (u32) -1)
3022 /* Clear the interrupt bit we expect to be set. */
3023 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3024 INT_MASK_PM(SDmaCleanupDone, 1) :
3025 INT_MASK_PM(SDmaCleanupDone, 0));
3026 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3032 * Set up our chip-specific interrupt handler.
3033 * The interrupt type has already been setup, so
3034 * we just need to do the registration and error checking.
3035 * If we are using MSIx interrupts, we may fall back to
3036 * INTx later, if the interrupt handler doesn't get called
3037 * within 1/2 second (see verify_interrupt()).
3039 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3041 int ret, i, msixnum;
3045 if (!dd->num_pports)
3050 * if not switching interrupt types, be sure interrupts are
3051 * disabled, and then clear anything pending at this point,
3052 * because we are starting clean.
3054 qib_7322_set_intr_state(dd, 0);
3056 /* clear the reset error, init error/hwerror mask */
3057 qib_7322_init_hwerrors(dd);
3059 /* clear any interrupt bits that might be set */
3060 qib_write_kreg(dd, kr_intclear, ~0ULL);
3062 /* make sure no pending MSIx intr, and clear diag reg */
3063 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3064 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3067 if (!dd->cspec->num_msix_entries) {
3068 /* Try to get INTx interrupt */
3070 if (!dd->pcidev->irq) {
3071 qib_dev_err(dd, "irq is 0, BIOS error? "
3072 "Interrupts won't work\n");
3075 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3076 IRQF_SHARED, QIB_DRV_NAME, dd);
3078 qib_dev_err(dd, "Couldn't setup INTx "
3079 "interrupt (irq=%d): %d\n",
3080 dd->pcidev->irq, ret);
3083 dd->cspec->irq = dd->pcidev->irq;
3084 dd->cspec->main_int_mask = ~0ULL;
3088 /* Try to get MSIx interrupts */
3089 memset(redirect, 0, sizeof redirect);
3092 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3093 irq_handler_t handler;
3099 if (i < ARRAY_SIZE(irq_table)) {
3100 if (irq_table[i].port) {
3101 /* skip if for a non-configured port */
3102 if (irq_table[i].port > dd->num_pports)
3104 arg = dd->pport + irq_table[i].port - 1;
3107 lsb = irq_table[i].lsb;
3108 handler = irq_table[i].handler;
3109 name = irq_table[i].name;
3113 ctxt = i - ARRAY_SIZE(irq_table);
3114 /* per krcvq context receive interrupt */
3115 arg = dd->rcd[ctxt];
3118 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3119 handler = qib_7322pintr;
3120 name = QIB_DRV_NAME " (kctx)";
3122 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3123 handler, 0, name, arg);
3126 * Shouldn't happen since the enable said we could
3127 * have as many as we are trying to setup here.
3129 qib_dev_err(dd, "Couldn't setup MSIx "
3130 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3131 dd->cspec->msix_entries[msixnum].vector,
3133 qib_7322_nomsix(dd);
3136 dd->cspec->msix_arg[msixnum] = arg;
3138 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3139 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3140 SYM_LSB(IntRedirect0, vec1);
3141 mask &= ~(1ULL << lsb);
3142 redirect[reg] |= ((u64) msixnum) << sh;
3144 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3145 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3148 /* Initialize the vector mapping */
3149 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3150 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3151 dd->cspec->main_int_mask = mask;
3156 * qib_7322_boardname - fill in the board name and note features
3157 * @dd: the qlogic_ib device
3159 * info will be based on the board revision register
3161 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3163 /* Will need enumeration of board-types here */
3165 u32 boardid, namelen;
3166 unsigned features = DUAL_PORT_CAP;
3168 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3172 n = "InfiniPath_QLE7342_Emulation";
3175 n = "InfiniPath_QLE7340";
3176 dd->flags |= QIB_HAS_QSFP;
3177 features = PORT_SPD_CAP;
3180 n = "InfiniPath_QLE7342";
3181 dd->flags |= QIB_HAS_QSFP;
3184 n = "InfiniPath_QMI7342";
3187 n = "InfiniPath_Unsupported7342";
3188 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3192 n = "InfiniPath_QMH7342";
3196 n = "InfiniPath_QME7342";
3199 n = "InfiniPath_QME7362";
3200 dd->flags |= QIB_HAS_QSFP;
3203 n = "InfiniPath_QLE7342_TEST";
3204 dd->flags |= QIB_HAS_QSFP;
3207 n = "InfiniPath_QLE73xy_UNKNOWN";
3208 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3211 dd->board_atten = 1; /* index into txdds_Xdr */
3213 namelen = strlen(n) + 1;
3214 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3216 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3218 snprintf(dd->boardname, namelen, "%s", n);
3220 snprintf(dd->boardversion, sizeof(dd->boardversion),
3221 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3222 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3223 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3224 dd->majrev, dd->minrev,
3225 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3227 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3228 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3229 " by module parameter\n", dd->unit);
3230 features &= PORT_SPD_CAP;
3237 * This routine sleeps, so it can only be called from user context, not
3238 * from interrupt context.
3240 static int qib_do_7322_reset(struct qib_devdata *dd)
3244 int i, msix_entries, ret = 1;
3246 u8 int_line, clinesz;
3247 unsigned long flags;
3249 /* Use dev_err so it shows up in logs, etc. */
3250 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3252 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3254 msix_entries = dd->cspec->num_msix_entries;
3256 /* no interrupts till re-initted */
3257 qib_7322_set_intr_state(dd, 0);
3260 qib_7322_nomsix(dd);
3261 /* can be up to 512 bytes, too big for stack */
3262 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3263 sizeof(u64), GFP_KERNEL);
3265 qib_dev_err(dd, "No mem to save MSIx data\n");
3267 msix_vecsave = NULL;
3270 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3271 * info that is set up by the BIOS, so we have to save and restore
3272 * it ourselves. There is some risk something could change it,
3273 * after we save it, but since we have disabled the MSIx, it
3274 * shouldn't be touched...
3276 for (i = 0; i < msix_entries; i++) {
3277 u64 vecaddr, vecdata;
3278 vecaddr = qib_read_kreg64(dd, 2 * i +
3279 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3280 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3281 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3283 msix_vecsave[2 * i] = vecaddr;
3284 /* save it without the masked bit set */
3285 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3289 dd->pport->cpspec->ibdeltainprog = 0;
3290 dd->pport->cpspec->ibsymdelta = 0;
3291 dd->pport->cpspec->iblnkerrdelta = 0;
3292 dd->pport->cpspec->ibmalfdelta = 0;
3293 dd->int_counter = 0; /* so we check interrupts work again */
3296 * Keep chip from being accessed until we are ready. Use
3297 * writeq() directly, to allow the write even though QIB_PRESENT
3300 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3301 dd->flags |= QIB_DOING_RESET;
3302 val = dd->control | QLOGIC_IB_C_RESET;
3303 writeq(val, &dd->kregbase[kr_control]);
3305 for (i = 1; i <= 5; i++) {
3307 * Allow MBIST, etc. to complete; longer on each retry.
3308 * We sometimes get machine checks from bus timeout if no
3309 * response, so for now, make it *really* long.
3311 msleep(1000 + (1 + i) * 3000);
3313 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3316 * Use readq directly, so we don't need to mark it as PRESENT
3317 * until we get a successful indication that all is well.
3319 val = readq(&dd->kregbase[kr_revision]);
3320 if (val == dd->revision)
3323 qib_dev_err(dd, "Failed to initialize after reset, "
3330 dd->flags |= QIB_PRESENT; /* it's back */
3333 /* restore the MSIx vector address and data if saved above */
3334 for (i = 0; i < msix_entries; i++) {
3335 dd->cspec->msix_entries[i].entry = i;
3336 if (!msix_vecsave || !msix_vecsave[2 * i])
3338 qib_write_kreg(dd, 2 * i +
3339 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3340 msix_vecsave[2 * i]);
3341 qib_write_kreg(dd, 1 + 2 * i +
3342 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3343 msix_vecsave[1 + 2 * i]);
3347 /* initialize the remaining registers. */
3348 for (i = 0; i < dd->num_pports; ++i)
3349 write_7322_init_portregs(&dd->pport[i]);
3350 write_7322_initregs(dd);
3352 if (qib_pcie_params(dd, dd->lbus_width,
3353 &dd->cspec->num_msix_entries,
3354 dd->cspec->msix_entries))
3355 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3356 "continuing anyway\n");
3358 qib_setup_7322_interrupt(dd, 1);
3360 for (i = 0; i < dd->num_pports; ++i) {
3361 struct qib_pportdata *ppd = &dd->pport[i];
3363 spin_lock_irqsave(&ppd->lflags_lock, flags);
3364 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3365 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3366 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3370 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3371 kfree(msix_vecsave);
3376 * qib_7322_put_tid - write a TID to the chip
3377 * @dd: the qlogic_ib device
3378 * @tidptr: pointer to the expected TID (in chip) to update
3379 * @tidtype: 0 for eager, 1 for expected
3380 * @pa: physical address of in memory buffer; tidinvalid if freeing
3382 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3383 u32 type, unsigned long pa)
3385 if (!(dd->flags & QIB_PRESENT))
3387 if (pa != dd->tidinvalid) {
3388 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3390 /* paranoia checks */
3391 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3392 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3396 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3397 qib_dev_err(dd, "Physical page address 0x%lx "
3398 "larger than supported\n", pa);
3402 if (type == RCVHQ_RCV_TYPE_EAGER)
3403 chippa |= dd->tidtemplate;
3404 else /* for now, always full 4KB page */
3405 chippa |= IBA7322_TID_SZ_4K;
3413 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3414 * @dd: the qlogic_ib device
3417 * clear all TID entries for a ctxt, expected and eager.
3418 * Used from qib_close().
3420 static void qib_7322_clear_tids(struct qib_devdata *dd,
3421 struct qib_ctxtdata *rcd)
3423 u64 __iomem *tidbase;
3424 unsigned long tidinv;
3428 if (!dd->kregbase || !rcd)
3433 tidinv = dd->tidinvalid;
3434 tidbase = (u64 __iomem *)
3435 ((char __iomem *) dd->kregbase +
3437 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3439 for (i = 0; i < dd->rcvtidcnt; i++)
3440 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3443 tidbase = (u64 __iomem *)
3444 ((char __iomem *) dd->kregbase +
3446 rcd->rcvegr_tid_base * sizeof(*tidbase));
3448 for (i = 0; i < rcd->rcvegrcnt; i++)
3449 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3454 * qib_7322_tidtemplate - setup constants for TID updates
3455 * @dd: the qlogic_ib device
3457 * We setup stuff that we use a lot, to avoid calculating each time
3459 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3462 * For now, we always allocate 4KB buffers (at init) so we can
3463 * receive max size packets. We may want a module parameter to
3464 * specify 2KB or 4KB and/or make it per port instead of per device
3465 * for those who want to reduce memory footprint. Note that the
3466 * rcvhdrentsize size must be large enough to hold the largest
3467 * IB header (currently 96 bytes) that we expect to handle (plus of
3468 * course the 2 dwords of RHF).
3470 if (dd->rcvegrbufsize == 2048)
3471 dd->tidtemplate = IBA7322_TID_SZ_2K;
3472 else if (dd->rcvegrbufsize == 4096)
3473 dd->tidtemplate = IBA7322_TID_SZ_4K;
3478 * qib_init_7322_get_base_info - set chip-specific flags for user code
3479 * @rcd: the qlogic_ib ctxt
3480 * @kbase: qib_base_info pointer
3482 * We set the PCIE flag because the lower bandwidth on PCIe vs
3483 * HyperTransport can affect some user packet algorithims.
3486 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3487 struct qib_base_info *kinfo)
3489 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3490 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3491 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3492 if (rcd->dd->cspec->r1)
3493 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3494 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3495 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3500 static struct qib_message_header *
3501 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3503 u32 offset = qib_hdrget_offset(rhf_addr);
3505 return (struct qib_message_header *)
3506 (rhf_addr - dd->rhf_offset + offset);
3510 * Configure number of contexts.
3512 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3514 unsigned long flags;
3517 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3518 dd->cspec->numctxts = nchipctxts;
3519 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3521 * Set the mask for which bits from the QPN are used
3522 * to select a context number.
3524 dd->qpn_mask = 0x3f;
3525 dd->first_user_ctxt = NUM_IB_PORTS +
3526 (qib_n_krcv_queues - 1) * dd->num_pports;
3527 if (dd->first_user_ctxt > nchipctxts)
3528 dd->first_user_ctxt = nchipctxts;
3529 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3531 dd->first_user_ctxt = NUM_IB_PORTS;
3532 dd->n_krcv_queues = 1;
3535 if (!qib_cfgctxts) {
3536 int nctxts = dd->first_user_ctxt + num_online_cpus();
3540 else if (nctxts <= 10)
3542 else if (nctxts <= nchipctxts)
3543 dd->ctxtcnt = nchipctxts;
3544 } else if (qib_cfgctxts < dd->num_pports)
3545 dd->ctxtcnt = dd->num_pports;
3546 else if (qib_cfgctxts <= nchipctxts)
3547 dd->ctxtcnt = qib_cfgctxts;
3548 if (!dd->ctxtcnt) /* none of the above, set to max */
3549 dd->ctxtcnt = nchipctxts;
3552 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3553 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3554 * Lock to be paranoid about later motion, etc.
3556 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3557 if (dd->ctxtcnt > 10)
3558 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3559 else if (dd->ctxtcnt > 6)
3560 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3561 /* else configure for default 6 receive ctxts */
3563 /* The XRC opcode is 5. */
3564 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3567 * RcvCtrl *must* be written here so that the
3568 * chip understands how to change rcvegrcnt below.
3570 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3571 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3573 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3574 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3576 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3578 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3579 dd->num_pports > 1 ? 1024U : 2048U);
3582 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3586 u64 maskr; /* right-justified mask */
3590 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3591 ret = ppd->link_width_enabled;
3594 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3595 ret = ppd->link_width_active;
3598 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3599 ret = ppd->link_speed_enabled;
3602 case QIB_IB_CFG_SPD: /* Get current Link spd */
3603 ret = ppd->link_speed_active;
3606 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3607 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3608 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3611 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3612 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3613 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3616 case QIB_IB_CFG_LINKLATENCY:
3617 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3618 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3621 case QIB_IB_CFG_OP_VLS:
3622 ret = ppd->vls_operational;
3625 case QIB_IB_CFG_VL_HIGH_CAP:
3629 case QIB_IB_CFG_VL_LOW_CAP:
3633 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3634 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3638 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3639 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3643 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3644 /* will only take effect when the link state changes */
3645 ret = (ppd->cpspec->ibcctrl_a &
3646 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3647 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3650 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3651 lsb = IBA7322_IBC_HRTBT_LSB;
3652 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3655 case QIB_IB_CFG_PMA_TICKS:
3657 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3658 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3660 if (ppd->link_speed_active == QIB_IB_QDR)
3662 else if (ppd->link_speed_active == QIB_IB_DDR)
3672 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3678 * Below again cribbed liberally from older version. Do not lean
3681 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3682 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3683 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3685 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3687 struct qib_devdata *dd = ppd->dd;
3688 u64 maskr; /* right-justified mask */
3691 unsigned long flags;
3694 case QIB_IB_CFG_LIDLMC:
3696 * Set LID and LMC. Combined to avoid possible hazard
3697 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3699 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3700 maskr = IBA7322_IBC_DLIDLMC_MASK;
3702 * For header-checking, the SLID in the packet will
3703 * be masked with SendIBSLMCMask, and compared
3704 * with SendIBSLIDAssignMask. Make sure we do not
3705 * set any bits not covered by the mask, or we get
3708 qib_write_kreg_port(ppd, krp_sendslid,
3709 val & (val >> 16) & SendIBSLIDAssignMask);
3710 qib_write_kreg_port(ppd, krp_sendslidmask,
3711 (val >> 16) & SendIBSLMCMask);
3714 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3715 ppd->link_width_enabled = val;
3716 /* convert IB value to chip register value */
3717 if (val == IB_WIDTH_1X)
3719 else if (val == IB_WIDTH_4X)
3723 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3724 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3727 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3729 * As with width, only write the actual register if the
3730 * link is currently down, otherwise takes effect on next
3731 * link change. Since setting is being explictly requested
3732 * (via MAD or sysfs), clear autoneg failure status if speed
3733 * autoneg is enabled.
3735 ppd->link_speed_enabled = val;
3736 val <<= IBA7322_IBC_SPEED_LSB;
3737 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3738 IBA7322_IBC_MAX_SPEED_MASK;
3739 if (val & (val - 1)) {
3740 /* Muliple speeds enabled */
3741 val |= IBA7322_IBC_IBTA_1_2_MASK |
3742 IBA7322_IBC_MAX_SPEED_MASK;
3743 spin_lock_irqsave(&ppd->lflags_lock, flags);
3744 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3745 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3746 } else if (val & IBA7322_IBC_SPEED_QDR)
3747 val |= IBA7322_IBC_IBTA_1_2_MASK;
3748 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3749 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3752 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3753 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3754 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3757 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3758 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3759 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3762 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3763 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3766 ppd->cpspec->ibcctrl_a &=
3767 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3768 ppd->cpspec->ibcctrl_a |= (u64) val <<
3769 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3770 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3771 ppd->cpspec->ibcctrl_a);
3772 qib_write_kreg(dd, kr_scratch, 0ULL);
3776 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3777 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3780 ppd->cpspec->ibcctrl_a &=
3781 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3782 ppd->cpspec->ibcctrl_a |= (u64) val <<
3783 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3784 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3785 ppd->cpspec->ibcctrl_a);
3786 qib_write_kreg(dd, kr_scratch, 0ULL);
3790 case QIB_IB_CFG_PKEYS: /* update pkeys */
3791 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3792 ((u64) ppd->pkeys[2] << 32) |
3793 ((u64) ppd->pkeys[3] << 48);
3794 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3797 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3798 /* will only take effect when the link state changes */
3799 if (val == IB_LINKINITCMD_POLL)
3800 ppd->cpspec->ibcctrl_a &=
3801 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3803 ppd->cpspec->ibcctrl_a |=
3804 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3805 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3806 qib_write_kreg(dd, kr_scratch, 0ULL);
3809 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3811 * Update our housekeeping variables, and set IBC max
3812 * size, same as init code; max IBC is max we allow in
3813 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3814 * Set even if it's unchanged, print debug message only
3817 val = (ppd->ibmaxlen >> 2) + 1;
3818 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3819 ppd->cpspec->ibcctrl_a |= (u64)val <<
3820 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3821 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3822 ppd->cpspec->ibcctrl_a);
3823 qib_write_kreg(dd, kr_scratch, 0ULL);
3826 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3827 switch (val & 0xffff0000) {
3828 case IB_LINKCMD_DOWN:
3829 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3830 ppd->cpspec->ibmalfusesnap = 1;
3831 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3833 if (!ppd->cpspec->ibdeltainprog &&
3834 qib_compat_ddr_negotiate) {
3835 ppd->cpspec->ibdeltainprog = 1;
3836 ppd->cpspec->ibsymsnap =
3837 read_7322_creg32_port(ppd,
3839 ppd->cpspec->iblnkerrsnap =
3840 read_7322_creg32_port(ppd,
3841 crp_iblinkerrrecov);
3845 case IB_LINKCMD_ARMED:
3846 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3847 if (ppd->cpspec->ibmalfusesnap) {
3848 ppd->cpspec->ibmalfusesnap = 0;
3849 ppd->cpspec->ibmalfdelta +=
3850 read_7322_creg32_port(ppd,
3852 ppd->cpspec->ibmalfsnap;
3856 case IB_LINKCMD_ACTIVE:
3857 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3862 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3865 switch (val & 0xffff) {
3866 case IB_LINKINITCMD_NOP:
3870 case IB_LINKINITCMD_POLL:
3871 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3874 case IB_LINKINITCMD_SLEEP:
3875 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3878 case IB_LINKINITCMD_DISABLE:
3879 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3880 ppd->cpspec->chase_end = 0;
3882 * stop state chase counter and timer, if running.
3883 * wait forpending timer, but don't clear .data (ppd)!
3885 if (ppd->cpspec->chase_timer.expires) {
3886 del_timer_sync(&ppd->cpspec->chase_timer);
3887 ppd->cpspec->chase_timer.expires = 0;
3893 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3897 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3900 case QIB_IB_CFG_OP_VLS:
3901 if (ppd->vls_operational != val) {
3902 ppd->vls_operational = val;
3907 case QIB_IB_CFG_VL_HIGH_LIMIT:
3908 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3911 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3916 lsb = IBA7322_IBC_HRTBT_LSB;
3917 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3920 case QIB_IB_CFG_PORT:
3921 /* val is the port number of the switch we are connected to. */
3922 if (ppd->dd->cspec->r1) {
3923 cancel_delayed_work(&ppd->cpspec->ipg_work);
3924 ppd->cpspec->ipg_tries = 0;
3932 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3933 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3934 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3935 qib_write_kreg(dd, kr_scratch, 0);
3940 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3945 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3946 if (!strncmp(what, "ibc", 3)) {
3947 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3949 val = 0; /* disable heart beat, so link will come up */
3950 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3951 ppd->dd->unit, ppd->port);
3952 } else if (!strncmp(what, "off", 3)) {
3953 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3955 /* enable heart beat again */
3956 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3957 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3958 "(normal)\n", ppd->dd->unit, ppd->port);
3962 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3963 ppd->cpspec->ibcctrl_a);
3964 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3965 << IBA7322_IBC_HRTBT_LSB);
3966 ppd->cpspec->ibcctrl_b = ctrlb | val;
3967 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3968 ppd->cpspec->ibcctrl_b);
3969 qib_write_kreg(ppd->dd, kr_scratch, 0);
3974 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3975 struct ib_vl_weight_elem *vl)
3979 for (i = 0; i < 16; i++, regno++, vl++) {
3980 u32 val = qib_read_kreg_port(ppd, regno);
3982 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
3983 SYM_RMASK(LowPriority0_0, VirtualLane);
3984 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
3985 SYM_RMASK(LowPriority0_0, Weight);
3989 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3990 struct ib_vl_weight_elem *vl)
3994 for (i = 0; i < 16; i++, regno++, vl++) {
3997 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
3998 SYM_LSB(LowPriority0_0, VirtualLane)) |
3999 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4000 SYM_LSB(LowPriority0_0, Weight));
4001 qib_write_kreg_port(ppd, regno, val);
4003 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4004 struct qib_devdata *dd = ppd->dd;
4005 unsigned long flags;
4007 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4008 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4009 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4010 qib_write_kreg(dd, kr_scratch, 0);
4011 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4015 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4018 case QIB_IB_TBL_VL_HIGH_ARB:
4019 get_vl_weights(ppd, krp_highprio_0, t);
4022 case QIB_IB_TBL_VL_LOW_ARB:
4023 get_vl_weights(ppd, krp_lowprio_0, t);
4032 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4035 case QIB_IB_TBL_VL_HIGH_ARB:
4036 set_vl_weights(ppd, krp_highprio_0, t);
4039 case QIB_IB_TBL_VL_LOW_ARB:
4040 set_vl_weights(ppd, krp_lowprio_0, t);
4049 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4050 u32 updegr, u32 egrhd)
4052 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4053 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4055 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4058 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4062 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4063 if (rcd->rcvhdrtail_kvaddr)
4064 tail = qib_get_rcvhdrtail(rcd);
4066 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4067 return head == tail;
4070 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4071 QIB_RCVCTRL_CTXT_DIS | \
4072 QIB_RCVCTRL_TIDFLOW_ENB | \
4073 QIB_RCVCTRL_TIDFLOW_DIS | \
4074 QIB_RCVCTRL_TAILUPD_ENB | \
4075 QIB_RCVCTRL_TAILUPD_DIS | \
4076 QIB_RCVCTRL_INTRAVAIL_ENB | \
4077 QIB_RCVCTRL_INTRAVAIL_DIS | \
4078 QIB_RCVCTRL_BP_ENB | \
4081 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4082 QIB_RCVCTRL_CTXT_DIS | \
4083 QIB_RCVCTRL_PKEY_DIS | \
4084 QIB_RCVCTRL_PKEY_ENB)
4087 * Modify the RCVCTRL register in chip-specific way. This
4088 * is a function because bit positions and (future) register
4089 * location is chip-specifc, but the needed operations are
4090 * generic. <op> is a bit-mask because we often want to
4091 * do multiple modifications.
4093 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4096 struct qib_devdata *dd = ppd->dd;
4097 struct qib_ctxtdata *rcd;
4099 unsigned long flags;
4101 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4103 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4104 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4105 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4106 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4107 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4108 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4109 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4110 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4111 if (op & QIB_RCVCTRL_PKEY_ENB)
4112 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4113 if (op & QIB_RCVCTRL_PKEY_DIS)
4114 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4116 mask = (1ULL << dd->ctxtcnt) - 1;
4119 mask = (1ULL << ctxt);
4120 rcd = dd->rcd[ctxt];
4122 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4124 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4125 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4126 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4127 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4129 /* Write these registers before the context is enabled. */
4130 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4131 rcd->rcvhdrqtailaddr_phys);
4132 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4136 if (op & QIB_RCVCTRL_CTXT_DIS)
4138 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4139 if (op & QIB_RCVCTRL_BP_ENB)
4140 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4141 if (op & QIB_RCVCTRL_BP_DIS)
4142 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4143 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4144 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4145 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4146 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4148 * Decide which registers to write depending on the ops enabled.
4149 * Special case is "flush" (no bits set at all)
4150 * which needs to write both.
4152 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4153 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4154 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4155 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4156 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4158 * Init the context registers also; if we were
4159 * disabled, tail and head should both be zero
4160 * already from the enable, but since we don't
4161 * know, we have to do it explictly.
4163 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4164 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4166 /* be sure enabling write seen; hd/tl should be 0 */
4167 (void) qib_read_kreg32(dd, kr_scratch);
4168 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4169 dd->rcd[ctxt]->head = val;
4170 /* If kctxt, interrupt on next receive. */
4171 if (ctxt < dd->first_user_ctxt)
4172 val |= dd->rhdrhead_intr_off;
4173 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4174 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4175 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4176 /* arm rcv interrupt */
4177 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4178 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4180 if (op & QIB_RCVCTRL_CTXT_DIS) {
4183 /* Now that the context is disabled, clear these registers. */
4185 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4186 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4187 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4188 qib_write_ureg(dd, ur_rcvflowtable + f,
4189 TIDFLOW_ERRBITS, ctxt);
4193 for (i = 0; i < dd->cfgctxts; i++) {
4194 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4196 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4197 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4198 qib_write_ureg(dd, ur_rcvflowtable + f,
4199 TIDFLOW_ERRBITS, i);
4203 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4207 * Modify the SENDCTRL register in chip-specific way. This
4208 * is a function where there are multiple such registers with
4209 * slightly different layouts.
4210 * The chip doesn't allow back-to-back sendctrl writes, so write
4211 * the scratch register after writing sendctrl.
4213 * Which register is written depends on the operation.
4214 * Most operate on the common register, while
4215 * SEND_ENB and SEND_DIS operate on the per-port ones.
4216 * SEND_ENB is included in common because it can change SPCL_TRIG
4218 #define SENDCTRL_COMMON_MODS (\
4219 QIB_SENDCTRL_CLEAR | \
4220 QIB_SENDCTRL_AVAIL_DIS | \
4221 QIB_SENDCTRL_AVAIL_ENB | \
4222 QIB_SENDCTRL_AVAIL_BLIP | \
4223 QIB_SENDCTRL_DISARM | \
4224 QIB_SENDCTRL_DISARM_ALL | \
4225 QIB_SENDCTRL_SEND_ENB)
4227 #define SENDCTRL_PORT_MODS (\
4228 QIB_SENDCTRL_CLEAR | \
4229 QIB_SENDCTRL_SEND_ENB | \
4230 QIB_SENDCTRL_SEND_DIS | \
4233 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4235 struct qib_devdata *dd = ppd->dd;
4236 u64 tmp_dd_sendctrl;
4237 unsigned long flags;
4239 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4241 /* First the dd ones that are "sticky", saved in shadow */
4242 if (op & QIB_SENDCTRL_CLEAR)
4244 if (op & QIB_SENDCTRL_AVAIL_DIS)
4245 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4246 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4247 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4248 if (dd->flags & QIB_USE_SPCL_TRIG)
4249 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4252 /* Then the ppd ones that are "sticky", saved in shadow */
4253 if (op & QIB_SENDCTRL_SEND_DIS)
4254 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4255 else if (op & QIB_SENDCTRL_SEND_ENB)
4256 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4258 if (op & QIB_SENDCTRL_DISARM_ALL) {
4261 tmp_dd_sendctrl = dd->sendctrl;
4262 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4264 * Disarm any buffers that are not yet launched,
4265 * disabling updates until done.
4267 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4268 for (i = 0; i < last; i++) {
4269 qib_write_kreg(dd, kr_sendctrl,
4271 SYM_MASK(SendCtrl, Disarm) | i);
4272 qib_write_kreg(dd, kr_scratch, 0);
4276 if (op & QIB_SENDCTRL_FLUSH) {
4277 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4280 * Now drain all the fifos. The Abort bit should never be
4281 * needed, so for now, at least, we don't use it.
4284 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4285 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4286 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4287 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4288 qib_write_kreg(dd, kr_scratch, 0);
4291 tmp_dd_sendctrl = dd->sendctrl;
4293 if (op & QIB_SENDCTRL_DISARM)
4294 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4295 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4296 SYM_LSB(SendCtrl, DisarmSendBuf));
4297 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4298 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4299 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4301 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4302 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4303 qib_write_kreg(dd, kr_scratch, 0);
4306 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4307 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4308 qib_write_kreg(dd, kr_scratch, 0);
4311 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4312 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4313 qib_write_kreg(dd, kr_scratch, 0);
4316 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4318 if (op & QIB_SENDCTRL_FLUSH) {
4321 * ensure writes have hit chip, then do a few
4322 * more reads, to allow DMA of pioavail registers
4323 * to occur, so in-memory copy is in sync with
4324 * the chip. Not always safe to sleep.
4326 v = qib_read_kreg32(dd, kr_scratch);
4327 qib_write_kreg(dd, kr_scratch, v);
4328 v = qib_read_kreg32(dd, kr_scratch);
4329 qib_write_kreg(dd, kr_scratch, v);
4330 qib_read_kreg32(dd, kr_scratch);
4334 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4335 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4336 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4339 * qib_portcntr_7322 - read a per-port chip counter
4340 * @ppd: the qlogic_ib pport
4341 * @creg: the counter to read (not a chip offset)
4343 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4345 struct qib_devdata *dd = ppd->dd;
4348 /* 0xffff for unimplemented or synthesized counters */
4349 static const u32 xlator[] = {
4350 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4351 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4352 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4353 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4354 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4355 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4356 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4357 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4358 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4359 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4360 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4361 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4362 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4363 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4364 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4365 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4366 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4367 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4368 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4369 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4370 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4371 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4372 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4373 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4374 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4375 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4376 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4377 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4378 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4379 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4381 * the next 3 aren't really counters, but were implemented
4382 * as counters in older chips, so still get accessed as
4383 * though they were counters from this code.
4385 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4386 [QIBPORTCNTR_PSSTART] = krp_psstart,
4387 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4388 /* pseudo-counter, summed for all ports */
4389 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4392 if (reg >= ARRAY_SIZE(xlator)) {
4393 qib_devinfo(ppd->dd->pcidev,
4394 "Unimplemented portcounter %u\n", reg);
4397 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4399 /* handle non-counters and special cases first */
4400 if (reg == QIBPORTCNTR_KHDROVFL) {
4403 /* sum over all kernel contexts (skip if mini_init) */
4404 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4405 struct qib_ctxtdata *rcd = dd->rcd[i];
4407 if (!rcd || rcd->ppd != ppd)
4409 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4412 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4414 * Used as part of the synthesis of port_rcv_errors
4415 * in the verbs code for IBTA counters. Not needed for 7322,
4416 * because all the errors are already counted by other cntrs.
4419 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4420 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4421 /* were counters in older chips, now per-port kernel regs */
4422 ret = qib_read_kreg_port(ppd, creg);
4427 * Only fast increment counters are 64 bits; use 32 bit reads to
4428 * avoid two independent reads when on Opteron.
4430 if (xlator[reg] & _PORT_64BIT_FLAG)
4431 ret = read_7322_creg_port(ppd, creg);
4433 ret = read_7322_creg32_port(ppd, creg);
4434 if (creg == crp_ibsymbolerr) {
4435 if (ppd->cpspec->ibdeltainprog)
4436 ret -= ret - ppd->cpspec->ibsymsnap;
4437 ret -= ppd->cpspec->ibsymdelta;
4438 } else if (creg == crp_iblinkerrrecov) {
4439 if (ppd->cpspec->ibdeltainprog)
4440 ret -= ret - ppd->cpspec->iblnkerrsnap;
4441 ret -= ppd->cpspec->iblnkerrdelta;
4442 } else if (creg == crp_errlink)
4443 ret -= ppd->cpspec->ibmalfdelta;
4444 else if (creg == crp_iblinkdown)
4445 ret += ppd->cpspec->iblnkdowndelta;
4451 * Device counter names (not port-specific), one line per stat,
4452 * single string. Used by utilities like ipathstats to print the stats
4453 * in a way which works for different versions of drivers, without changing
4454 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4455 * display by utility.
4456 * Non-error counters are first.
4457 * Start of "error" conters is indicated by a leading "E " on the first
4458 * "error" counter, and doesn't count in label length.
4459 * The EgrOvfl list needs to be last so we truncate them at the configured
4460 * context count for the device.
4461 * cntr7322indices contains the corresponding register indices.
4463 static const char cntr7322names[] =
4468 "RxTIDFloDrop\n" /* 7322 only */
4489 static const u32 cntr7322indices[] = {
4490 cr_lbint | _PORT_64BIT_FLAG,
4491 cr_lbstall | _PORT_64BIT_FLAG,
4495 cr_base_egrovfl + 0,
4496 cr_base_egrovfl + 1,
4497 cr_base_egrovfl + 2,
4498 cr_base_egrovfl + 3,
4499 cr_base_egrovfl + 4,
4500 cr_base_egrovfl + 5,
4501 cr_base_egrovfl + 6,
4502 cr_base_egrovfl + 7,
4503 cr_base_egrovfl + 8,
4504 cr_base_egrovfl + 9,
4505 cr_base_egrovfl + 10,
4506 cr_base_egrovfl + 11,
4507 cr_base_egrovfl + 12,
4508 cr_base_egrovfl + 13,
4509 cr_base_egrovfl + 14,
4510 cr_base_egrovfl + 15,
4511 cr_base_egrovfl + 16,
4512 cr_base_egrovfl + 17,
4516 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4517 * portcntr7322indices is somewhat complicated by some registers needing
4518 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4520 static const char portcntr7322names[] =
4528 "TxDmaDesc\n" /* 7220 and 7322-only */
4529 "E RxDlidFltr\n" /* 7220 and 7322-only */
4552 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4556 "RxQPBadCtxt\n" /* 7322-only from here down */
4560 static const u32 portcntr7322indices[] = {
4561 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4563 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4564 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4566 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4567 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4568 crp_txsdmadesc | _PORT_64BIT_FLAG,
4571 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4572 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4573 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4574 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4575 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4576 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4577 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4578 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4579 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4580 crp_rcvflowctrlviol,
4581 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4582 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4583 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4584 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4585 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4586 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4592 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4593 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4594 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4595 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4596 crp_rxqpinvalidctxt,
4600 /* do all the setup to make the counter reads efficient later */
4601 static void init_7322_cntrnames(struct qib_devdata *dd)
4606 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4608 /* we always have at least one counter before the egrovfl */
4609 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4611 s = strchr(s + 1, '\n');
4615 dd->cspec->ncntrs = i;
4617 /* full list; size is without terminating null */
4618 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4620 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4621 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4622 * sizeof(u64), GFP_KERNEL);
4623 if (!dd->cspec->cntrs)
4624 qib_dev_err(dd, "Failed allocation for counters\n");
4626 for (i = 0, s = (char *)portcntr7322names; s; i++)
4627 s = strchr(s + 1, '\n');
4628 dd->cspec->nportcntrs = i - 1;
4629 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4630 for (i = 0; i < dd->num_pports; ++i) {
4631 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4632 * sizeof(u64), GFP_KERNEL);
4633 if (!dd->pport[i].cpspec->portcntrs)
4634 qib_dev_err(dd, "Failed allocation for"
4639 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4645 ret = dd->cspec->cntrnamelen;
4647 ret = 0; /* final read after getting everything */
4649 *namep = (char *) cntr7322names;
4651 u64 *cntr = dd->cspec->cntrs;
4654 ret = dd->cspec->ncntrs * sizeof(u64);
4655 if (!cntr || pos >= ret) {
4656 /* everything read, or couldn't get memory */
4661 for (i = 0; i < dd->cspec->ncntrs; i++)
4662 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4663 *cntr++ = read_7322_creg(dd,
4664 cntr7322indices[i] &
4665 _PORT_CNTR_IDXMASK);
4667 *cntr++ = read_7322_creg32(dd,
4668 cntr7322indices[i]);
4674 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4675 char **namep, u64 **cntrp)
4680 ret = dd->cspec->portcntrnamelen;
4682 ret = 0; /* final read after getting everything */
4684 *namep = (char *)portcntr7322names;
4686 struct qib_pportdata *ppd = &dd->pport[port];
4687 u64 *cntr = ppd->cpspec->portcntrs;
4690 ret = dd->cspec->nportcntrs * sizeof(u64);
4691 if (!cntr || pos >= ret) {
4692 /* everything read, or couldn't get memory */
4697 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4698 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4699 *cntr++ = qib_portcntr_7322(ppd,
4700 portcntr7322indices[i] &
4701 _PORT_CNTR_IDXMASK);
4702 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4703 *cntr++ = read_7322_creg_port(ppd,
4704 portcntr7322indices[i] &
4705 _PORT_CNTR_IDXMASK);
4707 *cntr++ = read_7322_creg32_port(ppd,
4708 portcntr7322indices[i]);
4716 * qib_get_7322_faststats - get word counters from chip before they overflow
4717 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4719 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4720 * real purpose of this function is to maintain the notion of
4721 * "active time", which in turn is only logged into the eeprom,
4722 * which we don;t have, yet, for 7322-based boards.
4724 * called from add_timer
4726 static void qib_get_7322_faststats(unsigned long opaque)
4728 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4729 struct qib_pportdata *ppd;
4730 unsigned long flags;
4734 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4735 ppd = dd->pport + pidx;
4738 * If port isn't enabled or not operational ports, or
4739 * diags is running (can cause memory diags to fail)
4740 * skip this port this time.
4742 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4747 * Maintain an activity timer, based on traffic
4748 * exceeding a threshold, so we need to check the word-counts
4749 * even if they are 64-bit.
4751 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4752 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4753 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4754 traffic_wds -= ppd->dd->traffic_wds;
4755 ppd->dd->traffic_wds += traffic_wds;
4756 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4757 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4758 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4759 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4761 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4762 QIBL_LINKACTIVE)) &&
4763 ppd->cpspec->qdr_dfe_time &&
4764 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4765 ppd->cpspec->qdr_dfe_on = 0;
4767 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4768 ppd->dd->cspec->r1 ?
4769 QDR_STATIC_ADAPT_INIT_R1 :
4770 QDR_STATIC_ADAPT_INIT);
4774 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4778 * If we were using MSIx, try to fallback to INTx.
4780 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4782 if (!dd->cspec->num_msix_entries)
4783 return 0; /* already using INTx */
4785 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4786 " trying INTx interrupts\n");
4787 qib_7322_nomsix(dd);
4788 qib_enable_intx(dd->pcidev);
4789 qib_setup_7322_interrupt(dd, 0);
4794 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4795 * than resetting the IBC or external link state, and useful in some
4796 * cases to cause some retraining. To do this right, we reset IBC
4797 * as well, then return to previous state (which may be still in reset)
4798 * NOTE: some callers of this "know" this writes the current value
4799 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4800 * check all callers.
4802 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4805 struct qib_devdata *dd = ppd->dd;
4806 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4807 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4808 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4810 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4811 qib_write_kreg(dd, kr_hwerrmask,
4812 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4813 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4814 ppd->cpspec->ibcctrl_a &
4815 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4817 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4818 qib_read_kreg32(dd, kr_scratch);
4819 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4820 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4821 qib_write_kreg(dd, kr_scratch, 0ULL);
4822 qib_write_kreg(dd, kr_hwerrclear,
4823 SYM_MASK(HwErrClear, statusValidNoEopClear));
4824 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4828 * This code for non-IBTA-compliant IB speed negotiation is only known to
4829 * work for the SDR to DDR transition, and only between an HCA and a switch
4830 * with recent firmware. It is based on observed heuristics, rather than
4831 * actual knowledge of the non-compliant speed negotiation.
4832 * It has a number of hard-coded fields, since the hope is to rewrite this
4833 * when a spec is available on how the negoation is intended to work.
4835 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4836 u32 dcnt, u32 *data)
4840 u32 __iomem *piobuf;
4841 u32 pnum, control, len;
4842 struct qib_devdata *dd = ppd->dd;
4845 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4846 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4847 pbc = ((u64) control << 32) | len;
4848 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4853 /* disable header check on this packet, since it can't be valid */
4854 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4855 writeq(pbc, piobuf);
4857 qib_pio_copy(piobuf + 2, hdr, 7);
4858 qib_pio_copy(piobuf + 9, data, dcnt);
4859 if (dd->flags & QIB_USE_SPCL_TRIG) {
4860 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4863 __raw_writel(0xaebecede, piobuf + spcl_off);
4866 qib_sendbuf_done(dd, pnum);
4867 /* and re-enable hdr check */
4868 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4872 * _start packet gets sent twice at start, _done gets sent twice at end
4874 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4876 struct qib_devdata *dd = ppd->dd;
4878 u32 dw, i, hcnt, dcnt, *data;
4879 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4880 static u32 madpayload_start[0x40] = {
4881 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4882 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4883 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4885 static u32 madpayload_done[0x40] = {
4886 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4887 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4888 0x40000001, 0x1388, 0x15e, /* rest 0's */
4891 dcnt = ARRAY_SIZE(madpayload_start);
4892 hcnt = ARRAY_SIZE(hdr);
4894 /* for maintainability, do it at runtime */
4895 for (i = 0; i < hcnt; i++) {
4896 dw = (__force u32) cpu_to_be32(hdr[i]);
4899 for (i = 0; i < dcnt; i++) {
4900 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4901 madpayload_start[i] = dw;
4902 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4903 madpayload_done[i] = dw;
4908 data = which ? madpayload_done : madpayload_start;
4910 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4911 qib_read_kreg64(dd, kr_scratch);
4913 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4914 qib_read_kreg64(dd, kr_scratch);
4919 * Do the absolute minimum to cause an IB speed change, and make it
4920 * ready, but don't actually trigger the change. The caller will
4921 * do that when ready (if link is in Polling training state, it will
4922 * happen immediately, otherwise when link next goes down)
4924 * This routine should only be used as part of the DDR autonegotation
4925 * code for devices that are not compliant with IB 1.2 (or code that
4926 * fixes things up for same).
4928 * When link has gone down, and autoneg enabled, or autoneg has
4929 * failed and we give up until next time we set both speeds, and
4930 * then we want IBTA enabled as well as "use max enabled speed.
4932 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4935 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4936 IBA7322_IBC_IBTA_1_2_MASK |
4937 IBA7322_IBC_MAX_SPEED_MASK);
4939 if (speed & (speed - 1)) /* multiple speeds */
4940 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4941 IBA7322_IBC_IBTA_1_2_MASK |
4942 IBA7322_IBC_MAX_SPEED_MASK;
4944 newctrlb |= speed == QIB_IB_QDR ?
4945 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4946 ((speed == QIB_IB_DDR ?
4947 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4949 if (newctrlb == ppd->cpspec->ibcctrl_b)
4952 ppd->cpspec->ibcctrl_b = newctrlb;
4953 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4954 qib_write_kreg(ppd->dd, kr_scratch, 0);
4958 * This routine is only used when we are not talking to another
4959 * IB 1.2-compliant device that we think can do DDR.
4960 * (This includes all existing switch chips as of Oct 2007.)
4961 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4963 static void try_7322_autoneg(struct qib_pportdata *ppd)
4965 unsigned long flags;
4967 spin_lock_irqsave(&ppd->lflags_lock, flags);
4968 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
4969 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4970 qib_autoneg_7322_send(ppd, 0);
4971 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
4972 qib_7322_mini_pcs_reset(ppd);
4973 /* 2 msec is minimum length of a poll cycle */
4974 schedule_delayed_work(&ppd->cpspec->autoneg_work,
4975 msecs_to_jiffies(2));
4979 * Handle the empirically determined mechanism for auto-negotiation
4980 * of DDR speed with switches.
4982 static void autoneg_7322_work(struct work_struct *work)
4984 struct qib_pportdata *ppd;
4985 struct qib_devdata *dd;
4988 unsigned long flags;
4990 ppd = container_of(work, struct qib_chippport_specific,
4991 autoneg_work.work)->ppd;
4994 startms = jiffies_to_msecs(jiffies);
4997 * Busy wait for this first part, it should be at most a
4998 * few hundred usec, since we scheduled ourselves for 2msec.
5000 for (i = 0; i < 25; i++) {
5001 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5002 == IB_7322_LT_STATE_POLLQUIET) {
5003 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5009 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5010 goto done; /* we got there early or told to stop */
5012 /* we expect this to timeout */
5013 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5014 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5015 msecs_to_jiffies(90)))
5017 qib_7322_mini_pcs_reset(ppd);
5019 /* we expect this to timeout */
5020 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5021 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5022 msecs_to_jiffies(1700)))
5024 qib_7322_mini_pcs_reset(ppd);
5026 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5029 * Wait up to 250 msec for link to train and get to INIT at DDR;
5030 * this should terminate early.
5032 wait_event_timeout(ppd->cpspec->autoneg_wait,
5033 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5034 msecs_to_jiffies(250));
5036 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5037 spin_lock_irqsave(&ppd->lflags_lock, flags);
5038 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5039 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5040 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5041 ppd->cpspec->autoneg_tries = 0;
5043 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5044 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5049 * This routine is used to request IPG set in the QLogic switch.
5050 * Only called if r1.
5052 static void try_7322_ipg(struct qib_pportdata *ppd)
5054 struct qib_ibport *ibp = &ppd->ibport_data;
5055 struct ib_mad_send_buf *send_buf;
5056 struct ib_mad_agent *agent;
5061 agent = ibp->send_agent;
5065 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5066 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5067 if (IS_ERR(send_buf))
5071 struct ib_ah_attr attr;
5074 memset(&attr, 0, sizeof attr);
5075 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5076 attr.port_num = ppd->port;
5077 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5082 ibp->smi_ah = to_iah(ah);
5086 send_buf->ah = &ibp->smi_ah->ibah;
5090 smp = send_buf->mad;
5091 smp->base_version = IB_MGMT_BASE_VERSION;
5092 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5093 smp->class_version = 1;
5094 smp->method = IB_MGMT_METHOD_SEND;
5096 smp->attr_id = QIB_VENDOR_IPG;
5100 ret = ib_post_send_mad(send_buf, NULL);
5102 ib_free_send_mad(send_buf);
5104 delay = 2 << ppd->cpspec->ipg_tries;
5105 schedule_delayed_work(&ppd->cpspec->ipg_work, msecs_to_jiffies(delay));
5109 * Timeout handler for setting IPG.
5110 * Only called if r1.
5112 static void ipg_7322_work(struct work_struct *work)
5114 struct qib_pportdata *ppd;
5116 ppd = container_of(work, struct qib_chippport_specific,
5117 ipg_work.work)->ppd;
5118 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5119 && ++ppd->cpspec->ipg_tries <= 10)
5123 static u32 qib_7322_iblink_state(u64 ibcs)
5125 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5128 case IB_7322_L_STATE_INIT:
5129 state = IB_PORT_INIT;
5131 case IB_7322_L_STATE_ARM:
5132 state = IB_PORT_ARMED;
5134 case IB_7322_L_STATE_ACTIVE:
5136 case IB_7322_L_STATE_ACT_DEFER:
5137 state = IB_PORT_ACTIVE;
5139 default: /* fall through */
5140 case IB_7322_L_STATE_DOWN:
5141 state = IB_PORT_DOWN;
5147 /* returns the IBTA port state, rather than the IBC link training state */
5148 static u8 qib_7322_phys_portstate(u64 ibcs)
5150 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5151 return qib_7322_physportstate[state];
5154 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5156 int ret = 0, symadj = 0;
5157 unsigned long flags;
5160 spin_lock_irqsave(&ppd->lflags_lock, flags);
5161 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5162 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5164 /* Update our picture of width and speed from chip */
5165 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5166 ppd->link_speed_active = QIB_IB_QDR;
5168 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5169 ppd->link_speed_active = QIB_IB_DDR;
5172 ppd->link_speed_active = QIB_IB_SDR;
5175 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5176 ppd->link_width_active = IB_WIDTH_4X;
5179 ppd->link_width_active = IB_WIDTH_1X;
5180 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5185 /* Link went down. */
5186 /* do IPG MAD again after linkdown, even if last time failed */
5187 ppd->cpspec->ipg_tries = 0;
5188 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5189 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5190 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5192 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5193 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5194 QIBL_IB_AUTONEG_INPROG)))
5195 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5196 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5197 /* unlock the Tx settings, speed may change */
5198 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5199 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5200 reset_tx_deemphasis_override));
5201 qib_cancel_sends(ppd);
5202 /* on link down, ensure sane pcs state */
5203 qib_7322_mini_pcs_reset(ppd);
5204 spin_lock_irqsave(&ppd->sdma_lock, flags);
5205 if (__qib_sdma_running(ppd))
5206 __qib_sdma_process_event(ppd,
5207 qib_sdma_event_e70_go_idle);
5208 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5210 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5211 if (clr == ppd->cpspec->iblnkdownsnap)
5212 ppd->cpspec->iblnkdowndelta++;
5214 if (qib_compat_ddr_negotiate &&
5215 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5216 QIBL_IB_AUTONEG_INPROG)) &&
5217 ppd->link_speed_active == QIB_IB_SDR &&
5218 (ppd->link_speed_enabled & QIB_IB_DDR)
5219 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5220 /* we are SDR, and auto-negotiation enabled */
5221 ++ppd->cpspec->autoneg_tries;
5222 if (!ppd->cpspec->ibdeltainprog) {
5223 ppd->cpspec->ibdeltainprog = 1;
5224 ppd->cpspec->ibsymdelta +=
5225 read_7322_creg32_port(ppd,
5227 ppd->cpspec->ibsymsnap;
5228 ppd->cpspec->iblnkerrdelta +=
5229 read_7322_creg32_port(ppd,
5230 crp_iblinkerrrecov) -
5231 ppd->cpspec->iblnkerrsnap;
5233 try_7322_autoneg(ppd);
5234 ret = 1; /* no other IB status change processing */
5235 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5236 ppd->link_speed_active == QIB_IB_SDR) {
5237 qib_autoneg_7322_send(ppd, 1);
5238 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5239 qib_7322_mini_pcs_reset(ppd);
5241 ret = 1; /* no other IB status change processing */
5242 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5243 (ppd->link_speed_active & QIB_IB_DDR)) {
5244 spin_lock_irqsave(&ppd->lflags_lock, flags);
5245 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5246 QIBL_IB_AUTONEG_FAILED);
5247 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5248 ppd->cpspec->autoneg_tries = 0;
5249 /* re-enable SDR, for next link down */
5250 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5251 wake_up(&ppd->cpspec->autoneg_wait);
5253 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5255 * Clear autoneg failure flag, and do setup
5256 * so we'll try next time link goes down and
5257 * back to INIT (possibly connected to a
5258 * different device).
5260 spin_lock_irqsave(&ppd->lflags_lock, flags);
5261 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5262 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5263 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5266 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5268 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5270 if (!ppd->cpspec->recovery_init)
5271 setup_7322_link_recovery(ppd, 0);
5272 ppd->cpspec->qdr_dfe_time = jiffies +
5273 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5275 ppd->cpspec->ibmalfusesnap = 0;
5276 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5280 ppd->cpspec->iblnkdownsnap =
5281 read_7322_creg32_port(ppd, crp_iblinkdown);
5282 if (ppd->cpspec->ibdeltainprog) {
5283 ppd->cpspec->ibdeltainprog = 0;
5284 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5285 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5286 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5287 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5289 } else if (!ibup && qib_compat_ddr_negotiate &&
5290 !ppd->cpspec->ibdeltainprog &&
5291 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5292 ppd->cpspec->ibdeltainprog = 1;
5293 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5295 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5296 crp_iblinkerrrecov);
5300 qib_setup_7322_setextled(ppd, ibup);
5305 * Does read/modify/write to appropriate registers to
5306 * set output and direction bits selected by mask.
5307 * these are in their canonical postions (e.g. lsb of
5308 * dir will end up in D48 of extctrl on existing chips).
5309 * returns contents of GP Inputs.
5311 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5313 u64 read_val, new_out;
5314 unsigned long flags;
5317 /* some bits being written, lock access to GPIO */
5320 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5321 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5322 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5323 new_out = (dd->cspec->gpio_out & ~mask) | out;
5325 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5326 qib_write_kreg(dd, kr_gpio_out, new_out);
5327 dd->cspec->gpio_out = new_out;
5328 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5331 * It is unlikely that a read at this time would get valid
5332 * data on a pin whose direction line was set in the same
5333 * call to this function. We include the read here because
5334 * that allows us to potentially combine a change on one pin with
5335 * a read on another, and because the old code did something like
5338 read_val = qib_read_kreg64(dd, kr_extstatus);
5339 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5342 /* Enable writes to config EEPROM, if possible. Returns previous state */
5343 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5348 mask = 1 << QIB_EEPROM_WEN_NUM;
5349 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5350 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5352 return prev_wen & 1;
5356 * Read fundamental info we need to use the chip. These are
5357 * the registers that describe chip capabilities, and are
5358 * saved in shadow registers.
5360 static void get_7322_chip_params(struct qib_devdata *dd)
5366 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5368 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5370 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5371 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5372 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5373 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5374 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5376 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5377 dd->piobcnt2k = val & ~0U;
5378 dd->piobcnt4k = val >> 32;
5379 val = qib_read_kreg64(dd, kr_sendpiosize);
5380 dd->piosize2k = val & ~0U;
5381 dd->piosize4k = val >> 32;
5383 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5385 mtu = QIB_DEFAULT_MTU;
5386 dd->pport[0].ibmtu = (u32)mtu;
5387 dd->pport[1].ibmtu = (u32)mtu;
5389 /* these may be adjusted in init_chip_wc_pat() */
5390 dd->pio2kbase = (u32 __iomem *)
5391 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5392 dd->pio4kbase = (u32 __iomem *)
5393 ((char __iomem *) dd->kregbase +
5394 (dd->piobufbase >> 32));
5396 * 4K buffers take 2 pages; we use roundup just to be
5397 * paranoid; we calculate it once here, rather than on
5400 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5402 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5404 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5405 (sizeof(u64) * BITS_PER_BYTE / 2);
5409 * The chip base addresses in cspec and cpspec have to be set
5410 * after possible init_chip_wc_pat(), rather than in
5411 * get_7322_chip_params(), so split out as separate function
5413 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5416 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5418 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5419 (char __iomem *)dd->kregbase);
5421 dd->egrtidbase = (u64 __iomem *)
5422 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5424 /* port registers are defined as relative to base of chip */
5425 dd->pport[0].cpspec->kpregbase =
5426 (u64 __iomem *)((char __iomem *)dd->kregbase);
5427 dd->pport[1].cpspec->kpregbase =
5428 (u64 __iomem *)(dd->palign +
5429 (char __iomem *)dd->kregbase);
5430 dd->pport[0].cpspec->cpregbase =
5431 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5432 kr_counterregbase) + (char __iomem *)dd->kregbase);
5433 dd->pport[1].cpspec->cpregbase =
5434 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5435 kr_counterregbase) + (char __iomem *)dd->kregbase);
5439 * This is a fairly special-purpose observer, so we only support
5440 * the port-specific parts of SendCtrl
5443 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5444 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5445 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5446 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5447 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5448 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5449 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5451 static int sendctrl_hook(struct qib_devdata *dd,
5452 const struct diag_observer *op, u32 offs,
5453 u64 *data, u64 mask, int only_32)
5455 unsigned long flags;
5458 struct qib_pportdata *ppd = NULL;
5459 u64 local_data, all_bits;
5462 * The fixed correspondence between Physical ports and pports is
5463 * severed. We need to hunt for the ppd that corresponds
5464 * to the offset we got. And we have to do that without admitting
5465 * we know the stride, apparently.
5467 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5471 ppd = dd->pport + pidx;
5472 if (!ppd->cpspec->kpregbase)
5475 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5476 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5481 /* If pport is not being managed by driver, just avoid shadows. */
5482 if (pidx >= dd->num_pports)
5485 /* In any case, "idx" is flat index in kreg space */
5486 idx = offs / sizeof(u64);
5492 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5493 if (!ppd || (mask & all_bits) != all_bits) {
5495 * At least some mask bits are zero, so we need
5496 * to read. The judgement call is whether from
5497 * reg or shadow. First-cut: read reg, and complain
5498 * if any bits which should be shadowed are different
5499 * from their shadowed value.
5502 local_data = (u64)qib_read_kreg32(dd, idx);
5504 local_data = qib_read_kreg64(dd, idx);
5505 *data = (local_data & ~mask) | (*data & mask);
5509 * At least some mask bits are one, so we need
5510 * to write, but only shadow some bits.
5512 u64 sval, tval; /* Shadowed, transient */
5515 * New shadow val is bits we don't want to touch,
5516 * ORed with bits we do, that are intended for shadow.
5519 sval = ppd->p_sendctrl & ~mask;
5520 sval |= *data & SENDCTRL_SHADOWED & mask;
5521 ppd->p_sendctrl = sval;
5523 sval = *data & SENDCTRL_SHADOWED & mask;
5524 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5525 qib_write_kreg(dd, idx, tval);
5526 qib_write_kreg(dd, kr_scratch, 0Ull);
5528 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5529 return only_32 ? 4 : 8;
5532 static const struct diag_observer sendctrl_0_observer = {
5533 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5534 KREG_IDX(SendCtrl_0) * sizeof(u64)
5537 static const struct diag_observer sendctrl_1_observer = {
5538 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5539 KREG_IDX(SendCtrl_1) * sizeof(u64)
5542 static ushort sdma_fetch_prio = 8;
5543 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5544 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5546 /* Besides logging QSFP events, we set appropriate TxDDS values */
5547 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5549 static void qsfp_7322_event(struct work_struct *work)
5551 struct qib_qsfp_data *qd;
5552 struct qib_pportdata *ppd;
5557 qd = container_of(work, struct qib_qsfp_data, work);
5559 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5562 * Some QSFP's not only do not respond until the full power-up
5563 * time, but may behave badly if we try. So hold off responding
5567 u64 now = get_jiffies_64();
5568 if (time_after64(now, pwrup))
5572 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5574 * Need to change LE2 back to defaults if we couldn't
5575 * read the cable type (to handle cable swaps), so do this
5576 * even on failure to read cable information. We don't
5577 * get here for QME, so IS_QME check not needed here.
5579 le2 = (!ret && qd->cache.atten[1] >= qib_long_atten &&
5580 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5581 LE2_5m : LE2_DEFAULT;
5582 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5583 init_txdds_table(ppd, 0);
5587 * There is little we can do but complain to the user if QSFP
5588 * initialization fails.
5590 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5592 unsigned long flags;
5593 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5594 struct qib_devdata *dd = ppd->dd;
5595 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5597 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5599 qib_qsfp_init(qd, qsfp_7322_event);
5600 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5601 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5602 dd->cspec->gpio_mask |= mod_prs_bit;
5603 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5604 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5605 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5609 * called at device initialization time, and also if the txselect
5610 * module parameter is changed. This is used for cables that don't
5611 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5612 * We initialize to the default, then if there is a specific
5613 * unit,port match, we use that (and set it immediately, for the
5614 * current speed, if the link is at INIT or better).
5615 * String format is "default# unit#,port#=# ... u,p=#", separators must
5616 * be a SPACE character. A newline terminates. The u,p=# tuples may
5617 * optionally have "u,p=#,#", where the final # is the H1 value
5618 * The last specific match is used (actually, all are used, but last
5619 * one is the one that winds up set); if none at all, fall back on default.
5621 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5624 u32 pidx, unit, port, deflt, h1;
5629 str = txselect_list;
5631 /* default number is validated in setup_txselect() */
5632 deflt = simple_strtoul(str, &nxt, 0);
5633 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5634 dd->pport[pidx].cpspec->no_eep = deflt;
5636 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5637 if (IS_QME(dd) || IS_QMH(dd))
5638 txdds_size += TXDDS_MFG_SZ;
5640 while (*nxt && nxt[1]) {
5642 unit = simple_strtoul(str, &nxt, 0);
5643 if (nxt == str || !*nxt || *nxt != ',') {
5644 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5649 port = simple_strtoul(str, &nxt, 0);
5650 if (nxt == str || *nxt != '=') {
5651 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5656 val = simple_strtoul(str, &nxt, 0);
5658 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5662 if (val >= txdds_size)
5665 h1 = 0; /* gcc thinks it might be used uninitted */
5666 if (*nxt == ',' && nxt[1]) {
5668 h1 = (u32)simple_strtoul(str, &nxt, 0);
5670 while (*nxt && *nxt++ != ' ') /* skip */
5675 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5677 struct qib_pportdata *ppd = &dd->pport[pidx];
5679 if (ppd->port != port || !ppd->link_speed_supported)
5681 ppd->cpspec->no_eep = val;
5683 ppd->cpspec->h1_val = h1;
5684 /* now change the IBC and serdes, overriding generic */
5685 init_txdds_table(ppd, 1);
5691 if (change && !any) {
5692 /* no specific setting, use the default.
5693 * Change the IBC and serdes, but since it's
5694 * general, don't override specific settings.
5696 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5697 if (dd->pport[pidx].link_speed_supported)
5698 init_txdds_table(&dd->pport[pidx], 0);
5702 /* handle the txselect parameter changing */
5703 static int setup_txselect(const char *str, struct kernel_param *kp)
5705 struct qib_devdata *dd;
5708 if (strlen(str) >= MAX_ATTEN_LEN) {
5709 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5713 val = simple_strtoul(str, &n, 0);
5714 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5716 printk(KERN_INFO QIB_DRV_NAME
5717 "txselect_values must start with a number < %d\n",
5718 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5721 strcpy(txselect_list, str);
5723 list_for_each_entry(dd, &qib_dev_list, list)
5724 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5725 set_no_qsfp_atten(dd, 1);
5730 * Write the final few registers that depend on some of the
5731 * init setup. Done late in init, just before bringing up
5734 static int qib_late_7322_initreg(struct qib_devdata *dd)
5739 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5740 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5741 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5742 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5743 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5744 if (val != dd->pioavailregs_phys) {
5745 qib_dev_err(dd, "Catastrophic software error, "
5746 "SendPIOAvailAddr written as %lx, "
5747 "read back as %llx\n",
5748 (unsigned long) dd->pioavailregs_phys,
5749 (unsigned long long) val);
5753 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5754 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5755 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5756 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5758 qib_register_observer(dd, &sendctrl_0_observer);
5759 qib_register_observer(dd, &sendctrl_1_observer);
5761 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5762 qib_write_kreg(dd, kr_control, dd->control);
5764 * Set SendDmaFetchPriority and init Tx params, including
5765 * QSFP handler on boards that have QSFP.
5766 * First set our default attenuation entry for cables that
5767 * don't have valid attenuation.
5769 set_no_qsfp_atten(dd, 0);
5770 for (n = 0; n < dd->num_pports; ++n) {
5771 struct qib_pportdata *ppd = dd->pport + n;
5773 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5774 sdma_fetch_prio & 0xf);
5775 /* Initialize qsfp if present on board. */
5776 if (dd->flags & QIB_HAS_QSFP)
5777 qib_init_7322_qsfp(ppd);
5779 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5780 qib_write_kreg(dd, kr_control, dd->control);
5785 /* per IB port errors. */
5786 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5788 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5789 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5790 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5794 * Write the initialization per-port registers that need to be done at
5795 * driver load and after reset completes (i.e., that aren't done as part
5796 * of other init procedures called from qib_init.c).
5797 * Some of these should be redundant on reset, but play safe.
5799 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5804 if (!ppd->link_speed_supported) {
5805 /* no buffer credits for this port */
5806 for (i = 1; i < 8; i++)
5807 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5808 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5809 qib_write_kreg(ppd->dd, kr_scratch, 0);
5814 * Set the number of supported virtual lanes in IBC,
5815 * for flow control packet handling on unsupported VLs
5817 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5818 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5819 val |= (u64)(ppd->vls_supported - 1) <<
5820 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5821 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5823 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5825 /* enable tx header checking */
5826 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5827 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5828 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5830 qib_write_kreg_port(ppd, krp_ncmodectrl,
5831 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5834 * Unconditionally clear the bufmask bits. If SDMA is
5835 * enabled, we'll set them appropriately later.
5837 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5838 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5839 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5840 if (ppd->dd->cspec->r1)
5841 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5845 * Write the initialization per-device registers that need to be done at
5846 * driver load and after reset completes (i.e., that aren't done as part
5847 * of other init procedures called from qib_init.c). Also write per-port
5848 * registers that are affected by overall device config, such as QP mapping
5849 * Some of these should be redundant on reset, but play safe.
5851 static void write_7322_initregs(struct qib_devdata *dd)
5853 struct qib_pportdata *ppd;
5857 /* Set Multicast QPs received by port 2 to map to context one. */
5858 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5860 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5862 unsigned long flags;
5864 if (!dd->qpn_mask || !dd->pport[pidx].link_speed_supported)
5867 ppd = &dd->pport[pidx];
5869 /* be paranoid against later code motion, etc. */
5870 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5871 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5872 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5874 /* Initialize QP to context mapping */
5875 regno = krp_rcvqpmaptable;
5877 if (dd->num_pports > 1)
5878 n = dd->first_user_ctxt / dd->num_pports;
5880 n = dd->first_user_ctxt - 1;
5881 for (i = 0; i < 32; ) {
5884 if (dd->num_pports > 1)
5885 ctxt = (i % n) * dd->num_pports + pidx;
5889 ctxt = ppd->hw_pidx;
5890 val |= ctxt << (5 * (i % 6));
5893 qib_write_kreg_port(ppd, regno, val);
5898 qib_write_kreg_port(ppd, regno, val);
5902 * Setup up interrupt mitigation for kernel contexts, but
5903 * not user contexts (user contexts use interrupts when
5904 * stalled waiting for any packet, so want those interrupts
5907 for (i = 0; i < dd->first_user_ctxt; i++) {
5908 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5909 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5913 * Initialize as (disabled) rcvflow tables. Application code
5914 * will setup each flow as it uses the flow.
5915 * Doesn't clear any of the error bits that might be set.
5917 val = TIDFLOW_ERRBITS; /* these are W1C */
5918 for (i = 0; i < dd->cfgctxts; i++) {
5920 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5921 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5925 * dual cards init to dual port recovery, single port cards to
5926 * the one port. Dual port cards may later adjust to 1 port,
5927 * and then back to dual port if both ports are connected
5930 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5933 static int qib_init_7322_variables(struct qib_devdata *dd)
5935 struct qib_pportdata *ppd;
5936 unsigned features, pidx, sbufcnt;
5938 u32 sbufs, updthresh;
5940 /* pport structs are contiguous, allocated after devdata */
5941 ppd = (struct qib_pportdata *)(dd + 1);
5946 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5948 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5949 ppd[1].cpspec = &ppd[0].cpspec[1];
5950 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
5951 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
5953 spin_lock_init(&dd->cspec->rcvmod_lock);
5954 spin_lock_init(&dd->cspec->gpio_lock);
5956 /* we haven't yet set QIB_PRESENT, so use read directly */
5957 dd->revision = readq(&dd->kregbase[kr_revision]);
5959 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
5960 qib_dev_err(dd, "Revision register read failure, "
5961 "giving up initialization\n");
5965 dd->flags |= QIB_PRESENT; /* now register routines work */
5967 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
5968 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
5969 dd->cspec->r1 = dd->minrev == 1;
5971 get_7322_chip_params(dd);
5972 features = qib_7322_boardname(dd);
5974 /* now that piobcnt2k and 4k set, we can allocate these */
5975 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
5976 NUM_VL15_BUFS + BITS_PER_LONG - 1;
5977 sbufcnt /= BITS_PER_LONG;
5978 dd->cspec->sendchkenable = kmalloc(sbufcnt *
5979 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
5980 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
5981 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
5982 dd->cspec->sendibchk = kmalloc(sbufcnt *
5983 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
5984 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
5985 !dd->cspec->sendibchk) {
5986 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
5994 * GPIO bits for TWSI data and clock,
5995 * used for serial EEPROM.
5997 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
5998 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
5999 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6001 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6002 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6003 QIB_HAS_THRESH_UPDATE |
6004 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6005 dd->flags |= qib_special_trigger ?
6006 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6009 * Setup initial values. These may change when PAT is enabled, but
6010 * we need these to do initial chip register accesses.
6012 qib_7322_set_baseaddrs(dd);
6014 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6016 mtu = QIB_DEFAULT_MTU;
6018 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6019 /* all hwerrors become interrupts, unless special purposed */
6020 dd->cspec->hwerrmask = ~0ULL;
6021 /* link_recovery setup causes these errors, so ignore them,
6022 * other than clearing them when they occur */
6023 dd->cspec->hwerrmask &=
6024 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6025 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6026 HWE_MASK(LATriggered));
6028 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6029 struct qib_chippport_specific *cp = ppd->cpspec;
6030 ppd->link_speed_supported = features & PORT_SPD_CAP;
6031 features >>= PORT_SPD_CAP_SHIFT;
6032 if (!ppd->link_speed_supported) {
6033 /* single port mode (7340, or configured) */
6034 dd->skip_kctxt_mask |= 1 << pidx;
6036 /* Make sure port is disabled. */
6037 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6038 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6040 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6041 IBSerdesPClkNotDetectMask_0)
6042 | SYM_MASK(HwErrMask,
6043 SDmaMemReadErrMask_0));
6044 dd->cspec->int_enable_mask &= ~(
6045 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6046 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6047 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6048 SYM_MASK(IntMask, SDmaIntMask_0) |
6049 SYM_MASK(IntMask, ErrIntMask_0) |
6050 SYM_MASK(IntMask, SendDoneIntMask_0));
6052 /* Make sure port is disabled. */
6053 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6054 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6055 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6056 IBSerdesPClkNotDetectMask_1)
6057 | SYM_MASK(HwErrMask,
6058 SDmaMemReadErrMask_1));
6059 dd->cspec->int_enable_mask &= ~(
6060 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6061 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6062 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6063 SYM_MASK(IntMask, SDmaIntMask_1) |
6064 SYM_MASK(IntMask, ErrIntMask_1) |
6065 SYM_MASK(IntMask, SendDoneIntMask_1));
6071 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6073 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6074 ppd->link_width_enabled = IB_WIDTH_4X;
6075 ppd->link_speed_enabled = ppd->link_speed_supported;
6077 * Set the initial values to reasonable default, will be set
6078 * for real when link is up.
6080 ppd->link_width_active = IB_WIDTH_4X;
6081 ppd->link_speed_active = QIB_IB_SDR;
6082 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6083 switch (qib_num_cfg_vls) {
6085 ppd->vls_supported = IB_VL_VL0;
6088 ppd->vls_supported = IB_VL_VL0_1;
6091 qib_devinfo(dd->pcidev,
6092 "Invalid num_vls %u, using 4 VLs\n",
6094 qib_num_cfg_vls = 4;
6097 ppd->vls_supported = IB_VL_VL0_3;
6101 ppd->vls_supported = IB_VL_VL0_7;
6103 qib_devinfo(dd->pcidev,
6104 "Invalid num_vls %u for MTU %d "
6106 qib_num_cfg_vls, mtu);
6107 ppd->vls_supported = IB_VL_VL0_3;
6108 qib_num_cfg_vls = 4;
6112 ppd->vls_operational = ppd->vls_supported;
6114 init_waitqueue_head(&cp->autoneg_wait);
6115 INIT_DELAYED_WORK(&cp->autoneg_work,
6117 if (ppd->dd->cspec->r1)
6118 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6121 * For Mez and similar cards, no qsfp info, so do
6122 * the "cable info" setup here. Can be overridden
6123 * in adapter-specific routines.
6125 if (!(dd->flags & QIB_HAS_QSFP)) {
6126 if (!IS_QMH(dd) && !IS_QME(dd))
6127 qib_devinfo(dd->pcidev, "IB%u:%u: "
6128 "Unknown mezzanine card type\n",
6129 dd->unit, ppd->port);
6130 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6132 * Choose center value as default tx serdes setting
6133 * until changed through module parameter.
6135 ppd->cpspec->no_eep = IS_QMH(dd) ?
6136 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6138 cp->h1_val = H1_FORCE_VAL;
6140 /* Avoid writes to chip for mini_init */
6142 write_7322_init_portregs(ppd);
6144 init_timer(&cp->chase_timer);
6145 cp->chase_timer.function = reenable_chase;
6146 cp->chase_timer.data = (unsigned long)ppd;
6151 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6152 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6153 dd->rcvhdrsize = qib_rcvhdrsize ?
6154 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6155 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6157 /* we always allocate at least 2048 bytes for eager buffers */
6158 dd->rcvegrbufsize = max(mtu, 2048);
6160 qib_7322_tidtemplate(dd);
6163 * We can request a receive interrupt for 1 or
6164 * more packets from current offset.
6166 dd->rhdrhead_intr_off =
6167 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6169 /* setup the stats timer; the add_timer is done at end of init */
6170 init_timer(&dd->stats_timer);
6171 dd->stats_timer.function = qib_get_7322_faststats;
6172 dd->stats_timer.data = (unsigned long) dd;
6174 dd->ureg_align = 0x10000; /* 64KB alignment */
6176 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6178 qib_7322_config_ctxts(dd);
6179 qib_set_ctxtcnt(dd);
6182 resource_size_t vl15off;
6184 * We do not set WC on the VL15 buffers to avoid
6185 * a rare problem with unaligned writes from
6186 * interrupt-flushed store buffers, so we need
6187 * to map those separately here. We can't solve
6188 * this for the rarely used mtrr case.
6190 ret = init_chip_wc_pat(dd, 0);
6194 /* vl15 buffers start just after the 4k buffers */
6195 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6196 dd->piobcnt4k * dd->align4k;
6197 dd->piovl15base = ioremap_nocache(vl15off,
6198 NUM_VL15_BUFS * dd->align4k);
6199 if (!dd->piovl15base)
6202 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6207 if (!dd->num_pports) {
6208 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6209 goto bail; /* no error, so can still figure out why err */
6212 write_7322_initregs(dd);
6213 ret = qib_create_ctxts(dd);
6214 init_7322_cntrnames(dd);
6216 updthresh = 8U; /* update threshold */
6218 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6219 * reserve the update threshold amount for other kernel use, such
6220 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6221 * unless we aren't enabling SDMA, in which case we want to use
6222 * all the 4k bufs for the kernel.
6223 * if this was less than the update threshold, we could wait
6224 * a long time for an update. Coded this way because we
6225 * sometimes change the update threshold for various reasons,
6226 * and we want this to remain robust.
6228 if (dd->flags & QIB_HAS_SEND_DMA) {
6229 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6230 sbufs = updthresh > 3 ? updthresh : 3;
6232 dd->cspec->sdmabufcnt = 0;
6233 sbufs = dd->piobcnt4k;
6235 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6236 dd->cspec->sdmabufcnt;
6237 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6238 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6239 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6240 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6243 * If we have 16 user contexts, we will have 7 sbufs
6244 * per context, so reduce the update threshold to match. We
6245 * want to update before we actually run out, at low pbufs/ctxt
6246 * so give ourselves some margin.
6248 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6249 updthresh = dd->pbufsctxt - 2;
6250 dd->cspec->updthresh_dflt = updthresh;
6251 dd->cspec->updthresh = updthresh;
6253 /* before full enable, no interrupts, no locking needed */
6254 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6255 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6256 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6258 dd->psxmitwait_supported = 1;
6259 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6262 dd->ctxtcnt = 1; /* for other initialization code */
6267 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6270 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6271 struct qib_devdata *dd = ppd->dd;
6273 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6274 if (pbc & PBC_7322_VL15_SEND) {
6275 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6278 if ((plen + 1) > dd->piosize2kmax_dwords)
6279 first = dd->piobcnt2k;
6282 last = dd->cspec->lastbuf_for_pio;
6284 return qib_getsendbuf_range(dd, pbufnum, first, last);
6287 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6290 qib_write_kreg_port(ppd, krp_psinterval, intv);
6291 qib_write_kreg_port(ppd, krp_psstart, start);
6295 * Must be called with sdma_lock held, or before init finished.
6297 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6299 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6302 static struct sdma_set_state_action sdma_7322_action_table[] = {
6303 [qib_sdma_state_s00_hw_down] = {
6304 .go_s99_running_tofalse = 1,
6310 [qib_sdma_state_s10_hw_start_up_wait] = {
6316 [qib_sdma_state_s20_idle] = {
6322 [qib_sdma_state_s30_sw_clean_up_wait] = {
6328 [qib_sdma_state_s40_hw_clean_up_wait] = {
6334 [qib_sdma_state_s50_hw_halt_wait] = {
6340 [qib_sdma_state_s99_running] = {
6345 .go_s99_running_totrue = 1,
6349 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6351 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6354 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6356 struct qib_devdata *dd = ppd->dd;
6357 unsigned lastbuf, erstbuf;
6358 u64 senddmabufmask[3] = { 0 };
6361 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6362 qib_sdma_7322_setlengen(ppd);
6363 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6364 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6365 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6366 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6369 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6371 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6372 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6373 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6374 dd->cspec->sdmabufcnt);
6375 lastbuf = erstbuf + n;
6377 ppd->sdma_state.first_sendbuf = erstbuf;
6378 ppd->sdma_state.last_sendbuf = lastbuf;
6379 for (; erstbuf < lastbuf; ++erstbuf) {
6380 unsigned word = erstbuf / BITS_PER_LONG;
6381 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6384 senddmabufmask[word] |= 1ULL << bit;
6386 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6387 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6388 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6392 /* sdma_lock must be held */
6393 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6395 struct qib_devdata *dd = ppd->dd;
6403 use_dmahead = __qib_sdma_running(ppd) &&
6404 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6406 hwhead = use_dmahead ?
6407 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6408 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6410 swhead = ppd->sdma_descq_head;
6411 swtail = ppd->sdma_descq_tail;
6412 cnt = ppd->sdma_descq_cnt;
6414 if (swhead < swtail)
6416 sane = (hwhead >= swhead) & (hwhead <= swtail);
6417 else if (swhead > swtail)
6418 /* wrapped around */
6419 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6423 sane = (hwhead == swhead);
6425 if (unlikely(!sane)) {
6427 /* try one more time, directly from the register */
6431 /* proceed as if no progress */
6438 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6440 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6442 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6443 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6444 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6445 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6449 * Compute the amount of delay before sending the next packet if the
6450 * port's send rate differs from the static rate set for the QP.
6451 * The delay affects the next packet and the amount of the delay is
6452 * based on the length of the this packet.
6454 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6457 u8 snd_mult = ppd->delay_mult;
6458 u8 rcv_mult = ib_rate_to_delay[srate];
6461 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6463 /* Indicate VL15, else set the VL in the control word */
6465 ret |= PBC_7322_VL15_SEND_CTRL;
6467 ret |= vl << PBC_VL_NUM_LSB;
6468 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6474 * Enable the per-port VL15 send buffers for use.
6475 * They follow the rest of the buffers, without a config parameter.
6476 * This was in initregs, but that is done before the shadow
6477 * is set up, and this has to be done after the shadow is
6480 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6484 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6485 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6486 TXCHK_CHG_TYPE_KERN, NULL);
6489 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6491 if (rcd->ctxt < NUM_IB_PORTS) {
6492 if (rcd->dd->num_pports > 1) {
6493 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6494 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6496 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6497 rcd->rcvegr_tid_base = 0;
6500 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6501 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6502 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6506 #define QTXSLEEPS 5000
6507 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6508 u32 len, u32 which, struct qib_ctxtdata *rcd)
6511 const int last = start + len - 1;
6512 const int lastr = last / BITS_PER_LONG;
6514 int wait = rcd != NULL;
6515 unsigned long flags;
6518 unsigned long shadow;
6519 int cstart, previ = -1;
6522 * when flipping from kernel to user, we can't change
6523 * the checking type if the buffer is allocated to the
6524 * driver. It's OK the other direction, because it's
6525 * from close, and we have just disarm'ed all the
6526 * buffers. All the kernel to kernel changes are also
6529 for (cstart = start; cstart <= last; cstart++) {
6530 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6533 shadow = (unsigned long)
6534 le64_to_cpu(dd->pioavailregs_dma[i]);
6537 if (test_bit(((2 * cstart) +
6538 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6539 % BITS_PER_LONG, &shadow))
6546 if (sleeps == QTXSLEEPS)
6548 /* make sure we see an updated copy next time around */
6549 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6555 case TXCHK_CHG_TYPE_DIS1:
6557 * disable checking on a range; used by diags; just
6558 * one buffer, but still written generically
6560 for (i = start; i <= last; i++)
6561 clear_bit(i, dd->cspec->sendchkenable);
6564 case TXCHK_CHG_TYPE_ENAB1:
6566 * (re)enable checking on a range; used by diags; just
6567 * one buffer, but still written generically; read
6568 * scratch to be sure buffer actually triggered, not
6569 * just flushed from processor.
6571 qib_read_kreg32(dd, kr_scratch);
6572 for (i = start; i <= last; i++)
6573 set_bit(i, dd->cspec->sendchkenable);
6576 case TXCHK_CHG_TYPE_KERN:
6577 /* usable by kernel */
6578 for (i = start; i <= last; i++) {
6579 set_bit(i, dd->cspec->sendibchk);
6580 clear_bit(i, dd->cspec->sendgrhchk);
6582 spin_lock_irqsave(&dd->uctxt_lock, flags);
6583 /* see if we need to raise avail update threshold */
6584 for (i = dd->first_user_ctxt;
6585 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6586 && i < dd->cfgctxts; i++)
6587 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6588 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6589 < dd->cspec->updthresh_dflt)
6591 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6592 if (i == dd->cfgctxts) {
6593 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6594 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6595 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6596 dd->sendctrl |= (dd->cspec->updthresh &
6597 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6598 SYM_LSB(SendCtrl, AvailUpdThld);
6599 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6600 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6604 case TXCHK_CHG_TYPE_USER:
6605 /* for user process */
6606 for (i = start; i <= last; i++) {
6607 clear_bit(i, dd->cspec->sendibchk);
6608 set_bit(i, dd->cspec->sendgrhchk);
6610 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6611 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6612 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6613 dd->cspec->updthresh = (rcd->piocnt /
6614 rcd->subctxt_cnt) - 1;
6615 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6616 dd->sendctrl |= (dd->cspec->updthresh &
6617 SYM_RMASK(SendCtrl, AvailUpdThld))
6618 << SYM_LSB(SendCtrl, AvailUpdThld);
6619 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6620 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6622 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6629 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6630 qib_write_kreg(dd, kr_sendcheckmask + i,
6631 dd->cspec->sendchkenable[i]);
6633 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6634 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6635 dd->cspec->sendgrhchk[i]);
6636 qib_write_kreg(dd, kr_sendibpktmask + i,
6637 dd->cspec->sendibchk[i]);
6641 * Be sure whatever we did was seen by the chip and acted upon,
6642 * before we return. Mostly important for which >= 2.
6644 qib_read_kreg32(dd, kr_scratch);
6648 /* useful for trigger analyzers, etc. */
6649 static void writescratch(struct qib_devdata *dd, u32 val)
6651 qib_write_kreg(dd, kr_scratch, val);
6654 /* Dummy for now, use chip regs soon */
6655 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6661 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6662 * @dev: the pci_dev for qlogic_ib device
6663 * @ent: pci_device_id struct for this dev
6665 * Also allocates, inits, and returns the devdata struct for this
6668 * This is global, and is called directly at init to set up the
6669 * chip-specific function pointers for later use.
6671 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6672 const struct pci_device_id *ent)
6674 struct qib_devdata *dd;
6676 u32 tabsize, actual_cnt = 0;
6678 dd = qib_alloc_devdata(pdev,
6679 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6680 sizeof(struct qib_chip_specific) +
6681 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6685 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6686 dd->f_cleanup = qib_setup_7322_cleanup;
6687 dd->f_clear_tids = qib_7322_clear_tids;
6688 dd->f_free_irq = qib_7322_free_irq;
6689 dd->f_get_base_info = qib_7322_get_base_info;
6690 dd->f_get_msgheader = qib_7322_get_msgheader;
6691 dd->f_getsendbuf = qib_7322_getsendbuf;
6692 dd->f_gpio_mod = gpio_7322_mod;
6693 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6694 dd->f_hdrqempty = qib_7322_hdrqempty;
6695 dd->f_ib_updown = qib_7322_ib_updown;
6696 dd->f_init_ctxt = qib_7322_init_ctxt;
6697 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6698 dd->f_intr_fallback = qib_7322_intr_fallback;
6699 dd->f_late_initreg = qib_late_7322_initreg;
6700 dd->f_setpbc_control = qib_7322_setpbc_control;
6701 dd->f_portcntr = qib_portcntr_7322;
6702 dd->f_put_tid = qib_7322_put_tid;
6703 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6704 dd->f_rcvctrl = rcvctrl_7322_mod;
6705 dd->f_read_cntrs = qib_read_7322cntrs;
6706 dd->f_read_portcntrs = qib_read_7322portcntrs;
6707 dd->f_reset = qib_do_7322_reset;
6708 dd->f_init_sdma_regs = init_sdma_7322_regs;
6709 dd->f_sdma_busy = qib_sdma_7322_busy;
6710 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6711 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6712 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6713 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6714 dd->f_sendctrl = sendctrl_7322_mod;
6715 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6716 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6717 dd->f_iblink_state = qib_7322_iblink_state;
6718 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6719 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6720 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6721 dd->f_set_ib_loopback = qib_7322_set_loopback;
6722 dd->f_get_ib_table = qib_7322_get_ib_table;
6723 dd->f_set_ib_table = qib_7322_set_ib_table;
6724 dd->f_set_intr_state = qib_7322_set_intr_state;
6725 dd->f_setextled = qib_setup_7322_setextled;
6726 dd->f_txchk_change = qib_7322_txchk_change;
6727 dd->f_update_usrhead = qib_update_7322_usrhead;
6728 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6729 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6730 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6731 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6732 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6733 dd->f_writescratch = writescratch;
6734 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6736 * Do remaining PCIe setup and save PCIe values in dd.
6737 * Any error printing is already done by the init code.
6738 * On return, we have the chip mapped, but chip registers
6739 * are not set up until start of qib_init_7322_variables.
6741 ret = qib_pcie_ddinit(dd, pdev, ent);
6745 /* initialize chip-specific variables */
6746 ret = qib_init_7322_variables(dd);
6750 if (qib_mini_init || !dd->num_pports)
6754 * Determine number of vectors we want; depends on port count
6755 * and number of configured kernel receive queues actually used.
6756 * Should also depend on whether sdma is enabled or not, but
6757 * that's such a rare testing case it's not worth worrying about.
6759 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6760 for (i = 0; i < tabsize; i++)
6761 if ((i < ARRAY_SIZE(irq_table) &&
6762 irq_table[i].port <= dd->num_pports) ||
6763 (i >= ARRAY_SIZE(irq_table) &&
6764 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6766 tabsize = actual_cnt;
6767 dd->cspec->msix_entries = kmalloc(tabsize *
6768 sizeof(struct msix_entry), GFP_KERNEL);
6769 dd->cspec->msix_arg = kmalloc(tabsize *
6770 sizeof(void *), GFP_KERNEL);
6771 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6772 qib_dev_err(dd, "No memory for MSIx table\n");
6775 for (i = 0; i < tabsize; i++)
6776 dd->cspec->msix_entries[i].entry = i;
6778 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6779 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6780 "continuing anyway\n");
6781 /* may be less than we wanted, if not enough available */
6782 dd->cspec->num_msix_entries = tabsize;
6784 /* setup interrupt handler */
6785 qib_setup_7322_interrupt(dd, 1);
6787 /* clear diagctrl register, in case diags were running and crashed */
6788 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6793 qib_pcie_ddcleanup(dd);
6795 qib_free_devdata(dd);
6802 * Set the table entry at the specified index from the table specifed.
6803 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6804 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6805 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6806 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6808 #define DDS_ENT_AMP_LSB 14
6809 #define DDS_ENT_MAIN_LSB 9
6810 #define DDS_ENT_POST_LSB 5
6811 #define DDS_ENT_PRE_XTRA_LSB 3
6812 #define DDS_ENT_PRE_LSB 0
6815 * Set one entry in the TxDDS table for spec'd port
6816 * ridx picks one of the entries, while tp points
6817 * to the appropriate table entry.
6819 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6820 const struct txdds_ent *tp)
6822 struct qib_devdata *dd = ppd->dd;
6826 /* Get correct offset in chip-space, and in source table */
6827 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6829 * We do not use qib_write_kreg_port() because it was intended
6830 * only for registers in the lower "port specific" pages.
6831 * So do index calculation by hand.
6834 regidx += (dd->palign / sizeof(u64));
6836 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6837 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6838 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6839 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6840 qib_write_kreg(dd, regidx, pack_ent);
6841 /* Prevent back-to-back writes by hitting scratch */
6842 qib_write_kreg(ppd->dd, kr_scratch, 0);
6845 static const struct vendor_txdds_ent vendor_txdds[] = {
6846 { /* Amphenol 1m 30awg NoEq */
6847 { 0x41, 0x50, 0x48 }, "584470002 ",
6848 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6850 { /* Amphenol 3m 28awg NoEq */
6851 { 0x41, 0x50, 0x48 }, "584470004 ",
6852 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6854 { /* Finisar 3m OM2 Optical */
6855 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6856 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6858 { /* Finisar 30m OM2 Optical */
6859 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6860 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6862 { /* Finisar Default OM2 Optical */
6863 { 0x00, 0x90, 0x65 }, NULL,
6864 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6866 { /* Gore 1m 30awg NoEq */
6867 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6868 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6870 { /* Gore 2m 30awg NoEq */
6871 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6872 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6874 { /* Gore 1m 28awg NoEq */
6875 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6876 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6878 { /* Gore 3m 28awg NoEq */
6879 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6880 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6882 { /* Gore 5m 24awg Eq */
6883 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6884 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6886 { /* Gore 7m 24awg Eq */
6887 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6888 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6890 { /* Gore 5m 26awg Eq */
6891 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6892 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6894 { /* Gore 7m 26awg Eq */
6895 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6896 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6898 { /* Intersil 12m 24awg Active */
6899 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6900 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6902 { /* Intersil 10m 28awg Active */
6903 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6904 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6906 { /* Intersil 7m 30awg Active */
6907 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6908 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6910 { /* Intersil 5m 32awg Active */
6911 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6912 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6914 { /* Intersil Default Active */
6915 { 0x00, 0x30, 0xB4 }, NULL,
6916 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6918 { /* Luxtera 20m Active Optical */
6919 { 0x00, 0x25, 0x63 }, NULL,
6920 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6922 { /* Molex 1M Cu loopback */
6923 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6924 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6926 { /* Molex 2m 28awg NoEq */
6927 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6928 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6932 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6933 /* amp, pre, main, post */
6934 { 2, 2, 15, 6 }, /* Loopback */
6935 { 0, 0, 0, 1 }, /* 2 dB */
6936 { 0, 0, 0, 2 }, /* 3 dB */
6937 { 0, 0, 0, 3 }, /* 4 dB */
6938 { 0, 0, 0, 4 }, /* 5 dB */
6939 { 0, 0, 0, 5 }, /* 6 dB */
6940 { 0, 0, 0, 6 }, /* 7 dB */
6941 { 0, 0, 0, 7 }, /* 8 dB */
6942 { 0, 0, 0, 8 }, /* 9 dB */
6943 { 0, 0, 0, 9 }, /* 10 dB */
6944 { 0, 0, 0, 10 }, /* 11 dB */
6945 { 0, 0, 0, 11 }, /* 12 dB */
6946 { 0, 0, 0, 12 }, /* 13 dB */
6947 { 0, 0, 0, 13 }, /* 14 dB */
6948 { 0, 0, 0, 14 }, /* 15 dB */
6949 { 0, 0, 0, 15 }, /* 16 dB */
6952 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
6953 /* amp, pre, main, post */
6954 { 2, 2, 15, 6 }, /* Loopback */
6955 { 0, 0, 0, 8 }, /* 2 dB */
6956 { 0, 0, 0, 8 }, /* 3 dB */
6957 { 0, 0, 0, 9 }, /* 4 dB */
6958 { 0, 0, 0, 9 }, /* 5 dB */
6959 { 0, 0, 0, 10 }, /* 6 dB */
6960 { 0, 0, 0, 10 }, /* 7 dB */
6961 { 0, 0, 0, 11 }, /* 8 dB */
6962 { 0, 0, 0, 11 }, /* 9 dB */
6963 { 0, 0, 0, 12 }, /* 10 dB */
6964 { 0, 0, 0, 12 }, /* 11 dB */
6965 { 0, 0, 0, 13 }, /* 12 dB */
6966 { 0, 0, 0, 13 }, /* 13 dB */
6967 { 0, 0, 0, 14 }, /* 14 dB */
6968 { 0, 0, 0, 14 }, /* 15 dB */
6969 { 0, 0, 0, 15 }, /* 16 dB */
6972 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
6973 /* amp, pre, main, post */
6974 { 2, 2, 15, 6 }, /* Loopback */
6975 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
6976 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
6977 { 0, 1, 0, 11 }, /* 4 dB */
6978 { 0, 1, 0, 13 }, /* 5 dB */
6979 { 0, 1, 0, 15 }, /* 6 dB */
6980 { 0, 1, 3, 15 }, /* 7 dB */
6981 { 0, 1, 7, 15 }, /* 8 dB */
6982 { 0, 1, 7, 15 }, /* 9 dB */
6983 { 0, 1, 8, 15 }, /* 10 dB */
6984 { 0, 1, 9, 15 }, /* 11 dB */
6985 { 0, 1, 10, 15 }, /* 12 dB */
6986 { 0, 2, 6, 15 }, /* 13 dB */
6987 { 0, 2, 7, 15 }, /* 14 dB */
6988 { 0, 2, 8, 15 }, /* 15 dB */
6989 { 0, 2, 9, 15 }, /* 16 dB */
6993 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
6994 * These are mostly used for mez cards going through connectors
6995 * and backplane traces, but can be used to add other "unusual"
6996 * table values as well.
6998 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
6999 /* amp, pre, main, post */
7000 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7001 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7002 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7003 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7004 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7005 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7006 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7007 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7008 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7009 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7010 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7011 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7012 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7015 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7016 /* amp, pre, main, post */
7017 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7018 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7019 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7020 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7021 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7022 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7023 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7024 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7025 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7026 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7027 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7028 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7029 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7032 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7033 /* amp, pre, main, post */
7034 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7035 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7036 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7037 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7038 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7039 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7040 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7041 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7042 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7043 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7044 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7045 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7046 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7049 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7050 /* amp, pre, main, post */
7051 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7052 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7055 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7059 * The attenuation table starts at 2dB for entry 1,
7060 * with entry 0 being the loopback entry.
7064 else if (atten > TXDDS_TABLE_SZ)
7065 atten = TXDDS_TABLE_SZ - 1;
7068 return txdds + atten;
7072 * if override is set, the module parameter txselect has a value
7073 * for this specific port, so use it, rather than our normal mechanism.
7075 static void find_best_ent(struct qib_pportdata *ppd,
7076 const struct txdds_ent **sdr_dds,
7077 const struct txdds_ent **ddr_dds,
7078 const struct txdds_ent **qdr_dds, int override)
7080 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7083 /* Search table of known cables */
7084 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7085 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7087 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7089 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7097 /* Lookup serdes setting by cable type and attenuation */
7098 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7099 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7100 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7101 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7105 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7107 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7108 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7109 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7111 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7113 * If we have no (or incomplete) data from the cable
7114 * EEPROM, or no QSFP, or override is set, use the
7115 * module parameter value to index into the attentuation
7118 idx = ppd->cpspec->no_eep;
7119 *sdr_dds = &txdds_sdr[idx];
7120 *ddr_dds = &txdds_ddr[idx];
7121 *qdr_dds = &txdds_qdr[idx];
7122 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7123 /* similar to above, but index into the "extra" table. */
7124 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7125 *sdr_dds = &txdds_extra_sdr[idx];
7126 *ddr_dds = &txdds_extra_ddr[idx];
7127 *qdr_dds = &txdds_extra_qdr[idx];
7128 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7129 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7131 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7132 printk(KERN_INFO QIB_DRV_NAME
7133 " IB%u:%u use idx %u into txdds_mfg\n",
7134 ppd->dd->unit, ppd->port, idx);
7135 *sdr_dds = &txdds_extra_mfg[idx];
7136 *ddr_dds = &txdds_extra_mfg[idx];
7137 *qdr_dds = &txdds_extra_mfg[idx];
7139 /* this shouldn't happen, it's range checked */
7140 *sdr_dds = txdds_sdr + qib_long_atten;
7141 *ddr_dds = txdds_ddr + qib_long_atten;
7142 *qdr_dds = txdds_qdr + qib_long_atten;
7146 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7148 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7149 struct txdds_ent *dds;
7153 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7155 /* for mez cards or override, use the selected value for all entries */
7156 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7159 /* Fill in the first entry with the best entry found. */
7160 set_txdds(ppd, 0, sdr_dds);
7161 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7162 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7163 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7165 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7166 QIB_IB_QDR ? qdr_dds :
7167 (ppd->link_speed_active ==
7168 QIB_IB_DDR ? ddr_dds : sdr_dds));
7169 write_tx_serdes_param(ppd, dds);
7172 /* Fill in the remaining entries with the default table values. */
7173 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7174 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7175 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7176 single_ent ? ddr_dds : txdds_ddr + idx);
7177 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7178 single_ent ? qdr_dds : txdds_qdr + idx);
7182 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7183 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7184 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7185 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7186 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7187 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7188 #define AHB_TRANS_TRIES 10
7191 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7192 * 5=subsystem which is why most calls have "chan + chan >> 1"
7193 * for the channel argument.
7195 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7198 u32 rd_data, wr_data, sz_mask;
7199 u64 trans, acc, prev_acc;
7200 u32 ret = 0xBAD0BAD;
7203 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7204 /* From this point on, make sure we return access */
7205 acc = (quad << 1) | 1;
7206 qib_write_kreg(dd, KR_AHB_ACC, acc);
7208 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7209 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7210 if (trans & AHB_TRANS_RDY)
7213 if (tries >= AHB_TRANS_TRIES) {
7214 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7218 /* If mask is not all 1s, we need to read, but different SerDes
7219 * entities have different sizes
7221 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7222 wr_data = data & mask & sz_mask;
7223 if ((~mask & sz_mask) != 0) {
7224 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7225 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7227 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7228 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7229 if (trans & AHB_TRANS_RDY)
7232 if (tries >= AHB_TRANS_TRIES) {
7233 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7237 /* Re-read in case host split reads and read data first */
7238 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7239 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7240 wr_data |= (rd_data & ~mask & sz_mask);
7243 /* If mask is not zero, we need to write. */
7244 if (mask & sz_mask) {
7245 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7246 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7248 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7250 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7251 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7252 if (trans & AHB_TRANS_RDY)
7255 if (tries >= AHB_TRANS_TRIES) {
7256 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7263 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7267 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7270 struct qib_devdata *dd = ppd->dd;
7274 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7275 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7277 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7282 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7284 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7285 printk(KERN_INFO QIB_DRV_NAME " Turning LOS %s for port %d\n",
7286 (enable ? "on" : "off"), ppd->port);
7288 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7290 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7291 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7294 static int serdes_7322_init(struct qib_pportdata *ppd)
7297 if (ppd->dd->cspec->r1)
7298 ret = serdes_7322_init_old(ppd);
7300 ret = serdes_7322_init_new(ppd);
7304 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7309 * Initialize the Tx DDS tables. Also done every QSFP event,
7310 * for adapters with QSFP
7312 init_txdds_table(ppd, 0);
7314 /* ensure no tx overrides from earlier driver loads */
7315 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7316 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7317 reset_tx_deemphasis_override));
7319 /* Patch some SerDes defaults to "Better for IB" */
7320 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7321 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7323 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7324 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7325 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7326 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7328 /* May be overridden in qsfp_7322_event */
7329 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7330 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7332 /* enable LE1 adaptation for all but QME, which is disabled */
7333 le_val = IS_QME(ppd->dd) ? 0 : 1;
7334 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7336 /* Clear cmode-override, may be set from older driver */
7337 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7339 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7340 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7342 /* setup LoS params; these are subsystem, so chan == 5 */
7343 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7344 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7345 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7346 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7347 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7349 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7350 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7351 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7352 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7353 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7355 /* LoS filter select enabled */
7356 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7358 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7359 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7360 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7361 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7363 serdes_7322_los_enable(ppd, 1);
7365 /* rxbistena; set 0 to avoid effects of it switch later */
7366 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7368 /* Configure 4 DFE taps, and only they adapt */
7369 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7371 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7372 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7373 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7376 * Set receive adaptation mode. SDR and DDR adaptation are
7377 * always on, and QDR is initially enabled; later disabled.
7379 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7380 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7381 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7382 ppd->dd->cspec->r1 ?
7383 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7384 ppd->cpspec->qdr_dfe_on = 1;
7386 /* FLoop LOS gate: PPM filter enabled */
7387 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7389 /* rx offset center enabled */
7390 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7392 if (!ppd->dd->cspec->r1) {
7393 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7394 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7397 /* Set the frequency loop bandwidth to 15 */
7398 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7403 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7406 u32 le_val, rxcaldone;
7407 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7410 * Initialize the Tx DDS tables. Also done every QSFP event,
7411 * for adapters with QSFP
7413 init_txdds_table(ppd, 0);
7415 /* Clear cmode-override, may be set from older driver */
7416 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7418 /* ensure no tx overrides from earlier driver loads */
7419 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7420 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7421 reset_tx_deemphasis_override));
7423 /* START OF LSI SUGGESTED SERDES BRINGUP */
7424 /* Reset - Calibration Setup */
7425 /* Stop DFE adaptaion */
7426 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7428 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7429 /* Disable autoadapt for LE1 */
7430 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7432 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7434 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7435 /* Disable AFE Offset Cancel */
7436 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7437 /* Disable Timing Loop */
7438 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7439 /* Disable Frequency Loop */
7440 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7441 /* Disable Baseline Wander Correction */
7442 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7443 /* Disable RX Calibration */
7444 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7445 /* Disable RX Offset Calibration */
7446 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7448 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7450 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7451 /* Enable phase Calibration */
7452 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7453 /* DFE Bandwidth [2:14-12] */
7454 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7455 /* DFE Config (4 taps only) */
7456 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7457 /* Gain Loop Bandwidth */
7458 if (!ppd->dd->cspec->r1) {
7459 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7460 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7462 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7464 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7465 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7466 /* Data Rate Select [5:7-6] (leave as default) */
7467 /* RX Parralel Word Width [3:10-8] (leave as default) */
7470 /* Single- or Multi-channel reset */
7471 /* RX Analog reset */
7472 /* RX Digital reset */
7473 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7475 /* RX Analog reset */
7476 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7478 /* RX Digital reset */
7479 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7482 /* setup LoS params; these are subsystem, so chan == 5 */
7483 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7484 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7485 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7486 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7487 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7489 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7490 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7491 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7492 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7493 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7495 /* LoS filter select enabled */
7496 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7498 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7499 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7500 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7501 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7503 /* Turn on LOS on initial SERDES init */
7504 serdes_7322_los_enable(ppd, 1);
7505 /* FLoop LOS gate: PPM filter enabled */
7506 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7508 /* RX LATCH CALIBRATION */
7509 /* Enable Eyefinder Phase Calibration latch */
7510 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7511 /* Enable RX Offset Calibration latch */
7512 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7514 /* Start Calibration */
7515 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7516 tstart = get_jiffies_64();
7518 !time_after64(tstart, tstart + msecs_to_jiffies(500))) {
7520 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7521 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7522 (chan + (chan >> 1)),
7524 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7525 (~chan_done & (1 << chan)) == 0)
7526 chan_done &= ~(1 << chan);
7530 printk(KERN_INFO QIB_DRV_NAME
7531 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7532 IBSD(ppd->hw_pidx), chan_done);
7534 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7535 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7536 (chan + (chan >> 1)),
7538 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7539 printk(KERN_INFO QIB_DRV_NAME
7540 " Serdes %d chan %d calibration "
7541 "failed\n", IBSD(ppd->hw_pidx), chan);
7545 /* Turn off Calibration */
7546 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7550 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7551 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7552 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7553 /* Set LE2 Loop bandwidth */
7554 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7556 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7558 /* Enable H0 only */
7559 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7560 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7561 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7562 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7564 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7566 /* Set Frequency Loop Bandwidth */
7567 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7568 /* Enable Frequency Loop */
7569 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7570 /* Set Timing Loop Bandwidth */
7571 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7572 /* Enable Timing Loop */
7573 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7576 * Set receive adaptation mode. SDR and DDR adaptation are
7577 * always on, and QDR is initially enabled; later disabled.
7579 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7580 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7581 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7582 ppd->dd->cspec->r1 ?
7583 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7584 ppd->cpspec->qdr_dfe_on = 1;
7586 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7587 /* Disable auto adapt for LE1 */
7588 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7590 /* Enable AFE Offset Cancel */
7591 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7592 /* Enable Baseline Wander Correction */
7593 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7594 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7595 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7596 /* VGA output common mode */
7597 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7602 /* start adjust QMH serdes parameters */
7604 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7606 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7607 9, code << 9, 0x3f << 9);
7610 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7611 int enable, u32 tapenable)
7614 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7615 1, 3 << 10, 0x1f << 10);
7617 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7621 /* Set clock to 1, 0, 1, 0 */
7622 static void clock_man(struct qib_pportdata *ppd, int chan)
7624 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7626 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7628 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7630 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7635 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7636 * The caller must pass the settings appropriate for the current speed,
7637 * or not care if they are correct for the current speed.
7639 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7640 struct txdds_ent *txdds)
7644 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7645 /* field names for amp, main, post, pre, respectively */
7646 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7647 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7648 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7649 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7651 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7652 tx_override_deemphasis_select);
7653 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7654 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7656 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7657 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7659 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7660 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7662 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7663 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7665 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7669 * Set the parameters for mez cards on link bounce, so they are
7670 * always exactly what was requested. Similar logic to init_txdds
7671 * but does just the serdes.
7673 static void adj_tx_serdes(struct qib_pportdata *ppd)
7675 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7676 struct txdds_ent *dds;
7678 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7679 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7680 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7681 ddr_dds : sdr_dds));
7682 write_tx_serdes_param(ppd, dds);
7685 /* set QDR forced value for H1, if needed */
7686 static void force_h1(struct qib_pportdata *ppd)
7690 ppd->cpspec->qdr_reforce = 0;
7691 if (!ppd->dd->cspec->r1)
7694 for (chan = 0; chan < SERDES_CHANS; chan++) {
7695 set_man_mode_h1(ppd, chan, 1, 0);
7696 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7697 clock_man(ppd, chan);
7698 set_man_mode_h1(ppd, chan, 0, 0);
7702 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7703 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7705 #define R_OPCODE_LSB 3
7707 #define R_OP_SHIFT 2
7708 #define R_OP_UPDATE 3
7713 static int qib_r_grab(struct qib_devdata *dd)
7717 qib_write_kreg(dd, kr_r_access, val);
7718 qib_read_kreg32(dd, kr_scratch);
7722 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7723 * returns the current state of R_TDO
7725 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7729 for (timeout = 0; timeout < 100 ; ++timeout) {
7730 val = qib_read_kreg32(dd, kr_r_access);
7732 return (val >> R_TDO_LSB) & 1;
7737 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7738 int len, u8 *inp, u8 *outp)
7743 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7744 (R_OP_SHIFT << R_OPCODE_LSB);
7745 ret = qib_r_wait_for_rdy(dd);
7748 for (pos = 0; pos < len; ++pos) {
7751 outp[pos >> 3] &= ~(1 << (pos & 7));
7752 outp[pos >> 3] |= (ret << (pos & 7));
7755 int tdi = inp[pos >> 3] >> (pos & 7);
7756 val |= ((tdi & 1) << R_TDI_LSB);
7758 qib_write_kreg(dd, kr_r_access, val);
7759 qib_read_kreg32(dd, kr_scratch);
7760 ret = qib_r_wait_for_rdy(dd);
7764 /* Restore to NOP between operations. */
7765 val = SJA_EN | (bisten << BISTEN_LSB);
7766 qib_write_kreg(dd, kr_r_access, val);
7767 qib_read_kreg32(dd, kr_scratch);
7768 ret = qib_r_wait_for_rdy(dd);
7776 static int qib_r_update(struct qib_devdata *dd, int bisten)
7781 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7782 ret = qib_r_wait_for_rdy(dd);
7784 qib_write_kreg(dd, kr_r_access, val);
7785 qib_read_kreg32(dd, kr_scratch);
7790 #define BISTEN_PORT_SEL 15
7791 #define LEN_PORT_SEL 625
7792 #define BISTEN_AT 17
7794 #define BISTEN_ETM 16
7797 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7799 /* these are common for all IB port use cases. */
7800 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7801 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7804 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7807 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7808 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7809 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7810 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7811 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7812 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7814 static u8 at[BIT2BYTE(LEN_AT)] = {
7815 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7819 /* used for IB1 or IB2, only one in use */
7820 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7824 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7826 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7827 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7828 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7831 /* used when both IB1 and IB2 are in use */
7832 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7833 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7834 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7835 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7836 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7837 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7838 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7839 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7840 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7843 /* used when only IB1 is in use */
7844 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7845 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7846 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7847 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7848 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7849 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7850 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7851 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7852 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7855 /* used when only IB2 is in use */
7856 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7857 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7858 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7859 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7860 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7861 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7862 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7863 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7864 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7867 /* used when both IB1 and IB2 are in use */
7868 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7869 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7870 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7871 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7872 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7873 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7874 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7875 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7876 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7880 * Do setup to properly handle IB link recovery; if port is zero, we
7881 * are initializing to cover both ports; otherwise we are initializing
7882 * to cover a single port card, or the port has reached INIT and we may
7883 * need to switch coverage types.
7885 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7888 struct qib_devdata *dd = ppd->dd;
7890 if (!ppd->dd->cspec->r1)
7893 dd->cspec->recovery_ports_initted++;
7894 ppd->cpspec->recovery_init = 1;
7896 if (!both && dd->cspec->recovery_ports_initted == 1) {
7897 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7900 portsel = portsel_2port;
7904 if (qib_r_grab(dd) < 0 ||
7905 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7906 qib_r_update(dd, BISTEN_ETM) < 0 ||
7907 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7908 qib_r_update(dd, BISTEN_AT) < 0 ||
7909 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7910 portsel, NULL) < 0 ||
7911 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7912 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7913 qib_r_update(dd, BISTEN_AT) < 0 ||
7914 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7915 qib_r_update(dd, BISTEN_ETM) < 0)
7916 qib_dev_err(dd, "Failed IB link recovery setup\n");
7919 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7921 struct qib_devdata *dd = ppd->dd;
7924 if (dd->cspec->recovery_ports_initted != 1)
7925 return; /* rest doesn't apply to dualport */
7926 qib_write_kreg(dd, kr_control, dd->control |
7927 SYM_MASK(Control, FreezeMode));
7928 (void)qib_read_kreg64(dd, kr_scratch);
7929 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7930 fmask = qib_read_kreg64(dd, kr_act_fmask);
7933 * require a powercycle before we'll work again, and make
7934 * sure we get no more interrupts, and don't turn off
7937 ppd->dd->cspec->stay_in_freeze = 1;
7938 qib_7322_set_intr_state(ppd->dd, 0);
7939 qib_write_kreg(dd, kr_fmask, 0ULL);
7940 qib_dev_err(dd, "HCA unusable until powercycled\n");
7941 return; /* eventually reset */
7944 qib_write_kreg(ppd->dd, kr_hwerrclear,
7945 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7947 /* don't do the full clear_freeze(), not needed for this */
7948 qib_write_kreg(dd, kr_control, dd->control);
7949 qib_read_kreg32(dd, kr_scratch);
7950 /* take IBC out of reset */
7951 if (ppd->link_speed_supported) {
7952 ppd->cpspec->ibcctrl_a &=
7953 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7954 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7955 ppd->cpspec->ibcctrl_a);
7956 qib_read_kreg32(dd, kr_scratch);
7957 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7958 qib_set_ib_7322_lstate(ppd, 0,
7959 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);