4 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 * This header file is the base header file for qlogic_ib kernel code
39 * qib_user.h serves a similar purpose for user code.
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/mutex.h>
46 #include <linux/list.h>
47 #include <linux/scatterlist.h>
48 #include <linux/slab.h>
51 #include <linux/completion.h>
52 #include <linux/kref.h>
53 #include <linux/sched.h>
55 #include "qib_common.h"
56 #include "qib_verbs.h"
58 /* only s/w major version of QLogic_IB we can handle */
59 #define QIB_CHIP_VERS_MAJ 2U
61 /* don't care about this except printing */
62 #define QIB_CHIP_VERS_MIN 0U
64 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
65 #define QIB_OUI 0x001175
66 #define QIB_OUI_LSB 40
69 * per driver stats, either not device nor port-specific, or
70 * summed over all of the devices and ports.
71 * They are described by name via ipathfs filesystem, so layout
72 * and number of elements can change without breaking compatibility.
73 * If members are added or deleted qib_statnames[] in qib_fs.c must
76 struct qlogic_ib_stats {
77 __u64 sps_ints; /* number of interrupts handled */
78 __u64 sps_errints; /* number of error interrupts */
79 __u64 sps_txerrs; /* tx-related packet errors */
80 __u64 sps_rcverrs; /* non-crc rcv packet errors */
81 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
82 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
83 __u64 sps_ctxts; /* number of contexts currently open */
84 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
89 extern struct qlogic_ib_stats qib_stats;
90 extern struct pci_error_handlers qib_pci_err_handler;
91 extern struct pci_driver qib_driver;
93 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
95 * First-cut critierion for "device is active" is
96 * two thousand dwords combined Tx, Rx traffic per
97 * 5-second interval. SMA packets are 64 dwords,
98 * and occur "a few per second", presumably each way.
100 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
103 * Struct used to indicate which errors are logged in each of the
104 * error-counters that are logged to EEPROM. A counter is incremented
105 * _once_ (saturating at 255) for each event with any bits set in
106 * the error or hwerror register masks below.
108 #define QIB_EEP_LOG_CNT (4)
109 struct qib_eep_log_mask {
115 * Below contains all data related to a single context (formerly called port).
117 struct qib_ctxtdata {
119 dma_addr_t *rcvegrbuf_phys;
120 /* rcvhdrq base, needs mmap before useful */
122 /* kernel virtual address where hdrqtail is updated */
123 void *rcvhdrtail_kvaddr;
125 * temp buffer for expected send setup, allocated at open, instead
130 * Shared page for kernel to signal user processes that send buffers
131 * need disarming. The process should call QIB_CMD_DISARM_BUFS
132 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
134 unsigned long *user_event_mask;
135 /* when waiting for rcv or pioavail */
136 wait_queue_head_t wait;
138 * rcvegr bufs base, physical, must fit
139 * in 44 bits so 32 bit programs mmap64 44 bit works)
141 dma_addr_t rcvegr_phys;
142 /* mmap of hdrq, must fit in 44 bits */
143 dma_addr_t rcvhdrq_phys;
144 dma_addr_t rcvhdrqtailaddr_phys;
147 * number of opens (including slave sub-contexts) on this instance
148 * (ignoring forks, dup, etc. for now)
152 * how much space to leave at start of eager TID entries for
153 * protocol use, on each TID
155 /* instead of calculating it */
157 /* non-zero if ctxt is being shared. */
159 /* non-zero if ctxt is being shared. */
161 /* number of eager TID entries. */
163 /* index of first eager TID entry. */
165 /* number of pio bufs for this ctxt (all procs, if shared) */
167 /* first pio buffer for this ctxt */
169 /* chip offset of PIO buffers for this ctxt */
171 /* how many alloc_pages() chunks in rcvegrbuf_pages */
172 u32 rcvegrbuf_chunks;
173 /* how many egrbufs per chunk */
174 u16 rcvegrbufs_perchunk;
176 u16 rcvegrbufs_perchunk_shift;
177 /* order for rcvegrbuf_pages */
178 size_t rcvegrbuf_size;
179 /* rcvhdrq size (for freeing) */
181 /* per-context flags for fileops/intr communication */
183 /* next expected TID to check when looking for free */
185 /* WAIT_RCV that timed out, no interrupt */
187 /* WAIT_PIO that timed out, no interrupt */
189 /* WAIT_RCV already happened, no wait */
191 /* WAIT_PIO already happened, no wait */
193 /* total number of polled urgent packets */
195 /* saved total number of polled urgent packets for poll edge trigger */
197 /* pid of process using this ctxt */
199 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
200 /* same size as task_struct .comm[], command that opened context */
202 /* pkeys set by this use of this ctxt */
204 /* so file ops can get at unit */
205 struct qib_devdata *dd;
206 /* so funcs that need physical port can get it easily */
207 struct qib_pportdata *ppd;
208 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
209 void *subctxt_uregbase;
210 /* An array of pages for the eager receive buffers * N */
211 void *subctxt_rcvegrbuf;
212 /* An array of pages for the eager header queue entries * N */
213 void *subctxt_rcvhdr_base;
214 /* The version of the library which opened this ctxt */
216 /* Bitmask of active slaves */
218 /* Type of packets or conditions we want to poll for */
220 /* receive packet sequence counter */
223 /* ctxt rcvhdrq head offset */
226 /* QPs waiting for context processing */
227 struct list_head qp_wait_list;
230 struct qib_sge_state;
232 struct qib_sdma_txreq {
236 void (*callback)(struct qib_sdma_txreq *, int);
237 u16 start_idx; /* sdma private */
238 u16 next_descq_idx; /* sdma private */
239 struct list_head list; /* sdma private */
242 struct qib_sdma_desc {
246 struct qib_verbs_txreq {
247 struct qib_sdma_txreq txreq;
249 struct qib_swqe *wqe;
253 struct qib_pio_header *align_buf;
254 struct qib_mregion *mr;
255 struct qib_sge_state *ss;
258 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
259 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
260 #define QIB_SDMA_TXREQ_F_INTREQ 0x4
261 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8
262 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10
264 #define QIB_SDMA_TXREQ_S_OK 0
265 #define QIB_SDMA_TXREQ_S_SENDERROR 1
266 #define QIB_SDMA_TXREQ_S_ABORTED 2
267 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3
270 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
271 * Mostly for MADs that set or query link parameters, also ipath
274 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
275 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
276 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */
277 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
278 #define QIB_IB_CFG_SPD 5 /* current Link spd */
279 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
280 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
281 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
282 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
283 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
284 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
285 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
286 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
287 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
288 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
289 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */
290 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
291 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
292 #define QIB_IB_CFG_VL_HIGH_LIMIT 19
293 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
294 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
297 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
298 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
299 * QIB_IB_CFG_LINKDEFAULT cmd
301 #define IB_LINKCMD_DOWN (0 << 16)
302 #define IB_LINKCMD_ARMED (1 << 16)
303 #define IB_LINKCMD_ACTIVE (2 << 16)
304 #define IB_LINKINITCMD_NOP 0
305 #define IB_LINKINITCMD_POLL 1
306 #define IB_LINKINITCMD_SLEEP 2
307 #define IB_LINKINITCMD_DISABLE 3
310 * valid states passed to qib_set_linkstate() user call
312 #define QIB_IB_LINKDOWN 0
313 #define QIB_IB_LINKARM 1
314 #define QIB_IB_LINKACTIVE 2
315 #define QIB_IB_LINKDOWN_ONLY 3
316 #define QIB_IB_LINKDOWN_SLEEP 4
317 #define QIB_IB_LINKDOWN_DISABLE 5
320 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
321 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
322 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They
323 * are also the the possible values for qib_link_speed_enabled and active
324 * The values were chosen to match values used within the IB spec.
330 #define QIB_DEFAULT_MTU 4096
332 /* max number of IB ports supported per HCA */
333 #define QIB_MAX_IB_PORTS 2
336 * Possible IB config parameters for f_get/set_ib_table()
338 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
339 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
342 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
343 * these are bits so they can be combined, e.g.
344 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
346 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
347 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
348 #define QIB_RCVCTRL_CTXT_ENB 0x04
349 #define QIB_RCVCTRL_CTXT_DIS 0x08
350 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
351 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
352 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
353 #define QIB_RCVCTRL_PKEY_DIS 0x80
354 #define QIB_RCVCTRL_BP_ENB 0x0100
355 #define QIB_RCVCTRL_BP_DIS 0x0200
356 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
357 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
360 * Possible "operations" for f_sendctrl(ppd, op, var)
361 * these are bits so they can be combined, e.g.
362 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
363 * Some operations (e.g. DISARM, ABORT) are known to
364 * be "one-shot", so do not modify shadow.
366 #define QIB_SENDCTRL_DISARM (0x1000)
367 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
368 /* available (0x2000) */
369 #define QIB_SENDCTRL_AVAIL_DIS (0x4000)
370 #define QIB_SENDCTRL_AVAIL_ENB (0x8000)
371 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
372 #define QIB_SENDCTRL_SEND_DIS (0x20000)
373 #define QIB_SENDCTRL_SEND_ENB (0x40000)
374 #define QIB_SENDCTRL_FLUSH (0x80000)
375 #define QIB_SENDCTRL_CLEAR (0x100000)
376 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
379 * These are the generic indices for requesting per-port
380 * counter values via the f_portcntr function. They
381 * are always returned as 64 bit values, although most
382 * are 32 bit counters.
384 /* send-related counters */
385 #define QIBPORTCNTR_PKTSEND 0U
386 #define QIBPORTCNTR_WORDSEND 1U
387 #define QIBPORTCNTR_PSXMITDATA 2U
388 #define QIBPORTCNTR_PSXMITPKTS 3U
389 #define QIBPORTCNTR_PSXMITWAIT 4U
390 #define QIBPORTCNTR_SENDSTALL 5U
391 /* receive-related counters */
392 #define QIBPORTCNTR_PKTRCV 6U
393 #define QIBPORTCNTR_PSRCVDATA 7U
394 #define QIBPORTCNTR_PSRCVPKTS 8U
395 #define QIBPORTCNTR_RCVEBP 9U
396 #define QIBPORTCNTR_RCVOVFL 10U
397 #define QIBPORTCNTR_WORDRCV 11U
398 /* IB link related error counters */
399 #define QIBPORTCNTR_RXLOCALPHYERR 12U
400 #define QIBPORTCNTR_RXVLERR 13U
401 #define QIBPORTCNTR_ERRICRC 14U
402 #define QIBPORTCNTR_ERRVCRC 15U
403 #define QIBPORTCNTR_ERRLPCRC 16U
404 #define QIBPORTCNTR_BADFORMAT 17U
405 #define QIBPORTCNTR_ERR_RLEN 18U
406 #define QIBPORTCNTR_IBSYMBOLERR 19U
407 #define QIBPORTCNTR_INVALIDRLEN 20U
408 #define QIBPORTCNTR_UNSUPVL 21U
409 #define QIBPORTCNTR_EXCESSBUFOVFL 22U
410 #define QIBPORTCNTR_ERRLINK 23U
411 #define QIBPORTCNTR_IBLINKDOWN 24U
412 #define QIBPORTCNTR_IBLINKERRRECOV 25U
413 #define QIBPORTCNTR_LLI 26U
414 /* other error counters */
415 #define QIBPORTCNTR_RXDROPPKT 27U
416 #define QIBPORTCNTR_VL15PKTDROP 28U
417 #define QIBPORTCNTR_ERRPKEY 29U
418 #define QIBPORTCNTR_KHDROVFL 30U
419 /* sampling counters (these are actually control registers) */
420 #define QIBPORTCNTR_PSINTERVAL 31U
421 #define QIBPORTCNTR_PSSTART 32U
422 #define QIBPORTCNTR_PSSTAT 33U
424 /* how often we check for packet activity for "power on hours (in seconds) */
425 #define ACTIVITY_TIMER 5
427 /* Below is an opaque struct. Each chip (device) can maintain
428 * private data needed for its operation, but not germane to the
429 * rest of the driver. For convenience, we define another that
430 * is chip-specific, per-port
432 struct qib_chip_specific;
433 struct qib_chipport_specific;
435 enum qib_sdma_states {
436 qib_sdma_state_s00_hw_down,
437 qib_sdma_state_s10_hw_start_up_wait,
438 qib_sdma_state_s20_idle,
439 qib_sdma_state_s30_sw_clean_up_wait,
440 qib_sdma_state_s40_hw_clean_up_wait,
441 qib_sdma_state_s50_hw_halt_wait,
442 qib_sdma_state_s99_running,
445 enum qib_sdma_events {
446 qib_sdma_event_e00_go_hw_down,
447 qib_sdma_event_e10_go_hw_start,
448 qib_sdma_event_e20_hw_started,
449 qib_sdma_event_e30_go_running,
450 qib_sdma_event_e40_sw_cleaned,
451 qib_sdma_event_e50_hw_cleaned,
452 qib_sdma_event_e60_hw_halted,
453 qib_sdma_event_e70_go_idle,
454 qib_sdma_event_e7220_err_halted,
455 qib_sdma_event_e7322_err_halted,
456 qib_sdma_event_e90_timer_tick,
459 extern char *qib_sdma_state_names[];
460 extern char *qib_sdma_event_names[];
462 struct sdma_set_state_action {
463 unsigned op_enable:1;
464 unsigned op_intenable:1;
467 unsigned go_s99_running_tofalse:1;
468 unsigned go_s99_running_totrue:1;
471 struct qib_sdma_state {
473 struct completion comp;
474 enum qib_sdma_states current_state;
475 struct sdma_set_state_action *set_state_action;
477 unsigned go_s99_running;
478 unsigned first_sendbuf;
479 unsigned last_sendbuf; /* really last +1 */
480 /* debugging/devel */
481 enum qib_sdma_states previous_state;
482 unsigned previous_op;
483 enum qib_sdma_events last_event;
487 struct timer_list timer;
500 * The structure below encapsulates data relevant to a physical IB Port.
501 * Current chips support only one such port, but the separation
502 * clarifies things a bit. Note that to conform to IB conventions,
503 * port-numbers are one-based. The first or only port is port1.
505 struct qib_pportdata {
506 struct qib_ibport ibport_data;
508 struct qib_devdata *dd;
509 struct qib_chippport_specific *cpspec; /* chip-specific per-port */
510 struct kobject pport_kobj;
511 struct kobject sl2vl_kobj;
512 struct kobject diagc_kobj;
514 /* GUID for this interface, in network order */
517 /* QIB_POLL, etc. link-state specific flags, per port */
519 /* qib_lflags driver is waiting for */
521 spinlock_t lflags_lock;
522 /* number of (port-specific) interrupts for this port -- saturates... */
525 /* ref count for each pkey */
526 atomic_t pkeyrefs[4];
529 * this address is mapped readonly into user processes so they can
530 * get status cheaply, whenever they want. One qword of status per port
534 /* SendDMA related entries */
535 spinlock_t sdma_lock;
536 struct qib_sdma_state sdma_state;
537 unsigned long sdma_buf_jiffies;
538 struct qib_sdma_desc *sdma_descq;
539 u64 sdma_descq_added;
540 u64 sdma_descq_removed;
547 struct tasklet_struct sdma_sw_clean_up_task;
548 struct list_head sdma_activelist;
550 dma_addr_t sdma_descq_phys;
551 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
552 dma_addr_t sdma_head_phys;
554 wait_queue_head_t state_wait; /* for state_wanted */
556 /* HoL blocking for SMP replies */
558 struct timer_list hol_timer;
561 * Shadow copies of registers; size indicates read access size.
562 * Most of them are readonly, but some are write-only register,
563 * where we manipulate the bits in the shadow copy, and then write
564 * the shadow copy to qlogic_ib.
566 * We deliberately make most of these 32 bits, since they have
567 * restricted range. For any that we read, we won't to generate 32
568 * bit accesses, since Opteron will generate 2 separate 32 bit HT
569 * transactions for a 64 bit read, and we want to avoid unnecessary
573 /* This is the 64 bit group */
574 /* last ibcstatus. opaque outside chip-specific code */
577 /* these are the "32 bit" regs */
580 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
581 * all expect bit fields to be "unsigned long"
583 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
584 unsigned long p_sendctrl; /* shadow per-port sendctrl */
586 u32 ibmtu; /* The MTU programmed for this unit */
588 * Current max size IB packet (in bytes) including IB headers, that
589 * we can send. Changes when ibmtu changes.
593 * ibmaxlen at init time, limited by chip and by receive buffer
594 * size. Not changed after init.
597 /* LID programmed for this instance */
599 /* list of pkeys programmed; 0 if not set */
601 /* LID mask control */
603 u8 link_width_supported;
604 u8 link_speed_supported;
605 u8 link_width_enabled;
606 u8 link_speed_enabled;
607 u8 link_width_active;
608 u8 link_speed_active;
611 /* Rx Polarity inversion (compensate for ~tx on partner) */
614 u8 hw_pidx; /* physical port index */
615 u8 port; /* IB port number and index into dd->pports - 1 */
619 /* used to override LED behavior */
620 u8 led_override; /* Substituted for normal value, if non-zero */
621 u16 led_override_timeoff; /* delta to next timer event */
622 u8 led_override_vals[2]; /* Alternates per blink-frame */
623 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
624 atomic_t led_override_timer_active;
625 /* Used to flash LEDs in override mode */
626 struct timer_list led_override_timer;
627 struct xmit_wait cong_stats;
628 struct timer_list symerr_clear_timer;
631 /* Observers. Not to be taken lightly, possibly not to ship. */
633 * If a diag read or write is to (bottom <= offset <= top),
634 * the "hoook" is called, allowing, e.g. shadows to be
635 * updated in sync with the driver. struct diag_observer
636 * is the "visible" part.
638 struct diag_observer;
640 typedef int (*diag_hook) (struct qib_devdata *dd,
641 const struct diag_observer *op,
642 u32 offs, u64 *data, u64 mask, int only_32);
644 struct diag_observer {
650 extern int qib_register_observer(struct qib_devdata *dd,
651 const struct diag_observer *op);
653 /* Only declared here, not defined. Private to diags */
654 struct diag_observer_list_elt;
656 /* device data struct now contains only "general per-device" info.
657 * fields related to a physical IB port are in a qib_pportdata struct,
658 * described above) while fields only used by a particular chip-type are in
659 * a qib_chipdata struct, whose contents are opaque to this file.
662 struct qib_ibdev verbs_dev; /* must be first */
663 struct list_head list;
664 /* pointers to related structs for this device */
665 /* pci access data structure */
666 struct pci_dev *pcidev;
667 struct cdev *user_cdev;
668 struct cdev *diag_cdev;
669 struct device *user_device;
670 struct device *diag_device;
672 /* mem-mapped pointer to base of chip regs */
673 u64 __iomem *kregbase;
674 /* end of mem-mapped chip space excluding sendbuf and user regs */
675 u64 __iomem *kregend;
676 /* physical address of chip for io_remap, etc. */
677 resource_size_t physaddr;
678 /* qib_cfgctxts pointers */
679 struct qib_ctxtdata **rcd; /* Receive Context Data */
681 /* qib_pportdata, points to array of (physical) port-specific
682 * data structs, indexed by pidx (0..n-1)
684 struct qib_pportdata *pport;
685 struct qib_chip_specific *cspec; /* chip-specific */
687 /* kvirt address of 1st 2k pio buffer */
688 void __iomem *pio2kbase;
689 /* kvirt address of 1st 4k pio buffer */
690 void __iomem *pio4kbase;
691 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
692 void __iomem *piobase;
693 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */
694 u64 __iomem *userbase;
695 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
697 * points to area where PIOavail registers will be DMA'ed.
698 * Has to be on a page of it's own, because the page will be
699 * mapped into user program space. This copy is *ONLY* ever
700 * written by DMA, not by the driver! Need a copy per device
701 * when we get to multiple devices
703 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
704 /* physical address where updates occur */
705 dma_addr_t pioavailregs_phys;
707 /* device-specific implementations of functions needed by
708 * common code. Contrary to previous consensus, we can't
709 * really just point to a device-specific table, because we
710 * may need to "bend", e.g. *_f_put_tid
712 /* fallback to alternate interrupt type if possible */
713 int (*f_intr_fallback)(struct qib_devdata *);
714 /* hard reset chip */
715 int (*f_reset)(struct qib_devdata *);
716 void (*f_quiet_serdes)(struct qib_pportdata *);
717 int (*f_bringup_serdes)(struct qib_pportdata *);
718 int (*f_early_init)(struct qib_devdata *);
719 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
720 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
722 void (*f_cleanup)(struct qib_devdata *);
723 void (*f_setextled)(struct qib_pportdata *, u32);
724 /* fill out chip-specific fields */
725 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
727 void (*f_free_irq)(struct qib_devdata *);
728 struct qib_message_header *(*f_get_msgheader)
729 (struct qib_devdata *, __le32 *);
730 void (*f_config_ctxts)(struct qib_devdata *);
731 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
732 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
733 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
734 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
735 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
736 u32 (*f_iblink_state)(u64);
737 u8 (*f_ibphys_portstate)(u64);
738 void (*f_xgxs_reset)(struct qib_pportdata *);
739 /* per chip actions needed for IB Link up/down changes */
740 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
741 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
742 /* Read/modify/write of GPIO pins (potentially chip-specific */
743 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
745 /* Enable writes to config EEPROM (if supported) */
746 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
748 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
749 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
750 * (ctxt == -1) means "all contexts", only meaningful for
751 * clearing. Could remove if chip_spec shutdown properly done.
753 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
755 /* Read/modify/write sendctrl appropriately for op and port. */
756 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
757 void (*f_set_intr_state)(struct qib_devdata *, u32);
758 void (*f_set_armlaunch)(struct qib_devdata *, u32);
759 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
760 int (*f_late_initreg)(struct qib_devdata *);
761 int (*f_init_sdma_regs)(struct qib_pportdata *);
762 u16 (*f_sdma_gethead)(struct qib_pportdata *);
763 int (*f_sdma_busy)(struct qib_pportdata *);
764 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
765 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
766 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
767 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
768 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
769 void (*f_sdma_init_early)(struct qib_pportdata *);
770 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
771 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
772 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
773 u64 (*f_portcntr)(struct qib_pportdata *, u32);
774 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
776 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
778 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
779 void (*f_initvl15_bufs)(struct qib_devdata *);
780 void (*f_init_ctxt)(struct qib_ctxtdata *);
781 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
782 struct qib_ctxtdata *);
783 void (*f_writescratch)(struct qib_devdata *, u32);
784 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
786 char *boardname; /* human readable board info */
788 /* template for writing TIDs */
790 /* value to write to free TIDs */
793 /* number of registers used for pioavail */
795 /* device (not port) flags, basically device capabilities */
797 /* last buffer for user use */
800 /* saturating counter of (non-port-specific) device interrupts */
803 /* pio bufs allocated per ctxt */
805 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
808 * number of ctxts configured as max; zero is set to number chip
809 * supports, less gives more pio bufs/ctxt, etc.
813 * number of ctxts available for PSM open
818 * hint that we should update pioavailshadow before
819 * looking for a PIO buffer
823 /* internal debugging stats */
828 /* PCI Vendor ID (here for NodeInfo) */
830 /* PCI Device ID (here for NodeInfo) */
832 /* for write combining settings */
833 unsigned long wc_cookie;
834 unsigned long wc_base;
835 unsigned long wc_len;
837 /* shadow copy of struct page *'s for exp tid pages */
838 struct page **pageshadow;
839 /* shadow copy of dma handles for exp tid pages */
840 dma_addr_t *physshadow;
841 u64 __iomem *egrtidbase;
842 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
843 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
844 spinlock_t uctxt_lock; /* rcd and user context changes */
846 * per unit status, see also portdata statusp
847 * mapped readonly into user processes so they can get unit and
848 * IB link status cheaply
851 char *freezemsg; /* freeze msg if hw error put chip in freeze */
852 u32 freezelen; /* max length of freezemsg */
853 /* timer used to prevent stats overflow, error throttling, etc. */
854 struct timer_list stats_timer;
856 /* timer to verify interrupts work, and fallback if possible */
857 struct timer_list intrchk_timer;
858 unsigned long ureg_align; /* user register alignment */
861 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
864 spinlock_t pioavail_lock;
867 * Shadow copies of registers; size indicates read access size.
868 * Most of them are readonly, but some are write-only register,
869 * where we manipulate the bits in the shadow copy, and then write
870 * the shadow copy to qlogic_ib.
872 * We deliberately make most of these 32 bits, since they have
873 * restricted range. For any that we read, we won't to generate 32
874 * bit accesses, since Opteron will generate 2 separate 32 bit HT
875 * transactions for a 64 bit read, and we want to avoid unnecessary
879 /* This is the 64 bit group */
881 unsigned long pioavailshadow[6];
882 /* bitmap of send buffers available for the kernel to use with PIO. */
883 unsigned long pioavailkernel[6];
884 /* bitmap of send buffers which need to be disarmed. */
885 unsigned long pio_need_disarm[3];
886 /* bitmap of send buffers which are being written to. */
887 unsigned long pio_writing[3];
888 /* kr_revision shadow */
890 /* Base GUID for device (from eeprom, network order) */
894 * kr_sendpiobufbase value (chip offset of pio buffers), and the
895 * base of the 2KB buffer s(user processes only use 2K)
900 /* these are the "32 bit" regs */
902 /* number of GUIDs in the flash for this interface */
905 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
906 * all expect bit fields to be "unsigned long"
908 unsigned long rcvctrl; /* shadow per device rcvctrl */
909 unsigned long sendctrl; /* shadow per device sendctrl */
911 /* value we put in kr_rcvhdrcnt */
913 /* value we put in kr_rcvhdrsize */
915 /* value we put in kr_rcvhdrentsize */
917 /* kr_ctxtcnt value */
919 /* kr_pagealign value */
921 /* number of "2KB" PIO buffers */
923 /* size in bytes of "2KB" PIO buffers */
925 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
926 u32 piosize2kmax_dwords;
927 /* number of "4KB" PIO buffers */
929 /* size in bytes of "4KB" PIO buffers */
931 /* kr_rcvegrbase value */
933 /* kr_rcvtidbase value */
935 /* kr_rcvtidcnt value */
939 /* shadow the control register contents */
942 /* chip address space used by 4k pio buffers */
944 /* size of each rcvegrbuffer */
947 u16 rcvegrbufsize_shift;
948 /* localbus width (1, 2,4,8,16,32) from config space */
950 /* localbus speed in MHz */
952 int unit; /* unit # of this chip */
954 /* start of CHIP_SPEC move to chipspec, but need code changes */
955 /* low and high portions of MSI capability/vector */
957 /* saved after PCIe init for restore after reset */
959 /* MSI data (vector) saved for restore */
961 /* so we can rewrite it after a chip reset */
963 /* so we can rewrite it after a chip reset */
965 u64 rhdrhead_intr_off;
968 * ASCII serial number, from flash, large enough for original
969 * all digit strings, and longer QLogic serial number format
972 /* human readable board version */
974 u8 lbus_info[32]; /* human readable localbus info */
975 /* chip major rev, from qib_revision */
977 /* chip minor rev, from qib_revision */
980 /* Misc small ints */
981 /* Number of physical ports available */
983 /* Lowest context number which can be used by user processes */
989 u16 rhf_offset; /* offset of RHF within receive header entry */
992 * GPIO pins for twsi-connected devices, and device code for eeprom
999 /* Support (including locks) for EEPROM logging of errors and time */
1000 /* control access to actual counters, timer */
1001 spinlock_t eep_st_lock;
1002 /* control high-level access to EEPROM */
1003 struct mutex eep_lock;
1004 uint64_t traffic_wds;
1005 /* active time is kept in seconds, but logged in hours */
1006 atomic_t active_time;
1007 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
1008 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
1009 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
1012 * masks for which bits of errs, hwerrs that cause
1013 * each of the counters to increment.
1015 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1016 struct qib_diag_client *diag_client;
1017 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1018 struct diag_observer_list_elt *diag_observer_list;
1020 u8 psxmitwait_supported;
1021 /* cycle length of PS* counters in HW (in picoseconds) */
1022 u16 psxmitwait_check_rate;
1023 /* high volume overflow errors defered to tasklet */
1024 struct tasklet_struct error_tasklet;
1027 /* hol_state values */
1028 #define QIB_HOL_UP 0
1029 #define QIB_HOL_INIT 1
1031 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1032 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1033 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1034 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1035 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1037 /* operation types for f_txchk_change() */
1038 #define TXCHK_CHG_TYPE_DIS1 3
1039 #define TXCHK_CHG_TYPE_ENAB1 2
1040 #define TXCHK_CHG_TYPE_KERN 1
1041 #define TXCHK_CHG_TYPE_USER 0
1043 #define QIB_CHASE_TIME msecs_to_jiffies(145)
1044 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1046 /* Private data for file operations */
1047 struct qib_filedata {
1048 struct qib_ctxtdata *rcd;
1051 struct qib_user_sdma_queue *pq;
1052 int rec_cpu_num; /* for cpu affinity; -1 if none */
1055 extern struct list_head qib_dev_list;
1056 extern spinlock_t qib_devs_lock;
1057 extern struct qib_devdata *qib_lookup(int unit);
1058 extern u32 qib_cpulist_count;
1059 extern unsigned long *qib_cpulist;
1061 extern unsigned qib_wc_pat;
1062 int qib_init(struct qib_devdata *, int);
1063 int init_chip_wc_pat(struct qib_devdata *dd, u32);
1064 int qib_enable_wc(struct qib_devdata *dd);
1065 void qib_disable_wc(struct qib_devdata *dd);
1066 int qib_count_units(int *npresentp, int *nupp);
1067 int qib_count_active_units(void);
1069 int qib_cdev_init(int minor, const char *name,
1070 const struct file_operations *fops,
1071 struct cdev **cdevp, struct device **devp);
1072 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1073 int qib_dev_init(void);
1074 void qib_dev_cleanup(void);
1076 int qib_diag_add(struct qib_devdata *);
1077 void qib_diag_remove(struct qib_devdata *);
1078 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1079 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1081 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1082 void qib_bad_intrstatus(struct qib_devdata *);
1083 void qib_handle_urcv(struct qib_devdata *, u64);
1085 /* clean up any per-chip chip-specific stuff */
1086 void qib_chip_cleanup(struct qib_devdata *);
1087 /* clean up any chip type-specific stuff */
1088 void qib_chip_done(void);
1090 /* check to see if we have to force ordering for write combining */
1091 int qib_unordered_wc(void);
1092 void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1094 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1095 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1096 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1097 void qib_cancel_sends(struct qib_pportdata *);
1099 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1100 int qib_setup_eagerbufs(struct qib_ctxtdata *);
1101 void qib_set_ctxtcnt(struct qib_devdata *);
1102 int qib_create_ctxts(struct qib_devdata *dd);
1103 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32);
1104 void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1105 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1107 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1108 int qib_reset_device(int);
1109 int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1110 int qib_set_linkstate(struct qib_pportdata *, u8);
1111 int qib_set_mtu(struct qib_pportdata *, u16);
1112 int qib_set_lid(struct qib_pportdata *, u32, u8);
1113 void qib_hol_down(struct qib_pportdata *);
1114 void qib_hol_init(struct qib_pportdata *);
1115 void qib_hol_up(struct qib_pportdata *);
1116 void qib_hol_event(unsigned long);
1117 void qib_disable_after_error(struct qib_devdata *);
1118 int qib_set_uevent_bits(struct qib_pportdata *, const int);
1120 /* for use in system calls, where we want to know device type, etc. */
1121 #define ctxt_fp(fp) \
1122 (((struct qib_filedata *)(fp)->private_data)->rcd)
1123 #define subctxt_fp(fp) \
1124 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1125 #define tidcursor_fp(fp) \
1126 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1127 #define user_sdma_queue_fp(fp) \
1128 (((struct qib_filedata *)(fp)->private_data)->pq)
1130 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1135 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1137 return container_of(dev, struct qib_devdata, verbs_dev);
1140 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1142 return dd_from_dev(to_idev(ibdev));
1145 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1147 return container_of(ibp, struct qib_pportdata, ibport_data);
1150 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1152 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1153 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1155 WARN_ON(pidx >= dd->num_pports);
1156 return &dd->pport[pidx].ibport_data;
1160 * values for dd->flags (_device_ related flags) and
1162 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1163 #define QIB_INITTED 0x2 /* chip and driver up and initted */
1164 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1165 #define QIB_PRESENT 0x8 /* chip accesses can be done */
1166 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1167 #define QIB_HAS_THRESH_UPDATE 0x40
1168 #define QIB_HAS_SDMA_TIMEOUT 0x80
1169 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1170 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1171 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1172 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1173 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1174 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1175 #define QIB_BADINTR 0x8000 /* severe interrupt problems */
1176 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1177 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1180 * values for ppd->lflags (_ib_port_ related flags)
1182 #define QIBL_LINKV 0x1 /* IB link state valid */
1183 #define QIBL_LINKDOWN 0x8 /* IB link is down */
1184 #define QIBL_LINKINIT 0x10 /* IB link level is up */
1185 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1186 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1187 /* leave a gap for more IB-link state */
1188 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1189 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1190 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1191 * Do not try to bring up */
1192 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1194 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1195 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1198 /* ctxt_flag bit offsets */
1199 /* waiting for a packet to arrive */
1200 #define QIB_CTXT_WAITING_RCV 2
1201 /* master has not finished initializing */
1202 #define QIB_CTXT_MASTER_UNINIT 4
1203 /* waiting for an urgent packet to arrive */
1204 #define QIB_CTXT_WAITING_URG 5
1206 /* free up any allocated data at closes */
1207 void qib_free_data(struct qib_ctxtdata *dd);
1208 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1209 u32, struct qib_ctxtdata *);
1210 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1211 const struct pci_device_id *);
1212 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1213 const struct pci_device_id *);
1214 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1215 const struct pci_device_id *);
1216 void qib_free_devdata(struct qib_devdata *);
1217 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1219 #define QIB_TWSI_NO_DEV 0xFF
1220 /* Below qib_twsi_ functions must be called with eep_lock held */
1221 int qib_twsi_reset(struct qib_devdata *dd);
1222 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1224 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1225 const void *buffer, int len);
1226 void qib_get_eeprom_info(struct qib_devdata *);
1227 int qib_update_eeprom_log(struct qib_devdata *dd);
1228 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1229 void qib_dump_lookup_output_queue(struct qib_devdata *);
1230 void qib_force_pio_avail_update(struct qib_devdata *);
1231 void qib_clear_symerror_on_linkup(unsigned long opaque);
1234 * Set LED override, only the two LSBs have "public" meaning, but
1235 * any non-zero value substitutes them for the Link and LinkTrain
1238 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1239 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */
1240 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1242 /* send dma routines */
1243 int qib_setup_sdma(struct qib_pportdata *);
1244 void qib_teardown_sdma(struct qib_pportdata *);
1245 void __qib_sdma_intr(struct qib_pportdata *);
1246 void qib_sdma_intr(struct qib_pportdata *);
1247 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1248 u32, struct qib_verbs_txreq *);
1249 /* ppd->sdma_lock should be locked before calling this. */
1250 int qib_sdma_make_progress(struct qib_pportdata *dd);
1252 /* must be called under qib_sdma_lock */
1253 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1255 return ppd->sdma_descq_cnt -
1256 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1259 static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1261 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1263 int qib_sdma_running(struct qib_pportdata *);
1265 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1266 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1269 * number of words used for protocol header if not set by qib_userinit();
1271 #define QIB_DFLT_RCVHDRSIZE 9
1274 * We need to be able to handle an IB header of at least 24 dwords.
1275 * We need the rcvhdrq large enough to handle largest IB header, but
1276 * still have room for a 2KB MTU standard IB packet.
1277 * Additionally, some processor/memory controller combinations
1278 * benefit quite strongly from having the DMA'ed data be cacheline
1279 * aligned and a cacheline multiple, so we set the size to 32 dwords
1280 * (2 64-byte primary cachelines for pretty much all processors of
1281 * interest). The alignment hurts nothing, other than using somewhat
1284 #define QIB_RCVHDR_ENTSIZE 32
1286 int qib_get_user_pages(unsigned long, size_t, struct page **);
1287 void qib_release_user_pages(struct page **, size_t);
1288 int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1289 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1290 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1291 void qib_sendbuf_done(struct qib_devdata *, unsigned);
1293 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1295 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1298 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1301 * volatile because it's a DMA target from the chip, routine is
1302 * inlined, and don't want register caching or reordering.
1304 return (u32) le64_to_cpu(
1305 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1308 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1310 const struct qib_devdata *dd = rcd->dd;
1313 if (dd->flags & QIB_NODMA_RTAIL) {
1317 rhf_addr = (__le32 *) rcd->rcvhdrq +
1318 rcd->head + dd->rhf_offset;
1319 seq = qib_hdrget_seq(rhf_addr);
1320 hdrqtail = rcd->head;
1321 if (seq == rcd->seq_cnt)
1324 hdrqtail = qib_get_rcvhdrtail(rcd);
1333 extern const char ib_qib_version[];
1335 int qib_device_create(struct qib_devdata *);
1336 void qib_device_remove(struct qib_devdata *);
1338 int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1339 struct kobject *kobj);
1340 int qib_verbs_register_sysfs(struct qib_devdata *);
1341 void qib_verbs_unregister_sysfs(struct qib_devdata *);
1342 /* Hook for sysfs read of QSFP */
1343 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1345 int __init qib_init_qibfs(void);
1346 int __exit qib_exit_qibfs(void);
1348 int qibfs_add(struct qib_devdata *);
1349 int qibfs_remove(struct qib_devdata *);
1351 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1352 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1353 const struct pci_device_id *);
1354 void qib_pcie_ddcleanup(struct qib_devdata *);
1355 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct msix_entry *);
1356 int qib_reinit_intr(struct qib_devdata *);
1357 void qib_enable_intx(struct pci_dev *);
1358 void qib_nomsi(struct qib_devdata *);
1359 void qib_nomsix(struct qib_devdata *);
1360 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1361 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1364 * dma_addr wrappers - all 0's invalid for hw
1366 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1368 const char *qib_get_unit_name(int unit);
1371 * Flush write combining store buffers (if present) and perform a write
1374 #if defined(CONFIG_X86_64)
1375 #define qib_flush_wc() asm volatile("sfence" : : : "memory")
1377 #define qib_flush_wc() wmb() /* no reorder around wc flush */
1380 /* global module parameter variables */
1381 extern unsigned qib_ibmtu;
1382 extern ushort qib_cfgctxts;
1383 extern ushort qib_num_cfg_vls;
1384 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1385 extern unsigned qib_n_krcv_queues;
1386 extern unsigned qib_sdma_fetch_arb;
1387 extern unsigned qib_compat_ddr_negotiate;
1388 extern int qib_special_trigger;
1390 extern struct mutex qib_mutex;
1392 /* Number of seconds before our card status check... */
1393 #define STATUS_TIMEOUT 60
1395 #define QIB_DRV_NAME "ib_qib"
1396 #define QIB_USER_MINOR_BASE 0
1397 #define QIB_TRACE_MINOR 127
1398 #define QIB_DIAGPKT_MINOR 128
1399 #define QIB_DIAG_MINOR_BASE 129
1400 #define QIB_NMINORS 255
1402 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1403 #define PCI_VENDOR_ID_QLOGIC 0x1077
1404 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1405 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1406 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1409 * qib_early_err is used (only!) to print early errors before devdata is
1410 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1411 * cleanup when devdata may have been freed, etc. qib_dev_porterr is
1412 * the same as qib_dev_err, but is used when the message really needs
1413 * the IB port# to be definitive as to what's happening..
1414 * All of these go to the trace log, and the trace log entry is done
1415 * first to avoid possible serial port delays from printk.
1417 #define qib_early_err(dev, fmt, ...) \
1419 dev_err(dev, fmt, ##__VA_ARGS__); \
1422 #define qib_dev_err(dd, fmt, ...) \
1424 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1425 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1428 #define qib_dev_porterr(dd, port, fmt, ...) \
1430 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1431 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1435 #define qib_devinfo(pcidev, fmt, ...) \
1437 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1441 * this is used for formatting hw error messages...
1443 struct qib_hwerror_msgs {
1449 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1451 /* in qib_intr.c... */
1452 void qib_format_hwerrors(u64 hwerrs,
1453 const struct qib_hwerror_msgs *hwerrmsgs,
1454 size_t nhwerrmsgs, char *msg, size_t lmsg);
1455 #endif /* _QIB_KERNEL_H */