arch/arm/mach-s3c24xx/mach-rx3715.c

   1 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
   2  *
   3  * Copyright (c) 2003-2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.handhelds.org/projects/rx3715.html
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18 #include <linux/memblock.h>
  19 #include <linux/timer.h>
  20 #include <linux/init.h>
  21 #include <linux/tty.h>
  22 #include <linux/console.h>
  23 #include <linux/device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/serial_s3c.h>
  27 #include <linux/serial.h>
  28 #include <linux/io.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/nand_ecc.h>
  32 #include <linux/mtd/partitions.h>
  33
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/map.h>
  37
  38 #include <linux/platform_data/mtd-nand-s3c2410.h>
  39
  40 #include <asm/irq.h>
  41 #include <asm/mach-types.h>
  42
  43 #include <mach/fb.h>
  44 #include <mach/hardware.h>
  45 #include <mach/regs-gpio.h>
  46 #include <mach/regs-lcd.h>
  47 #include <mach/gpio-samsung.h>
  48
  49 #include <plat/clock.h>
  50 #include <plat/cpu.h>
  51 #include <plat/devs.h>
  52 #include <plat/pm.h>
  53 #include <plat/samsung-time.h>
  54
  55 #include "common.h"
  56 #include "h1940.h"
  57
  58 static struct map_desc rx3715_iodesc[] __initdata = {
  59         /* dump ISA space somewhere unused */
  60
  61         {
  62                 .virtual        = (u32)S3C24XX_VA_ISA_WORD,
  63                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  64                 .length         = SZ_1M,
  65                 .type           = MT_DEVICE,
  66         }, {
  67                 .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
  68                 .pfn            = __phys_to_pfn(S3C2410_CS3),
  69                 .length         = SZ_1M,
  70                 .type           = MT_DEVICE,
  71         },
  72 };
  73
  74 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
  75         [0] = {
  76                 .hwport      = 0,
  77                 .flags       = 0,
  78                 .ucon        = 0x3c5,
  79                 .ulcon       = 0x03,
  80                 .ufcon       = 0x51,
  81                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  82         },
  83         [1] = {
  84                 .hwport      = 1,
  85                 .flags       = 0,
  86                 .ucon        = 0x3c5,
  87                 .ulcon       = 0x03,
  88                 .ufcon       = 0x00,
  89                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  90         },
  91         /* IR port */
  92         [2] = {
  93                 .hwport      = 2,
  94                 .uart_flags  = UPF_CONS_FLOW,
  95                 .ucon        = 0x3c5,
  96                 .ulcon       = 0x43,
  97                 .ufcon       = 0x51,
  98                 .clk_sel        = S3C2410_UCON_CLKSEL3,
  99         }
 100 };
 101
 102 /* framebuffer lcd controller information */
 103
 104 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
 105         .lcdcon5 =      S3C2410_LCDCON5_INVVLINE |
 106                         S3C2410_LCDCON5_FRM565 |
 107                         S3C2410_LCDCON5_HWSWP,
 108
 109         .type           = S3C2410_LCDCON1_TFT,
 110         .width          = 240,
 111         .height         = 320,
 112
 113         .pixclock       = 260000,
 114         .xres           = 240,
 115         .yres           = 320,
 116         .bpp            = 16,
 117         .left_margin    = 36,
 118         .right_margin   = 36,
 119         .hsync_len      = 8,
 120         .upper_margin   = 6,
 121         .lower_margin   = 7,
 122         .vsync_len      = 3,
 123 };
 124
 125 static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
 126
 127         .displays =     &rx3715_lcdcfg,
 128         .num_displays = 1,
 129         .default_display = 0,
 130
 131         .lpcsel =       0xf82,
 132
 133         .gpccon =       0xaa955699,
 134         .gpccon_mask =  0xffc003cc,
 135         .gpcup =        0x0000ffff,
 136         .gpcup_mask =   0xffffffff,
 137
 138         .gpdcon =       0xaa95aaa1,
 139         .gpdcon_mask =  0xffc0fff0,
 140         .gpdup =        0x0000faff,
 141         .gpdup_mask =   0xffffffff,
 142 };
 143
 144 static struct mtd_partition __initdata rx3715_nand_part[] = {
 145         [0] = {
 146                 .name           = "Whole Flash",
 147                 .offset         = 0,
 148                 .size           = MTDPART_SIZ_FULL,
 149                 .mask_flags     = MTD_WRITEABLE,
 150         }
 151 };
 152
 153 static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
 154         [0] = {
 155                 .name           = "Internal",
 156                 .nr_chips       = 1,
 157                 .nr_partitions  = ARRAY_SIZE(rx3715_nand_part),
 158                 .partitions     = rx3715_nand_part,
 159         },
 160 };
 161
 162 static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
 163         .tacls          = 25,
 164         .twrph0         = 50,
 165         .twrph1         = 15,
 166         .nr_sets        = ARRAY_SIZE(rx3715_nand_sets),
 167         .sets           = rx3715_nand_sets,
 168 };
 169
 170 static struct platform_device *rx3715_devices[] __initdata = {
 171         &s3c_device_ohci,
 172         &s3c_device_lcd,
 173         &s3c_device_wdt,
 174         &s3c_device_i2c0,
 175         &s3c_device_iis,
 176         &s3c_device_nand,
 177 };
 178
 179 static void __init rx3715_map_io(void)
 180 {
 181         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
 182         s3c24xx_init_clocks(16934000);
 183         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
 184         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 185 }
 186
 187 /* H1940 and RX3715 need to reserve this for suspend */
 188 static void __init rx3715_reserve(void)
 189 {
 190         memblock_reserve(0x30003000, 0x1000);
 191         memblock_reserve(0x30081000, 0x1000);
 192 }
 193
 194 static void __init rx3715_init_machine(void)
 195 {
 196 #ifdef CONFIG_PM_H1940
 197         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 198 #endif
 199         s3c_pm_init();
 200
 201         s3c_nand_set_platdata(&rx3715_nand_info);
 202         s3c24xx_fb_set_platdata(&rx3715_fb_info);
 203         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 204 }
 205
 206 MACHINE_START(RX3715, "IPAQ-RX3715")
 207         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
 208         .atag_offset    = 0x100,
 209         .map_io         = rx3715_map_io,
 210         .reserve        = rx3715_reserve,
 211         .init_irq       = s3c2440_init_irq,
 212         .init_machine   = rx3715_init_machine,
 213         .init_time      = samsung_timer_init,
 214         .restart        = s3c244x_restart,
 215 MACHINE_END