2 * Copyright (c) 2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
5 * S3C2410,S3C2440,S3C2442 Clock control support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/errno.h>
27 #include <linux/err.h>
28 #include <linux/device.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial_s3c.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
39 #include <mach/regs-clock.h>
40 #include <mach/regs-gpio.h>
42 #include <plat/clock.h>
45 int s3c2410_clkcon_enable(struct clk *clk, int enable)
47 unsigned int clocks = clk->ctrlbit;
50 clkcon = __raw_readl(S3C2410_CLKCON);
57 /* ensure none of the special function bits set */
58 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
60 __raw_writel(clkcon, S3C2410_CLKCON);
65 static int s3c2410_upll_enable(struct clk *clk, int enable)
67 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
68 unsigned long orig = clkslow;
71 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
73 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
75 __raw_writel(clkslow, S3C2410_CLKSLOW);
77 /* if we started the UPLL, then allow to settle */
79 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
85 /* standard clock definitions */
87 static struct clk init_clocks_off[] = {
91 .enable = s3c2410_clkcon_enable,
92 .ctrlbit = S3C2410_CLKCON_NAND,
96 .enable = s3c2410_clkcon_enable,
97 .ctrlbit = S3C2410_CLKCON_SDI,
101 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_ADC,
106 .enable = s3c2410_clkcon_enable,
107 .ctrlbit = S3C2410_CLKCON_IIC,
111 .enable = s3c2410_clkcon_enable,
112 .ctrlbit = S3C2410_CLKCON_IIS,
116 .enable = s3c2410_clkcon_enable,
117 .ctrlbit = S3C2410_CLKCON_SPI,
121 static struct clk clk_lcd = {
124 .enable = s3c2410_clkcon_enable,
125 .ctrlbit = S3C2410_CLKCON_LCDC,
128 static struct clk clk_gpio = {
131 .enable = s3c2410_clkcon_enable,
132 .ctrlbit = S3C2410_CLKCON_GPIO,
135 static struct clk clk_usb_host = {
138 .enable = s3c2410_clkcon_enable,
139 .ctrlbit = S3C2410_CLKCON_USBH,
142 static struct clk clk_usb_device = {
143 .name = "usb-device",
145 .enable = s3c2410_clkcon_enable,
146 .ctrlbit = S3C2410_CLKCON_USBD,
149 static struct clk clk_timers = {
152 .enable = s3c2410_clkcon_enable,
153 .ctrlbit = S3C2410_CLKCON_PWMT,
156 struct clk s3c24xx_clk_uart0 = {
158 .devname = "s3c2410-uart.0",
160 .enable = s3c2410_clkcon_enable,
161 .ctrlbit = S3C2410_CLKCON_UART0,
164 struct clk s3c24xx_clk_uart1 = {
166 .devname = "s3c2410-uart.1",
168 .enable = s3c2410_clkcon_enable,
169 .ctrlbit = S3C2410_CLKCON_UART1,
172 struct clk s3c24xx_clk_uart2 = {
174 .devname = "s3c2410-uart.2",
176 .enable = s3c2410_clkcon_enable,
177 .ctrlbit = S3C2410_CLKCON_UART2,
180 static struct clk clk_rtc = {
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
187 static struct clk clk_watchdog = {
193 static struct clk clk_usb_bus_host = {
194 .name = "usb-bus-host",
195 .parent = &clk_usb_bus,
198 static struct clk clk_usb_bus_gadget = {
199 .name = "usb-bus-gadget",
200 .parent = &clk_usb_bus,
203 static struct clk *init_clocks[] = {
218 /* s3c2410_baseclk_add()
220 * Add all the clocks used by the s3c2410 or compatible CPUs
221 * such as the S3C2440 and S3C2442.
223 * We cannot use a system device as we are needed before any
224 * of the init-calls that initialise the devices are actually
228 int __init s3c2410_baseclk_add(void)
230 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
231 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
236 clk_upll.enable = s3c2410_upll_enable;
238 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
239 printk(KERN_ERR "failed to register usb bus clock\n");
241 /* register clocks from clock array */
243 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
244 struct clk *clkp = init_clocks[ptr];
246 /* ensure that we note the clock state */
248 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
250 ret = s3c24xx_register_clock(clkp);
252 printk(KERN_ERR "Failed to register clock %s (%d)\n",
257 /* We must be careful disabling the clocks we are not intending to
258 * be using at boot time, as subsystems such as the LCD which do
259 * their own DMA requests to the bus can cause the system to lockup
260 * if they where in the middle of requesting bus access.
262 * Disabling the LCD clock if the LCD is active is very dangerous,
263 * and therefore the bootloader should be careful to not enable
264 * the LCD clock if it is not needed.
267 /* install (and disable) the clocks we do not need immediately */
269 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
270 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
272 /* show the clock-slow value */
274 xtal = clk_get(NULL, "xtal");
276 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
277 print_mhz(clk_get_rate(xtal) /
278 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
279 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
280 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
281 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");