arch/arm/mach-exynos/cpuidle.c

   1 /* linux/arch/arm/mach-exynos4/cpuidle.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/cpu_pm.h>
  15 #include <linux/io.h>
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/time.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <asm/proc-fns.h>
  22 #include <asm/smp_scu.h>
  23 #include <asm/suspend.h>
  24 #include <asm/unified.h>
  25 #include <asm/cpuidle.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29
  30 #include <mach/map.h>
  31
  32 #include "common.h"
  33 #include "regs-pmu.h"
  34
  35 #define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
  36                         S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
  37                         (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
  38 #define REG_DIRECTGO_FLAG       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
  39                         S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
  40                         (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
  41
  42 #define S5P_CHECK_AFTR          0xFCBA0D10
  43
  44 #define EXYNOS5_PWR_CTRL1                       (S5P_VA_CMU + 0x01020)
  45 #define EXYNOS5_PWR_CTRL2                       (S5P_VA_CMU + 0x01024)
  46
  47 #define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
  48 #define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
  49 #define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
  50 #define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
  51 #define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
  52 #define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
  53 #define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
  54 #define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
  55
  56 #define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
  57 #define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
  58 #define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
  59 #define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
  60 #define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
  61 #define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
  62
  63 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
  64                                 struct cpuidle_driver *drv,
  65                                 int index);
  66
  67 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
  68
  69 static struct cpuidle_driver exynos4_idle_driver = {
  70         .name                   = "exynos4_idle",
  71         .owner                  = THIS_MODULE,
  72         .states = {
  73                 [0] = ARM_CPUIDLE_WFI_STATE,
  74                 [1] = {
  75                         .enter                  = exynos4_enter_lowpower,
  76                         .exit_latency           = 300,
  77                         .target_residency       = 100000,
  78                         .flags                  = CPUIDLE_FLAG_TIME_VALID,
  79                         .name                   = "C1",
  80                         .desc                   = "ARM power down",
  81                 },
  82         },
  83         .state_count = 2,
  84         .safe_state_index = 0,
  85 };
  86
  87 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
  88 static void exynos4_set_wakeupmask(void)
  89 {
  90         __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
  91 }
  92
  93 static unsigned int g_pwr_ctrl, g_diag_reg;
  94
  95 static void save_cpu_arch_register(void)
  96 {
  97         /*read power control register*/
  98         asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
  99         /*read diagnostic register*/
 100         asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
 101         return;
 102 }
 103
 104 static void restore_cpu_arch_register(void)
 105 {
 106         /*write power control register*/
 107         asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
 108         /*write diagnostic register*/
 109         asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
 110         return;
 111 }
 112
 113 static int idle_finisher(unsigned long flags)
 114 {
 115         cpu_do_idle();
 116         return 1;
 117 }
 118
 119 static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
 120                                 struct cpuidle_driver *drv,
 121                                 int index)
 122 {
 123         unsigned long tmp;
 124
 125         exynos4_set_wakeupmask();
 126
 127         /* Set value of power down register for aftr mode */
 128         exynos_sys_powerdown_conf(SYS_AFTR);
 129
 130         __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
 131         __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
 132
 133         save_cpu_arch_register();
 134
 135         /* Setting Central Sequence Register for power down mode */
 136         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 137         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 138         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 139
 140         cpu_pm_enter();
 141         cpu_suspend(0, idle_finisher);
 142
 143 #ifdef CONFIG_SMP
 144         if (!soc_is_exynos5250())
 145                 scu_enable(S5P_VA_SCU);
 146 #endif
 147         cpu_pm_exit();
 148
 149         restore_cpu_arch_register();
 150
 151         /*
 152          * If PMU failed while entering sleep mode, WFI will be
 153          * ignored by PMU and then exiting cpu_do_idle().
 154          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 155          * in this situation.
 156          */
 157         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 158         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 159                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 160                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 161         }
 162
 163         /* Clear wakeup state register */
 164         __raw_writel(0x0, S5P_WAKEUP_STAT);
 165
 166         return index;
 167 }
 168
 169 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
 170                                 struct cpuidle_driver *drv,
 171                                 int index)
 172 {
 173         int new_index = index;
 174
 175         /* AFTR can only be entered when cores other than CPU0 are offline */
 176         if (num_online_cpus() > 1 || dev->cpu != 0)
 177                 new_index = drv->safe_state_index;
 178
 179         if (new_index == 0)
 180                 return arm_cpuidle_simple_enter(dev, drv, new_index);
 181         else
 182                 return exynos4_enter_core0_aftr(dev, drv, new_index);
 183 }
 184
 185 static void __init exynos5_core_down_clk(void)
 186 {
 187         unsigned int tmp;
 188
 189         /*
 190          * Enable arm clock down (in idle) and set arm divider
 191          * ratios in WFI/WFE state.
 192          */
 193         tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
 194               PWR_CTRL1_CORE1_DOWN_RATIO | \
 195               PWR_CTRL1_DIV2_DOWN_EN     | \
 196               PWR_CTRL1_DIV1_DOWN_EN     | \
 197               PWR_CTRL1_USE_CORE1_WFE    | \
 198               PWR_CTRL1_USE_CORE0_WFE    | \
 199               PWR_CTRL1_USE_CORE1_WFI    | \
 200               PWR_CTRL1_USE_CORE0_WFI;
 201         __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
 202
 203         /*
 204          * Enable arm clock up (on exiting idle). Set arm divider
 205          * ratios when not in idle along with the standby duration
 206          * ratios.
 207          */
 208         tmp = PWR_CTRL2_DIV2_UP_EN       | \
 209               PWR_CTRL2_DIV1_UP_EN       | \
 210               PWR_CTRL2_DUR_STANDBY2_VAL | \
 211               PWR_CTRL2_DUR_STANDBY1_VAL | \
 212               PWR_CTRL2_CORE2_UP_RATIO   | \
 213               PWR_CTRL2_CORE1_UP_RATIO;
 214         __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
 215 }
 216
 217 static int exynos_cpuidle_probe(struct platform_device *pdev)
 218 {
 219         int cpu_id, ret;
 220         struct cpuidle_device *device;
 221
 222         if (soc_is_exynos5250())
 223                 exynos5_core_down_clk();
 224
 225         if (soc_is_exynos5440())
 226                 exynos4_idle_driver.state_count = 1;
 227
 228         ret = cpuidle_register_driver(&exynos4_idle_driver);
 229         if (ret) {
 230                 dev_err(&pdev->dev, "failed to register cpuidle driver\n");
 231                 return ret;
 232         }
 233
 234         for_each_online_cpu(cpu_id) {
 235                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
 236                 device->cpu = cpu_id;
 237
 238                 ret = cpuidle_register_device(device);
 239                 if (ret) {
 240                         dev_err(&pdev->dev, "failed to register cpuidle device\n");
 241                         return ret;
 242                 }
 243         }
 244
 245         return 0;
 246 }
 247
 248 static struct platform_driver exynos_cpuidle_driver = {
 249         .probe  = exynos_cpuidle_probe,
 250         .driver = {
 251                 .name = "exynos_cpuidle",
 252                 .owner = THIS_MODULE,
 253         },
 254 };
 255
 256 module_platform_driver(exynos_cpuidle_driver);