arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/console.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/regulator/machine.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_data/at24.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/flash.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/mach/arch.h>
  26 #include <mach/common.h>
  27 #include <mach/cp_intc.h>
  28 #include <mach/da8xx.h>
  29 #include <linux/platform_data/mtd-davinci.h>
  30 #include <linux/platform_data/mtd-davinci-aemif.h>
  31 #include <mach/mux.h>
  32 #include <linux/platform_data/spi-davinci.h>
  33
  34 #define MITYOMAPL138_PHY_ID             ""
  35
  36 #define FACTORY_CONFIG_MAGIC    0x012C0138
  37 #define FACTORY_CONFIG_VERSION  0x00010001
  38
  39 /* Data Held in On-Board I2C device */
  40 struct factory_config {
  41         u32     magic;
  42         u32     version;
  43         u8      mac[6];
  44         u32     fpga_type;
  45         u32     spare;
  46         u32     serialnumber;
  47         char    partnum[32];
  48 };
  49
  50 static struct factory_config factory_config;
  51
  52 struct part_no_info {
  53         const char      *part_no;       /* part number string of interest */
  54         int             max_freq;       /* khz */
  55 };
  56
  57 static struct part_no_info mityomapl138_pn_info[] = {
  58         {
  59                 .part_no        = "L138-C",
  60                 .max_freq       = 300000,
  61         },
  62         {
  63                 .part_no        = "L138-D",
  64                 .max_freq       = 375000,
  65         },
  66         {
  67                 .part_no        = "L138-F",
  68                 .max_freq       = 456000,
  69         },
  70         {
  71                 .part_no        = "1808-C",
  72                 .max_freq       = 300000,
  73         },
  74         {
  75                 .part_no        = "1808-D",
  76                 .max_freq       = 375000,
  77         },
  78         {
  79                 .part_no        = "1808-F",
  80                 .max_freq       = 456000,
  81         },
  82         {
  83                 .part_no        = "1810-D",
  84                 .max_freq       = 375000,
  85         },
  86 };
  87
  88 #ifdef CONFIG_CPU_FREQ
  89 static void mityomapl138_cpufreq_init(const char *partnum)
  90 {
  91         int i, ret;
  92
  93         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  94                 /*
  95                  * the part number has additional characters beyond what is
  96                  * stored in the table.  This information is not needed for
  97                  * determining the speed grade, and would require several
  98                  * more table entries.  Only check the first N characters
  99                  * for a match.
 100                  */
 101                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 102                              strlen(mityomapl138_pn_info[i].part_no))) {
 103                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 104                         break;
 105                 }
 106         }
 107
 108         ret = da850_register_cpufreq("pll0_sysclk3");
 109         if (ret)
 110                 pr_warning("cpufreq registration failed: %d\n", ret);
 111 }
 112 #else
 113 static void mityomapl138_cpufreq_init(const char *partnum) { }
 114 #endif
 115
 116 static void read_factory_config(struct memory_accessor *a, void *context)
 117 {
 118         int ret;
 119         const char *partnum = NULL;
 120         struct davinci_soc_info *soc_info = &davinci_soc_info;
 121
 122         ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
 123         if (ret != sizeof(struct factory_config)) {
 124                 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
 125                                 ret);
 126                 goto bad_config;
 127         }
 128
 129         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 130                 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
 131                                 factory_config.magic);
 132                 goto bad_config;
 133         }
 134
 135         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 136                 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
 137                                 factory_config.version);
 138                 goto bad_config;
 139         }
 140
 141         pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
 142         if (is_valid_ether_addr(factory_config.mac))
 143                 memcpy(soc_info->emac_pdata->mac_addr,
 144                         factory_config.mac, ETH_ALEN);
 145         else
 146                 pr_warning("MityOMAPL138: Invalid MAC found "
 147                                 "in factory config block\n");
 148
 149         partnum = factory_config.partnum;
 150         pr_info("MityOMAPL138: Part Number = %s\n", partnum);
 151
 152 bad_config:
 153         /* default maximum speed is valid for all platforms */
 154         mityomapl138_cpufreq_init(partnum);
 155 }
 156
 157 static struct at24_platform_data mityomapl138_fd_chip = {
 158         .byte_len       = 256,
 159         .page_size      = 8,
 160         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
 161         .setup          = read_factory_config,
 162         .context        = NULL,
 163 };
 164
 165 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 166         .bus_freq       = 100,  /* kHz */
 167         .bus_delay      = 0,    /* usec */
 168 };
 169
 170 /* TPS65023 voltage regulator support */
 171 /* 1.2V Core */
 172 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 173         {
 174                 .supply = "cvdd",
 175         },
 176 };
 177
 178 /* 1.8V */
 179 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 180         {
 181                 .supply = "usb0_vdda18",
 182         },
 183         {
 184                 .supply = "usb1_vdda18",
 185         },
 186         {
 187                 .supply = "ddr_dvdd18",
 188         },
 189         {
 190                 .supply = "sata_vddr",
 191         },
 192 };
 193
 194 /* 1.2V */
 195 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 196         {
 197                 .supply = "sata_vdd",
 198         },
 199         {
 200                 .supply = "usb_cvdd",
 201         },
 202         {
 203                 .supply = "pll0_vdda",
 204         },
 205         {
 206                 .supply = "pll1_vdda",
 207         },
 208 };
 209
 210 /* 1.8V Aux LDO, not used */
 211 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 212         {
 213                 .supply = "1.8v_aux",
 214         },
 215 };
 216
 217 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 218 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 219         {
 220                 .supply = "vccaux",
 221         },
 222 };
 223
 224 static struct regulator_init_data tps65023_regulator_data[] = {
 225         /* dcdc1 */
 226         {
 227                 .constraints = {
 228                         .min_uV = 1150000,
 229                         .max_uV = 1350000,
 230                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 231                                           REGULATOR_CHANGE_STATUS,
 232                         .boot_on = 1,
 233                 },
 234                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 235                 .consumer_supplies = tps65023_dcdc1_consumers,
 236         },
 237         /* dcdc2 */
 238         {
 239                 .constraints = {
 240                         .min_uV = 1800000,
 241                         .max_uV = 1800000,
 242                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 243                         .boot_on = 1,
 244                 },
 245                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 246                 .consumer_supplies = tps65023_dcdc2_consumers,
 247         },
 248         /* dcdc3 */
 249         {
 250                 .constraints = {
 251                         .min_uV = 1200000,
 252                         .max_uV = 1200000,
 253                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 254                         .boot_on = 1,
 255                 },
 256                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 257                 .consumer_supplies = tps65023_dcdc3_consumers,
 258         },
 259         /* ldo1 */
 260         {
 261                 .constraints = {
 262                         .min_uV = 1800000,
 263                         .max_uV = 1800000,
 264                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 265                         .boot_on = 1,
 266                 },
 267                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 268                 .consumer_supplies = tps65023_ldo1_consumers,
 269         },
 270         /* ldo2 */
 271         {
 272                 .constraints = {
 273                         .min_uV = 2500000,
 274                         .max_uV = 3300000,
 275                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 276                                           REGULATOR_CHANGE_STATUS,
 277                         .boot_on = 1,
 278                 },
 279                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 280                 .consumer_supplies = tps65023_ldo2_consumers,
 281         },
 282 };
 283
 284 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 285         {
 286                 I2C_BOARD_INFO("tps65023", 0x48),
 287                 .platform_data = &tps65023_regulator_data[0],
 288         },
 289         {
 290                 I2C_BOARD_INFO("24c02", 0x50),
 291                 .platform_data = &mityomapl138_fd_chip,
 292         },
 293 };
 294
 295 static int __init pmic_tps65023_init(void)
 296 {
 297         return i2c_register_board_info(1, mityomap_tps65023_info,
 298                                         ARRAY_SIZE(mityomap_tps65023_info));
 299 }
 300
 301 /*
 302  * SPI Devices:
 303  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 304  */
 305 static struct mtd_partition spi_flash_partitions[] = {
 306         [0] = {
 307                 .name           = "ubl",
 308                 .offset         = 0,
 309                 .size           = SZ_64K,
 310                 .mask_flags     = MTD_WRITEABLE,
 311         },
 312         [1] = {
 313                 .name           = "u-boot",
 314                 .offset         = MTDPART_OFS_APPEND,
 315                 .size           = SZ_512K,
 316                 .mask_flags     = MTD_WRITEABLE,
 317         },
 318         [2] = {
 319                 .name           = "u-boot-env",
 320                 .offset         = MTDPART_OFS_APPEND,
 321                 .size           = SZ_64K,
 322                 .mask_flags     = MTD_WRITEABLE,
 323         },
 324         [3] = {
 325                 .name           = "periph-config",
 326                 .offset         = MTDPART_OFS_APPEND,
 327                 .size           = SZ_64K,
 328                 .mask_flags     = MTD_WRITEABLE,
 329         },
 330         [4] = {
 331                 .name           = "reserved",
 332                 .offset         = MTDPART_OFS_APPEND,
 333                 .size           = SZ_256K + SZ_64K,
 334         },
 335         [5] = {
 336                 .name           = "kernel",
 337                 .offset         = MTDPART_OFS_APPEND,
 338                 .size           = SZ_2M + SZ_1M,
 339         },
 340         [6] = {
 341                 .name           = "fpga",
 342                 .offset         = MTDPART_OFS_APPEND,
 343                 .size           = SZ_2M,
 344         },
 345         [7] = {
 346                 .name           = "spare",
 347                 .offset         = MTDPART_OFS_APPEND,
 348                 .size           = MTDPART_SIZ_FULL,
 349         },
 350 };
 351
 352 static struct flash_platform_data mityomapl138_spi_flash_data = {
 353         .name           = "m25p80",
 354         .parts          = spi_flash_partitions,
 355         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 356         .type           = "m24p64",
 357 };
 358
 359 static struct davinci_spi_config spi_eprom_config = {
 360         .io_type        = SPI_IO_TYPE_DMA,
 361         .c2tdelay       = 8,
 362         .t2cdelay       = 8,
 363 };
 364
 365 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 366         {
 367                 .modalias               = "m25p80",
 368                 .platform_data          = &mityomapl138_spi_flash_data,
 369                 .controller_data        = &spi_eprom_config,
 370                 .mode                   = SPI_MODE_0,
 371                 .max_speed_hz           = 30000000,
 372                 .bus_num                = 1,
 373                 .chip_select            = 0,
 374         },
 375 };
 376
 377 /*
 378  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 379  * (128K blocks).
 380  */
 381 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 382         {
 383                 .name           = "rootfs",
 384                 .offset         = 0,
 385                 .size           = SZ_128M,
 386                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 387         },
 388         {
 389                 .name           = "homefs",
 390                 .offset         = MTDPART_OFS_APPEND,
 391                 .size           = MTDPART_SIZ_FULL,
 392                 .mask_flags     = 0,
 393         },
 394 };
 395
 396 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 397         .parts          = mityomapl138_nandflash_partition,
 398         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 399         .ecc_mode       = NAND_ECC_HW,
 400         .bbt_options    = NAND_BBT_USE_FLASH,
 401         .options        = NAND_BUSWIDTH_16,
 402         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 403 };
 404
 405 static struct resource mityomapl138_nandflash_resource[] = {
 406         {
 407                 .start  = DA8XX_AEMIF_CS3_BASE,
 408                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 409                 .flags  = IORESOURCE_MEM,
 410         },
 411         {
 412                 .start  = DA8XX_AEMIF_CTL_BASE,
 413                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 414                 .flags  = IORESOURCE_MEM,
 415         },
 416 };
 417
 418 static struct platform_device mityomapl138_nandflash_device = {
 419         .name           = "davinci_nand",
 420         .id             = 1,
 421         .dev            = {
 422                 .platform_data  = &mityomapl138_nandflash_data,
 423         },
 424         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 425         .resource       = mityomapl138_nandflash_resource,
 426 };
 427
 428 static struct platform_device *mityomapl138_devices[] __initdata = {
 429         &mityomapl138_nandflash_device,
 430 };
 431
 432 static void __init mityomapl138_setup_nand(void)
 433 {
 434         platform_add_devices(mityomapl138_devices,
 435                                  ARRAY_SIZE(mityomapl138_devices));
 436
 437         if (davinci_aemif_setup(&mityomapl138_nandflash_device))
 438                 pr_warn("%s: Cannot configure AEMIF.\n", __func__);
 439 }
 440
 441 static const short mityomap_mii_pins[] = {
 442         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 443         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 444         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 445         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 446         DA850_MDIO_D,
 447         -1
 448 };
 449
 450 static const short mityomap_rmii_pins[] = {
 451         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 452         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 453         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 454         DA850_MDIO_D,
 455         -1
 456 };
 457
 458 static void __init mityomapl138_config_emac(void)
 459 {
 460         void __iomem *cfg_chip3_base;
 461         int ret;
 462         u32 val;
 463         struct davinci_soc_info *soc_info = &davinci_soc_info;
 464
 465         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 466
 467         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 468         val = __raw_readl(cfg_chip3_base);
 469
 470         if (soc_info->emac_pdata->rmii_en) {
 471                 val |= BIT(8);
 472                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 473                 pr_info("RMII PHY configured\n");
 474         } else {
 475                 val &= ~BIT(8);
 476                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 477                 pr_info("MII PHY configured\n");
 478         }
 479
 480         if (ret) {
 481                 pr_warning("mii/rmii mux setup failed: %d\n", ret);
 482                 return;
 483         }
 484
 485         /* configure the CFGCHIP3 register for RMII or MII */
 486         __raw_writel(val, cfg_chip3_base);
 487
 488         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 489
 490         ret = da8xx_register_emac();
 491         if (ret)
 492                 pr_warning("emac registration failed: %d\n", ret);
 493 }
 494
 495 static struct davinci_pm_config da850_pm_pdata = {
 496         .sleepcount = 128,
 497 };
 498
 499 static struct platform_device da850_pm_device = {
 500         .name   = "pm-davinci",
 501         .dev = {
 502                 .platform_data  = &da850_pm_pdata,
 503         },
 504         .id     = -1,
 505 };
 506
 507 static void __init mityomapl138_init(void)
 508 {
 509         int ret;
 510
 511         /* for now, no special EDMA channels are reserved */
 512         ret = da850_register_edma(NULL);
 513         if (ret)
 514                 pr_warning("edma registration failed: %d\n", ret);
 515
 516         ret = da8xx_register_watchdog();
 517         if (ret)
 518                 pr_warning("watchdog registration failed: %d\n", ret);
 519
 520         davinci_serial_init(da8xx_serial_device);
 521
 522         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 523         if (ret)
 524                 pr_warning("i2c0 registration failed: %d\n", ret);
 525
 526         ret = pmic_tps65023_init();
 527         if (ret)
 528                 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
 529
 530         mityomapl138_setup_nand();
 531
 532         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 533                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 534         if (ret)
 535                 pr_warn("spi info registration failed: %d\n", ret);
 536
 537         ret = da8xx_register_spi_bus(1,
 538                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 539         if (ret)
 540                 pr_warning("spi 1 registration failed: %d\n", ret);
 541
 542         mityomapl138_config_emac();
 543
 544         ret = da8xx_register_rtc();
 545         if (ret)
 546                 pr_warning("rtc setup failed: %d\n", ret);
 547
 548         ret = da8xx_register_cpuidle();
 549         if (ret)
 550                 pr_warning("cpuidle registration failed: %d\n", ret);
 551
 552         ret = da850_register_pm(&da850_pm_device);
 553         if (ret)
 554                 pr_warning("da850_evm_init: suspend registration failed: %d\n",
 555                                 ret);
 556 }
 557
 558 #ifdef CONFIG_SERIAL_8250_CONSOLE
 559 static int __init mityomapl138_console_init(void)
 560 {
 561         if (!machine_is_mityomapl138())
 562                 return 0;
 563
 564         return add_preferred_console("ttyS", 1, "115200");
 565 }
 566 console_initcall(mityomapl138_console_init);
 567 #endif
 568
 569 static void __init mityomapl138_map_io(void)
 570 {
 571         da850_init();
 572 }
 573
 574 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 575         .atag_offset    = 0x100,
 576         .map_io         = mityomapl138_map_io,
 577         .init_irq       = cp_intc_init,
 578         .init_time      = davinci_timer_init,
 579         .init_machine   = mityomapl138_init,
 580         .init_late      = davinci_init_late,
 581         .dma_zone_size  = SZ_128M,
 582         .restart        = da8xx_restart,
 583 MACHINE_END