2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 #ifndef __ARM_KVM_MMU_H__
20 #define __ARM_KVM_MMU_H__
22 #include <asm/memory.h>
26 * We directly use the kernel VA for the HYP, as we can directly share
27 * the mapping (HTTBR "covers" TTBR1).
29 #define HYP_PAGE_OFFSET_MASK UL(~0)
30 #define HYP_PAGE_OFFSET PAGE_OFFSET
31 #define KERN_TO_HYP(kva) (kva)
34 * Our virtual mapping for the boot-time MMU-enable code. Must be
35 * shared across all the page-tables. Conveniently, we use the vectors
36 * page, where no kernel data will ever be shared with HYP.
38 #define TRAMPOLINE_VA UL(CONFIG_VECTORS_BASE)
42 #include <asm/cacheflush.h>
43 #include <asm/pgalloc.h>
45 int create_hyp_mappings(void *from, void *to);
46 int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
47 void free_boot_hyp_pgd(void);
48 void free_hyp_pgds(void);
50 int kvm_alloc_stage2_pgd(struct kvm *kvm);
51 void kvm_free_stage2_pgd(struct kvm *kvm);
52 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
53 phys_addr_t pa, unsigned long size);
55 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
57 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
59 phys_addr_t kvm_mmu_get_httbr(void);
60 phys_addr_t kvm_mmu_get_boot_httbr(void);
61 phys_addr_t kvm_get_idmap_vector(void);
62 int kvm_mmu_init(void);
63 void kvm_clear_hyp_idmap(void);
65 static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd)
71 static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
75 * flush_pmd_entry just takes a void pointer and cleans the necessary
76 * cache entries, so we can reuse the function for ptes.
81 static inline bool kvm_is_write_fault(unsigned long hsr)
83 unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
84 if (hsr_ec == HSR_EC_IABT)
86 else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
92 static inline void kvm_clean_pgd(pgd_t *pgd)
94 clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
97 static inline void kvm_clean_pmd_entry(pmd_t *pmd)
102 static inline void kvm_clean_pte(pte_t *pte)
104 clean_pte_table(pte);
107 static inline void kvm_set_s2pte_writable(pte_t *pte)
109 pte_val(*pte) |= L_PTE_S2_RDWR;
112 static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
114 pmd_val(*pmd) |= L_PMD_S2_RDWR;
117 /* Open coded p*d_addr_end that can deal with 64bit addresses */
118 #define kvm_pgd_addr_end(addr, end) \
119 ({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
120 (__boundary - 1 < (end) - 1)? __boundary: (end); \
123 #define kvm_pud_addr_end(addr,end) (end)
125 #define kvm_pmd_addr_end(addr, end) \
126 ({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
127 (__boundary - 1 < (end) - 1)? __boundary: (end); \
132 #define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
134 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
136 return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
139 static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
142 if (!vcpu_has_cache_enabled(vcpu))
143 kvm_flush_dcache_to_poc((void *)hva, size);
146 * If we are going to insert an instruction page and the icache is
147 * either VIPT or PIPT, there is a potential problem where the host
148 * (or another VM) may have used the same page as this guest, and we
149 * read incorrect data from the icache. If we're using a PIPT cache,
150 * we can invalidate just that page, but if we are using a VIPT cache
151 * we need to invalidate the entire icache - damn shame - as written
152 * in the ARM ARM (DDI 0406C.b - Page B3-1393).
154 * VIVT caches are tagged using both the ASID and the VMID and doesn't
155 * need any kind of flushing (DDI 0406C.b - Page B3-1392).
157 if (icache_is_pipt()) {
158 __cpuc_coherent_user_range(hva, hva + size);
159 } else if (!icache_is_vivt_asid_tagged()) {
160 /* any kind of VIPT cache */
161 __flush_icache_all();
165 #define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
167 void stage2_flush_vm(struct kvm *kvm);
169 #endif /* !__ASSEMBLY__ */
171 #endif /* __ARM_KVM_MMU_H__ */