arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra124";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         host1x@0,50000000 {
  15                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  16                 reg = <0x0 0x50000000 0x0 0x00034000>;
  17                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  18                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  19                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  20                 resets = <&tegra_car 28>;
  21                 reset-names = "host1x";
  22
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25
  26                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  27
  28                 dc@0,54200000 {
  29                         compatible = "nvidia,tegra124-dc";
  30                         reg = <0x0 0x54200000 0x0 0x00040000>;
  31                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
  33                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  34                         clock-names = "dc", "parent";
  35                         resets = <&tegra_car 27>;
  36                         reset-names = "dc";
  37
  38                         nvidia,head = <0>;
  39                 };
  40
  41                 dc@0,54240000 {
  42                         compatible = "nvidia,tegra124-dc";
  43                         reg = <0x0 0x54240000 0x0 0x00040000>;
  44                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
  46                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  47                         clock-names = "dc", "parent";
  48                         resets = <&tegra_car 26>;
  49                         reset-names = "dc";
  50
  51                         nvidia,head = <1>;
  52                 };
  53
  54                 sor@0,54540000 {
  55                         compatible = "nvidia,tegra124-sor";
  56                         reg = <0x0 0x54540000 0x0 0x00040000>;
  57                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  58                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
  59                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
  60                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
  61                                  <&tegra_car TEGRA124_CLK_CLK_M>;
  62                         clock-names = "sor", "parent", "dp", "safe";
  63                         resets = <&tegra_car 182>;
  64                         reset-names = "sor";
  65                         status = "disabled";
  66                 };
  67
  68                 dpaux@0,545c0000 {
  69                         compatible = "nvidia,tegra124-dpaux";
  70                         reg = <0x0 0x545c0000 0x0 0x00040000>;
  71                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  72                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
  73                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
  74                         clock-names = "dpaux", "parent";
  75                         resets = <&tegra_car 181>;
  76                         reset-names = "dpaux";
  77                         status = "disabled";
  78                 };
  79         };
  80
  81         gic: interrupt-controller@0,50041000 {
  82                 compatible = "arm,cortex-a15-gic";
  83                 #interrupt-cells = <3>;
  84                 interrupt-controller;
  85                 reg = <0x0 0x50041000 0x0 0x1000>,
  86                       <0x0 0x50042000 0x0 0x1000>,
  87                       <0x0 0x50044000 0x0 0x2000>,
  88                       <0x0 0x50046000 0x0 0x2000>;
  89                 interrupts = <GIC_PPI 9
  90                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  91         };
  92
  93         timer@0,60005000 {
  94                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
  95                 reg = <0x0 0x60005000 0x0 0x400>;
  96                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  97                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  98                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  99                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 100                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 101                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 102                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 103         };
 104
 105         tegra_car: clock@0,60006000 {
 106                 compatible = "nvidia,tegra124-car";
 107                 reg = <0x0 0x60006000 0x0 0x1000>;
 108                 #clock-cells = <1>;
 109                 #reset-cells = <1>;
 110         };
 111
 112         gpio: gpio@0,6000d000 {
 113                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 114                 reg = <0x0 0x6000d000 0x0 0x1000>;
 115                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 116                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 117                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127         };
 128
 129         apbdma: dma@0,60020000 {
 130                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 131                 reg = <0x0 0x60020000 0x0 0x1400>;
 132                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 135                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 136                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 138                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 164                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 165                 resets = <&tegra_car 34>;
 166                 reset-names = "dma";
 167                 #dma-cells = <1>;
 168         };
 169
 170         pinmux: pinmux@0,70000868 {
 171                 compatible = "nvidia,tegra124-pinmux";
 172                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 173                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 174         };
 175
 176         /*
 177          * There are two serial driver i.e. 8250 based simple serial
 178          * driver and APB DMA based serial driver for higher baudrate
 179          * and performace. To enable the 8250 based driver, the compatible
 180          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 181          * the APB DMA based serial driver, the comptible is
 182          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 183          */
 184         serial@0,70006000 {
 185                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 186                 reg = <0x0 0x70006000 0x0 0x40>;
 187                 reg-shift = <2>;
 188                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 190                 resets = <&tegra_car 6>;
 191                 reset-names = "serial";
 192                 dmas = <&apbdma 8>, <&apbdma 8>;
 193                 dma-names = "rx", "tx";
 194                 status = "disabled";
 195         };
 196
 197         serial@0,70006040 {
 198                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 199                 reg = <0x0 0x70006040 0x0 0x40>;
 200                 reg-shift = <2>;
 201                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 203                 resets = <&tegra_car 7>;
 204                 reset-names = "serial";
 205                 dmas = <&apbdma 9>, <&apbdma 9>;
 206                 dma-names = "rx", "tx";
 207                 status = "disabled";
 208         };
 209
 210         serial@0,70006200 {
 211                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 212                 reg = <0x0 0x70006200 0x0 0x40>;
 213                 reg-shift = <2>;
 214                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 216                 resets = <&tegra_car 55>;
 217                 reset-names = "serial";
 218                 dmas = <&apbdma 10>, <&apbdma 10>;
 219                 dma-names = "rx", "tx";
 220                 status = "disabled";
 221         };
 222
 223         serial@0,70006300 {
 224                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 225                 reg = <0x0 0x70006300 0x0 0x40>;
 226                 reg-shift = <2>;
 227                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 229                 resets = <&tegra_car 65>;
 230                 reset-names = "serial";
 231                 dmas = <&apbdma 19>, <&apbdma 19>;
 232                 dma-names = "rx", "tx";
 233                 status = "disabled";
 234         };
 235
 236         serial@0,70006400 {
 237                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 238                 reg = <0x0 0x70006400 0x0 0x40>;
 239                 reg-shift = <2>;
 240                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
 242                 resets = <&tegra_car 66>;
 243                 reset-names = "serial";
 244                 dmas = <&apbdma 20>, <&apbdma 20>;
 245                 dma-names = "rx", "tx";
 246                 status = "disabled";
 247         };
 248
 249         pwm@0,7000a000 {
 250                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 251                 reg = <0x0 0x7000a000 0x0 0x100>;
 252                 #pwm-cells = <2>;
 253                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 254                 resets = <&tegra_car 17>;
 255                 reset-names = "pwm";
 256                 status = "disabled";
 257         };
 258
 259         i2c@0,7000c000 {
 260                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 261                 reg = <0x0 0x7000c000 0x0 0x100>;
 262                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 266                 clock-names = "div-clk";
 267                 resets = <&tegra_car 12>;
 268                 reset-names = "i2c";
 269                 dmas = <&apbdma 21>, <&apbdma 21>;
 270                 dma-names = "rx", "tx";
 271                 status = "disabled";
 272         };
 273
 274         i2c@0,7000c400 {
 275                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 276                 reg = <0x0 0x7000c400 0x0 0x100>;
 277                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 281                 clock-names = "div-clk";
 282                 resets = <&tegra_car 54>;
 283                 reset-names = "i2c";
 284                 dmas = <&apbdma 22>, <&apbdma 22>;
 285                 dma-names = "rx", "tx";
 286                 status = "disabled";
 287         };
 288
 289         i2c@0,7000c500 {
 290                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 291                 reg = <0x0 0x7000c500 0x0 0x100>;
 292                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 296                 clock-names = "div-clk";
 297                 resets = <&tegra_car 67>;
 298                 reset-names = "i2c";
 299                 dmas = <&apbdma 23>, <&apbdma 23>;
 300                 dma-names = "rx", "tx";
 301                 status = "disabled";
 302         };
 303
 304         i2c@0,7000c700 {
 305                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 306                 reg = <0x0 0x7000c700 0x0 0x100>;
 307                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 311                 clock-names = "div-clk";
 312                 resets = <&tegra_car 103>;
 313                 reset-names = "i2c";
 314                 dmas = <&apbdma 26>, <&apbdma 26>;
 315                 dma-names = "rx", "tx";
 316                 status = "disabled";
 317         };
 318
 319         i2c@0,7000d000 {
 320                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 321                 reg = <0x0 0x7000d000 0x0 0x100>;
 322                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 326                 clock-names = "div-clk";
 327                 resets = <&tegra_car 47>;
 328                 reset-names = "i2c";
 329                 dmas = <&apbdma 24>, <&apbdma 24>;
 330                 dma-names = "rx", "tx";
 331                 status = "disabled";
 332         };
 333
 334         i2c@0,7000d100 {
 335                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 336                 reg = <0x0 0x7000d100 0x0 0x100>;
 337                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 341                 clock-names = "div-clk";
 342                 resets = <&tegra_car 166>;
 343                 reset-names = "i2c";
 344                 dmas = <&apbdma 30>, <&apbdma 30>;
 345                 dma-names = "rx", "tx";
 346                 status = "disabled";
 347         };
 348
 349         spi@0,7000d400 {
 350                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 351                 reg = <0x0 0x7000d400 0x0 0x200>;
 352                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 356                 clock-names = "spi";
 357                 resets = <&tegra_car 41>;
 358                 reset-names = "spi";
 359                 dmas = <&apbdma 15>, <&apbdma 15>;
 360                 dma-names = "rx", "tx";
 361                 status = "disabled";
 362         };
 363
 364         spi@0,7000d600 {
 365                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 366                 reg = <0x0 0x7000d600 0x0 0x200>;
 367                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 371                 clock-names = "spi";
 372                 resets = <&tegra_car 44>;
 373                 reset-names = "spi";
 374                 dmas = <&apbdma 16>, <&apbdma 16>;
 375                 dma-names = "rx", "tx";
 376                 status = "disabled";
 377         };
 378
 379         spi@0,7000d800 {
 380                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 381                 reg = <0x0 0x7000d800 0x0 0x200>;
 382                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 386                 clock-names = "spi";
 387                 resets = <&tegra_car 46>;
 388                 reset-names = "spi";
 389                 dmas = <&apbdma 17>, <&apbdma 17>;
 390                 dma-names = "rx", "tx";
 391                 status = "disabled";
 392         };
 393
 394         spi@0,7000da00 {
 395                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 396                 reg = <0x0 0x7000da00 0x0 0x200>;
 397                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 401                 clock-names = "spi";
 402                 resets = <&tegra_car 68>;
 403                 reset-names = "spi";
 404                 dmas = <&apbdma 18>, <&apbdma 18>;
 405                 dma-names = "rx", "tx";
 406                 status = "disabled";
 407         };
 408
 409         spi@0,7000dc00 {
 410                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 411                 reg = <0x0 0x7000dc00 0x0 0x200>;
 412                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 416                 clock-names = "spi";
 417                 resets = <&tegra_car 104>;
 418                 reset-names = "spi";
 419                 dmas = <&apbdma 27>, <&apbdma 27>;
 420                 dma-names = "rx", "tx";
 421                 status = "disabled";
 422         };
 423
 424         spi@0,7000de00 {
 425                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 426                 reg = <0x0 0x7000de00 0x0 0x200>;
 427                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 431                 clock-names = "spi";
 432                 resets = <&tegra_car 105>;
 433                 reset-names = "spi";
 434                 dmas = <&apbdma 28>, <&apbdma 28>;
 435                 dma-names = "rx", "tx";
 436                 status = "disabled";
 437         };
 438
 439         rtc@0,7000e000 {
 440                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 441                 reg = <0x0 0x7000e000 0x0 0x100>;
 442                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 444         };
 445
 446         pmc@0,7000e400 {
 447                 compatible = "nvidia,tegra124-pmc";
 448                 reg = <0x0 0x7000e400 0x0 0x400>;
 449                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 450                 clock-names = "pclk", "clk32k_in";
 451         };
 452
 453         sdhci@0,700b0000 {
 454                 compatible = "nvidia,tegra124-sdhci";
 455                 reg = <0x0 0x700b0000 0x0 0x200>;
 456                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 457                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 458                 resets = <&tegra_car 14>;
 459                 reset-names = "sdhci";
 460                 status = "disabled";
 461         };
 462
 463         sdhci@0,700b0200 {
 464                 compatible = "nvidia,tegra124-sdhci";
 465                 reg = <0x0 0x700b0200 0x0 0x200>;
 466                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 468                 resets = <&tegra_car 9>;
 469                 reset-names = "sdhci";
 470                 status = "disabled";
 471         };
 472
 473         sdhci@0,700b0400 {
 474                 compatible = "nvidia,tegra124-sdhci";
 475                 reg = <0x0 0x700b0400 0x0 0x200>;
 476                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 477                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 478                 resets = <&tegra_car 69>;
 479                 reset-names = "sdhci";
 480                 status = "disabled";
 481         };
 482
 483         sdhci@0,700b0600 {
 484                 compatible = "nvidia,tegra124-sdhci";
 485                 reg = <0x0 0x700b0600 0x0 0x200>;
 486                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 488                 resets = <&tegra_car 15>;
 489                 reset-names = "sdhci";
 490                 status = "disabled";
 491         };
 492
 493         ahub@0,70300000 {
 494                 compatible = "nvidia,tegra124-ahub";
 495                 reg = <0x0 0x70300000 0x0 0x200>,
 496                       <0x0 0x70300800 0x0 0x800>,
 497                       <0x0 0x70300200 0x0 0x600>;
 498                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 500                          <&tegra_car TEGRA124_CLK_APBIF>;
 501                 clock-names = "d_audio", "apbif";
 502                 resets = <&tegra_car 106>, /* d_audio */
 503                          <&tegra_car 107>, /* apbif */
 504                          <&tegra_car 30>,  /* i2s0 */
 505                          <&tegra_car 11>,  /* i2s1 */
 506                          <&tegra_car 18>,  /* i2s2 */
 507                          <&tegra_car 101>, /* i2s3 */
 508                          <&tegra_car 102>, /* i2s4 */
 509                          <&tegra_car 108>, /* dam0 */
 510                          <&tegra_car 109>, /* dam1 */
 511                          <&tegra_car 110>, /* dam2 */
 512                          <&tegra_car 10>,  /* spdif */
 513                          <&tegra_car 153>, /* amx */
 514                          <&tegra_car 185>, /* amx1 */
 515                          <&tegra_car 154>, /* adx */
 516                          <&tegra_car 180>, /* adx1 */
 517                          <&tegra_car 186>, /* afc0 */
 518                          <&tegra_car 187>, /* afc1 */
 519                          <&tegra_car 188>, /* afc2 */
 520                          <&tegra_car 189>, /* afc3 */
 521                          <&tegra_car 190>, /* afc4 */
 522                          <&tegra_car 191>; /* afc5 */
 523                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 524                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 525                               "spdif", "amx", "amx1", "adx", "adx1",
 526                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 527                 dmas = <&apbdma 1>, <&apbdma 1>,
 528                        <&apbdma 2>, <&apbdma 2>,
 529                        <&apbdma 3>, <&apbdma 3>,
 530                        <&apbdma 4>, <&apbdma 4>,
 531                        <&apbdma 6>, <&apbdma 6>,
 532                        <&apbdma 7>, <&apbdma 7>,
 533                        <&apbdma 12>, <&apbdma 12>,
 534                        <&apbdma 13>, <&apbdma 13>,
 535                        <&apbdma 14>, <&apbdma 14>,
 536                        <&apbdma 29>, <&apbdma 29>;
 537                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 538                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 539                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 540                             "rx9", "tx9";
 541                 ranges;
 542                 #address-cells = <2>;
 543                 #size-cells = <2>;
 544
 545                 tegra_i2s0: i2s@0,70301000 {
 546                         compatible = "nvidia,tegra124-i2s";
 547                         reg = <0x0 0x70301000 0x0 0x100>;
 548                         nvidia,ahub-cif-ids = <4 4>;
 549                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 550                         resets = <&tegra_car 30>;
 551                         reset-names = "i2s";
 552                         status = "disabled";
 553                 };
 554
 555                 tegra_i2s1: i2s@0,70301100 {
 556                         compatible = "nvidia,tegra124-i2s";
 557                         reg = <0x0 0x70301100 0x0 0x100>;
 558                         nvidia,ahub-cif-ids = <5 5>;
 559                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 560                         resets = <&tegra_car 11>;
 561                         reset-names = "i2s";
 562                         status = "disabled";
 563                 };
 564
 565                 tegra_i2s2: i2s@0,70301200 {
 566                         compatible = "nvidia,tegra124-i2s";
 567                         reg = <0x0 0x70301200 0x0 0x100>;
 568                         nvidia,ahub-cif-ids = <6 6>;
 569                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 570                         resets = <&tegra_car 18>;
 571                         reset-names = "i2s";
 572                         status = "disabled";
 573                 };
 574
 575                 tegra_i2s3: i2s@0,70301300 {
 576                         compatible = "nvidia,tegra124-i2s";
 577                         reg = <0x0 0x70301300 0x0 0x100>;
 578                         nvidia,ahub-cif-ids = <7 7>;
 579                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 580                         resets = <&tegra_car 101>;
 581                         reset-names = "i2s";
 582                         status = "disabled";
 583                 };
 584
 585                 tegra_i2s4: i2s@0,70301400 {
 586                         compatible = "nvidia,tegra124-i2s";
 587                         reg = <0x0 0x70301400 0x0 0x100>;
 588                         nvidia,ahub-cif-ids = <8 8>;
 589                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 590                         resets = <&tegra_car 102>;
 591                         reset-names = "i2s";
 592                         status = "disabled";
 593                 };
 594         };
 595
 596         usb@0,7d000000 {
 597                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 598                 reg = <0x0 0x7d000000 0x0 0x4000>;
 599                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 600                 phy_type = "utmi";
 601                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 602                 resets = <&tegra_car 22>;
 603                 reset-names = "usb";
 604                 nvidia,phy = <&phy1>;
 605                 status = "disabled";
 606         };
 607
 608         phy1: usb-phy@0,7d000000 {
 609                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 610                 reg = <0x0 0x7d000000 0x0 0x4000>,
 611                       <0x0 0x7d000000 0x0 0x4000>;
 612                 phy_type = "utmi";
 613                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 614                          <&tegra_car TEGRA124_CLK_PLL_U>,
 615                          <&tegra_car TEGRA124_CLK_USBD>;
 616                 clock-names = "reg", "pll_u", "utmi-pads";
 617                 nvidia,hssync-start-delay = <0>;
 618                 nvidia,idle-wait-delay = <17>;
 619                 nvidia,elastic-limit = <16>;
 620                 nvidia,term-range-adj = <6>;
 621                 nvidia,xcvr-setup = <9>;
 622                 nvidia,xcvr-lsfslew = <0>;
 623                 nvidia,xcvr-lsrslew = <3>;
 624                 nvidia,hssquelch-level = <2>;
 625                 nvidia,hsdiscon-level = <5>;
 626                 nvidia,xcvr-hsslew = <12>;
 627                 status = "disabled";
 628         };
 629
 630         usb@0,7d004000 {
 631                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 632                 reg = <0x0 0x7d004000 0x0 0x4000>;
 633                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 634                 phy_type = "utmi";
 635                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 636                 resets = <&tegra_car 58>;
 637                 reset-names = "usb";
 638                 nvidia,phy = <&phy2>;
 639                 status = "disabled";
 640         };
 641
 642         phy2: usb-phy@0,7d004000 {
 643                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 644                 reg = <0x0 0x7d004000 0x0 0x4000>,
 645                       <0x0 0x7d000000 0x0 0x4000>;
 646                 phy_type = "utmi";
 647                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 648                          <&tegra_car TEGRA124_CLK_PLL_U>,
 649                          <&tegra_car TEGRA124_CLK_USBD>;
 650                 clock-names = "reg", "pll_u", "utmi-pads";
 651                 nvidia,hssync-start-delay = <0>;
 652                 nvidia,idle-wait-delay = <17>;
 653                 nvidia,elastic-limit = <16>;
 654                 nvidia,term-range-adj = <6>;
 655                 nvidia,xcvr-setup = <9>;
 656                 nvidia,xcvr-lsfslew = <0>;
 657                 nvidia,xcvr-lsrslew = <3>;
 658                 nvidia,hssquelch-level = <2>;
 659                 nvidia,hsdiscon-level = <5>;
 660                 nvidia,xcvr-hsslew = <12>;
 661                 status = "disabled";
 662         };
 663
 664         usb@0,7d008000 {
 665                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 666                 reg = <0x0 0x7d008000 0x0 0x4000>;
 667                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 668                 phy_type = "utmi";
 669                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 670                 resets = <&tegra_car 59>;
 671                 reset-names = "usb";
 672                 nvidia,phy = <&phy3>;
 673                 status = "disabled";
 674         };
 675
 676         phy3: usb-phy@0,7d008000 {
 677                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 678                 reg = <0x0 0x7d008000 0x0 0x4000>,
 679                       <0x0 0x7d000000 0x0 0x4000>;
 680                 phy_type = "utmi";
 681                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 682                          <&tegra_car TEGRA124_CLK_PLL_U>,
 683                          <&tegra_car TEGRA124_CLK_USBD>;
 684                 clock-names = "reg", "pll_u", "utmi-pads";
 685                 nvidia,hssync-start-delay = <0>;
 686                 nvidia,idle-wait-delay = <17>;
 687                 nvidia,elastic-limit = <16>;
 688                 nvidia,term-range-adj = <6>;
 689                 nvidia,xcvr-setup = <9>;
 690                 nvidia,xcvr-lsfslew = <0>;
 691                 nvidia,xcvr-lsrslew = <3>;
 692                 nvidia,hssquelch-level = <2>;
 693                 nvidia,hsdiscon-level = <5>;
 694                 nvidia,xcvr-hsslew = <12>;
 695                 status = "disabled";
 696         };
 697
 698         cpus {
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701
 702                 cpu@0 {
 703                         device_type = "cpu";
 704                         compatible = "arm,cortex-a15";
 705                         reg = <0>;
 706                 };
 707
 708                 cpu@1 {
 709                         device_type = "cpu";
 710                         compatible = "arm,cortex-a15";
 711                         reg = <1>;
 712                 };
 713
 714                 cpu@2 {
 715                         device_type = "cpu";
 716                         compatible = "arm,cortex-a15";
 717                         reg = <2>;
 718                 };
 719
 720                 cpu@3 {
 721                         device_type = "cpu";
 722                         compatible = "arm,cortex-a15";
 723                         reg = <3>;
 724                 };
 725         };
 726
 727         timer {
 728                 compatible = "arm,armv7-timer";
 729                 interrupts = <GIC_PPI 13
 730                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 731                              <GIC_PPI 14
 732                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 733                              <GIC_PPI 11
 734                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 735                              <GIC_PPI 10
 736                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 737         };
 738 };