arch/arm/boot/dts/qcom-msm8960.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6
   7 / {
   8         model = "Qualcomm MSM8960";
   9         compatible = "qcom,msm8960";
  10         interrupt-parent = <&intc>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15                 interrupts = <1 14 0x304>;
  16                 compatible = "qcom,krait";
  17                 enable-method = "qcom,kpss-acc-v1";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                         qcom,acc = <&acc0>;
  24                         qcom,saw = <&saw0>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         next-level-cache = <&L2>;
  31                         qcom,acc = <&acc1>;
  32                         qcom,saw = <&saw1>;
  33                 };
  34
  35                 L2: l2-cache {
  36                         compatible = "cache";
  37                         cache-level = <2>;
  38                         interrupts = <0 2 0x4>;
  39                 };
  40         };
  41
  42         cpu-pmu {
  43                 compatible = "qcom,krait-pmu";
  44                 interrupts = <1 10 0x304>;
  45                 qcom,no-pc-write;
  46         };
  47
  48         intc: interrupt-controller@2000000 {
  49                 compatible = "qcom,msm-qgic2";
  50                 interrupt-controller;
  51                 #interrupt-cells = <3>;
  52                 reg = < 0x02000000 0x1000 >,
  53                       < 0x02002000 0x1000 >;
  54         };
  55
  56         timer@200a000 {
  57                 compatible = "qcom,kpss-timer", "qcom,msm-timer";
  58                 interrupts = <1 1 0x301>,
  59                              <1 2 0x301>,
  60                              <1 3 0x301>;
  61                 reg = <0x0200a000 0x100>;
  62                 clock-frequency = <27000000>,
  63                                   <32768>;
  64                 cpu-offset = <0x80000>;
  65         };
  66
  67         msmgpio: gpio@800000 {
  68                 compatible = "qcom,msm-gpio";
  69                 gpio-controller;
  70                 #gpio-cells = <2>;
  71                 ngpio = <150>;
  72                 interrupts = <0 16 0x4>;
  73                 interrupt-controller;
  74                 #interrupt-cells = <2>;
  75                 reg = <0x800000 0x4000>;
  76         };
  77
  78         gcc: clock-controller@900000 {
  79                 compatible = "qcom,gcc-msm8960";
  80                 #clock-cells = <1>;
  81                 #reset-cells = <1>;
  82                 reg = <0x900000 0x4000>;
  83         };
  84
  85         clock-controller@4000000 {
  86                 compatible = "qcom,mmcc-msm8960";
  87                 reg = <0x4000000 0x1000>;
  88                 #clock-cells = <1>;
  89                 #reset-cells = <1>;
  90         };
  91
  92         acc0: clock-controller@2088000 {
  93                 compatible = "qcom,kpss-acc-v1";
  94                 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  95         };
  96
  97         acc1: clock-controller@2098000 {
  98                 compatible = "qcom,kpss-acc-v1";
  99                 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 100         };
 101
 102         saw0: regulator@2089000 {
 103                 compatible = "qcom,saw2";
 104                 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 105                 regulator;
 106         };
 107
 108         saw1: regulator@2099000 {
 109                 compatible = "qcom,saw2";
 110                 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 111                 regulator;
 112         };
 113
 114         serial@16440000 {
 115                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 116                 reg = <0x16440000 0x1000>,
 117                       <0x16400000 0x1000>;
 118                 interrupts = <0 154 0x0>;
 119                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 120                 clock-names = "core", "iface";
 121         };
 122
 123         qcom,ssbi@500000 {
 124                 compatible = "qcom,ssbi";
 125                 reg = <0x500000 0x1000>;
 126                 qcom,controller-type = "pmic-arbiter";
 127         };
 128
 129         rng@1a500000 {
 130                 compatible = "qcom,prng";
 131                 reg = <0x1a500000 0x200>;
 132                 clocks = <&gcc PRNG_CLK>;
 133                 clock-names = "core";
 134         };
 135 };